diff options
Diffstat (limited to 'drivers/gpu/drm/i915/intel_i2c.c')
-rw-r--r-- | drivers/gpu/drm/i915/intel_i2c.c | 25 |
1 files changed, 21 insertions, 4 deletions
diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c index 82d04c5899d2..d3b903bce7c5 100644 --- a/drivers/gpu/drm/i915/intel_i2c.c +++ b/drivers/gpu/drm/i915/intel_i2c.c | |||
@@ -259,7 +259,7 @@ gmbus_xfer(struct i2c_adapter *adapter, | |||
259 | if (wait_for(I915_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER | GMBUS_HW_RDY), 50)) | 259 | if (wait_for(I915_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER | GMBUS_HW_RDY), 50)) |
260 | goto timeout; | 260 | goto timeout; |
261 | if (I915_READ(GMBUS2 + reg_offset) & GMBUS_SATOER) | 261 | if (I915_READ(GMBUS2 + reg_offset) & GMBUS_SATOER) |
262 | return 0; | 262 | goto clear_err; |
263 | 263 | ||
264 | val = I915_READ(GMBUS3 + reg_offset); | 264 | val = I915_READ(GMBUS3 + reg_offset); |
265 | do { | 265 | do { |
@@ -287,7 +287,7 @@ gmbus_xfer(struct i2c_adapter *adapter, | |||
287 | if (wait_for(I915_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER | GMBUS_HW_RDY), 50)) | 287 | if (wait_for(I915_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER | GMBUS_HW_RDY), 50)) |
288 | goto timeout; | 288 | goto timeout; |
289 | if (I915_READ(GMBUS2 + reg_offset) & GMBUS_SATOER) | 289 | if (I915_READ(GMBUS2 + reg_offset) & GMBUS_SATOER) |
290 | return 0; | 290 | goto clear_err; |
291 | 291 | ||
292 | val = loop = 0; | 292 | val = loop = 0; |
293 | do { | 293 | do { |
@@ -302,14 +302,31 @@ gmbus_xfer(struct i2c_adapter *adapter, | |||
302 | if (i + 1 < num && wait_for(I915_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER | GMBUS_HW_WAIT_PHASE), 50)) | 302 | if (i + 1 < num && wait_for(I915_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER | GMBUS_HW_WAIT_PHASE), 50)) |
303 | goto timeout; | 303 | goto timeout; |
304 | if (I915_READ(GMBUS2 + reg_offset) & GMBUS_SATOER) | 304 | if (I915_READ(GMBUS2 + reg_offset) & GMBUS_SATOER) |
305 | return 0; | 305 | goto clear_err; |
306 | } | 306 | } |
307 | 307 | ||
308 | return num; | 308 | goto done; |
309 | |||
310 | clear_err: | ||
311 | /* Toggle the Software Clear Interrupt bit. This has the effect | ||
312 | * of resetting the GMBUS controller and so clearing the | ||
313 | * BUS_ERROR raised by the slave's NAK. | ||
314 | */ | ||
315 | I915_WRITE(GMBUS1 + reg_offset, GMBUS_SW_CLR_INT); | ||
316 | I915_WRITE(GMBUS1 + reg_offset, 0); | ||
317 | |||
318 | done: | ||
319 | /* Mark the GMBUS interface as disabled. We will re-enable it at the | ||
320 | * start of the next xfer, till then let it sleep. | ||
321 | */ | ||
322 | I915_WRITE(GMBUS0 + reg_offset, 0); | ||
323 | return i; | ||
309 | 324 | ||
310 | timeout: | 325 | timeout: |
311 | DRM_INFO("GMBUS timed out, falling back to bit banging on pin %d [%s]\n", | 326 | DRM_INFO("GMBUS timed out, falling back to bit banging on pin %d [%s]\n", |
312 | bus->reg0 & 0xff, bus->adapter.name); | 327 | bus->reg0 & 0xff, bus->adapter.name); |
328 | I915_WRITE(GMBUS0 + reg_offset, 0); | ||
329 | |||
313 | /* Hardware may not support GMBUS over these pins? Try GPIO bitbanging instead. */ | 330 | /* Hardware may not support GMBUS over these pins? Try GPIO bitbanging instead. */ |
314 | bus->force_bit = intel_gpio_create(dev_priv, bus->reg0 & 0xff); | 331 | bus->force_bit = intel_gpio_create(dev_priv, bus->reg0 & 0xff); |
315 | if (!bus->force_bit) | 332 | if (!bus->force_bit) |