1 files changed, 38 insertions, 6 deletions

diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
index 716409a57244..300aee3296c2 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -103,7 +103,7 @@ parse_lfp_panel_data(struct drm_i915_private *dev_priv,
         struct bdb_lvds_lfp_data_entry *entry;
         struct lvds_dvo_timing *dvo_timing;
         struct drm_display_mode *panel_fixed_mode;
-        int lfp_data_size;
+        int lfp_data_size, dvo_timing_offset;
 
         /* Defaults if we can't find VBT info */
         dev_priv->lvds_dither = 0;
@@ -132,7 +132,16 @@ parse_lfp_panel_data(struct drm_i915_private *dev_priv,
         entry = (struct bdb_lvds_lfp_data_entry *)
                 ((uint8_t *)lvds_lfp_data->data + (lfp_data_size *
                                                    lvds_options->panel_type));
-        dvo_timing = &entry->dvo_timing;
+        dvo_timing_offset = lvds_lfp_data_ptrs->ptr[0].dvo_timing_offset -
+                lvds_lfp_data_ptrs->ptr[0].fp_timing_offset;
+
+        /*
+         * the size of fp_timing varies on the different platform.
+         * So calculate the DVO timing relative offset in LVDS data
+         * entry to get the DVO timing entry
+         */
+        dvo_timing = (struct lvds_dvo_timing *)
+                        ((unsigned char *)entry + dvo_timing_offset);
 
         panel_fixed_mode = kzalloc(sizeof(*panel_fixed_mode), GFP_KERNEL);
 
@@ -195,10 +204,12 @@ parse_general_features(struct drm_i915_private *dev_priv,
                 dev_priv->lvds_use_ssc = general->enable_ssc;
 
                 if (dev_priv->lvds_use_ssc) {
-                  if (IS_I855(dev_priv->dev))
-                    dev_priv->lvds_ssc_freq = general->ssc_freq ? 66 : 48;
-                  else
-                    dev_priv->lvds_ssc_freq = general->ssc_freq ? 100 : 96;
+                        if (IS_I85X(dev_priv->dev))
+                                dev_priv->lvds_ssc_freq =
+                                        general->ssc_freq ? 66 : 48;
+                        else
+                                dev_priv->lvds_ssc_freq =
+                                        general->ssc_freq ? 100 : 96;
                 }
         }
 }
@@ -285,6 +296,25 @@ parse_sdvo_device_mapping(struct drm_i915_private *dev_priv,
         }
         return;
 }
+
+static void
+parse_driver_features(struct drm_i915_private *dev_priv,
+                       struct bdb_header *bdb)
+{
+        struct drm_device *dev = dev_priv->dev;
+        struct bdb_driver_features *driver;
+
+        /* set default for chips without eDP */
+        if (!SUPPORTS_EDP(dev)) {
+                dev_priv->edp_support = 0;
+                return;
+        }
+
+        driver = find_section(bdb, BDB_DRIVER_FEATURES);
+        if (driver && driver->lvds_config == BDB_DRIVER_FEATURE_EDP)
+                dev_priv->edp_support = 1;
+}
+
 /**
  * intel_init_bios - initialize VBIOS settings & find VBT
  * @dev: DRM device
@@ -335,6 +365,8 @@ intel_init_bios(struct drm_device *dev)
         parse_lfp_panel_data(dev_priv, bdb);
         parse_sdvo_panel_data(dev_priv, bdb);
         parse_sdvo_device_mapping(dev_priv, bdb);
+        parse_driver_features(dev_priv, bdb);
+
         pci_unmap_rom(pdev, bios);
 
         return 0;