diff options
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 488 |
1 files changed, 464 insertions, 24 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 9d24d65f0c3e..2d49b9507ed0 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h | |||
| @@ -27,6 +27,11 @@ | |||
| 27 | 27 | ||
| 28 | #define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a))) | 28 | #define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a))) |
| 29 | 29 | ||
| 30 | #define _PORT(port, a, b) ((a) + (port)*((b)-(a))) | ||
| 31 | |||
| 32 | #define _MASKED_BIT_ENABLE(a) (((a) << 16) | (a)) | ||
| 33 | #define _MASKED_BIT_DISABLE(a) ((a) << 16) | ||
| 34 | |||
| 30 | /* | 35 | /* |
| 31 | * The Bridge device's PCI config space has information about the | 36 | * The Bridge device's PCI config space has information about the |
| 32 | * fb aperture size and the amount of pre-reserved memory. | 37 | * fb aperture size and the amount of pre-reserved memory. |
| @@ -77,6 +82,7 @@ | |||
| 77 | #define GRDOM_FULL (0<<2) | 82 | #define GRDOM_FULL (0<<2) |
| 78 | #define GRDOM_RENDER (1<<2) | 83 | #define GRDOM_RENDER (1<<2) |
| 79 | #define GRDOM_MEDIA (3<<2) | 84 | #define GRDOM_MEDIA (3<<2) |
| 85 | #define GRDOM_RESET_ENABLE (1<<0) | ||
| 80 | 86 | ||
| 81 | #define GEN6_MBCUNIT_SNPCR 0x900c /* for LLC config */ | 87 | #define GEN6_MBCUNIT_SNPCR 0x900c /* for LLC config */ |
| 82 | #define GEN6_MBC_SNPCR_SHIFT 21 | 88 | #define GEN6_MBC_SNPCR_SHIFT 21 |
| @@ -125,6 +131,13 @@ | |||
| 125 | #define ECOCHK_PPGTT_CACHE64B (0x3<<3) | 131 | #define ECOCHK_PPGTT_CACHE64B (0x3<<3) |
| 126 | #define ECOCHK_PPGTT_CACHE4B (0x0<<3) | 132 | #define ECOCHK_PPGTT_CACHE4B (0x0<<3) |
| 127 | 133 | ||
| 134 | #define GAC_ECO_BITS 0x14090 | ||
| 135 | #define ECOBITS_PPGTT_CACHE64B (3<<8) | ||
| 136 | #define ECOBITS_PPGTT_CACHE4B (0<<8) | ||
| 137 | |||
| 138 | #define GAB_CTL 0x24000 | ||
| 139 | #define GAB_CTL_CONT_AFTER_PAGEFAULT (1<<8) | ||
| 140 | |||
| 128 | /* VGA stuff */ | 141 | /* VGA stuff */ |
| 129 | 142 | ||
| 130 | #define VGA_ST01_MDA 0x3ba | 143 | #define VGA_ST01_MDA 0x3ba |
| @@ -222,6 +235,7 @@ | |||
| 222 | #define MI_BATCH_NON_SECURE (1) | 235 | #define MI_BATCH_NON_SECURE (1) |
| 223 | #define MI_BATCH_NON_SECURE_I965 (1<<8) | 236 | #define MI_BATCH_NON_SECURE_I965 (1<<8) |
| 224 | #define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0) | 237 | #define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0) |
| 238 | #define MI_BATCH_GTT (2<<6) /* aliased with (1<<7) on gen4 */ | ||
| 225 | #define MI_SEMAPHORE_MBOX MI_INSTR(0x16, 1) /* gen6+ */ | 239 | #define MI_SEMAPHORE_MBOX MI_INSTR(0x16, 1) /* gen6+ */ |
| 226 | #define MI_SEMAPHORE_GLOBAL_GTT (1<<22) | 240 | #define MI_SEMAPHORE_GLOBAL_GTT (1<<22) |
| 227 | #define MI_SEMAPHORE_UPDATE (1<<21) | 241 | #define MI_SEMAPHORE_UPDATE (1<<21) |
| @@ -301,6 +315,61 @@ | |||
| 301 | #define DEBUG_RESET_RENDER (1<<8) | 315 | #define DEBUG_RESET_RENDER (1<<8) |
| 302 | #define DEBUG_RESET_DISPLAY (1<<9) | 316 | #define DEBUG_RESET_DISPLAY (1<<9) |
| 303 | 317 | ||
| 318 | /* | ||
| 319 | * DPIO - a special bus for various display related registers to hide behind: | ||
| 320 | * 0x800c: m1, m2, n, p1, p2, k dividers | ||
| 321 | * 0x8014: REF and SFR select | ||
| 322 | * 0x8014: N divider, VCO select | ||
| 323 | * 0x801c/3c: core clock bits | ||
| 324 | * 0x8048/68: low pass filter coefficients | ||
| 325 | * 0x8100: fast clock controls | ||
| 326 | */ | ||
| 327 | #define DPIO_PKT 0x2100 | ||
| 328 | #define DPIO_RID (0<<24) | ||
| 329 | #define DPIO_OP_WRITE (1<<16) | ||
| 330 | #define DPIO_OP_READ (0<<16) | ||
| 331 | #define DPIO_PORTID (0x12<<8) | ||
| 332 | #define DPIO_BYTE (0xf<<4) | ||
| 333 | #define DPIO_BUSY (1<<0) /* status only */ | ||
| 334 | #define DPIO_DATA 0x2104 | ||
| 335 | #define DPIO_REG 0x2108 | ||
| 336 | #define DPIO_CTL 0x2110 | ||
| 337 | #define DPIO_MODSEL1 (1<<3) /* if ref clk b == 27 */ | ||
| 338 | #define DPIO_MODSEL0 (1<<2) /* if ref clk a == 27 */ | ||
| 339 | #define DPIO_SFR_BYPASS (1<<1) | ||
| 340 | #define DPIO_RESET (1<<0) | ||
| 341 | |||
| 342 | #define _DPIO_DIV_A 0x800c | ||
| 343 | #define DPIO_POST_DIV_SHIFT (28) /* 3 bits */ | ||
| 344 | #define DPIO_K_SHIFT (24) /* 4 bits */ | ||
| 345 | #define DPIO_P1_SHIFT (21) /* 3 bits */ | ||
| 346 | #define DPIO_P2_SHIFT (16) /* 5 bits */ | ||
| 347 | #define DPIO_N_SHIFT (12) /* 4 bits */ | ||
| 348 | #define DPIO_ENABLE_CALIBRATION (1<<11) | ||
| 349 | #define DPIO_M1DIV_SHIFT (8) /* 3 bits */ | ||
| 350 | #define DPIO_M2DIV_MASK 0xff | ||
| 351 | #define _DPIO_DIV_B 0x802c | ||
| 352 | #define DPIO_DIV(pipe) _PIPE(pipe, _DPIO_DIV_A, _DPIO_DIV_B) | ||
| 353 | |||
| 354 | #define _DPIO_REFSFR_A 0x8014 | ||
| 355 | #define DPIO_REFSEL_OVERRIDE 27 | ||
| 356 | #define DPIO_PLL_MODESEL_SHIFT 24 /* 3 bits */ | ||
| 357 | #define DPIO_BIAS_CURRENT_CTL_SHIFT 21 /* 3 bits, always 0x7 */ | ||
| 358 | #define DPIO_PLL_REFCLK_SEL_SHIFT 16 /* 2 bits */ | ||
| 359 | #define DPIO_DRIVER_CTL_SHIFT 12 /* always set to 0x8 */ | ||
| 360 | #define DPIO_CLK_BIAS_CTL_SHIFT 8 /* always set to 0x5 */ | ||
| 361 | #define _DPIO_REFSFR_B 0x8034 | ||
| 362 | #define DPIO_REFSFR(pipe) _PIPE(pipe, _DPIO_REFSFR_A, _DPIO_REFSFR_B) | ||
| 363 | |||
| 364 | #define _DPIO_CORE_CLK_A 0x801c | ||
| 365 | #define _DPIO_CORE_CLK_B 0x803c | ||
| 366 | #define DPIO_CORE_CLK(pipe) _PIPE(pipe, _DPIO_CORE_CLK_A, _DPIO_CORE_CLK_B) | ||
| 367 | |||
| 368 | #define _DPIO_LFP_COEFF_A 0x8048 | ||
| 369 | #define _DPIO_LFP_COEFF_B 0x8068 | ||
| 370 | #define DPIO_LFP_COEFF(pipe) _PIPE(pipe, _DPIO_LFP_COEFF_A, _DPIO_LFP_COEFF_B) | ||
| 371 | |||
| 372 | #define DPIO_FASTCLK_DISABLE 0x8100 | ||
| 304 | 373 | ||
| 305 | /* | 374 | /* |
| 306 | * Fence registers | 375 | * Fence registers |
| @@ -360,8 +429,6 @@ | |||
| 360 | #define ARB_MODE 0x04030 | 429 | #define ARB_MODE 0x04030 |
| 361 | #define ARB_MODE_SWIZZLE_SNB (1<<4) | 430 | #define ARB_MODE_SWIZZLE_SNB (1<<4) |
| 362 | #define ARB_MODE_SWIZZLE_IVB (1<<5) | 431 | #define ARB_MODE_SWIZZLE_IVB (1<<5) |
| 363 | #define ARB_MODE_ENABLE(x) GFX_MODE_ENABLE(x) | ||
| 364 | #define ARB_MODE_DISABLE(x) GFX_MODE_DISABLE(x) | ||
| 365 | #define RENDER_HWS_PGA_GEN7 (0x04080) | 432 | #define RENDER_HWS_PGA_GEN7 (0x04080) |
| 366 | #define RING_FAULT_REG(ring) (0x4094 + 0x100*(ring)->id) | 433 | #define RING_FAULT_REG(ring) (0x4094 + 0x100*(ring)->id) |
| 367 | #define DONE_REG 0x40b0 | 434 | #define DONE_REG 0x40b0 |
| @@ -417,6 +484,7 @@ | |||
| 417 | #define INSTDONE 0x02090 | 484 | #define INSTDONE 0x02090 |
| 418 | #define NOPID 0x02094 | 485 | #define NOPID 0x02094 |
| 419 | #define HWSTAM 0x02098 | 486 | #define HWSTAM 0x02098 |
| 487 | #define DMA_FADD_I8XX 0x020d0 | ||
| 420 | 488 | ||
| 421 | #define ERROR_GEN6 0x040a0 | 489 | #define ERROR_GEN6 0x040a0 |
| 422 | 490 | ||
| @@ -432,6 +500,7 @@ | |||
| 432 | */ | 500 | */ |
| 433 | # define _3D_CHICKEN2_WM_READ_PIPELINED (1 << 14) | 501 | # define _3D_CHICKEN2_WM_READ_PIPELINED (1 << 14) |
| 434 | #define _3D_CHICKEN3 0x02090 | 502 | #define _3D_CHICKEN3 0x02090 |
| 503 | #define _3D_CHICKEN_SF_DISABLE_FASTCLIP_CULL (1 << 5) | ||
| 435 | 504 | ||
| 436 | #define MI_MODE 0x0209c | 505 | #define MI_MODE 0x0209c |
| 437 | # define VS_TIMER_DISPATCH (1 << 6) | 506 | # define VS_TIMER_DISPATCH (1 << 6) |
| @@ -447,14 +516,16 @@ | |||
| 447 | #define GFX_PSMI_GRANULARITY (1<<10) | 516 | #define GFX_PSMI_GRANULARITY (1<<10) |
| 448 | #define GFX_PPGTT_ENABLE (1<<9) | 517 | #define GFX_PPGTT_ENABLE (1<<9) |
| 449 | 518 | ||
| 450 | #define GFX_MODE_ENABLE(bit) (((bit) << 16) | (bit)) | ||
| 451 | #define GFX_MODE_DISABLE(bit) (((bit) << 16) | (0)) | ||
| 452 | |||
| 453 | #define SCPD0 0x0209c /* 915+ only */ | 519 | #define SCPD0 0x0209c /* 915+ only */ |
| 454 | #define IER 0x020a0 | 520 | #define IER 0x020a0 |
| 455 | #define IIR 0x020a4 | 521 | #define IIR 0x020a4 |
| 456 | #define IMR 0x020a8 | 522 | #define IMR 0x020a8 |
| 457 | #define ISR 0x020ac | 523 | #define ISR 0x020ac |
| 524 | #define VLV_IIR_RW 0x182084 | ||
| 525 | #define VLV_IER 0x1820a0 | ||
| 526 | #define VLV_IIR 0x1820a4 | ||
| 527 | #define VLV_IMR 0x1820a8 | ||
| 528 | #define VLV_ISR 0x1820ac | ||
| 458 | #define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18) | 529 | #define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18) |
| 459 | #define I915_DISPLAY_PORT_INTERRUPT (1<<17) | 530 | #define I915_DISPLAY_PORT_INTERRUPT (1<<17) |
| 460 | #define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15) | 531 | #define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15) |
| @@ -500,7 +571,6 @@ | |||
| 500 | #define LM_BURST_LENGTH 0x00000700 | 571 | #define LM_BURST_LENGTH 0x00000700 |
| 501 | #define LM_FIFO_WATERMARK 0x0000001F | 572 | #define LM_FIFO_WATERMARK 0x0000001F |
| 502 | #define MI_ARB_STATE 0x020e4 /* 915+ only */ | 573 | #define MI_ARB_STATE 0x020e4 /* 915+ only */ |
| 503 | #define MI_ARB_MASK_SHIFT 16 /* shift for enable bits */ | ||
| 504 | 574 | ||
| 505 | /* Make render/texture TLB fetches lower priorty than associated data | 575 | /* Make render/texture TLB fetches lower priorty than associated data |
| 506 | * fetches. This is not turned on by default | 576 | * fetches. This is not turned on by default |
| @@ -565,7 +635,6 @@ | |||
| 565 | #define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */ | 635 | #define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */ |
| 566 | 636 | ||
| 567 | #define CACHE_MODE_0 0x02120 /* 915+ only */ | 637 | #define CACHE_MODE_0 0x02120 /* 915+ only */ |
| 568 | #define CM0_MASK_SHIFT 16 | ||
| 569 | #define CM0_IZ_OPT_DISABLE (1<<6) | 638 | #define CM0_IZ_OPT_DISABLE (1<<6) |
| 570 | #define CM0_ZR_OPT_DISABLE (1<<5) | 639 | #define CM0_ZR_OPT_DISABLE (1<<5) |
| 571 | #define CM0_STC_EVICT_DISABLE_LRA_SNB (1<<5) | 640 | #define CM0_STC_EVICT_DISABLE_LRA_SNB (1<<5) |
| @@ -579,7 +648,12 @@ | |||
| 579 | #define ECO_GATING_CX_ONLY (1<<3) | 648 | #define ECO_GATING_CX_ONLY (1<<3) |
| 580 | #define ECO_FLIP_DONE (1<<0) | 649 | #define ECO_FLIP_DONE (1<<0) |
| 581 | 650 | ||
| 582 | /* GEN6 interrupt control */ | 651 | #define CACHE_MODE_1 0x7004 /* IVB+ */ |
| 652 | #define PIXEL_SUBSPAN_COLLECT_OPT_DISABLE (1<<6) | ||
| 653 | |||
| 654 | /* GEN6 interrupt control | ||
| 655 | * Note that the per-ring interrupt bits do alias with the global interrupt bits | ||
| 656 | * in GTIMR. */ | ||
| 583 | #define GEN6_RENDER_HWSTAM 0x2098 | 657 | #define GEN6_RENDER_HWSTAM 0x2098 |
| 584 | #define GEN6_RENDER_IMR 0x20a8 | 658 | #define GEN6_RENDER_IMR 0x20a8 |
| 585 | #define GEN6_RENDER_CONTEXT_SWITCH_INTERRUPT (1 << 8) | 659 | #define GEN6_RENDER_CONTEXT_SWITCH_INTERRUPT (1 << 8) |
| @@ -615,6 +689,21 @@ | |||
| 615 | 689 | ||
| 616 | #define GEN6_BSD_RNCID 0x12198 | 690 | #define GEN6_BSD_RNCID 0x12198 |
| 617 | 691 | ||
| 692 | #define GEN7_FF_THREAD_MODE 0x20a0 | ||
| 693 | #define GEN7_FF_SCHED_MASK 0x0077070 | ||
| 694 | #define GEN7_FF_TS_SCHED_HS1 (0x5<<16) | ||
| 695 | #define GEN7_FF_TS_SCHED_HS0 (0x3<<16) | ||
| 696 | #define GEN7_FF_TS_SCHED_LOAD_BALANCE (0x1<<16) | ||
| 697 | #define GEN7_FF_TS_SCHED_HW (0x0<<16) /* Default */ | ||
| 698 | #define GEN7_FF_VS_SCHED_HS1 (0x5<<12) | ||
| 699 | #define GEN7_FF_VS_SCHED_HS0 (0x3<<12) | ||
| 700 | #define GEN7_FF_VS_SCHED_LOAD_BALANCE (0x1<<12) /* Default */ | ||
| 701 | #define GEN7_FF_VS_SCHED_HW (0x0<<12) | ||
| 702 | #define GEN7_FF_DS_SCHED_HS1 (0x5<<4) | ||
| 703 | #define GEN7_FF_DS_SCHED_HS0 (0x3<<4) | ||
| 704 | #define GEN7_FF_DS_SCHED_LOAD_BALANCE (0x1<<4) /* Default */ | ||
| 705 | #define GEN7_FF_DS_SCHED_HW (0x0<<4) | ||
| 706 | |||
| 618 | /* | 707 | /* |
| 619 | * Framebuffer compression (915+ only) | 708 | * Framebuffer compression (915+ only) |
| 620 | */ | 709 | */ |
| @@ -743,9 +832,9 @@ | |||
| 743 | #define GMBUS_PORT_PANEL 3 | 832 | #define GMBUS_PORT_PANEL 3 |
| 744 | #define GMBUS_PORT_DPC 4 /* HDMIC */ | 833 | #define GMBUS_PORT_DPC 4 /* HDMIC */ |
| 745 | #define GMBUS_PORT_DPB 5 /* SDVO, HDMIB */ | 834 | #define GMBUS_PORT_DPB 5 /* SDVO, HDMIB */ |
| 746 | /* 6 reserved */ | 835 | #define GMBUS_PORT_DPD 6 /* HDMID */ |
| 747 | #define GMBUS_PORT_DPD 7 /* HDMID */ | 836 | #define GMBUS_PORT_RESERVED 7 /* 7 reserved */ |
| 748 | #define GMBUS_NUM_PORTS 8 | 837 | #define GMBUS_NUM_PORTS (GMBUS_PORT_DPD - GMBUS_PORT_SSC + 1) |
| 749 | #define GMBUS1 0x5104 /* command/status */ | 838 | #define GMBUS1 0x5104 /* command/status */ |
| 750 | #define GMBUS_SW_CLR_INT (1<<31) | 839 | #define GMBUS_SW_CLR_INT (1<<31) |
| 751 | #define GMBUS_SW_RDY (1<<30) | 840 | #define GMBUS_SW_RDY (1<<30) |
| @@ -797,7 +886,9 @@ | |||
| 797 | #define DPLL(pipe) _PIPE(pipe, _DPLL_A, _DPLL_B) | 886 | #define DPLL(pipe) _PIPE(pipe, _DPLL_A, _DPLL_B) |
| 798 | #define DPLL_VCO_ENABLE (1 << 31) | 887 | #define DPLL_VCO_ENABLE (1 << 31) |
| 799 | #define DPLL_DVO_HIGH_SPEED (1 << 30) | 888 | #define DPLL_DVO_HIGH_SPEED (1 << 30) |
| 889 | #define DPLL_EXT_BUFFER_ENABLE_VLV (1 << 30) | ||
| 800 | #define DPLL_SYNCLOCK_ENABLE (1 << 29) | 890 | #define DPLL_SYNCLOCK_ENABLE (1 << 29) |
| 891 | #define DPLL_REFA_CLK_ENABLE_VLV (1 << 29) | ||
| 801 | #define DPLL_VGA_MODE_DIS (1 << 28) | 892 | #define DPLL_VGA_MODE_DIS (1 << 28) |
| 802 | #define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */ | 893 | #define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */ |
| 803 | #define DPLLB_MODE_LVDS (2 << 26) /* i915 */ | 894 | #define DPLLB_MODE_LVDS (2 << 26) /* i915 */ |
| @@ -809,6 +900,7 @@ | |||
| 809 | #define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */ | 900 | #define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */ |
| 810 | #define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */ | 901 | #define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */ |
| 811 | #define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */ | 902 | #define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */ |
| 903 | #define DPLL_INTEGRATED_CLOCK_VLV (1<<13) | ||
| 812 | 904 | ||
| 813 | #define SRX_INDEX 0x3c4 | 905 | #define SRX_INDEX 0x3c4 |
| 814 | #define SRX_DATA 0x3c5 | 906 | #define SRX_DATA 0x3c5 |
| @@ -904,6 +996,7 @@ | |||
| 904 | #define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0 | 996 | #define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0 |
| 905 | #define _DPLL_B_MD 0x06020 /* 965+ only */ | 997 | #define _DPLL_B_MD 0x06020 /* 965+ only */ |
| 906 | #define DPLL_MD(pipe) _PIPE(pipe, _DPLL_A_MD, _DPLL_B_MD) | 998 | #define DPLL_MD(pipe) _PIPE(pipe, _DPLL_A_MD, _DPLL_B_MD) |
| 999 | |||
| 907 | #define _FPA0 0x06040 | 1000 | #define _FPA0 0x06040 |
| 908 | #define _FPA1 0x06044 | 1001 | #define _FPA1 0x06044 |
| 909 | #define _FPB0 0x06048 | 1002 | #define _FPB0 0x06048 |
| @@ -1044,6 +1137,9 @@ | |||
| 1044 | #define RAMCLK_GATE_D 0x6210 /* CRL only */ | 1137 | #define RAMCLK_GATE_D 0x6210 /* CRL only */ |
| 1045 | #define DEUC 0x6214 /* CRL only */ | 1138 | #define DEUC 0x6214 /* CRL only */ |
| 1046 | 1139 | ||
| 1140 | #define FW_BLC_SELF_VLV 0x6500 | ||
| 1141 | #define FW_CSPWRDWNEN (1<<15) | ||
| 1142 | |||
| 1047 | /* | 1143 | /* |
| 1048 | * Palette regs | 1144 | * Palette regs |
| 1049 | */ | 1145 | */ |
| @@ -1601,9 +1697,12 @@ | |||
| 1601 | /* Video Data Island Packet control */ | 1697 | /* Video Data Island Packet control */ |
| 1602 | #define VIDEO_DIP_DATA 0x61178 | 1698 | #define VIDEO_DIP_DATA 0x61178 |
| 1603 | #define VIDEO_DIP_CTL 0x61170 | 1699 | #define VIDEO_DIP_CTL 0x61170 |
| 1700 | /* Pre HSW: */ | ||
| 1604 | #define VIDEO_DIP_ENABLE (1 << 31) | 1701 | #define VIDEO_DIP_ENABLE (1 << 31) |
| 1605 | #define VIDEO_DIP_PORT_B (1 << 29) | 1702 | #define VIDEO_DIP_PORT_B (1 << 29) |
| 1606 | #define VIDEO_DIP_PORT_C (2 << 29) | 1703 | #define VIDEO_DIP_PORT_C (2 << 29) |
| 1704 | #define VIDEO_DIP_PORT_D (3 << 29) | ||
| 1705 | #define VIDEO_DIP_PORT_MASK (3 << 29) | ||
| 1607 | #define VIDEO_DIP_ENABLE_AVI (1 << 21) | 1706 | #define VIDEO_DIP_ENABLE_AVI (1 << 21) |
| 1608 | #define VIDEO_DIP_ENABLE_VENDOR (2 << 21) | 1707 | #define VIDEO_DIP_ENABLE_VENDOR (2 << 21) |
| 1609 | #define VIDEO_DIP_ENABLE_SPD (8 << 21) | 1708 | #define VIDEO_DIP_ENABLE_SPD (8 << 21) |
| @@ -1614,6 +1713,10 @@ | |||
| 1614 | #define VIDEO_DIP_FREQ_ONCE (0 << 16) | 1713 | #define VIDEO_DIP_FREQ_ONCE (0 << 16) |
| 1615 | #define VIDEO_DIP_FREQ_VSYNC (1 << 16) | 1714 | #define VIDEO_DIP_FREQ_VSYNC (1 << 16) |
| 1616 | #define VIDEO_DIP_FREQ_2VSYNC (2 << 16) | 1715 | #define VIDEO_DIP_FREQ_2VSYNC (2 << 16) |
| 1716 | #define VIDEO_DIP_FREQ_MASK (3 << 16) | ||
| 1717 | /* HSW and later: */ | ||
| 1718 | #define VIDEO_DIP_ENABLE_AVI_HSW (1 << 12) | ||
| 1719 | #define VIDEO_DIP_ENABLE_SPD_HSW (1 << 0) | ||
| 1617 | 1720 | ||
| 1618 | /* Panel power sequencing */ | 1721 | /* Panel power sequencing */ |
| 1619 | #define PP_STATUS 0x61200 | 1722 | #define PP_STATUS 0x61200 |
| @@ -2380,7 +2483,8 @@ | |||
| 2380 | 2483 | ||
| 2381 | /* Pipe A */ | 2484 | /* Pipe A */ |
| 2382 | #define _PIPEADSL 0x70000 | 2485 | #define _PIPEADSL 0x70000 |
| 2383 | #define DSL_LINEMASK 0x00000fff | 2486 | #define DSL_LINEMASK_GEN2 0x00000fff |
| 2487 | #define DSL_LINEMASK_GEN3 0x00001fff | ||
| 2384 | #define _PIPEACONF 0x70008 | 2488 | #define _PIPEACONF 0x70008 |
| 2385 | #define PIPECONF_ENABLE (1<<31) | 2489 | #define PIPECONF_ENABLE (1<<31) |
| 2386 | #define PIPECONF_DISABLE 0 | 2490 | #define PIPECONF_DISABLE 0 |
| @@ -2422,23 +2526,30 @@ | |||
| 2422 | #define PIPECONF_DITHER_TYPE_TEMP (3<<2) | 2526 | #define PIPECONF_DITHER_TYPE_TEMP (3<<2) |
| 2423 | #define _PIPEASTAT 0x70024 | 2527 | #define _PIPEASTAT 0x70024 |
| 2424 | #define PIPE_FIFO_UNDERRUN_STATUS (1UL<<31) | 2528 | #define PIPE_FIFO_UNDERRUN_STATUS (1UL<<31) |
| 2529 | #define SPRITE1_FLIPDONE_INT_EN_VLV (1UL<<30) | ||
| 2425 | #define PIPE_CRC_ERROR_ENABLE (1UL<<29) | 2530 | #define PIPE_CRC_ERROR_ENABLE (1UL<<29) |
| 2426 | #define PIPE_CRC_DONE_ENABLE (1UL<<28) | 2531 | #define PIPE_CRC_DONE_ENABLE (1UL<<28) |
| 2427 | #define PIPE_GMBUS_EVENT_ENABLE (1UL<<27) | 2532 | #define PIPE_GMBUS_EVENT_ENABLE (1UL<<27) |
| 2533 | #define PLANE_FLIP_DONE_INT_EN_VLV (1UL<<26) | ||
| 2428 | #define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL<<26) | 2534 | #define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL<<26) |
| 2429 | #define PIPE_VSYNC_INTERRUPT_ENABLE (1UL<<25) | 2535 | #define PIPE_VSYNC_INTERRUPT_ENABLE (1UL<<25) |
| 2430 | #define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24) | 2536 | #define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24) |
| 2431 | #define PIPE_DPST_EVENT_ENABLE (1UL<<23) | 2537 | #define PIPE_DPST_EVENT_ENABLE (1UL<<23) |
| 2538 | #define SPRITE0_FLIP_DONE_INT_EN_VLV (1UL<<26) | ||
| 2432 | #define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL<<22) | 2539 | #define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL<<22) |
| 2433 | #define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21) | 2540 | #define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21) |
| 2434 | #define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20) | 2541 | #define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20) |
| 2435 | #define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL<<18) /* pre-965 */ | 2542 | #define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL<<18) /* pre-965 */ |
| 2436 | #define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */ | 2543 | #define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */ |
| 2437 | #define PIPE_VBLANK_INTERRUPT_ENABLE (1UL<<17) | 2544 | #define PIPE_VBLANK_INTERRUPT_ENABLE (1UL<<17) |
| 2545 | #define PIPEA_HBLANK_INT_EN_VLV (1UL<<16) | ||
| 2438 | #define PIPE_OVERLAY_UPDATED_ENABLE (1UL<<16) | 2546 | #define PIPE_OVERLAY_UPDATED_ENABLE (1UL<<16) |
| 2547 | #define SPRITE1_FLIPDONE_INT_STATUS_VLV (1UL<<15) | ||
| 2548 | #define SPRITE0_FLIPDONE_INT_STATUS_VLV (1UL<<15) | ||
| 2439 | #define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL<<13) | 2549 | #define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL<<13) |
| 2440 | #define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL<<12) | 2550 | #define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL<<12) |
| 2441 | #define PIPE_GMBUS_INTERRUPT_STATUS (1UL<<11) | 2551 | #define PIPE_GMBUS_INTERRUPT_STATUS (1UL<<11) |
| 2552 | #define PLANE_FLIPDONE_INT_STATUS_VLV (1UL<<10) | ||
| 2442 | #define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL<<10) | 2553 | #define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL<<10) |
| 2443 | #define PIPE_VSYNC_INTERRUPT_STATUS (1UL<<9) | 2554 | #define PIPE_VSYNC_INTERRUPT_STATUS (1UL<<9) |
| 2444 | #define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL<<8) | 2555 | #define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL<<8) |
| @@ -2463,6 +2574,40 @@ | |||
| 2463 | #define PIPEFRAMEPIXEL(pipe) _PIPE(pipe, _PIPEAFRAMEPIXEL, _PIPEBFRAMEPIXEL) | 2574 | #define PIPEFRAMEPIXEL(pipe) _PIPE(pipe, _PIPEAFRAMEPIXEL, _PIPEBFRAMEPIXEL) |
| 2464 | #define PIPESTAT(pipe) _PIPE(pipe, _PIPEASTAT, _PIPEBSTAT) | 2575 | #define PIPESTAT(pipe) _PIPE(pipe, _PIPEASTAT, _PIPEBSTAT) |
| 2465 | 2576 | ||
| 2577 | #define VLV_DPFLIPSTAT 0x70028 | ||
| 2578 | #define PIPEB_LINE_COMPARE_STATUS (1<<29) | ||
| 2579 | #define PIPEB_HLINE_INT_EN (1<<28) | ||
| 2580 | #define PIPEB_VBLANK_INT_EN (1<<27) | ||
| 2581 | #define SPRITED_FLIPDONE_INT_EN (1<<26) | ||
| 2582 | #define SPRITEC_FLIPDONE_INT_EN (1<<25) | ||
| 2583 | #define PLANEB_FLIPDONE_INT_EN (1<<24) | ||
| 2584 | #define PIPEA_LINE_COMPARE_STATUS (1<<21) | ||
| 2585 | #define PIPEA_HLINE_INT_EN (1<<20) | ||
| 2586 | #define PIPEA_VBLANK_INT_EN (1<<19) | ||
| 2587 | #define SPRITEB_FLIPDONE_INT_EN (1<<18) | ||
| 2588 | #define SPRITEA_FLIPDONE_INT_EN (1<<17) | ||
| 2589 | #define PLANEA_FLIPDONE_INT_EN (1<<16) | ||
| 2590 | |||
| 2591 | #define DPINVGTT 0x7002c /* VLV only */ | ||
| 2592 | #define CURSORB_INVALID_GTT_INT_EN (1<<23) | ||
| 2593 | #define CURSORA_INVALID_GTT_INT_EN (1<<22) | ||
| 2594 | #define SPRITED_INVALID_GTT_INT_EN (1<<21) | ||
| 2595 | #define SPRITEC_INVALID_GTT_INT_EN (1<<20) | ||
| 2596 | #define PLANEB_INVALID_GTT_INT_EN (1<<19) | ||
| 2597 | #define SPRITEB_INVALID_GTT_INT_EN (1<<18) | ||
| 2598 | #define SPRITEA_INVALID_GTT_INT_EN (1<<17) | ||
| 2599 | #define PLANEA_INVALID_GTT_INT_EN (1<<16) | ||
| 2600 | #define DPINVGTT_EN_MASK 0xff0000 | ||
| 2601 | #define CURSORB_INVALID_GTT_STATUS (1<<7) | ||
| 2602 | #define CURSORA_INVALID_GTT_STATUS (1<<6) | ||
| 2603 | #define SPRITED_INVALID_GTT_STATUS (1<<5) | ||
| 2604 | #define SPRITEC_INVALID_GTT_STATUS (1<<4) | ||
| 2605 | #define PLANEB_INVALID_GTT_STATUS (1<<3) | ||
| 2606 | #define SPRITEB_INVALID_GTT_STATUS (1<<2) | ||
| 2607 | #define SPRITEA_INVALID_GTT_STATUS (1<<1) | ||
| 2608 | #define PLANEA_INVALID_GTT_STATUS (1<<0) | ||
| 2609 | #define DPINVGTT_STATUS_MASK 0xff | ||
| 2610 | |||
| 2466 | #define DSPARB 0x70030 | 2611 | #define DSPARB 0x70030 |
| 2467 | #define DSPARB_CSTART_MASK (0x7f << 7) | 2612 | #define DSPARB_CSTART_MASK (0x7f << 7) |
| 2468 | #define DSPARB_CSTART_SHIFT 7 | 2613 | #define DSPARB_CSTART_SHIFT 7 |
| @@ -2492,11 +2637,28 @@ | |||
| 2492 | #define DSPFW_HPLL_CURSOR_MASK (0x3f<<16) | 2637 | #define DSPFW_HPLL_CURSOR_MASK (0x3f<<16) |
| 2493 | #define DSPFW_HPLL_SR_MASK (0x1ff) | 2638 | #define DSPFW_HPLL_SR_MASK (0x1ff) |
| 2494 | 2639 | ||
| 2640 | /* drain latency register values*/ | ||
| 2641 | #define DRAIN_LATENCY_PRECISION_32 32 | ||
| 2642 | #define DRAIN_LATENCY_PRECISION_16 16 | ||
| 2643 | #define VLV_DDL1 0x70050 | ||
| 2644 | #define DDL_CURSORA_PRECISION_32 (1<<31) | ||
| 2645 | #define DDL_CURSORA_PRECISION_16 (0<<31) | ||
| 2646 | #define DDL_CURSORA_SHIFT 24 | ||
| 2647 | #define DDL_PLANEA_PRECISION_32 (1<<7) | ||
| 2648 | #define DDL_PLANEA_PRECISION_16 (0<<7) | ||
| 2649 | #define VLV_DDL2 0x70054 | ||
| 2650 | #define DDL_CURSORB_PRECISION_32 (1<<31) | ||
| 2651 | #define DDL_CURSORB_PRECISION_16 (0<<31) | ||
| 2652 | #define DDL_CURSORB_SHIFT 24 | ||
| 2653 | #define DDL_PLANEB_PRECISION_32 (1<<7) | ||
| 2654 | #define DDL_PLANEB_PRECISION_16 (0<<7) | ||
| 2655 | |||
| 2495 | /* FIFO watermark sizes etc */ | 2656 | /* FIFO watermark sizes etc */ |
| 2496 | #define G4X_FIFO_LINE_SIZE 64 | 2657 | #define G4X_FIFO_LINE_SIZE 64 |
| 2497 | #define I915_FIFO_LINE_SIZE 64 | 2658 | #define I915_FIFO_LINE_SIZE 64 |
| 2498 | #define I830_FIFO_LINE_SIZE 32 | 2659 | #define I830_FIFO_LINE_SIZE 32 |
| 2499 | 2660 | ||
| 2661 | #define VALLEYVIEW_FIFO_SIZE 255 | ||
| 2500 | #define G4X_FIFO_SIZE 127 | 2662 | #define G4X_FIFO_SIZE 127 |
| 2501 | #define I965_FIFO_SIZE 512 | 2663 | #define I965_FIFO_SIZE 512 |
| 2502 | #define I945_FIFO_SIZE 127 | 2664 | #define I945_FIFO_SIZE 127 |
| @@ -2504,6 +2666,7 @@ | |||
| 2504 | #define I855GM_FIFO_SIZE 127 /* In cachelines */ | 2666 | #define I855GM_FIFO_SIZE 127 /* In cachelines */ |
| 2505 | #define I830_FIFO_SIZE 95 | 2667 | #define I830_FIFO_SIZE 95 |
| 2506 | 2668 | ||
| 2669 | #define VALLEYVIEW_MAX_WM 0xff | ||
| 2507 | #define G4X_MAX_WM 0x3f | 2670 | #define G4X_MAX_WM 0x3f |
| 2508 | #define I915_MAX_WM 0x3f | 2671 | #define I915_MAX_WM 0x3f |
| 2509 | 2672 | ||
| @@ -2518,6 +2681,7 @@ | |||
| 2518 | #define PINEVIEW_CURSOR_DFT_WM 0 | 2681 | #define PINEVIEW_CURSOR_DFT_WM 0 |
| 2519 | #define PINEVIEW_CURSOR_GUARD_WM 5 | 2682 | #define PINEVIEW_CURSOR_GUARD_WM 5 |
| 2520 | 2683 | ||
| 2684 | #define VALLEYVIEW_CURSOR_MAX_WM 64 | ||
| 2521 | #define I965_CURSOR_FIFO 64 | 2685 | #define I965_CURSOR_FIFO 64 |
| 2522 | #define I965_CURSOR_MAX_WM 32 | 2686 | #define I965_CURSOR_MAX_WM 32 |
| 2523 | #define I965_CURSOR_DFT_WM 8 | 2687 | #define I965_CURSOR_DFT_WM 8 |
| @@ -2726,6 +2890,13 @@ | |||
| 2726 | #define DSPSURF(plane) _PIPE(plane, _DSPASURF, _DSPBSURF) | 2890 | #define DSPSURF(plane) _PIPE(plane, _DSPASURF, _DSPBSURF) |
| 2727 | #define DSPTILEOFF(plane) _PIPE(plane, _DSPATILEOFF, _DSPBTILEOFF) | 2891 | #define DSPTILEOFF(plane) _PIPE(plane, _DSPATILEOFF, _DSPBTILEOFF) |
| 2728 | 2892 | ||
| 2893 | /* Display/Sprite base address macros */ | ||
| 2894 | #define DISP_BASEADDR_MASK (0xfffff000) | ||
| 2895 | #define I915_LO_DISPBASE(val) (val & ~DISP_BASEADDR_MASK) | ||
| 2896 | #define I915_HI_DISPBASE(val) (val & DISP_BASEADDR_MASK) | ||
| 2897 | #define I915_MODIFY_DISPBASE(reg, gfx_addr) \ | ||
| 2898 | (I915_WRITE(reg, gfx_addr | I915_LO_DISPBASE(I915_READ(reg)))) | ||
| 2899 | |||
| 2729 | /* VBIOS flags */ | 2900 | /* VBIOS flags */ |
| 2730 | #define SWF00 0x71410 | 2901 | #define SWF00 0x71410 |
| 2731 | #define SWF01 0x71414 | 2902 | #define SWF01 0x71414 |
| @@ -3058,25 +3229,38 @@ | |||
| 3058 | #define DE_PCH_EVENT_IVB (1<<28) | 3229 | #define DE_PCH_EVENT_IVB (1<<28) |
| 3059 | #define DE_DP_A_HOTPLUG_IVB (1<<27) | 3230 | #define DE_DP_A_HOTPLUG_IVB (1<<27) |
| 3060 | #define DE_AUX_CHANNEL_A_IVB (1<<26) | 3231 | #define DE_AUX_CHANNEL_A_IVB (1<<26) |
| 3232 | #define DE_SPRITEC_FLIP_DONE_IVB (1<<14) | ||
| 3233 | #define DE_PLANEC_FLIP_DONE_IVB (1<<13) | ||
| 3234 | #define DE_PIPEC_VBLANK_IVB (1<<10) | ||
| 3061 | #define DE_SPRITEB_FLIP_DONE_IVB (1<<9) | 3235 | #define DE_SPRITEB_FLIP_DONE_IVB (1<<9) |
| 3062 | #define DE_SPRITEA_FLIP_DONE_IVB (1<<4) | ||
| 3063 | #define DE_PLANEB_FLIP_DONE_IVB (1<<8) | 3236 | #define DE_PLANEB_FLIP_DONE_IVB (1<<8) |
| 3064 | #define DE_PLANEA_FLIP_DONE_IVB (1<<3) | ||
| 3065 | #define DE_PIPEB_VBLANK_IVB (1<<5) | 3237 | #define DE_PIPEB_VBLANK_IVB (1<<5) |
| 3238 | #define DE_SPRITEA_FLIP_DONE_IVB (1<<4) | ||
| 3239 | #define DE_PLANEA_FLIP_DONE_IVB (1<<3) | ||
| 3066 | #define DE_PIPEA_VBLANK_IVB (1<<0) | 3240 | #define DE_PIPEA_VBLANK_IVB (1<<0) |
| 3067 | 3241 | ||
| 3242 | #define VLV_MASTER_IER 0x4400c /* Gunit master IER */ | ||
| 3243 | #define MASTER_INTERRUPT_ENABLE (1<<31) | ||
| 3244 | |||
| 3068 | #define DEISR 0x44000 | 3245 | #define DEISR 0x44000 |
| 3069 | #define DEIMR 0x44004 | 3246 | #define DEIMR 0x44004 |
| 3070 | #define DEIIR 0x44008 | 3247 | #define DEIIR 0x44008 |
| 3071 | #define DEIER 0x4400c | 3248 | #define DEIER 0x4400c |
| 3072 | 3249 | ||
| 3073 | /* GT interrupt */ | 3250 | /* GT interrupt. |
| 3074 | #define GT_PIPE_NOTIFY (1 << 4) | 3251 | * Note that for gen6+ the ring-specific interrupt bits do alias with the |
| 3075 | #define GT_SYNC_STATUS (1 << 2) | 3252 | * corresponding bits in the per-ring interrupt control registers. */ |
| 3076 | #define GT_USER_INTERRUPT (1 << 0) | 3253 | #define GT_GEN6_BLT_FLUSHDW_NOTIFY_INTERRUPT (1 << 26) |
| 3077 | #define GT_BSD_USER_INTERRUPT (1 << 5) | 3254 | #define GT_GEN6_BLT_CS_ERROR_INTERRUPT (1 << 25) |
| 3078 | #define GT_GEN6_BSD_USER_INTERRUPT (1 << 12) | 3255 | #define GT_GEN6_BLT_USER_INTERRUPT (1 << 22) |
| 3079 | #define GT_BLT_USER_INTERRUPT (1 << 22) | 3256 | #define GT_GEN6_BSD_CS_ERROR_INTERRUPT (1 << 15) |
| 3257 | #define GT_GEN6_BSD_USER_INTERRUPT (1 << 12) | ||
| 3258 | #define GT_BSD_USER_INTERRUPT (1 << 5) /* ilk only */ | ||
| 3259 | #define GT_GEN7_L3_PARITY_ERROR_INTERRUPT (1 << 5) | ||
| 3260 | #define GT_PIPE_NOTIFY (1 << 4) | ||
| 3261 | #define GT_RENDER_CS_ERROR_INTERRUPT (1 << 3) | ||
| 3262 | #define GT_SYNC_STATUS (1 << 2) | ||
| 3263 | #define GT_USER_INTERRUPT (1 << 0) | ||
| 3080 | 3264 | ||
| 3081 | #define GTISR 0x44010 | 3265 | #define GTISR 0x44010 |
| 3082 | #define GTIMR 0x44014 | 3266 | #define GTIMR 0x44014 |
| @@ -3226,15 +3410,15 @@ | |||
| 3226 | 3410 | ||
| 3227 | #define _PCH_DPLL_A 0xc6014 | 3411 | #define _PCH_DPLL_A 0xc6014 |
| 3228 | #define _PCH_DPLL_B 0xc6018 | 3412 | #define _PCH_DPLL_B 0xc6018 |
| 3229 | #define PCH_DPLL(pipe) (pipe == 0 ? _PCH_DPLL_A : _PCH_DPLL_B) | 3413 | #define _PCH_DPLL(pll) (pll == 0 ? _PCH_DPLL_A : _PCH_DPLL_B) |
| 3230 | 3414 | ||
| 3231 | #define _PCH_FPA0 0xc6040 | 3415 | #define _PCH_FPA0 0xc6040 |
| 3232 | #define FP_CB_TUNE (0x3<<22) | 3416 | #define FP_CB_TUNE (0x3<<22) |
| 3233 | #define _PCH_FPA1 0xc6044 | 3417 | #define _PCH_FPA1 0xc6044 |
| 3234 | #define _PCH_FPB0 0xc6048 | 3418 | #define _PCH_FPB0 0xc6048 |
| 3235 | #define _PCH_FPB1 0xc604c | 3419 | #define _PCH_FPB1 0xc604c |
| 3236 | #define PCH_FP0(pipe) (pipe == 0 ? _PCH_FPA0 : _PCH_FPB0) | 3420 | #define _PCH_FP0(pll) (pll == 0 ? _PCH_FPA0 : _PCH_FPB0) |
| 3237 | #define PCH_FP1(pipe) (pipe == 0 ? _PCH_FPA1 : _PCH_FPB1) | 3421 | #define _PCH_FP1(pll) (pll == 0 ? _PCH_FPA1 : _PCH_FPB1) |
| 3238 | 3422 | ||
| 3239 | #define PCH_DPLL_TEST 0xc606c | 3423 | #define PCH_DPLL_TEST 0xc606c |
| 3240 | 3424 | ||
| @@ -3329,6 +3513,57 @@ | |||
| 3329 | #define TVIDEO_DIP_DATA(pipe) _PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B) | 3513 | #define TVIDEO_DIP_DATA(pipe) _PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B) |
| 3330 | #define TVIDEO_DIP_GCP(pipe) _PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B) | 3514 | #define TVIDEO_DIP_GCP(pipe) _PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B) |
| 3331 | 3515 | ||
| 3516 | #define VLV_VIDEO_DIP_CTL_A 0x60220 | ||
| 3517 | #define VLV_VIDEO_DIP_DATA_A 0x60208 | ||
| 3518 | #define VLV_VIDEO_DIP_GDCP_PAYLOAD_A 0x60210 | ||
| 3519 | |||
| 3520 | #define VLV_VIDEO_DIP_CTL_B 0x61170 | ||
| 3521 | #define VLV_VIDEO_DIP_DATA_B 0x61174 | ||
| 3522 | #define VLV_VIDEO_DIP_GDCP_PAYLOAD_B 0x61178 | ||
| 3523 | |||
| 3524 | #define VLV_TVIDEO_DIP_CTL(pipe) \ | ||
| 3525 | _PIPE(pipe, VLV_VIDEO_DIP_CTL_A, VLV_VIDEO_DIP_CTL_B) | ||
| 3526 | #define VLV_TVIDEO_DIP_DATA(pipe) \ | ||
| 3527 | _PIPE(pipe, VLV_VIDEO_DIP_DATA_A, VLV_VIDEO_DIP_DATA_B) | ||
| 3528 | #define VLV_TVIDEO_DIP_GCP(pipe) \ | ||
| 3529 | _PIPE(pipe, VLV_VIDEO_DIP_GDCP_PAYLOAD_A, VLV_VIDEO_DIP_GDCP_PAYLOAD_B) | ||
| 3530 | |||
| 3531 | /* Haswell DIP controls */ | ||
| 3532 | #define HSW_VIDEO_DIP_CTL_A 0x60200 | ||
| 3533 | #define HSW_VIDEO_DIP_AVI_DATA_A 0x60220 | ||
| 3534 | #define HSW_VIDEO_DIP_VS_DATA_A 0x60260 | ||
| 3535 | #define HSW_VIDEO_DIP_SPD_DATA_A 0x602A0 | ||
| 3536 | #define HSW_VIDEO_DIP_GMP_DATA_A 0x602E0 | ||
| 3537 | #define HSW_VIDEO_DIP_VSC_DATA_A 0x60320 | ||
| 3538 | #define HSW_VIDEO_DIP_AVI_ECC_A 0x60240 | ||
| 3539 | #define HSW_VIDEO_DIP_VS_ECC_A 0x60280 | ||
| 3540 | #define HSW_VIDEO_DIP_SPD_ECC_A 0x602C0 | ||
| 3541 | #define HSW_VIDEO_DIP_GMP_ECC_A 0x60300 | ||
| 3542 | #define HSW_VIDEO_DIP_VSC_ECC_A 0x60344 | ||
| 3543 | #define HSW_VIDEO_DIP_GCP_A 0x60210 | ||
| 3544 | |||
| 3545 | #define HSW_VIDEO_DIP_CTL_B 0x61200 | ||
| 3546 | #define HSW_VIDEO_DIP_AVI_DATA_B 0x61220 | ||
| 3547 | #define HSW_VIDEO_DIP_VS_DATA_B 0x61260 | ||
| 3548 | #define HSW_VIDEO_DIP_SPD_DATA_B 0x612A0 | ||
| 3549 | #define HSW_VIDEO_DIP_GMP_DATA_B 0x612E0 | ||
| 3550 | #define HSW_VIDEO_DIP_VSC_DATA_B 0x61320 | ||
| 3551 | #define HSW_VIDEO_DIP_BVI_ECC_B 0x61240 | ||
| 3552 | #define HSW_VIDEO_DIP_VS_ECC_B 0x61280 | ||
| 3553 | #define HSW_VIDEO_DIP_SPD_ECC_B 0x612C0 | ||
| 3554 | #define HSW_VIDEO_DIP_GMP_ECC_B 0x61300 | ||
| 3555 | #define HSW_VIDEO_DIP_VSC_ECC_B 0x61344 | ||
| 3556 | #define HSW_VIDEO_DIP_GCP_B 0x61210 | ||
| 3557 | |||
| 3558 | #define HSW_TVIDEO_DIP_CTL(pipe) \ | ||
| 3559 | _PIPE(pipe, HSW_VIDEO_DIP_CTL_A, HSW_VIDEO_DIP_CTL_B) | ||
| 3560 | #define HSW_TVIDEO_DIP_AVI_DATA(pipe) \ | ||
| 3561 | _PIPE(pipe, HSW_VIDEO_DIP_AVI_DATA_A, HSW_VIDEO_DIP_AVI_DATA_B) | ||
| 3562 | #define HSW_TVIDEO_DIP_SPD_DATA(pipe) \ | ||
| 3563 | _PIPE(pipe, HSW_VIDEO_DIP_SPD_DATA_A, HSW_VIDEO_DIP_SPD_DATA_B) | ||
| 3564 | #define HSW_TVIDEO_DIP_GCP(pipe) \ | ||
| 3565 | _PIPE(pipe, HSW_VIDEO_DIP_GCP_A, HSW_VIDEO_DIP_GCP_B) | ||
| 3566 | |||
| 3332 | #define _TRANS_HTOTAL_B 0xe1000 | 3567 | #define _TRANS_HTOTAL_B 0xe1000 |
| 3333 | #define _TRANS_HBLANK_B 0xe1004 | 3568 | #define _TRANS_HBLANK_B 0xe1004 |
| 3334 | #define _TRANS_HSYNC_B 0xe1008 | 3569 | #define _TRANS_HSYNC_B 0xe1008 |
| @@ -3489,6 +3724,9 @@ | |||
| 3489 | #define FDI_LINK_TRAIN_PATTERN_IDLE_CPT (2<<8) | 3724 | #define FDI_LINK_TRAIN_PATTERN_IDLE_CPT (2<<8) |
| 3490 | #define FDI_LINK_TRAIN_NORMAL_CPT (3<<8) | 3725 | #define FDI_LINK_TRAIN_NORMAL_CPT (3<<8) |
| 3491 | #define FDI_LINK_TRAIN_PATTERN_MASK_CPT (3<<8) | 3726 | #define FDI_LINK_TRAIN_PATTERN_MASK_CPT (3<<8) |
| 3727 | /* LPT */ | ||
| 3728 | #define FDI_PORT_WIDTH_2X_LPT (1<<19) | ||
| 3729 | #define FDI_PORT_WIDTH_1X_LPT (0<<19) | ||
| 3492 | 3730 | ||
| 3493 | #define _FDI_RXA_MISC 0xf0010 | 3731 | #define _FDI_RXA_MISC 0xf0010 |
| 3494 | #define _FDI_RXB_MISC 0xf1010 | 3732 | #define _FDI_RXB_MISC 0xf1010 |
| @@ -3549,6 +3787,7 @@ | |||
| 3549 | #define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1<<16) | 3787 | #define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1<<16) |
| 3550 | 3788 | ||
| 3551 | /* or SDVOB */ | 3789 | /* or SDVOB */ |
| 3790 | #define VLV_HDMIB 0x61140 | ||
| 3552 | #define HDMIB 0xe1140 | 3791 | #define HDMIB 0xe1140 |
| 3553 | #define PORT_ENABLE (1 << 31) | 3792 | #define PORT_ENABLE (1 << 31) |
| 3554 | #define TRANSCODER(pipe) ((pipe) << 30) | 3793 | #define TRANSCODER(pipe) ((pipe) << 30) |
| @@ -3714,6 +3953,8 @@ | |||
| 3714 | #define EDP_LINK_TRAIN_VOL_EMP_MASK_IVB (0x3f<<22) | 3953 | #define EDP_LINK_TRAIN_VOL_EMP_MASK_IVB (0x3f<<22) |
| 3715 | 3954 | ||
| 3716 | #define FORCEWAKE 0xA18C | 3955 | #define FORCEWAKE 0xA18C |
| 3956 | #define FORCEWAKE_VLV 0x1300b0 | ||
| 3957 | #define FORCEWAKE_ACK_VLV 0x1300b4 | ||
| 3717 | #define FORCEWAKE_ACK 0x130090 | 3958 | #define FORCEWAKE_ACK 0x130090 |
| 3718 | #define FORCEWAKE_MT 0xa188 /* multi-threaded */ | 3959 | #define FORCEWAKE_MT 0xa188 /* multi-threaded */ |
| 3719 | #define FORCEWAKE_MT_ACK 0x130040 | 3960 | #define FORCEWAKE_MT_ACK 0x130040 |
| @@ -3731,6 +3972,7 @@ | |||
| 3731 | 3972 | ||
| 3732 | #define GEN6_UCGCTL1 0x9400 | 3973 | #define GEN6_UCGCTL1 0x9400 |
| 3733 | # define GEN6_BLBUNIT_CLOCK_GATE_DISABLE (1 << 5) | 3974 | # define GEN6_BLBUNIT_CLOCK_GATE_DISABLE (1 << 5) |
| 3975 | # define GEN6_CSUNIT_CLOCK_GATE_DISABLE (1 << 7) | ||
| 3734 | 3976 | ||
| 3735 | #define GEN6_UCGCTL2 0x9404 | 3977 | #define GEN6_UCGCTL2 0x9404 |
| 3736 | # define GEN6_RCZUNIT_CLOCK_GATE_DISABLE (1 << 13) | 3978 | # define GEN6_RCZUNIT_CLOCK_GATE_DISABLE (1 << 13) |
| @@ -3811,6 +4053,11 @@ | |||
| 3811 | GEN6_PM_RP_DOWN_THRESHOLD | \ | 4053 | GEN6_PM_RP_DOWN_THRESHOLD | \ |
| 3812 | GEN6_PM_RP_DOWN_TIMEOUT) | 4054 | GEN6_PM_RP_DOWN_TIMEOUT) |
| 3813 | 4055 | ||
| 4056 | #define GEN6_GT_GFX_RC6_LOCKED 0x138104 | ||
| 4057 | #define GEN6_GT_GFX_RC6 0x138108 | ||
| 4058 | #define GEN6_GT_GFX_RC6p 0x13810C | ||
| 4059 | #define GEN6_GT_GFX_RC6pp 0x138110 | ||
| 4060 | |||
| 3814 | #define GEN6_PCODE_MAILBOX 0x138124 | 4061 | #define GEN6_PCODE_MAILBOX 0x138124 |
| 3815 | #define GEN6_PCODE_READY (1<<31) | 4062 | #define GEN6_PCODE_READY (1<<31) |
| 3816 | #define GEN6_READ_OC_PARAMS 0xc | 4063 | #define GEN6_READ_OC_PARAMS 0xc |
| @@ -3870,4 +4117,197 @@ | |||
| 3870 | #define AUD_CONFIG_PIXEL_CLOCK_HDMI (0xf << 16) | 4117 | #define AUD_CONFIG_PIXEL_CLOCK_HDMI (0xf << 16) |
| 3871 | #define AUD_CONFIG_DISABLE_NCTS (1 << 3) | 4118 | #define AUD_CONFIG_DISABLE_NCTS (1 << 3) |
| 3872 | 4119 | ||
| 4120 | /* HSW Power Wells */ | ||
| 4121 | #define HSW_PWR_WELL_CTL1 0x45400 /* BIOS */ | ||
| 4122 | #define HSW_PWR_WELL_CTL2 0x45404 /* Driver */ | ||
| 4123 | #define HSW_PWR_WELL_CTL3 0x45408 /* KVMR */ | ||
| 4124 | #define HSW_PWR_WELL_CTL4 0x4540C /* Debug */ | ||
| 4125 | #define HSW_PWR_WELL_ENABLE (1<<31) | ||
| 4126 | #define HSW_PWR_WELL_STATE (1<<30) | ||
| 4127 | #define HSW_PWR_WELL_CTL5 0x45410 | ||
| 4128 | #define HSW_PWR_WELL_ENABLE_SINGLE_STEP (1<<31) | ||
| 4129 | #define HSW_PWR_WELL_PWR_GATE_OVERRIDE (1<<20) | ||
| 4130 | #define HSW_PWR_WELL_FORCE_ON (1<<19) | ||
| 4131 | #define HSW_PWR_WELL_CTL6 0x45414 | ||
| 4132 | |||
| 4133 | /* Per-pipe DDI Function Control */ | ||
| 4134 | #define PIPE_DDI_FUNC_CTL_A 0x60400 | ||
| 4135 | #define PIPE_DDI_FUNC_CTL_B 0x61400 | ||
| 4136 | #define PIPE_DDI_FUNC_CTL_C 0x62400 | ||
| 4137 | #define PIPE_DDI_FUNC_CTL_EDP 0x6F400 | ||
| 4138 | #define DDI_FUNC_CTL(pipe) _PIPE(pipe, \ | ||
| 4139 | PIPE_DDI_FUNC_CTL_A, \ | ||
| 4140 | PIPE_DDI_FUNC_CTL_B) | ||
| 4141 | #define PIPE_DDI_FUNC_ENABLE (1<<31) | ||
| 4142 | /* Those bits are ignored by pipe EDP since it can only connect to DDI A */ | ||
| 4143 | #define PIPE_DDI_PORT_MASK (0xf<<28) | ||
| 4144 | #define PIPE_DDI_SELECT_PORT(x) ((x)<<28) | ||
| 4145 | #define PIPE_DDI_MODE_SELECT_HDMI (0<<24) | ||
| 4146 | #define PIPE_DDI_MODE_SELECT_DVI (1<<24) | ||
| 4147 | #define PIPE_DDI_MODE_SELECT_DP_SST (2<<24) | ||
| 4148 | #define PIPE_DDI_MODE_SELECT_DP_MST (3<<24) | ||
| 4149 | #define PIPE_DDI_MODE_SELECT_FDI (4<<24) | ||
| 4150 | #define PIPE_DDI_BPC_8 (0<<20) | ||
| 4151 | #define PIPE_DDI_BPC_10 (1<<20) | ||
| 4152 | #define PIPE_DDI_BPC_6 (2<<20) | ||
| 4153 | #define PIPE_DDI_BPC_12 (3<<20) | ||
| 4154 | #define PIPE_DDI_BFI_ENABLE (1<<4) | ||
| 4155 | #define PIPE_DDI_PORT_WIDTH_X1 (0<<1) | ||
| 4156 | #define PIPE_DDI_PORT_WIDTH_X2 (1<<1) | ||
| 4157 | #define PIPE_DDI_PORT_WIDTH_X4 (3<<1) | ||
| 4158 | |||
| 4159 | /* DisplayPort Transport Control */ | ||
| 4160 | #define DP_TP_CTL_A 0x64040 | ||
| 4161 | #define DP_TP_CTL_B 0x64140 | ||
| 4162 | #define DP_TP_CTL(port) _PORT(port, \ | ||
| 4163 | DP_TP_CTL_A, \ | ||
| 4164 | DP_TP_CTL_B) | ||
| 4165 | #define DP_TP_CTL_ENABLE (1<<31) | ||
| 4166 | #define DP_TP_CTL_MODE_SST (0<<27) | ||
| 4167 | #define DP_TP_CTL_MODE_MST (1<<27) | ||
| 4168 | #define DP_TP_CTL_ENHANCED_FRAME_ENABLE (1<<18) | ||
| 4169 | #define DP_TP_CTL_FDI_AUTOTRAIN (1<<15) | ||
| 4170 | #define DP_TP_CTL_LINK_TRAIN_MASK (7<<8) | ||
| 4171 | #define DP_TP_CTL_LINK_TRAIN_PAT1 (0<<8) | ||
| 4172 | #define DP_TP_CTL_LINK_TRAIN_PAT2 (1<<8) | ||
| 4173 | #define DP_TP_CTL_LINK_TRAIN_NORMAL (3<<8) | ||
| 4174 | |||
| 4175 | /* DisplayPort Transport Status */ | ||
| 4176 | #define DP_TP_STATUS_A 0x64044 | ||
| 4177 | #define DP_TP_STATUS_B 0x64144 | ||
| 4178 | #define DP_TP_STATUS(port) _PORT(port, \ | ||
| 4179 | DP_TP_STATUS_A, \ | ||
| 4180 | DP_TP_STATUS_B) | ||
| 4181 | #define DP_TP_STATUS_AUTOTRAIN_DONE (1<<12) | ||
| 4182 | |||
| 4183 | /* DDI Buffer Control */ | ||
| 4184 | #define DDI_BUF_CTL_A 0x64000 | ||
| 4185 | #define DDI_BUF_CTL_B 0x64100 | ||
| 4186 | #define DDI_BUF_CTL(port) _PORT(port, \ | ||
| 4187 | DDI_BUF_CTL_A, \ | ||
| 4188 | DDI_BUF_CTL_B) | ||
| 4189 | #define DDI_BUF_CTL_ENABLE (1<<31) | ||
| 4190 | #define DDI_BUF_EMP_400MV_0DB_HSW (0<<24) /* Sel0 */ | ||
| 4191 | #define DDI_BUF_EMP_400MV_3_5DB_HSW (1<<24) /* Sel1 */ | ||
| 4192 | #define DDI_BUF_EMP_400MV_6DB_HSW (2<<24) /* Sel2 */ | ||
| 4193 | #define DDI_BUF_EMP_400MV_9_5DB_HSW (3<<24) /* Sel3 */ | ||
| 4194 | #define DDI_BUF_EMP_600MV_0DB_HSW (4<<24) /* Sel4 */ | ||
| 4195 | #define DDI_BUF_EMP_600MV_3_5DB_HSW (5<<24) /* Sel5 */ | ||
| 4196 | #define DDI_BUF_EMP_600MV_6DB_HSW (6<<24) /* Sel6 */ | ||
| 4197 | #define DDI_BUF_EMP_800MV_0DB_HSW (7<<24) /* Sel7 */ | ||
| 4198 | #define DDI_BUF_EMP_800MV_3_5DB_HSW (8<<24) /* Sel8 */ | ||
| 4199 | #define DDI_BUF_EMP_MASK (0xf<<24) | ||
| 4200 | #define DDI_BUF_IS_IDLE (1<<7) | ||
| 4201 | #define DDI_PORT_WIDTH_X1 (0<<1) | ||
| 4202 | #define DDI_PORT_WIDTH_X2 (1<<1) | ||
| 4203 | #define DDI_PORT_WIDTH_X4 (3<<1) | ||
| 4204 | #define DDI_INIT_DISPLAY_DETECTED (1<<0) | ||
| 4205 | |||
| 4206 | /* DDI Buffer Translations */ | ||
| 4207 | #define DDI_BUF_TRANS_A 0x64E00 | ||
| 4208 | #define DDI_BUF_TRANS_B 0x64E60 | ||
| 4209 | #define DDI_BUF_TRANS(port) _PORT(port, \ | ||
| 4210 | DDI_BUF_TRANS_A, \ | ||
| 4211 | DDI_BUF_TRANS_B) | ||
| 4212 | |||
| 4213 | /* Sideband Interface (SBI) is programmed indirectly, via | ||
| 4214 | * SBI_ADDR, which contains the register offset; and SBI_DATA, | ||
| 4215 | * which contains the payload */ | ||
| 4216 | #define SBI_ADDR 0xC6000 | ||
| 4217 | #define SBI_DATA 0xC6004 | ||
| 4218 | #define SBI_CTL_STAT 0xC6008 | ||
| 4219 | #define SBI_CTL_OP_CRRD (0x6<<8) | ||
| 4220 | #define SBI_CTL_OP_CRWR (0x7<<8) | ||
| 4221 | #define SBI_RESPONSE_FAIL (0x1<<1) | ||
| 4222 | #define SBI_RESPONSE_SUCCESS (0x0<<1) | ||
| 4223 | #define SBI_BUSY (0x1<<0) | ||
| 4224 | #define SBI_READY (0x0<<0) | ||
| 4225 | |||
| 4226 | /* SBI offsets */ | ||
| 4227 | #define SBI_SSCDIVINTPHASE6 0x0600 | ||
| 4228 | #define SBI_SSCDIVINTPHASE_DIVSEL_MASK ((0x7f)<<1) | ||
| 4229 | #define SBI_SSCDIVINTPHASE_DIVSEL(x) ((x)<<1) | ||
| 4230 | #define SBI_SSCDIVINTPHASE_INCVAL_MASK ((0x7f)<<8) | ||
| 4231 | #define SBI_SSCDIVINTPHASE_INCVAL(x) ((x)<<8) | ||
| 4232 | #define SBI_SSCDIVINTPHASE_DIR(x) ((x)<<15) | ||
| 4233 | #define SBI_SSCDIVINTPHASE_PROPAGATE (1<<0) | ||
| 4234 | #define SBI_SSCCTL 0x020c | ||
| 4235 | #define SBI_SSCCTL6 0x060C | ||
| 4236 | #define SBI_SSCCTL_DISABLE (1<<0) | ||
| 4237 | #define SBI_SSCAUXDIV6 0x0610 | ||
| 4238 | #define SBI_SSCAUXDIV_FINALDIV2SEL(x) ((x)<<4) | ||
| 4239 | #define SBI_DBUFF0 0x2a00 | ||
| 4240 | |||
| 4241 | /* LPT PIXCLK_GATE */ | ||
| 4242 | #define PIXCLK_GATE 0xC6020 | ||
| 4243 | #define PIXCLK_GATE_UNGATE 1<<0 | ||
| 4244 | #define PIXCLK_GATE_GATE 0<<0 | ||
| 4245 | |||
| 4246 | /* SPLL */ | ||
| 4247 | #define SPLL_CTL 0x46020 | ||
| 4248 | #define SPLL_PLL_ENABLE (1<<31) | ||
| 4249 | #define SPLL_PLL_SCC (1<<28) | ||
| 4250 | #define SPLL_PLL_NON_SCC (2<<28) | ||
| 4251 | #define SPLL_PLL_FREQ_810MHz (0<<26) | ||
| 4252 | #define SPLL_PLL_FREQ_1350MHz (1<<26) | ||
| 4253 | |||
| 4254 | /* WRPLL */ | ||
| 4255 | #define WRPLL_CTL1 0x46040 | ||
| 4256 | #define WRPLL_CTL2 0x46060 | ||
| 4257 | #define WRPLL_PLL_ENABLE (1<<31) | ||
| 4258 | #define WRPLL_PLL_SELECT_SSC (0x01<<28) | ||
| 4259 | #define WRPLL_PLL_SELECT_NON_SCC (0x02<<28) | ||
| 4260 | #define WRPLL_PLL_SELECT_LCPLL_2700 (0x03<<28) | ||
| 4261 | /* WRPLL divider programming */ | ||
| 4262 | #define WRPLL_DIVIDER_REFERENCE(x) ((x)<<0) | ||
| 4263 | #define WRPLL_DIVIDER_POST(x) ((x)<<8) | ||
| 4264 | #define WRPLL_DIVIDER_FEEDBACK(x) ((x)<<16) | ||
| 4265 | |||
| 4266 | /* Port clock selection */ | ||
| 4267 | #define PORT_CLK_SEL_A 0x46100 | ||
| 4268 | #define PORT_CLK_SEL_B 0x46104 | ||
| 4269 | #define PORT_CLK_SEL(port) _PORT(port, \ | ||
| 4270 | PORT_CLK_SEL_A, \ | ||
| 4271 | PORT_CLK_SEL_B) | ||
| 4272 | #define PORT_CLK_SEL_LCPLL_2700 (0<<29) | ||
| 4273 | #define PORT_CLK_SEL_LCPLL_1350 (1<<29) | ||
| 4274 | #define PORT_CLK_SEL_LCPLL_810 (2<<29) | ||
| 4275 | #define PORT_CLK_SEL_SPLL (3<<29) | ||
| 4276 | #define PORT_CLK_SEL_WRPLL1 (4<<29) | ||
| 4277 | #define PORT_CLK_SEL_WRPLL2 (5<<29) | ||
| 4278 | |||
| 4279 | /* Pipe clock selection */ | ||
| 4280 | #define PIPE_CLK_SEL_A 0x46140 | ||
| 4281 | #define PIPE_CLK_SEL_B 0x46144 | ||
| 4282 | #define PIPE_CLK_SEL(pipe) _PIPE(pipe, \ | ||
| 4283 | PIPE_CLK_SEL_A, \ | ||
| 4284 | PIPE_CLK_SEL_B) | ||
| 4285 | /* For each pipe, we need to select the corresponding port clock */ | ||
| 4286 | #define PIPE_CLK_SEL_DISABLED (0x0<<29) | ||
| 4287 | #define PIPE_CLK_SEL_PORT(x) ((x+1)<<29) | ||
| 4288 | |||
| 4289 | /* LCPLL Control */ | ||
| 4290 | #define LCPLL_CTL 0x130040 | ||
| 4291 | #define LCPLL_PLL_DISABLE (1<<31) | ||
| 4292 | #define LCPLL_PLL_LOCK (1<<30) | ||
| 4293 | #define LCPLL_CD_CLOCK_DISABLE (1<<25) | ||
| 4294 | #define LCPLL_CD2X_CLOCK_DISABLE (1<<23) | ||
| 4295 | |||
| 4296 | /* Pipe WM_LINETIME - watermark line time */ | ||
| 4297 | #define PIPE_WM_LINETIME_A 0x45270 | ||
| 4298 | #define PIPE_WM_LINETIME_B 0x45274 | ||
| 4299 | #define PIPE_WM_LINETIME(pipe) _PIPE(pipe, \ | ||
| 4300 | PIPE_WM_LINETIME_A, \ | ||
| 4301 | PIPE_WM_LINETIME_A) | ||
| 4302 | #define PIPE_WM_LINETIME_MASK (0x1ff) | ||
| 4303 | #define PIPE_WM_LINETIME_TIME(x) ((x)) | ||
| 4304 | #define PIPE_WM_LINETIME_IPS_LINETIME_MASK (0x1ff<<16) | ||
| 4305 | #define PIPE_WM_LINETIME_IPS_LINETIME(x) ((x)<<16) | ||
| 4306 | |||
| 4307 | /* SFUSE_STRAP */ | ||
| 4308 | #define SFUSE_STRAP 0xc2014 | ||
| 4309 | #define SFUSE_STRAP_DDIB_DETECTED (1<<2) | ||
| 4310 | #define SFUSE_STRAP_DDIC_DETECTED (1<<1) | ||
| 4311 | #define SFUSE_STRAP_DDID_DETECTED (1<<0) | ||
| 4312 | |||
| 3873 | #endif /* _I915_REG_H_ */ | 4313 | #endif /* _I915_REG_H_ */ |