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-rw-r--r--drivers/cpufreq/Kconfig.arm6
-rw-r--r--drivers/cpufreq/Makefile2
-rw-r--r--drivers/cpufreq/sa1100-cpufreq.c247
-rw-r--r--drivers/cpufreq/sa1110-cpufreq.c406
4 files changed, 661 insertions, 0 deletions
diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm
index 97f208daf8ae..09da6a3f0e8f 100644
--- a/drivers/cpufreq/Kconfig.arm
+++ b/drivers/cpufreq/Kconfig.arm
@@ -127,6 +127,12 @@ config ARM_S5PV210_CPUFREQ
127 127
128 If in doubt, say N. 128 If in doubt, say N.
129 129
130config ARM_SA1100_CPUFREQ
131 bool
132
133config ARM_SA1110_CPUFREQ
134 bool
135
130config ARM_SPEAR_CPUFREQ 136config ARM_SPEAR_CPUFREQ
131 bool "SPEAr CPUFreq support" 137 bool "SPEAr CPUFreq support"
132 depends on PLAT_SPEAR 138 depends on PLAT_SPEAR
diff --git a/drivers/cpufreq/Makefile b/drivers/cpufreq/Makefile
index 8d5801645f9d..8b21016ac157 100644
--- a/drivers/cpufreq/Makefile
+++ b/drivers/cpufreq/Makefile
@@ -66,6 +66,8 @@ obj-$(CONFIG_PXA3xx) += pxa3xx-cpufreq.o
66obj-$(CONFIG_ARM_S3C2416_CPUFREQ) += s3c2416-cpufreq.o 66obj-$(CONFIG_ARM_S3C2416_CPUFREQ) += s3c2416-cpufreq.o
67obj-$(CONFIG_ARM_S3C64XX_CPUFREQ) += s3c64xx-cpufreq.o 67obj-$(CONFIG_ARM_S3C64XX_CPUFREQ) += s3c64xx-cpufreq.o
68obj-$(CONFIG_ARM_S5PV210_CPUFREQ) += s5pv210-cpufreq.o 68obj-$(CONFIG_ARM_S5PV210_CPUFREQ) += s5pv210-cpufreq.o
69obj-$(CONFIG_ARM_SA1100_CPUFREQ) += sa1100-cpufreq.o
70obj-$(CONFIG_ARM_SA1110_CPUFREQ) += sa1110-cpufreq.o
69obj-$(CONFIG_ARM_SPEAR_CPUFREQ) += spear-cpufreq.o 71obj-$(CONFIG_ARM_SPEAR_CPUFREQ) += spear-cpufreq.o
70obj-$(CONFIG_ARCH_TEGRA) += tegra-cpufreq.o 72obj-$(CONFIG_ARCH_TEGRA) += tegra-cpufreq.o
71 73
diff --git a/drivers/cpufreq/sa1100-cpufreq.c b/drivers/cpufreq/sa1100-cpufreq.c
new file mode 100644
index 000000000000..cff18e87ca58
--- /dev/null
+++ b/drivers/cpufreq/sa1100-cpufreq.c
@@ -0,0 +1,247 @@
1/*
2 * cpu-sa1100.c: clock scaling for the SA1100
3 *
4 * Copyright (C) 2000 2001, The Delft University of Technology
5 *
6 * Authors:
7 * - Johan Pouwelse (J.A.Pouwelse@its.tudelft.nl): initial version
8 * - Erik Mouw (J.A.K.Mouw@its.tudelft.nl):
9 * - major rewrite for linux-2.3.99
10 * - rewritten for the more generic power management scheme in
11 * linux-2.4.5-rmk1
12 *
13 * This software has been developed while working on the LART
14 * computing board (http://www.lartmaker.nl/), which is
15 * sponsored by the Mobile Multi-media Communications
16 * (http://www.mobimedia.org/) and Ubiquitous Communications
17 * (http://www.ubicom.tudelft.nl/) projects.
18 *
19 * The authors can be reached at:
20 *
21 * Erik Mouw
22 * Information and Communication Theory Group
23 * Faculty of Information Technology and Systems
24 * Delft University of Technology
25 * P.O. Box 5031
26 * 2600 GA Delft
27 * The Netherlands
28 *
29 *
30 * This program is free software; you can redistribute it and/or modify
31 * it under the terms of the GNU General Public License as published by
32 * the Free Software Foundation; either version 2 of the License, or
33 * (at your option) any later version.
34 *
35 * This program is distributed in the hope that it will be useful,
36 * but WITHOUT ANY WARRANTY; without even the implied warranty of
37 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
38 * GNU General Public License for more details.
39 *
40 * You should have received a copy of the GNU General Public License
41 * along with this program; if not, write to the Free Software
42 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
43 *
44 *
45 * Theory of operations
46 * ====================
47 *
48 * Clock scaling can be used to lower the power consumption of the CPU
49 * core. This will give you a somewhat longer running time.
50 *
51 * The SA-1100 has a single register to change the core clock speed:
52 *
53 * PPCR 0x90020014 PLL config
54 *
55 * However, the DRAM timings are closely related to the core clock
56 * speed, so we need to change these, too. The used registers are:
57 *
58 * MDCNFG 0xA0000000 DRAM config
59 * MDCAS0 0xA0000004 Access waveform
60 * MDCAS1 0xA0000008 Access waveform
61 * MDCAS2 0xA000000C Access waveform
62 *
63 * Care must be taken to change the DRAM parameters the correct way,
64 * because otherwise the DRAM becomes unusable and the kernel will
65 * crash.
66 *
67 * The simple solution to avoid a kernel crash is to put the actual
68 * clock change in ROM and jump to that code from the kernel. The main
69 * disadvantage is that the ROM has to be modified, which is not
70 * possible on all SA-1100 platforms. Another disadvantage is that
71 * jumping to ROM makes clock switching unnecessary complicated.
72 *
73 * The idea behind this driver is that the memory configuration can be
74 * changed while running from DRAM (even with interrupts turned on!)
75 * as long as all re-configuration steps yield a valid DRAM
76 * configuration. The advantages are clear: it will run on all SA-1100
77 * platforms, and the code is very simple.
78 *
79 * If you really want to understand what is going on in
80 * sa1100_update_dram_timings(), you'll have to read sections 8.2,
81 * 9.5.7.3, and 10.2 from the "Intel StrongARM SA-1100 Microprocessor
82 * Developers Manual" (available for free from Intel).
83 *
84 */
85
86#include <linux/kernel.h>
87#include <linux/types.h>
88#include <linux/init.h>
89#include <linux/cpufreq.h>
90#include <linux/io.h>
91
92#include <asm/cputype.h>
93
94#include <mach/generic.h>
95#include <mach/hardware.h>
96
97struct sa1100_dram_regs {
98 int speed;
99 u32 mdcnfg;
100 u32 mdcas0;
101 u32 mdcas1;
102 u32 mdcas2;
103};
104
105
106static struct cpufreq_driver sa1100_driver;
107
108static struct sa1100_dram_regs sa1100_dram_settings[] = {
109 /*speed, mdcnfg, mdcas0, mdcas1, mdcas2, clock freq */
110 { 59000, 0x00dc88a3, 0xcccccccf, 0xfffffffc, 0xffffffff},/* 59.0 MHz */
111 { 73700, 0x011490a3, 0xcccccccf, 0xfffffffc, 0xffffffff},/* 73.7 MHz */
112 { 88500, 0x014e90a3, 0xcccccccf, 0xfffffffc, 0xffffffff},/* 88.5 MHz */
113 {103200, 0x01889923, 0xcccccccf, 0xfffffffc, 0xffffffff},/* 103.2 MHz */
114 {118000, 0x01c29923, 0x9999998f, 0xfffffff9, 0xffffffff},/* 118.0 MHz */
115 {132700, 0x01fb2123, 0x9999998f, 0xfffffff9, 0xffffffff},/* 132.7 MHz */
116 {147500, 0x02352123, 0x3333330f, 0xfffffff3, 0xffffffff},/* 147.5 MHz */
117 {162200, 0x026b29a3, 0x38e38e1f, 0xfff8e38e, 0xffffffff},/* 162.2 MHz */
118 {176900, 0x02a329a3, 0x71c71c1f, 0xfff1c71c, 0xffffffff},/* 176.9 MHz */
119 {191700, 0x02dd31a3, 0xe38e383f, 0xffe38e38, 0xffffffff},/* 191.7 MHz */
120 {206400, 0x03153223, 0xc71c703f, 0xffc71c71, 0xffffffff},/* 206.4 MHz */
121 {221200, 0x034fba23, 0xc71c703f, 0xffc71c71, 0xffffffff},/* 221.2 MHz */
122 {235900, 0x03853a23, 0xe1e1e07f, 0xe1e1e1e1, 0xffffffe1},/* 235.9 MHz */
123 {250700, 0x03bf3aa3, 0xc3c3c07f, 0xc3c3c3c3, 0xffffffc3},/* 250.7 MHz */
124 {265400, 0x03f7c2a3, 0xc3c3c07f, 0xc3c3c3c3, 0xffffffc3},/* 265.4 MHz */
125 {280200, 0x0431c2a3, 0x878780ff, 0x87878787, 0xffffff87},/* 280.2 MHz */
126 { 0, 0, 0, 0, 0 } /* last entry */
127};
128
129static void sa1100_update_dram_timings(int current_speed, int new_speed)
130{
131 struct sa1100_dram_regs *settings = sa1100_dram_settings;
132
133 /* find speed */
134 while (settings->speed != 0) {
135 if (new_speed == settings->speed)
136 break;
137
138 settings++;
139 }
140
141 if (settings->speed == 0) {
142 panic("%s: couldn't find dram setting for speed %d\n",
143 __func__, new_speed);
144 }
145
146 /* No risk, no fun: run with interrupts on! */
147 if (new_speed > current_speed) {
148 /* We're going FASTER, so first relax the memory
149 * timings before changing the core frequency
150 */
151
152 /* Half the memory access clock */
153 MDCNFG |= MDCNFG_CDB2;
154
155 /* The order of these statements IS important, keep 8
156 * pulses!!
157 */
158 MDCAS2 = settings->mdcas2;
159 MDCAS1 = settings->mdcas1;
160 MDCAS0 = settings->mdcas0;
161 MDCNFG = settings->mdcnfg;
162 } else {
163 /* We're going SLOWER: first decrease the core
164 * frequency and then tighten the memory settings.
165 */
166
167 /* Half the memory access clock */
168 MDCNFG |= MDCNFG_CDB2;
169
170 /* The order of these statements IS important, keep 8
171 * pulses!!
172 */
173 MDCAS0 = settings->mdcas0;
174 MDCAS1 = settings->mdcas1;
175 MDCAS2 = settings->mdcas2;
176 MDCNFG = settings->mdcnfg;
177 }
178}
179
180static int sa1100_target(struct cpufreq_policy *policy,
181 unsigned int target_freq,
182 unsigned int relation)
183{
184 unsigned int cur = sa11x0_getspeed(0);
185 unsigned int new_ppcr;
186 struct cpufreq_freqs freqs;
187
188 new_ppcr = sa11x0_freq_to_ppcr(target_freq);
189 switch (relation) {
190 case CPUFREQ_RELATION_L:
191 if (sa11x0_ppcr_to_freq(new_ppcr) > policy->max)
192 new_ppcr--;
193 break;
194 case CPUFREQ_RELATION_H:
195 if ((sa11x0_ppcr_to_freq(new_ppcr) > target_freq) &&
196 (sa11x0_ppcr_to_freq(new_ppcr - 1) >= policy->min))
197 new_ppcr--;
198 break;
199 }
200
201 freqs.old = cur;
202 freqs.new = sa11x0_ppcr_to_freq(new_ppcr);
203
204 cpufreq_notify_transition(policy, &freqs, CPUFREQ_PRECHANGE);
205
206 if (freqs.new > cur)
207 sa1100_update_dram_timings(cur, freqs.new);
208
209 PPCR = new_ppcr;
210
211 if (freqs.new < cur)
212 sa1100_update_dram_timings(cur, freqs.new);
213
214 cpufreq_notify_transition(policy, &freqs, CPUFREQ_POSTCHANGE);
215
216 return 0;
217}
218
219static int __init sa1100_cpu_init(struct cpufreq_policy *policy)
220{
221 if (policy->cpu != 0)
222 return -EINVAL;
223 policy->cur = policy->min = policy->max = sa11x0_getspeed(0);
224 policy->cpuinfo.min_freq = 59000;
225 policy->cpuinfo.max_freq = 287000;
226 policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;
227 return 0;
228}
229
230static struct cpufreq_driver sa1100_driver __refdata = {
231 .flags = CPUFREQ_STICKY,
232 .verify = sa11x0_verify_speed,
233 .target = sa1100_target,
234 .get = sa11x0_getspeed,
235 .init = sa1100_cpu_init,
236 .name = "sa1100",
237};
238
239static int __init sa1100_dram_init(void)
240{
241 if (cpu_is_sa1100())
242 return cpufreq_register_driver(&sa1100_driver);
243 else
244 return -ENODEV;
245}
246
247arch_initcall(sa1100_dram_init);
diff --git a/drivers/cpufreq/sa1110-cpufreq.c b/drivers/cpufreq/sa1110-cpufreq.c
new file mode 100644
index 000000000000..39c90b6f4286
--- /dev/null
+++ b/drivers/cpufreq/sa1110-cpufreq.c
@@ -0,0 +1,406 @@
1/*
2 * linux/arch/arm/mach-sa1100/cpu-sa1110.c
3 *
4 * Copyright (C) 2001 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * Note: there are two erratas that apply to the SA1110 here:
11 * 7 - SDRAM auto-power-up failure (rev A0)
12 * 13 - Corruption of internal register reads/writes following
13 * SDRAM reads (rev A0, B0, B1)
14 *
15 * We ignore rev. A0 and B0 devices; I don't think they're worth supporting.
16 *
17 * The SDRAM type can be passed on the command line as cpu_sa1110.sdram=type
18 */
19#include <linux/cpufreq.h>
20#include <linux/delay.h>
21#include <linux/init.h>
22#include <linux/io.h>
23#include <linux/kernel.h>
24#include <linux/moduleparam.h>
25#include <linux/types.h>
26
27#include <asm/cputype.h>
28#include <asm/mach-types.h>
29
30#include <mach/generic.h>
31#include <mach/hardware.h>
32
33#undef DEBUG
34
35struct sdram_params {
36 const char name[20];
37 u_char rows; /* bits */
38 u_char cas_latency; /* cycles */
39 u_char tck; /* clock cycle time (ns) */
40 u_char trcd; /* activate to r/w (ns) */
41 u_char trp; /* precharge to activate (ns) */
42 u_char twr; /* write recovery time (ns) */
43 u_short refresh; /* refresh time for array (us) */
44};
45
46struct sdram_info {
47 u_int mdcnfg;
48 u_int mdrefr;
49 u_int mdcas[3];
50};
51
52static struct sdram_params sdram_tbl[] __initdata = {
53 { /* Toshiba TC59SM716 CL2 */
54 .name = "TC59SM716-CL2",
55 .rows = 12,
56 .tck = 10,
57 .trcd = 20,
58 .trp = 20,
59 .twr = 10,
60 .refresh = 64000,
61 .cas_latency = 2,
62 }, { /* Toshiba TC59SM716 CL3 */
63 .name = "TC59SM716-CL3",
64 .rows = 12,
65 .tck = 8,
66 .trcd = 20,
67 .trp = 20,
68 .twr = 8,
69 .refresh = 64000,
70 .cas_latency = 3,
71 }, { /* Samsung K4S641632D TC75 */
72 .name = "K4S641632D",
73 .rows = 14,
74 .tck = 9,
75 .trcd = 27,
76 .trp = 20,
77 .twr = 9,
78 .refresh = 64000,
79 .cas_latency = 3,
80 }, { /* Samsung K4S281632B-1H */
81 .name = "K4S281632B-1H",
82 .rows = 12,
83 .tck = 10,
84 .trp = 20,
85 .twr = 10,
86 .refresh = 64000,
87 .cas_latency = 3,
88 }, { /* Samsung KM416S4030CT */
89 .name = "KM416S4030CT",
90 .rows = 13,
91 .tck = 8,
92 .trcd = 24, /* 3 CLKs */
93 .trp = 24, /* 3 CLKs */
94 .twr = 16, /* Trdl: 2 CLKs */
95 .refresh = 64000,
96 .cas_latency = 3,
97 }, { /* Winbond W982516AH75L CL3 */
98 .name = "W982516AH75L",
99 .rows = 16,
100 .tck = 8,
101 .trcd = 20,
102 .trp = 20,
103 .twr = 8,
104 .refresh = 64000,
105 .cas_latency = 3,
106 }, { /* Micron MT48LC8M16A2TG-75 */
107 .name = "MT48LC8M16A2TG-75",
108 .rows = 12,
109 .tck = 8,
110 .trcd = 20,
111 .trp = 20,
112 .twr = 8,
113 .refresh = 64000,
114 .cas_latency = 3,
115 },
116};
117
118static struct sdram_params sdram_params;
119
120/*
121 * Given a period in ns and frequency in khz, calculate the number of
122 * cycles of frequency in period. Note that we round up to the next
123 * cycle, even if we are only slightly over.
124 */
125static inline u_int ns_to_cycles(u_int ns, u_int khz)
126{
127 return (ns * khz + 999999) / 1000000;
128}
129
130/*
131 * Create the MDCAS register bit pattern.
132 */
133static inline void set_mdcas(u_int *mdcas, int delayed, u_int rcd)
134{
135 u_int shift;
136
137 rcd = 2 * rcd - 1;
138 shift = delayed + 1 + rcd;
139
140 mdcas[0] = (1 << rcd) - 1;
141 mdcas[0] |= 0x55555555 << shift;
142 mdcas[1] = mdcas[2] = 0x55555555 << (shift & 1);
143}
144
145static void
146sdram_calculate_timing(struct sdram_info *sd, u_int cpu_khz,
147 struct sdram_params *sdram)
148{
149 u_int mem_khz, sd_khz, trp, twr;
150
151 mem_khz = cpu_khz / 2;
152 sd_khz = mem_khz;
153
154 /*
155 * If SDCLK would invalidate the SDRAM timings,
156 * run SDCLK at half speed.
157 *
158 * CPU steppings prior to B2 must either run the memory at
159 * half speed or use delayed read latching (errata 13).
160 */
161 if ((ns_to_cycles(sdram->tck, sd_khz) > 1) ||
162 (CPU_REVISION < CPU_SA1110_B2 && sd_khz < 62000))
163 sd_khz /= 2;
164
165 sd->mdcnfg = MDCNFG & 0x007f007f;
166
167 twr = ns_to_cycles(sdram->twr, mem_khz);
168
169 /* trp should always be >1 */
170 trp = ns_to_cycles(sdram->trp, mem_khz) - 1;
171 if (trp < 1)
172 trp = 1;
173
174 sd->mdcnfg |= trp << 8;
175 sd->mdcnfg |= trp << 24;
176 sd->mdcnfg |= sdram->cas_latency << 12;
177 sd->mdcnfg |= sdram->cas_latency << 28;
178 sd->mdcnfg |= twr << 14;
179 sd->mdcnfg |= twr << 30;
180
181 sd->mdrefr = MDREFR & 0xffbffff0;
182 sd->mdrefr |= 7;
183
184 if (sd_khz != mem_khz)
185 sd->mdrefr |= MDREFR_K1DB2;
186
187 /* initial number of '1's in MDCAS + 1 */
188 set_mdcas(sd->mdcas, sd_khz >= 62000,
189 ns_to_cycles(sdram->trcd, mem_khz));
190
191#ifdef DEBUG
192 printk(KERN_DEBUG "MDCNFG: %08x MDREFR: %08x MDCAS0: %08x MDCAS1: %08x MDCAS2: %08x\n",
193 sd->mdcnfg, sd->mdrefr, sd->mdcas[0], sd->mdcas[1],
194 sd->mdcas[2]);
195#endif
196}
197
198/*
199 * Set the SDRAM refresh rate.
200 */
201static inline void sdram_set_refresh(u_int dri)
202{
203 MDREFR = (MDREFR & 0xffff000f) | (dri << 4);
204 (void) MDREFR;
205}
206
207/*
208 * Update the refresh period. We do this such that we always refresh
209 * the SDRAMs within their permissible period. The refresh period is
210 * always a multiple of the memory clock (fixed at cpu_clock / 2).
211 *
212 * FIXME: we don't currently take account of burst accesses here,
213 * but neither do Intels DM nor Angel.
214 */
215static void
216sdram_update_refresh(u_int cpu_khz, struct sdram_params *sdram)
217{
218 u_int ns_row = (sdram->refresh * 1000) >> sdram->rows;
219 u_int dri = ns_to_cycles(ns_row, cpu_khz / 2) / 32;
220
221#ifdef DEBUG
222 mdelay(250);
223 printk(KERN_DEBUG "new dri value = %d\n", dri);
224#endif
225
226 sdram_set_refresh(dri);
227}
228
229/*
230 * Ok, set the CPU frequency.
231 */
232static int sa1110_target(struct cpufreq_policy *policy,
233 unsigned int target_freq,
234 unsigned int relation)
235{
236 struct sdram_params *sdram = &sdram_params;
237 struct cpufreq_freqs freqs;
238 struct sdram_info sd;
239 unsigned long flags;
240 unsigned int ppcr, unused;
241
242 switch (relation) {
243 case CPUFREQ_RELATION_L:
244 ppcr = sa11x0_freq_to_ppcr(target_freq);
245 if (sa11x0_ppcr_to_freq(ppcr) > policy->max)
246 ppcr--;
247 break;
248 case CPUFREQ_RELATION_H:
249 ppcr = sa11x0_freq_to_ppcr(target_freq);
250 if (ppcr && (sa11x0_ppcr_to_freq(ppcr) > target_freq) &&
251 (sa11x0_ppcr_to_freq(ppcr-1) >= policy->min))
252 ppcr--;
253 break;
254 default:
255 return -EINVAL;
256 }
257
258 freqs.old = sa11x0_getspeed(0);
259 freqs.new = sa11x0_ppcr_to_freq(ppcr);
260
261 sdram_calculate_timing(&sd, freqs.new, sdram);
262
263#if 0
264 /*
265 * These values are wrong according to the SA1110 documentation
266 * and errata, but they seem to work. Need to get a storage
267 * scope on to the SDRAM signals to work out why.
268 */
269 if (policy->max < 147500) {
270 sd.mdrefr |= MDREFR_K1DB2;
271 sd.mdcas[0] = 0xaaaaaa7f;
272 } else {
273 sd.mdrefr &= ~MDREFR_K1DB2;
274 sd.mdcas[0] = 0xaaaaaa9f;
275 }
276 sd.mdcas[1] = 0xaaaaaaaa;
277 sd.mdcas[2] = 0xaaaaaaaa;
278#endif
279
280 cpufreq_notify_transition(policy, &freqs, CPUFREQ_PRECHANGE);
281
282 /*
283 * The clock could be going away for some time. Set the SDRAMs
284 * to refresh rapidly (every 64 memory clock cycles). To get
285 * through the whole array, we need to wait 262144 mclk cycles.
286 * We wait 20ms to be safe.
287 */
288 sdram_set_refresh(2);
289 if (!irqs_disabled())
290 msleep(20);
291 else
292 mdelay(20);
293
294 /*
295 * Reprogram the DRAM timings with interrupts disabled, and
296 * ensure that we are doing this within a complete cache line.
297 * This means that we won't access SDRAM for the duration of
298 * the programming.
299 */
300 local_irq_save(flags);
301 asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
302 udelay(10);
303 __asm__ __volatile__("\n\
304 b 2f \n\
305 .align 5 \n\
3061: str %3, [%1, #0] @ MDCNFG \n\
307 str %4, [%1, #28] @ MDREFR \n\
308 str %5, [%1, #4] @ MDCAS0 \n\
309 str %6, [%1, #8] @ MDCAS1 \n\
310 str %7, [%1, #12] @ MDCAS2 \n\
311 str %8, [%2, #0] @ PPCR \n\
312 ldr %0, [%1, #0] \n\
313 b 3f \n\
3142: b 1b \n\
3153: nop \n\
316 nop"
317 : "=&r" (unused)
318 : "r" (&MDCNFG), "r" (&PPCR), "0" (sd.mdcnfg),
319 "r" (sd.mdrefr), "r" (sd.mdcas[0]),
320 "r" (sd.mdcas[1]), "r" (sd.mdcas[2]), "r" (ppcr));
321 local_irq_restore(flags);
322
323 /*
324 * Now, return the SDRAM refresh back to normal.
325 */
326 sdram_update_refresh(freqs.new, sdram);
327
328 cpufreq_notify_transition(policy, &freqs, CPUFREQ_POSTCHANGE);
329
330 return 0;
331}
332
333static int __init sa1110_cpu_init(struct cpufreq_policy *policy)
334{
335 if (policy->cpu != 0)
336 return -EINVAL;
337 policy->cur = policy->min = policy->max = sa11x0_getspeed(0);
338 policy->cpuinfo.min_freq = 59000;
339 policy->cpuinfo.max_freq = 287000;
340 policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;
341 return 0;
342}
343
344/* sa1110_driver needs __refdata because it must remain after init registers
345 * it with cpufreq_register_driver() */
346static struct cpufreq_driver sa1110_driver __refdata = {
347 .flags = CPUFREQ_STICKY,
348 .verify = sa11x0_verify_speed,
349 .target = sa1110_target,
350 .get = sa11x0_getspeed,
351 .init = sa1110_cpu_init,
352 .name = "sa1110",
353};
354
355static struct sdram_params *sa1110_find_sdram(const char *name)
356{
357 struct sdram_params *sdram;
358
359 for (sdram = sdram_tbl; sdram < sdram_tbl + ARRAY_SIZE(sdram_tbl);
360 sdram++)
361 if (strcmp(name, sdram->name) == 0)
362 return sdram;
363
364 return NULL;
365}
366
367static char sdram_name[16];
368
369static int __init sa1110_clk_init(void)
370{
371 struct sdram_params *sdram;
372 const char *name = sdram_name;
373
374 if (!cpu_is_sa1110())
375 return -ENODEV;
376
377 if (!name[0]) {
378 if (machine_is_assabet())
379 name = "TC59SM716-CL3";
380 if (machine_is_pt_system3())
381 name = "K4S641632D";
382 if (machine_is_h3100())
383 name = "KM416S4030CT";
384 if (machine_is_jornada720())
385 name = "K4S281632B-1H";
386 if (machine_is_nanoengine())
387 name = "MT48LC8M16A2TG-75";
388 }
389
390 sdram = sa1110_find_sdram(name);
391 if (sdram) {
392 printk(KERN_DEBUG "SDRAM: tck: %d trcd: %d trp: %d"
393 " twr: %d refresh: %d cas_latency: %d\n",
394 sdram->tck, sdram->trcd, sdram->trp,
395 sdram->twr, sdram->refresh, sdram->cas_latency);
396
397 memcpy(&sdram_params, sdram, sizeof(sdram_params));
398
399 return cpufreq_register_driver(&sa1110_driver);
400 }
401
402 return 0;
403}
404
405module_param_string(sdram, sdram_name, sizeof(sdram_name), 0);
406arch_initcall(sa1110_clk_init);
generated by cgit v1.2.2 (git 2.25.0) at 2026-01-09 06:45:22 -0500