diff options
Diffstat (limited to 'drivers/char/synclink.c')
-rw-r--r-- | drivers/char/synclink.c | 258 |
1 files changed, 126 insertions, 132 deletions
diff --git a/drivers/char/synclink.c b/drivers/char/synclink.c index a3237d48a584..fadab1d9510f 100644 --- a/drivers/char/synclink.c +++ b/drivers/char/synclink.c | |||
@@ -218,9 +218,9 @@ struct mgsl_struct { | |||
218 | 218 | ||
219 | u32 pending_bh; | 219 | u32 pending_bh; |
220 | 220 | ||
221 | int bh_running; /* Protection from multiple */ | 221 | bool bh_running; /* Protection from multiple */ |
222 | int isr_overflow; | 222 | int isr_overflow; |
223 | int bh_requested; | 223 | bool bh_requested; |
224 | 224 | ||
225 | int dcd_chkcount; /* check counts to prevent */ | 225 | int dcd_chkcount; /* check counts to prevent */ |
226 | int cts_chkcount; /* too many IRQs if a signal */ | 226 | int cts_chkcount; /* too many IRQs if a signal */ |
@@ -250,12 +250,12 @@ struct mgsl_struct { | |||
250 | int tx_holding_count; /* number of tx holding buffers waiting */ | 250 | int tx_holding_count; /* number of tx holding buffers waiting */ |
251 | struct tx_holding_buffer tx_holding_buffers[MAX_TX_HOLDING_BUFFERS]; | 251 | struct tx_holding_buffer tx_holding_buffers[MAX_TX_HOLDING_BUFFERS]; |
252 | 252 | ||
253 | int rx_enabled; | 253 | bool rx_enabled; |
254 | int rx_overflow; | 254 | bool rx_overflow; |
255 | int rx_rcc_underrun; | 255 | bool rx_rcc_underrun; |
256 | 256 | ||
257 | int tx_enabled; | 257 | bool tx_enabled; |
258 | int tx_active; | 258 | bool tx_active; |
259 | u32 idle_mode; | 259 | u32 idle_mode; |
260 | 260 | ||
261 | u16 cmr_value; | 261 | u16 cmr_value; |
@@ -269,14 +269,14 @@ struct mgsl_struct { | |||
269 | 269 | ||
270 | unsigned int io_base; /* base I/O address of adapter */ | 270 | unsigned int io_base; /* base I/O address of adapter */ |
271 | unsigned int io_addr_size; /* size of the I/O address range */ | 271 | unsigned int io_addr_size; /* size of the I/O address range */ |
272 | int io_addr_requested; /* nonzero if I/O address requested */ | 272 | bool io_addr_requested; /* true if I/O address requested */ |
273 | 273 | ||
274 | unsigned int irq_level; /* interrupt level */ | 274 | unsigned int irq_level; /* interrupt level */ |
275 | unsigned long irq_flags; | 275 | unsigned long irq_flags; |
276 | int irq_requested; /* nonzero if IRQ requested */ | 276 | bool irq_requested; /* true if IRQ requested */ |
277 | 277 | ||
278 | unsigned int dma_level; /* DMA channel */ | 278 | unsigned int dma_level; /* DMA channel */ |
279 | int dma_requested; /* nonzero if dma channel requested */ | 279 | bool dma_requested; /* true if dma channel requested */ |
280 | 280 | ||
281 | u16 mbre_bit; | 281 | u16 mbre_bit; |
282 | u16 loopback_bits; | 282 | u16 loopback_bits; |
@@ -286,27 +286,27 @@ struct mgsl_struct { | |||
286 | 286 | ||
287 | unsigned char serial_signals; /* current serial signal states */ | 287 | unsigned char serial_signals; /* current serial signal states */ |
288 | 288 | ||
289 | int irq_occurred; /* for diagnostics use */ | 289 | bool irq_occurred; /* for diagnostics use */ |
290 | unsigned int init_error; /* Initialization startup error (DIAGS) */ | 290 | unsigned int init_error; /* Initialization startup error (DIAGS) */ |
291 | int fDiagnosticsmode; /* Driver in Diagnostic mode? (DIAGS) */ | 291 | int fDiagnosticsmode; /* Driver in Diagnostic mode? (DIAGS) */ |
292 | 292 | ||
293 | u32 last_mem_alloc; | 293 | u32 last_mem_alloc; |
294 | unsigned char* memory_base; /* shared memory address (PCI only) */ | 294 | unsigned char* memory_base; /* shared memory address (PCI only) */ |
295 | u32 phys_memory_base; | 295 | u32 phys_memory_base; |
296 | int shared_mem_requested; | 296 | bool shared_mem_requested; |
297 | 297 | ||
298 | unsigned char* lcr_base; /* local config registers (PCI only) */ | 298 | unsigned char* lcr_base; /* local config registers (PCI only) */ |
299 | u32 phys_lcr_base; | 299 | u32 phys_lcr_base; |
300 | u32 lcr_offset; | 300 | u32 lcr_offset; |
301 | int lcr_mem_requested; | 301 | bool lcr_mem_requested; |
302 | 302 | ||
303 | u32 misc_ctrl_value; | 303 | u32 misc_ctrl_value; |
304 | char flag_buf[MAX_ASYNC_BUFFER_SIZE]; | 304 | char flag_buf[MAX_ASYNC_BUFFER_SIZE]; |
305 | char char_buf[MAX_ASYNC_BUFFER_SIZE]; | 305 | char char_buf[MAX_ASYNC_BUFFER_SIZE]; |
306 | BOOLEAN drop_rts_on_tx_done; | 306 | bool drop_rts_on_tx_done; |
307 | 307 | ||
308 | BOOLEAN loopmode_insert_requested; | 308 | bool loopmode_insert_requested; |
309 | BOOLEAN loopmode_send_done_requested; | 309 | bool loopmode_send_done_requested; |
310 | 310 | ||
311 | struct _input_signal_events input_signal_events; | 311 | struct _input_signal_events input_signal_events; |
312 | 312 | ||
@@ -752,10 +752,10 @@ static void mgsl_trace_block(struct mgsl_struct *info,const char* data, int coun | |||
752 | /* | 752 | /* |
753 | * Adapter diagnostic routines | 753 | * Adapter diagnostic routines |
754 | */ | 754 | */ |
755 | static BOOLEAN mgsl_register_test( struct mgsl_struct *info ); | 755 | static bool mgsl_register_test( struct mgsl_struct *info ); |
756 | static BOOLEAN mgsl_irq_test( struct mgsl_struct *info ); | 756 | static bool mgsl_irq_test( struct mgsl_struct *info ); |
757 | static BOOLEAN mgsl_dma_test( struct mgsl_struct *info ); | 757 | static bool mgsl_dma_test( struct mgsl_struct *info ); |
758 | static BOOLEAN mgsl_memory_test( struct mgsl_struct *info ); | 758 | static bool mgsl_memory_test( struct mgsl_struct *info ); |
759 | static int mgsl_adapter_test( struct mgsl_struct *info ); | 759 | static int mgsl_adapter_test( struct mgsl_struct *info ); |
760 | 760 | ||
761 | /* | 761 | /* |
@@ -770,8 +770,8 @@ static struct mgsl_struct* mgsl_allocate_device(void); | |||
770 | * DMA buffer manupulation functions. | 770 | * DMA buffer manupulation functions. |
771 | */ | 771 | */ |
772 | static void mgsl_free_rx_frame_buffers( struct mgsl_struct *info, unsigned int StartIndex, unsigned int EndIndex ); | 772 | static void mgsl_free_rx_frame_buffers( struct mgsl_struct *info, unsigned int StartIndex, unsigned int EndIndex ); |
773 | static int mgsl_get_rx_frame( struct mgsl_struct *info ); | 773 | static bool mgsl_get_rx_frame( struct mgsl_struct *info ); |
774 | static int mgsl_get_raw_rx_frame( struct mgsl_struct *info ); | 774 | static bool mgsl_get_raw_rx_frame( struct mgsl_struct *info ); |
775 | static void mgsl_reset_rx_dma_buffers( struct mgsl_struct *info ); | 775 | static void mgsl_reset_rx_dma_buffers( struct mgsl_struct *info ); |
776 | static void mgsl_reset_tx_dma_buffers( struct mgsl_struct *info ); | 776 | static void mgsl_reset_tx_dma_buffers( struct mgsl_struct *info ); |
777 | static int num_free_tx_dma_buffers(struct mgsl_struct *info); | 777 | static int num_free_tx_dma_buffers(struct mgsl_struct *info); |
@@ -791,7 +791,7 @@ static int mgsl_alloc_intermediate_rxbuffer_memory(struct mgsl_struct *info); | |||
791 | static void mgsl_free_intermediate_rxbuffer_memory(struct mgsl_struct *info); | 791 | static void mgsl_free_intermediate_rxbuffer_memory(struct mgsl_struct *info); |
792 | static int mgsl_alloc_intermediate_txbuffer_memory(struct mgsl_struct *info); | 792 | static int mgsl_alloc_intermediate_txbuffer_memory(struct mgsl_struct *info); |
793 | static void mgsl_free_intermediate_txbuffer_memory(struct mgsl_struct *info); | 793 | static void mgsl_free_intermediate_txbuffer_memory(struct mgsl_struct *info); |
794 | static int load_next_tx_holding_buffer(struct mgsl_struct *info); | 794 | static bool load_next_tx_holding_buffer(struct mgsl_struct *info); |
795 | static int save_tx_buffer_request(struct mgsl_struct *info,const char *Buffer, unsigned int BufferSize); | 795 | static int save_tx_buffer_request(struct mgsl_struct *info,const char *Buffer, unsigned int BufferSize); |
796 | 796 | ||
797 | /* | 797 | /* |
@@ -847,7 +847,7 @@ static int mgsl_wait_event(struct mgsl_struct * info, int __user *mask); | |||
847 | static int mgsl_loopmode_send_done( struct mgsl_struct * info ); | 847 | static int mgsl_loopmode_send_done( struct mgsl_struct * info ); |
848 | 848 | ||
849 | /* set non-zero on successful registration with PCI subsystem */ | 849 | /* set non-zero on successful registration with PCI subsystem */ |
850 | static int pci_registered; | 850 | static bool pci_registered; |
851 | 851 | ||
852 | /* | 852 | /* |
853 | * Global linked list of SyncLink devices | 853 | * Global linked list of SyncLink devices |
@@ -1054,8 +1054,8 @@ static int mgsl_bh_action(struct mgsl_struct *info) | |||
1054 | 1054 | ||
1055 | if (!rc) { | 1055 | if (!rc) { |
1056 | /* Mark BH routine as complete */ | 1056 | /* Mark BH routine as complete */ |
1057 | info->bh_running = 0; | 1057 | info->bh_running = false; |
1058 | info->bh_requested = 0; | 1058 | info->bh_requested = false; |
1059 | } | 1059 | } |
1060 | 1060 | ||
1061 | spin_unlock_irqrestore(&info->irq_spinlock,flags); | 1061 | spin_unlock_irqrestore(&info->irq_spinlock,flags); |
@@ -1079,7 +1079,7 @@ static void mgsl_bh_handler(struct work_struct *work) | |||
1079 | printk( "%s(%d):mgsl_bh_handler(%s) entry\n", | 1079 | printk( "%s(%d):mgsl_bh_handler(%s) entry\n", |
1080 | __FILE__,__LINE__,info->device_name); | 1080 | __FILE__,__LINE__,info->device_name); |
1081 | 1081 | ||
1082 | info->bh_running = 1; | 1082 | info->bh_running = true; |
1083 | 1083 | ||
1084 | while((action = mgsl_bh_action(info)) != 0) { | 1084 | while((action = mgsl_bh_action(info)) != 0) { |
1085 | 1085 | ||
@@ -1113,7 +1113,7 @@ static void mgsl_bh_handler(struct work_struct *work) | |||
1113 | 1113 | ||
1114 | static void mgsl_bh_receive(struct mgsl_struct *info) | 1114 | static void mgsl_bh_receive(struct mgsl_struct *info) |
1115 | { | 1115 | { |
1116 | int (*get_rx_frame)(struct mgsl_struct *info) = | 1116 | bool (*get_rx_frame)(struct mgsl_struct *info) = |
1117 | (info->params.mode == MGSL_MODE_HDLC ? mgsl_get_rx_frame : mgsl_get_raw_rx_frame); | 1117 | (info->params.mode == MGSL_MODE_HDLC ? mgsl_get_rx_frame : mgsl_get_raw_rx_frame); |
1118 | 1118 | ||
1119 | if ( debug_level >= DEBUG_LEVEL_BH ) | 1119 | if ( debug_level >= DEBUG_LEVEL_BH ) |
@@ -1187,7 +1187,7 @@ static void mgsl_isr_receive_status( struct mgsl_struct *info ) | |||
1187 | usc_loopmode_active(info) ) | 1187 | usc_loopmode_active(info) ) |
1188 | { | 1188 | { |
1189 | ++info->icount.rxabort; | 1189 | ++info->icount.rxabort; |
1190 | info->loopmode_insert_requested = FALSE; | 1190 | info->loopmode_insert_requested = false; |
1191 | 1191 | ||
1192 | /* clear CMR:13 to start echoing RxD to TxD */ | 1192 | /* clear CMR:13 to start echoing RxD to TxD */ |
1193 | info->cmr_value &= ~BIT13; | 1193 | info->cmr_value &= ~BIT13; |
@@ -1257,7 +1257,7 @@ static void mgsl_isr_transmit_status( struct mgsl_struct *info ) | |||
1257 | else | 1257 | else |
1258 | info->icount.txunder++; | 1258 | info->icount.txunder++; |
1259 | 1259 | ||
1260 | info->tx_active = 0; | 1260 | info->tx_active = false; |
1261 | info->xmit_cnt = info->xmit_head = info->xmit_tail = 0; | 1261 | info->xmit_cnt = info->xmit_head = info->xmit_tail = 0; |
1262 | del_timer(&info->tx_timer); | 1262 | del_timer(&info->tx_timer); |
1263 | 1263 | ||
@@ -1267,7 +1267,7 @@ static void mgsl_isr_transmit_status( struct mgsl_struct *info ) | |||
1267 | info->serial_signals &= ~SerialSignal_RTS; | 1267 | info->serial_signals &= ~SerialSignal_RTS; |
1268 | usc_set_serial_signals( info ); | 1268 | usc_set_serial_signals( info ); |
1269 | } | 1269 | } |
1270 | info->drop_rts_on_tx_done = 0; | 1270 | info->drop_rts_on_tx_done = false; |
1271 | } | 1271 | } |
1272 | 1272 | ||
1273 | #if SYNCLINK_GENERIC_HDLC | 1273 | #if SYNCLINK_GENERIC_HDLC |
@@ -1403,7 +1403,7 @@ static void mgsl_isr_io_pin( struct mgsl_struct *info ) | |||
1403 | usc_OutReg( info, SICR, | 1403 | usc_OutReg( info, SICR, |
1404 | (unsigned short)(usc_InReg(info,SICR) & ~(SICR_TXC_ACTIVE+SICR_TXC_INACTIVE)) ); | 1404 | (unsigned short)(usc_InReg(info,SICR) & ~(SICR_TXC_ACTIVE+SICR_TXC_INACTIVE)) ); |
1405 | usc_UnlatchIostatusBits( info, MISCSTATUS_TXC_LATCHED ); | 1405 | usc_UnlatchIostatusBits( info, MISCSTATUS_TXC_LATCHED ); |
1406 | info->irq_occurred = 1; | 1406 | info->irq_occurred = true; |
1407 | } | 1407 | } |
1408 | 1408 | ||
1409 | } /* end of mgsl_isr_io_pin() */ | 1409 | } /* end of mgsl_isr_io_pin() */ |
@@ -1431,7 +1431,7 @@ static void mgsl_isr_transmit_data( struct mgsl_struct *info ) | |||
1431 | if ( info->xmit_cnt ) | 1431 | if ( info->xmit_cnt ) |
1432 | usc_load_txfifo( info ); | 1432 | usc_load_txfifo( info ); |
1433 | else | 1433 | else |
1434 | info->tx_active = 0; | 1434 | info->tx_active = false; |
1435 | 1435 | ||
1436 | if (info->xmit_cnt < WAKEUP_CHARS) | 1436 | if (info->xmit_cnt < WAKEUP_CHARS) |
1437 | info->pending_bh |= BH_TRANSMIT; | 1437 | info->pending_bh |= BH_TRANSMIT; |
@@ -1568,7 +1568,7 @@ static void mgsl_isr_misc( struct mgsl_struct *info ) | |||
1568 | 1568 | ||
1569 | /* schedule BH handler to restart receiver */ | 1569 | /* schedule BH handler to restart receiver */ |
1570 | info->pending_bh |= BH_RECEIVE; | 1570 | info->pending_bh |= BH_RECEIVE; |
1571 | info->rx_rcc_underrun = 1; | 1571 | info->rx_rcc_underrun = true; |
1572 | } | 1572 | } |
1573 | 1573 | ||
1574 | usc_ClearIrqPendingBits( info, MISC ); | 1574 | usc_ClearIrqPendingBits( info, MISC ); |
@@ -1626,7 +1626,7 @@ static void mgsl_isr_receive_dma( struct mgsl_struct *info ) | |||
1626 | info->pending_bh |= BH_RECEIVE; | 1626 | info->pending_bh |= BH_RECEIVE; |
1627 | 1627 | ||
1628 | if ( status & BIT3 ) { | 1628 | if ( status & BIT3 ) { |
1629 | info->rx_overflow = 1; | 1629 | info->rx_overflow = true; |
1630 | info->icount.buf_overrun++; | 1630 | info->icount.buf_overrun++; |
1631 | } | 1631 | } |
1632 | 1632 | ||
@@ -1745,7 +1745,7 @@ static irqreturn_t mgsl_interrupt(int dummy, void *dev_id) | |||
1745 | printk("%s(%d):%s queueing bh task.\n", | 1745 | printk("%s(%d):%s queueing bh task.\n", |
1746 | __FILE__,__LINE__,info->device_name); | 1746 | __FILE__,__LINE__,info->device_name); |
1747 | schedule_work(&info->task); | 1747 | schedule_work(&info->task); |
1748 | info->bh_requested = 1; | 1748 | info->bh_requested = true; |
1749 | } | 1749 | } |
1750 | 1750 | ||
1751 | spin_unlock(&info->irq_spinlock); | 1751 | spin_unlock(&info->irq_spinlock); |
@@ -3303,7 +3303,8 @@ static int block_til_ready(struct tty_struct *tty, struct file * filp, | |||
3303 | { | 3303 | { |
3304 | DECLARE_WAITQUEUE(wait, current); | 3304 | DECLARE_WAITQUEUE(wait, current); |
3305 | int retval; | 3305 | int retval; |
3306 | int do_clocal = 0, extra_count = 0; | 3306 | bool do_clocal = false; |
3307 | bool extra_count = false; | ||
3307 | unsigned long flags; | 3308 | unsigned long flags; |
3308 | 3309 | ||
3309 | if (debug_level >= DEBUG_LEVEL_INFO) | 3310 | if (debug_level >= DEBUG_LEVEL_INFO) |
@@ -3317,7 +3318,7 @@ static int block_til_ready(struct tty_struct *tty, struct file * filp, | |||
3317 | } | 3318 | } |
3318 | 3319 | ||
3319 | if (tty->termios->c_cflag & CLOCAL) | 3320 | if (tty->termios->c_cflag & CLOCAL) |
3320 | do_clocal = 1; | 3321 | do_clocal = true; |
3321 | 3322 | ||
3322 | /* Wait for carrier detect and the line to become | 3323 | /* Wait for carrier detect and the line to become |
3323 | * free (i.e., not in use by the callout). While we are in | 3324 | * free (i.e., not in use by the callout). While we are in |
@@ -3335,7 +3336,7 @@ static int block_til_ready(struct tty_struct *tty, struct file * filp, | |||
3335 | 3336 | ||
3336 | spin_lock_irqsave(&info->irq_spinlock, flags); | 3337 | spin_lock_irqsave(&info->irq_spinlock, flags); |
3337 | if (!tty_hung_up_p(filp)) { | 3338 | if (!tty_hung_up_p(filp)) { |
3338 | extra_count = 1; | 3339 | extra_count = true; |
3339 | info->count--; | 3340 | info->count--; |
3340 | } | 3341 | } |
3341 | spin_unlock_irqrestore(&info->irq_spinlock, flags); | 3342 | spin_unlock_irqrestore(&info->irq_spinlock, flags); |
@@ -4043,13 +4044,13 @@ static void mgsl_free_intermediate_txbuffer_memory(struct mgsl_struct *info) | |||
4043 | * | 4044 | * |
4044 | * info pointer to device instance data | 4045 | * info pointer to device instance data |
4045 | * | 4046 | * |
4046 | * Return Value: 1 if next buffered tx request loaded | 4047 | * Return Value: true if next buffered tx request loaded |
4047 | * into adapter's tx dma buffer, | 4048 | * into adapter's tx dma buffer, |
4048 | * 0 otherwise | 4049 | * false otherwise |
4049 | */ | 4050 | */ |
4050 | static int load_next_tx_holding_buffer(struct mgsl_struct *info) | 4051 | static bool load_next_tx_holding_buffer(struct mgsl_struct *info) |
4051 | { | 4052 | { |
4052 | int ret = 0; | 4053 | bool ret = false; |
4053 | 4054 | ||
4054 | if ( info->tx_holding_count ) { | 4055 | if ( info->tx_holding_count ) { |
4055 | /* determine if we have enough tx dma buffers | 4056 | /* determine if we have enough tx dma buffers |
@@ -4073,7 +4074,7 @@ static int load_next_tx_holding_buffer(struct mgsl_struct *info) | |||
4073 | /* restart transmit timer */ | 4074 | /* restart transmit timer */ |
4074 | mod_timer(&info->tx_timer, jiffies + msecs_to_jiffies(5000)); | 4075 | mod_timer(&info->tx_timer, jiffies + msecs_to_jiffies(5000)); |
4075 | 4076 | ||
4076 | ret = 1; | 4077 | ret = true; |
4077 | } | 4078 | } |
4078 | } | 4079 | } |
4079 | 4080 | ||
@@ -4119,7 +4120,7 @@ static int mgsl_claim_resources(struct mgsl_struct *info) | |||
4119 | __FILE__,__LINE__,info->device_name, info->io_base); | 4120 | __FILE__,__LINE__,info->device_name, info->io_base); |
4120 | return -ENODEV; | 4121 | return -ENODEV; |
4121 | } | 4122 | } |
4122 | info->io_addr_requested = 1; | 4123 | info->io_addr_requested = true; |
4123 | 4124 | ||
4124 | if ( request_irq(info->irq_level,mgsl_interrupt,info->irq_flags, | 4125 | if ( request_irq(info->irq_level,mgsl_interrupt,info->irq_flags, |
4125 | info->device_name, info ) < 0 ) { | 4126 | info->device_name, info ) < 0 ) { |
@@ -4127,7 +4128,7 @@ static int mgsl_claim_resources(struct mgsl_struct *info) | |||
4127 | __FILE__,__LINE__,info->device_name, info->irq_level ); | 4128 | __FILE__,__LINE__,info->device_name, info->irq_level ); |
4128 | goto errout; | 4129 | goto errout; |
4129 | } | 4130 | } |
4130 | info->irq_requested = 1; | 4131 | info->irq_requested = true; |
4131 | 4132 | ||
4132 | if ( info->bus_type == MGSL_BUS_TYPE_PCI ) { | 4133 | if ( info->bus_type == MGSL_BUS_TYPE_PCI ) { |
4133 | if (request_mem_region(info->phys_memory_base,0x40000,"synclink") == NULL) { | 4134 | if (request_mem_region(info->phys_memory_base,0x40000,"synclink") == NULL) { |
@@ -4135,13 +4136,13 @@ static int mgsl_claim_resources(struct mgsl_struct *info) | |||
4135 | __FILE__,__LINE__,info->device_name, info->phys_memory_base); | 4136 | __FILE__,__LINE__,info->device_name, info->phys_memory_base); |
4136 | goto errout; | 4137 | goto errout; |
4137 | } | 4138 | } |
4138 | info->shared_mem_requested = 1; | 4139 | info->shared_mem_requested = true; |
4139 | if (request_mem_region(info->phys_lcr_base + info->lcr_offset,128,"synclink") == NULL) { | 4140 | if (request_mem_region(info->phys_lcr_base + info->lcr_offset,128,"synclink") == NULL) { |
4140 | printk( "%s(%d):lcr mem addr conflict device %s Addr=%08X\n", | 4141 | printk( "%s(%d):lcr mem addr conflict device %s Addr=%08X\n", |
4141 | __FILE__,__LINE__,info->device_name, info->phys_lcr_base + info->lcr_offset); | 4142 | __FILE__,__LINE__,info->device_name, info->phys_lcr_base + info->lcr_offset); |
4142 | goto errout; | 4143 | goto errout; |
4143 | } | 4144 | } |
4144 | info->lcr_mem_requested = 1; | 4145 | info->lcr_mem_requested = true; |
4145 | 4146 | ||
4146 | info->memory_base = ioremap(info->phys_memory_base,0x40000); | 4147 | info->memory_base = ioremap(info->phys_memory_base,0x40000); |
4147 | if (!info->memory_base) { | 4148 | if (!info->memory_base) { |
@@ -4172,7 +4173,7 @@ static int mgsl_claim_resources(struct mgsl_struct *info) | |||
4172 | mgsl_release_resources( info ); | 4173 | mgsl_release_resources( info ); |
4173 | return -ENODEV; | 4174 | return -ENODEV; |
4174 | } | 4175 | } |
4175 | info->dma_requested = 1; | 4176 | info->dma_requested = true; |
4176 | 4177 | ||
4177 | /* ISA adapter uses bus master DMA */ | 4178 | /* ISA adapter uses bus master DMA */ |
4178 | set_dma_mode(info->dma_level,DMA_MODE_CASCADE); | 4179 | set_dma_mode(info->dma_level,DMA_MODE_CASCADE); |
@@ -4200,12 +4201,12 @@ static void mgsl_release_resources(struct mgsl_struct *info) | |||
4200 | 4201 | ||
4201 | if ( info->irq_requested ) { | 4202 | if ( info->irq_requested ) { |
4202 | free_irq(info->irq_level, info); | 4203 | free_irq(info->irq_level, info); |
4203 | info->irq_requested = 0; | 4204 | info->irq_requested = false; |
4204 | } | 4205 | } |
4205 | if ( info->dma_requested ) { | 4206 | if ( info->dma_requested ) { |
4206 | disable_dma(info->dma_level); | 4207 | disable_dma(info->dma_level); |
4207 | free_dma(info->dma_level); | 4208 | free_dma(info->dma_level); |
4208 | info->dma_requested = 0; | 4209 | info->dma_requested = false; |
4209 | } | 4210 | } |
4210 | mgsl_free_dma_buffers(info); | 4211 | mgsl_free_dma_buffers(info); |
4211 | mgsl_free_intermediate_rxbuffer_memory(info); | 4212 | mgsl_free_intermediate_rxbuffer_memory(info); |
@@ -4213,15 +4214,15 @@ static void mgsl_release_resources(struct mgsl_struct *info) | |||
4213 | 4214 | ||
4214 | if ( info->io_addr_requested ) { | 4215 | if ( info->io_addr_requested ) { |
4215 | release_region(info->io_base,info->io_addr_size); | 4216 | release_region(info->io_base,info->io_addr_size); |
4216 | info->io_addr_requested = 0; | 4217 | info->io_addr_requested = false; |
4217 | } | 4218 | } |
4218 | if ( info->shared_mem_requested ) { | 4219 | if ( info->shared_mem_requested ) { |
4219 | release_mem_region(info->phys_memory_base,0x40000); | 4220 | release_mem_region(info->phys_memory_base,0x40000); |
4220 | info->shared_mem_requested = 0; | 4221 | info->shared_mem_requested = false; |
4221 | } | 4222 | } |
4222 | if ( info->lcr_mem_requested ) { | 4223 | if ( info->lcr_mem_requested ) { |
4223 | release_mem_region(info->phys_lcr_base + info->lcr_offset,128); | 4224 | release_mem_region(info->phys_lcr_base + info->lcr_offset,128); |
4224 | info->lcr_mem_requested = 0; | 4225 | info->lcr_mem_requested = false; |
4225 | } | 4226 | } |
4226 | if (info->memory_base){ | 4227 | if (info->memory_base){ |
4227 | iounmap(info->memory_base); | 4228 | iounmap(info->memory_base); |
@@ -4486,7 +4487,7 @@ static int __init synclink_init(void) | |||
4486 | if ((rc = pci_register_driver(&synclink_pci_driver)) < 0) | 4487 | if ((rc = pci_register_driver(&synclink_pci_driver)) < 0) |
4487 | printk("%s:failed to register PCI driver, error=%d\n",__FILE__,rc); | 4488 | printk("%s:failed to register PCI driver, error=%d\n",__FILE__,rc); |
4488 | else | 4489 | else |
4489 | pci_registered = 1; | 4490 | pci_registered = true; |
4490 | 4491 | ||
4491 | if ((rc = mgsl_init_tty()) < 0) | 4492 | if ((rc = mgsl_init_tty()) < 0) |
4492 | goto error; | 4493 | goto error; |
@@ -4679,7 +4680,7 @@ static u16 usc_InReg( struct mgsl_struct *info, u16 RegAddr ) | |||
4679 | static void usc_set_sdlc_mode( struct mgsl_struct *info ) | 4680 | static void usc_set_sdlc_mode( struct mgsl_struct *info ) |
4680 | { | 4681 | { |
4681 | u16 RegValue; | 4682 | u16 RegValue; |
4682 | int PreSL1660; | 4683 | bool PreSL1660; |
4683 | 4684 | ||
4684 | /* | 4685 | /* |
4685 | * determine if the IUSC on the adapter is pre-SL1660. If | 4686 | * determine if the IUSC on the adapter is pre-SL1660. If |
@@ -4692,11 +4693,7 @@ static void usc_set_sdlc_mode( struct mgsl_struct *info ) | |||
4692 | */ | 4693 | */ |
4693 | usc_OutReg(info,TMCR,0x1f); | 4694 | usc_OutReg(info,TMCR,0x1f); |
4694 | RegValue=usc_InReg(info,TMDR); | 4695 | RegValue=usc_InReg(info,TMDR); |
4695 | if ( RegValue == IUSC_PRE_SL1660 ) | 4696 | PreSL1660 = (RegValue == IUSC_PRE_SL1660); |
4696 | PreSL1660 = 1; | ||
4697 | else | ||
4698 | PreSL1660 = 0; | ||
4699 | |||
4700 | 4697 | ||
4701 | if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE ) | 4698 | if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE ) |
4702 | { | 4699 | { |
@@ -5382,9 +5379,9 @@ static void usc_process_rxoverrun_sync( struct mgsl_struct *info ) | |||
5382 | int start_index; | 5379 | int start_index; |
5383 | int end_index; | 5380 | int end_index; |
5384 | int frame_start_index; | 5381 | int frame_start_index; |
5385 | int start_of_frame_found = FALSE; | 5382 | bool start_of_frame_found = false; |
5386 | int end_of_frame_found = FALSE; | 5383 | bool end_of_frame_found = false; |
5387 | int reprogram_dma = FALSE; | 5384 | bool reprogram_dma = false; |
5388 | 5385 | ||
5389 | DMABUFFERENTRY *buffer_list = info->rx_buffer_list; | 5386 | DMABUFFERENTRY *buffer_list = info->rx_buffer_list; |
5390 | u32 phys_addr; | 5387 | u32 phys_addr; |
@@ -5410,9 +5407,9 @@ static void usc_process_rxoverrun_sync( struct mgsl_struct *info ) | |||
5410 | 5407 | ||
5411 | if ( !start_of_frame_found ) | 5408 | if ( !start_of_frame_found ) |
5412 | { | 5409 | { |
5413 | start_of_frame_found = TRUE; | 5410 | start_of_frame_found = true; |
5414 | frame_start_index = end_index; | 5411 | frame_start_index = end_index; |
5415 | end_of_frame_found = FALSE; | 5412 | end_of_frame_found = false; |
5416 | } | 5413 | } |
5417 | 5414 | ||
5418 | if ( buffer_list[end_index].status ) | 5415 | if ( buffer_list[end_index].status ) |
@@ -5423,8 +5420,8 @@ static void usc_process_rxoverrun_sync( struct mgsl_struct *info ) | |||
5423 | /* We want to leave the buffers for this frame intact. */ | 5420 | /* We want to leave the buffers for this frame intact. */ |
5424 | /* Move on to next possible frame. */ | 5421 | /* Move on to next possible frame. */ |
5425 | 5422 | ||
5426 | start_of_frame_found = FALSE; | 5423 | start_of_frame_found = false; |
5427 | end_of_frame_found = TRUE; | 5424 | end_of_frame_found = true; |
5428 | } | 5425 | } |
5429 | 5426 | ||
5430 | /* advance to next buffer entry in linked list */ | 5427 | /* advance to next buffer entry in linked list */ |
@@ -5439,8 +5436,8 @@ static void usc_process_rxoverrun_sync( struct mgsl_struct *info ) | |||
5439 | /* completely screwed, reset all receive buffers! */ | 5436 | /* completely screwed, reset all receive buffers! */ |
5440 | mgsl_reset_rx_dma_buffers( info ); | 5437 | mgsl_reset_rx_dma_buffers( info ); |
5441 | frame_start_index = 0; | 5438 | frame_start_index = 0; |
5442 | start_of_frame_found = FALSE; | 5439 | start_of_frame_found = false; |
5443 | reprogram_dma = TRUE; | 5440 | reprogram_dma = true; |
5444 | break; | 5441 | break; |
5445 | } | 5442 | } |
5446 | } | 5443 | } |
@@ -5466,7 +5463,7 @@ static void usc_process_rxoverrun_sync( struct mgsl_struct *info ) | |||
5466 | 5463 | ||
5467 | } while( start_index != end_index ); | 5464 | } while( start_index != end_index ); |
5468 | 5465 | ||
5469 | reprogram_dma = TRUE; | 5466 | reprogram_dma = true; |
5470 | } | 5467 | } |
5471 | 5468 | ||
5472 | if ( reprogram_dma ) | 5469 | if ( reprogram_dma ) |
@@ -5536,9 +5533,9 @@ static void usc_stop_receiver( struct mgsl_struct *info ) | |||
5536 | usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) ); | 5533 | usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) ); |
5537 | usc_RTCmd( info, RTCmd_PurgeRxFifo ); | 5534 | usc_RTCmd( info, RTCmd_PurgeRxFifo ); |
5538 | 5535 | ||
5539 | info->rx_enabled = 0; | 5536 | info->rx_enabled = false; |
5540 | info->rx_overflow = 0; | 5537 | info->rx_overflow = false; |
5541 | info->rx_rcc_underrun = 0; | 5538 | info->rx_rcc_underrun = false; |
5542 | 5539 | ||
5543 | } /* end of stop_receiver() */ | 5540 | } /* end of stop_receiver() */ |
5544 | 5541 | ||
@@ -5601,7 +5598,7 @@ static void usc_start_receiver( struct mgsl_struct *info ) | |||
5601 | 5598 | ||
5602 | usc_OutReg( info, CCSR, 0x1020 ); | 5599 | usc_OutReg( info, CCSR, 0x1020 ); |
5603 | 5600 | ||
5604 | info->rx_enabled = 1; | 5601 | info->rx_enabled = true; |
5605 | 5602 | ||
5606 | } /* end of usc_start_receiver() */ | 5603 | } /* end of usc_start_receiver() */ |
5607 | 5604 | ||
@@ -5628,14 +5625,14 @@ static void usc_start_transmitter( struct mgsl_struct *info ) | |||
5628 | /* RTS and set a flag indicating that the driver should */ | 5625 | /* RTS and set a flag indicating that the driver should */ |
5629 | /* negate RTS when the transmission completes. */ | 5626 | /* negate RTS when the transmission completes. */ |
5630 | 5627 | ||
5631 | info->drop_rts_on_tx_done = 0; | 5628 | info->drop_rts_on_tx_done = false; |
5632 | 5629 | ||
5633 | if ( info->params.flags & HDLC_FLAG_AUTO_RTS ) { | 5630 | if ( info->params.flags & HDLC_FLAG_AUTO_RTS ) { |
5634 | usc_get_serial_signals( info ); | 5631 | usc_get_serial_signals( info ); |
5635 | if ( !(info->serial_signals & SerialSignal_RTS) ) { | 5632 | if ( !(info->serial_signals & SerialSignal_RTS) ) { |
5636 | info->serial_signals |= SerialSignal_RTS; | 5633 | info->serial_signals |= SerialSignal_RTS; |
5637 | usc_set_serial_signals( info ); | 5634 | usc_set_serial_signals( info ); |
5638 | info->drop_rts_on_tx_done = 1; | 5635 | info->drop_rts_on_tx_done = true; |
5639 | } | 5636 | } |
5640 | } | 5637 | } |
5641 | 5638 | ||
@@ -5699,11 +5696,11 @@ static void usc_start_transmitter( struct mgsl_struct *info ) | |||
5699 | mod_timer(&info->tx_timer, jiffies + | 5696 | mod_timer(&info->tx_timer, jiffies + |
5700 | msecs_to_jiffies(5000)); | 5697 | msecs_to_jiffies(5000)); |
5701 | } | 5698 | } |
5702 | info->tx_active = 1; | 5699 | info->tx_active = true; |
5703 | } | 5700 | } |
5704 | 5701 | ||
5705 | if ( !info->tx_enabled ) { | 5702 | if ( !info->tx_enabled ) { |
5706 | info->tx_enabled = 1; | 5703 | info->tx_enabled = true; |
5707 | if ( info->params.flags & HDLC_FLAG_AUTO_CTS ) | 5704 | if ( info->params.flags & HDLC_FLAG_AUTO_CTS ) |
5708 | usc_EnableTransmitter(info,ENABLE_AUTO_CTS); | 5705 | usc_EnableTransmitter(info,ENABLE_AUTO_CTS); |
5709 | else | 5706 | else |
@@ -5735,8 +5732,8 @@ static void usc_stop_transmitter( struct mgsl_struct *info ) | |||
5735 | usc_DmaCmd( info, DmaCmd_ResetTxChannel ); | 5732 | usc_DmaCmd( info, DmaCmd_ResetTxChannel ); |
5736 | usc_RTCmd( info, RTCmd_PurgeTxFifo ); | 5733 | usc_RTCmd( info, RTCmd_PurgeTxFifo ); |
5737 | 5734 | ||
5738 | info->tx_enabled = 0; | 5735 | info->tx_enabled = false; |
5739 | info->tx_active = 0; | 5736 | info->tx_active = false; |
5740 | 5737 | ||
5741 | } /* end of usc_stop_transmitter() */ | 5738 | } /* end of usc_stop_transmitter() */ |
5742 | 5739 | ||
@@ -6520,7 +6517,7 @@ static void mgsl_reset_rx_dma_buffers( struct mgsl_struct *info ) | |||
6520 | */ | 6517 | */ |
6521 | static void mgsl_free_rx_frame_buffers( struct mgsl_struct *info, unsigned int StartIndex, unsigned int EndIndex ) | 6518 | static void mgsl_free_rx_frame_buffers( struct mgsl_struct *info, unsigned int StartIndex, unsigned int EndIndex ) |
6522 | { | 6519 | { |
6523 | int Done = 0; | 6520 | bool Done = false; |
6524 | DMABUFFERENTRY *pBufEntry; | 6521 | DMABUFFERENTRY *pBufEntry; |
6525 | unsigned int Index; | 6522 | unsigned int Index; |
6526 | 6523 | ||
@@ -6534,7 +6531,7 @@ static void mgsl_free_rx_frame_buffers( struct mgsl_struct *info, unsigned int S | |||
6534 | 6531 | ||
6535 | if ( Index == EndIndex ) { | 6532 | if ( Index == EndIndex ) { |
6536 | /* This is the last buffer of the frame! */ | 6533 | /* This is the last buffer of the frame! */ |
6537 | Done = 1; | 6534 | Done = true; |
6538 | } | 6535 | } |
6539 | 6536 | ||
6540 | /* reset current buffer for reuse */ | 6537 | /* reset current buffer for reuse */ |
@@ -6559,18 +6556,18 @@ static void mgsl_free_rx_frame_buffers( struct mgsl_struct *info, unsigned int S | |||
6559 | * receive DMA buffers. Only frames received without errors are returned. | 6556 | * receive DMA buffers. Only frames received without errors are returned. |
6560 | * | 6557 | * |
6561 | * Arguments: info pointer to device extension | 6558 | * Arguments: info pointer to device extension |
6562 | * Return Value: 1 if frame returned, otherwise 0 | 6559 | * Return Value: true if frame returned, otherwise false |
6563 | */ | 6560 | */ |
6564 | static int mgsl_get_rx_frame(struct mgsl_struct *info) | 6561 | static bool mgsl_get_rx_frame(struct mgsl_struct *info) |
6565 | { | 6562 | { |
6566 | unsigned int StartIndex, EndIndex; /* index of 1st and last buffers of Rx frame */ | 6563 | unsigned int StartIndex, EndIndex; /* index of 1st and last buffers of Rx frame */ |
6567 | unsigned short status; | 6564 | unsigned short status; |
6568 | DMABUFFERENTRY *pBufEntry; | 6565 | DMABUFFERENTRY *pBufEntry; |
6569 | unsigned int framesize = 0; | 6566 | unsigned int framesize = 0; |
6570 | int ReturnCode = 0; | 6567 | bool ReturnCode = false; |
6571 | unsigned long flags; | 6568 | unsigned long flags; |
6572 | struct tty_struct *tty = info->tty; | 6569 | struct tty_struct *tty = info->tty; |
6573 | int return_frame = 0; | 6570 | bool return_frame = false; |
6574 | 6571 | ||
6575 | /* | 6572 | /* |
6576 | * current_rx_buffer points to the 1st buffer of the next available | 6573 | * current_rx_buffer points to the 1st buffer of the next available |
@@ -6629,7 +6626,7 @@ static int mgsl_get_rx_frame(struct mgsl_struct *info) | |||
6629 | else { | 6626 | else { |
6630 | info->icount.rxcrc++; | 6627 | info->icount.rxcrc++; |
6631 | if ( info->params.crc_type & HDLC_CRC_RETURN_EX ) | 6628 | if ( info->params.crc_type & HDLC_CRC_RETURN_EX ) |
6632 | return_frame = 1; | 6629 | return_frame = true; |
6633 | } | 6630 | } |
6634 | framesize = 0; | 6631 | framesize = 0; |
6635 | #if SYNCLINK_GENERIC_HDLC | 6632 | #if SYNCLINK_GENERIC_HDLC |
@@ -6640,7 +6637,7 @@ static int mgsl_get_rx_frame(struct mgsl_struct *info) | |||
6640 | } | 6637 | } |
6641 | #endif | 6638 | #endif |
6642 | } else | 6639 | } else |
6643 | return_frame = 1; | 6640 | return_frame = true; |
6644 | 6641 | ||
6645 | if ( return_frame ) { | 6642 | if ( return_frame ) { |
6646 | /* receive frame has no errors, get frame size. | 6643 | /* receive frame has no errors, get frame size. |
@@ -6719,7 +6716,7 @@ static int mgsl_get_rx_frame(struct mgsl_struct *info) | |||
6719 | /* Free the buffers used by this frame. */ | 6716 | /* Free the buffers used by this frame. */ |
6720 | mgsl_free_rx_frame_buffers( info, StartIndex, EndIndex ); | 6717 | mgsl_free_rx_frame_buffers( info, StartIndex, EndIndex ); |
6721 | 6718 | ||
6722 | ReturnCode = 1; | 6719 | ReturnCode = true; |
6723 | 6720 | ||
6724 | Cleanup: | 6721 | Cleanup: |
6725 | 6722 | ||
@@ -6758,15 +6755,15 @@ Cleanup: | |||
6758 | * last Rx DMA buffer and return that last portion of the frame. | 6755 | * last Rx DMA buffer and return that last portion of the frame. |
6759 | * | 6756 | * |
6760 | * Arguments: info pointer to device extension | 6757 | * Arguments: info pointer to device extension |
6761 | * Return Value: 1 if frame returned, otherwise 0 | 6758 | * Return Value: true if frame returned, otherwise false |
6762 | */ | 6759 | */ |
6763 | static int mgsl_get_raw_rx_frame(struct mgsl_struct *info) | 6760 | static bool mgsl_get_raw_rx_frame(struct mgsl_struct *info) |
6764 | { | 6761 | { |
6765 | unsigned int CurrentIndex, NextIndex; | 6762 | unsigned int CurrentIndex, NextIndex; |
6766 | unsigned short status; | 6763 | unsigned short status; |
6767 | DMABUFFERENTRY *pBufEntry; | 6764 | DMABUFFERENTRY *pBufEntry; |
6768 | unsigned int framesize = 0; | 6765 | unsigned int framesize = 0; |
6769 | int ReturnCode = 0; | 6766 | bool ReturnCode = false; |
6770 | unsigned long flags; | 6767 | unsigned long flags; |
6771 | struct tty_struct *tty = info->tty; | 6768 | struct tty_struct *tty = info->tty; |
6772 | 6769 | ||
@@ -6891,7 +6888,7 @@ static int mgsl_get_raw_rx_frame(struct mgsl_struct *info) | |||
6891 | /* Free the buffers used by this frame. */ | 6888 | /* Free the buffers used by this frame. */ |
6892 | mgsl_free_rx_frame_buffers( info, CurrentIndex, CurrentIndex ); | 6889 | mgsl_free_rx_frame_buffers( info, CurrentIndex, CurrentIndex ); |
6893 | 6890 | ||
6894 | ReturnCode = 1; | 6891 | ReturnCode = true; |
6895 | } | 6892 | } |
6896 | 6893 | ||
6897 | 6894 | ||
@@ -7000,15 +6997,15 @@ static void mgsl_load_tx_dma_buffer(struct mgsl_struct *info, | |||
7000 | * Performs a register test of the 16C32. | 6997 | * Performs a register test of the 16C32. |
7001 | * | 6998 | * |
7002 | * Arguments: info pointer to device instance data | 6999 | * Arguments: info pointer to device instance data |
7003 | * Return Value: TRUE if test passed, otherwise FALSE | 7000 | * Return Value: true if test passed, otherwise false |
7004 | */ | 7001 | */ |
7005 | static BOOLEAN mgsl_register_test( struct mgsl_struct *info ) | 7002 | static bool mgsl_register_test( struct mgsl_struct *info ) |
7006 | { | 7003 | { |
7007 | static unsigned short BitPatterns[] = | 7004 | static unsigned short BitPatterns[] = |
7008 | { 0x0000, 0xffff, 0xaaaa, 0x5555, 0x1234, 0x6969, 0x9696, 0x0f0f }; | 7005 | { 0x0000, 0xffff, 0xaaaa, 0x5555, 0x1234, 0x6969, 0x9696, 0x0f0f }; |
7009 | static unsigned int Patterncount = ARRAY_SIZE(BitPatterns); | 7006 | static unsigned int Patterncount = ARRAY_SIZE(BitPatterns); |
7010 | unsigned int i; | 7007 | unsigned int i; |
7011 | BOOLEAN rc = TRUE; | 7008 | bool rc = true; |
7012 | unsigned long flags; | 7009 | unsigned long flags; |
7013 | 7010 | ||
7014 | spin_lock_irqsave(&info->irq_spinlock,flags); | 7011 | spin_lock_irqsave(&info->irq_spinlock,flags); |
@@ -7019,10 +7016,10 @@ static BOOLEAN mgsl_register_test( struct mgsl_struct *info ) | |||
7019 | if ( (usc_InReg( info, SICR ) != 0) || | 7016 | if ( (usc_InReg( info, SICR ) != 0) || |
7020 | (usc_InReg( info, IVR ) != 0) || | 7017 | (usc_InReg( info, IVR ) != 0) || |
7021 | (usc_InDmaReg( info, DIVR ) != 0) ){ | 7018 | (usc_InDmaReg( info, DIVR ) != 0) ){ |
7022 | rc = FALSE; | 7019 | rc = false; |
7023 | } | 7020 | } |
7024 | 7021 | ||
7025 | if ( rc == TRUE ){ | 7022 | if ( rc ){ |
7026 | /* Write bit patterns to various registers but do it out of */ | 7023 | /* Write bit patterns to various registers but do it out of */ |
7027 | /* sync, then read back and verify values. */ | 7024 | /* sync, then read back and verify values. */ |
7028 | 7025 | ||
@@ -7040,7 +7037,7 @@ static BOOLEAN mgsl_register_test( struct mgsl_struct *info ) | |||
7040 | (usc_InReg( info, RCLR ) != BitPatterns[(i+3)%Patterncount]) || | 7037 | (usc_InReg( info, RCLR ) != BitPatterns[(i+3)%Patterncount]) || |
7041 | (usc_InReg( info, RSR ) != BitPatterns[(i+4)%Patterncount]) || | 7038 | (usc_InReg( info, RSR ) != BitPatterns[(i+4)%Patterncount]) || |
7042 | (usc_InDmaReg( info, TBCR ) != BitPatterns[(i+5)%Patterncount]) ){ | 7039 | (usc_InDmaReg( info, TBCR ) != BitPatterns[(i+5)%Patterncount]) ){ |
7043 | rc = FALSE; | 7040 | rc = false; |
7044 | break; | 7041 | break; |
7045 | } | 7042 | } |
7046 | } | 7043 | } |
@@ -7056,9 +7053,9 @@ static BOOLEAN mgsl_register_test( struct mgsl_struct *info ) | |||
7056 | /* mgsl_irq_test() Perform interrupt test of the 16C32. | 7053 | /* mgsl_irq_test() Perform interrupt test of the 16C32. |
7057 | * | 7054 | * |
7058 | * Arguments: info pointer to device instance data | 7055 | * Arguments: info pointer to device instance data |
7059 | * Return Value: TRUE if test passed, otherwise FALSE | 7056 | * Return Value: true if test passed, otherwise false |
7060 | */ | 7057 | */ |
7061 | static BOOLEAN mgsl_irq_test( struct mgsl_struct *info ) | 7058 | static bool mgsl_irq_test( struct mgsl_struct *info ) |
7062 | { | 7059 | { |
7063 | unsigned long EndTime; | 7060 | unsigned long EndTime; |
7064 | unsigned long flags; | 7061 | unsigned long flags; |
@@ -7068,10 +7065,10 @@ static BOOLEAN mgsl_irq_test( struct mgsl_struct *info ) | |||
7068 | 7065 | ||
7069 | /* | 7066 | /* |
7070 | * Setup 16C32 to interrupt on TxC pin (14MHz clock) transition. | 7067 | * Setup 16C32 to interrupt on TxC pin (14MHz clock) transition. |
7071 | * The ISR sets irq_occurred to 1. | 7068 | * The ISR sets irq_occurred to true. |
7072 | */ | 7069 | */ |
7073 | 7070 | ||
7074 | info->irq_occurred = FALSE; | 7071 | info->irq_occurred = false; |
7075 | 7072 | ||
7076 | /* Enable INTEN gate for ISA adapter (Port 6, Bit12) */ | 7073 | /* Enable INTEN gate for ISA adapter (Port 6, Bit12) */ |
7077 | /* Enable INTEN (Port 6, Bit12) */ | 7074 | /* Enable INTEN (Port 6, Bit12) */ |
@@ -7097,10 +7094,7 @@ static BOOLEAN mgsl_irq_test( struct mgsl_struct *info ) | |||
7097 | usc_reset(info); | 7094 | usc_reset(info); |
7098 | spin_unlock_irqrestore(&info->irq_spinlock,flags); | 7095 | spin_unlock_irqrestore(&info->irq_spinlock,flags); |
7099 | 7096 | ||
7100 | if ( !info->irq_occurred ) | 7097 | return info->irq_occurred; |
7101 | return FALSE; | ||
7102 | else | ||
7103 | return TRUE; | ||
7104 | 7098 | ||
7105 | } /* end of mgsl_irq_test() */ | 7099 | } /* end of mgsl_irq_test() */ |
7106 | 7100 | ||
@@ -7111,16 +7105,16 @@ static BOOLEAN mgsl_irq_test( struct mgsl_struct *info ) | |||
7111 | * using single buffer DMA mode. | 7105 | * using single buffer DMA mode. |
7112 | * | 7106 | * |
7113 | * Arguments: info pointer to device instance data | 7107 | * Arguments: info pointer to device instance data |
7114 | * Return Value: TRUE if test passed, otherwise FALSE | 7108 | * Return Value: true if test passed, otherwise false |
7115 | */ | 7109 | */ |
7116 | static BOOLEAN mgsl_dma_test( struct mgsl_struct *info ) | 7110 | static bool mgsl_dma_test( struct mgsl_struct *info ) |
7117 | { | 7111 | { |
7118 | unsigned short FifoLevel; | 7112 | unsigned short FifoLevel; |
7119 | unsigned long phys_addr; | 7113 | unsigned long phys_addr; |
7120 | unsigned int FrameSize; | 7114 | unsigned int FrameSize; |
7121 | unsigned int i; | 7115 | unsigned int i; |
7122 | char *TmpPtr; | 7116 | char *TmpPtr; |
7123 | BOOLEAN rc = TRUE; | 7117 | bool rc = true; |
7124 | unsigned short status=0; | 7118 | unsigned short status=0; |
7125 | unsigned long EndTime; | 7119 | unsigned long EndTime; |
7126 | unsigned long flags; | 7120 | unsigned long flags; |
@@ -7233,7 +7227,7 @@ static BOOLEAN mgsl_dma_test( struct mgsl_struct *info ) | |||
7233 | 7227 | ||
7234 | for(;;) { | 7228 | for(;;) { |
7235 | if (time_after(jiffies, EndTime)) { | 7229 | if (time_after(jiffies, EndTime)) { |
7236 | rc = FALSE; | 7230 | rc = false; |
7237 | break; | 7231 | break; |
7238 | } | 7232 | } |
7239 | 7233 | ||
@@ -7289,7 +7283,7 @@ static BOOLEAN mgsl_dma_test( struct mgsl_struct *info ) | |||
7289 | 7283 | ||
7290 | for(;;) { | 7284 | for(;;) { |
7291 | if (time_after(jiffies, EndTime)) { | 7285 | if (time_after(jiffies, EndTime)) { |
7292 | rc = FALSE; | 7286 | rc = false; |
7293 | break; | 7287 | break; |
7294 | } | 7288 | } |
7295 | 7289 | ||
@@ -7309,7 +7303,7 @@ static BOOLEAN mgsl_dma_test( struct mgsl_struct *info ) | |||
7309 | } | 7303 | } |
7310 | 7304 | ||
7311 | 7305 | ||
7312 | if ( rc == TRUE ) | 7306 | if ( rc ) |
7313 | { | 7307 | { |
7314 | /* Enable 16C32 transmitter. */ | 7308 | /* Enable 16C32 transmitter. */ |
7315 | 7309 | ||
@@ -7337,7 +7331,7 @@ static BOOLEAN mgsl_dma_test( struct mgsl_struct *info ) | |||
7337 | 7331 | ||
7338 | while ( !(status & (BIT6+BIT5+BIT4+BIT2+BIT1)) ) { | 7332 | while ( !(status & (BIT6+BIT5+BIT4+BIT2+BIT1)) ) { |
7339 | if (time_after(jiffies, EndTime)) { | 7333 | if (time_after(jiffies, EndTime)) { |
7340 | rc = FALSE; | 7334 | rc = false; |
7341 | break; | 7335 | break; |
7342 | } | 7336 | } |
7343 | 7337 | ||
@@ -7348,13 +7342,13 @@ static BOOLEAN mgsl_dma_test( struct mgsl_struct *info ) | |||
7348 | } | 7342 | } |
7349 | 7343 | ||
7350 | 7344 | ||
7351 | if ( rc == TRUE ){ | 7345 | if ( rc ){ |
7352 | /* CHECK FOR TRANSMIT ERRORS */ | 7346 | /* CHECK FOR TRANSMIT ERRORS */ |
7353 | if ( status & (BIT5 + BIT1) ) | 7347 | if ( status & (BIT5 + BIT1) ) |
7354 | rc = FALSE; | 7348 | rc = false; |
7355 | } | 7349 | } |
7356 | 7350 | ||
7357 | if ( rc == TRUE ) { | 7351 | if ( rc ) { |
7358 | /* WAIT FOR RECEIVE COMPLETE */ | 7352 | /* WAIT FOR RECEIVE COMPLETE */ |
7359 | 7353 | ||
7360 | /* Wait 100ms */ | 7354 | /* Wait 100ms */ |
@@ -7364,7 +7358,7 @@ static BOOLEAN mgsl_dma_test( struct mgsl_struct *info ) | |||
7364 | status=info->rx_buffer_list[0].status; | 7358 | status=info->rx_buffer_list[0].status; |
7365 | while ( status == 0 ) { | 7359 | while ( status == 0 ) { |
7366 | if (time_after(jiffies, EndTime)) { | 7360 | if (time_after(jiffies, EndTime)) { |
7367 | rc = FALSE; | 7361 | rc = false; |
7368 | break; | 7362 | break; |
7369 | } | 7363 | } |
7370 | status=info->rx_buffer_list[0].status; | 7364 | status=info->rx_buffer_list[0].status; |
@@ -7372,17 +7366,17 @@ static BOOLEAN mgsl_dma_test( struct mgsl_struct *info ) | |||
7372 | } | 7366 | } |
7373 | 7367 | ||
7374 | 7368 | ||
7375 | if ( rc == TRUE ) { | 7369 | if ( rc ) { |
7376 | /* CHECK FOR RECEIVE ERRORS */ | 7370 | /* CHECK FOR RECEIVE ERRORS */ |
7377 | status = info->rx_buffer_list[0].status; | 7371 | status = info->rx_buffer_list[0].status; |
7378 | 7372 | ||
7379 | if ( status & (BIT8 + BIT3 + BIT1) ) { | 7373 | if ( status & (BIT8 + BIT3 + BIT1) ) { |
7380 | /* receive error has occurred */ | 7374 | /* receive error has occurred */ |
7381 | rc = FALSE; | 7375 | rc = false; |
7382 | } else { | 7376 | } else { |
7383 | if ( memcmp( info->tx_buffer_list[0].virt_addr , | 7377 | if ( memcmp( info->tx_buffer_list[0].virt_addr , |
7384 | info->rx_buffer_list[0].virt_addr, FrameSize ) ){ | 7378 | info->rx_buffer_list[0].virt_addr, FrameSize ) ){ |
7385 | rc = FALSE; | 7379 | rc = false; |
7386 | } | 7380 | } |
7387 | } | 7381 | } |
7388 | } | 7382 | } |
@@ -7445,9 +7439,9 @@ static int mgsl_adapter_test( struct mgsl_struct *info ) | |||
7445 | * Test the shared memory on a PCI adapter. | 7439 | * Test the shared memory on a PCI adapter. |
7446 | * | 7440 | * |
7447 | * Arguments: info pointer to device instance data | 7441 | * Arguments: info pointer to device instance data |
7448 | * Return Value: TRUE if test passed, otherwise FALSE | 7442 | * Return Value: true if test passed, otherwise false |
7449 | */ | 7443 | */ |
7450 | static BOOLEAN mgsl_memory_test( struct mgsl_struct *info ) | 7444 | static bool mgsl_memory_test( struct mgsl_struct *info ) |
7451 | { | 7445 | { |
7452 | static unsigned long BitPatterns[] = | 7446 | static unsigned long BitPatterns[] = |
7453 | { 0x0, 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999, 0xffffffff, 0x12345678 }; | 7447 | { 0x0, 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999, 0xffffffff, 0x12345678 }; |
@@ -7457,7 +7451,7 @@ static BOOLEAN mgsl_memory_test( struct mgsl_struct *info ) | |||
7457 | unsigned long * TestAddr; | 7451 | unsigned long * TestAddr; |
7458 | 7452 | ||
7459 | if ( info->bus_type != MGSL_BUS_TYPE_PCI ) | 7453 | if ( info->bus_type != MGSL_BUS_TYPE_PCI ) |
7460 | return TRUE; | 7454 | return true; |
7461 | 7455 | ||
7462 | TestAddr = (unsigned long *)info->memory_base; | 7456 | TestAddr = (unsigned long *)info->memory_base; |
7463 | 7457 | ||
@@ -7466,7 +7460,7 @@ static BOOLEAN mgsl_memory_test( struct mgsl_struct *info ) | |||
7466 | for ( i = 0 ; i < Patterncount ; i++ ) { | 7460 | for ( i = 0 ; i < Patterncount ; i++ ) { |
7467 | *TestAddr = BitPatterns[i]; | 7461 | *TestAddr = BitPatterns[i]; |
7468 | if ( *TestAddr != BitPatterns[i] ) | 7462 | if ( *TestAddr != BitPatterns[i] ) |
7469 | return FALSE; | 7463 | return false; |
7470 | } | 7464 | } |
7471 | 7465 | ||
7472 | /* Test address lines with incrementing pattern over */ | 7466 | /* Test address lines with incrementing pattern over */ |
@@ -7481,13 +7475,13 @@ static BOOLEAN mgsl_memory_test( struct mgsl_struct *info ) | |||
7481 | 7475 | ||
7482 | for ( i = 0 ; i < TestLimit ; i++ ) { | 7476 | for ( i = 0 ; i < TestLimit ; i++ ) { |
7483 | if ( *TestAddr != i * 4 ) | 7477 | if ( *TestAddr != i * 4 ) |
7484 | return FALSE; | 7478 | return false; |
7485 | TestAddr++; | 7479 | TestAddr++; |
7486 | } | 7480 | } |
7487 | 7481 | ||
7488 | memset( info->memory_base, 0, SHARED_MEM_ADDRESS_SIZE ); | 7482 | memset( info->memory_base, 0, SHARED_MEM_ADDRESS_SIZE ); |
7489 | 7483 | ||
7490 | return TRUE; | 7484 | return true; |
7491 | 7485 | ||
7492 | } /* End Of mgsl_memory_test() */ | 7486 | } /* End Of mgsl_memory_test() */ |
7493 | 7487 | ||
@@ -7604,7 +7598,7 @@ static void mgsl_tx_timeout(unsigned long context) | |||
7604 | info->icount.txtimeout++; | 7598 | info->icount.txtimeout++; |
7605 | } | 7599 | } |
7606 | spin_lock_irqsave(&info->irq_spinlock,flags); | 7600 | spin_lock_irqsave(&info->irq_spinlock,flags); |
7607 | info->tx_active = 0; | 7601 | info->tx_active = false; |
7608 | info->xmit_cnt = info->xmit_head = info->xmit_tail = 0; | 7602 | info->xmit_cnt = info->xmit_head = info->xmit_tail = 0; |
7609 | 7603 | ||
7610 | if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE ) | 7604 | if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE ) |
@@ -7632,7 +7626,7 @@ static int mgsl_loopmode_send_done( struct mgsl_struct * info ) | |||
7632 | spin_lock_irqsave(&info->irq_spinlock,flags); | 7626 | spin_lock_irqsave(&info->irq_spinlock,flags); |
7633 | if (info->params.flags & HDLC_FLAG_HDLC_LOOPMODE) { | 7627 | if (info->params.flags & HDLC_FLAG_HDLC_LOOPMODE) { |
7634 | if (info->tx_active) | 7628 | if (info->tx_active) |
7635 | info->loopmode_send_done_requested = TRUE; | 7629 | info->loopmode_send_done_requested = true; |
7636 | else | 7630 | else |
7637 | usc_loopmode_send_done(info); | 7631 | usc_loopmode_send_done(info); |
7638 | } | 7632 | } |
@@ -7646,7 +7640,7 @@ static int mgsl_loopmode_send_done( struct mgsl_struct * info ) | |||
7646 | */ | 7640 | */ |
7647 | static void usc_loopmode_send_done( struct mgsl_struct * info ) | 7641 | static void usc_loopmode_send_done( struct mgsl_struct * info ) |
7648 | { | 7642 | { |
7649 | info->loopmode_send_done_requested = FALSE; | 7643 | info->loopmode_send_done_requested = false; |
7650 | /* clear CMR:13 to 0 to start echoing RxData to TxData */ | 7644 | /* clear CMR:13 to 0 to start echoing RxData to TxData */ |
7651 | info->cmr_value &= ~BIT13; | 7645 | info->cmr_value &= ~BIT13; |
7652 | usc_OutReg(info, CMR, info->cmr_value); | 7646 | usc_OutReg(info, CMR, info->cmr_value); |
@@ -7668,7 +7662,7 @@ static void usc_loopmode_cancel_transmit( struct mgsl_struct * info ) | |||
7668 | */ | 7662 | */ |
7669 | static void usc_loopmode_insert_request( struct mgsl_struct * info ) | 7663 | static void usc_loopmode_insert_request( struct mgsl_struct * info ) |
7670 | { | 7664 | { |
7671 | info->loopmode_insert_requested = TRUE; | 7665 | info->loopmode_insert_requested = true; |
7672 | 7666 | ||
7673 | /* enable RxAbort irq. On next RxAbort, clear CMR:13 to | 7667 | /* enable RxAbort irq. On next RxAbort, clear CMR:13 to |
7674 | * begin repeating TxData on RxData (complete insertion) | 7668 | * begin repeating TxData on RxData (complete insertion) |