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-rw-r--r--arch/arm/include/asm/smp_scu.h8
-rw-r--r--arch/arm/kernel/smp_scu.c2
-rw-r--r--arch/arm/mach-highbank/highbank.c3
-rw-r--r--arch/arm/mach-highbank/sysregs.h4
-rw-r--r--arch/arm/net/bpf_jit_32.c15
-rw-r--r--arch/m68k/include/asm/processor.h1
-rw-r--r--arch/s390/kernel/time.c3
-rw-r--r--arch/tile/Kconfig2
-rw-r--r--arch/tile/include/asm/io.h6
-rw-r--r--arch/tile/include/asm/irqflags.h32
-rw-r--r--arch/tile/include/uapi/arch/interrupts_32.h394
-rw-r--r--arch/tile/include/uapi/arch/interrupts_64.h346
-rw-r--r--arch/tile/kernel/intvec_64.S4
-rw-r--r--arch/tile/kernel/process.c2
-rw-r--r--arch/tile/kernel/reboot.c2
-rw-r--r--arch/tile/kernel/setup.c5
-rw-r--r--arch/tile/kernel/stack.c3
-rw-r--r--arch/tile/lib/cacheflush.c2
-rw-r--r--arch/tile/lib/cpumask.c2
-rw-r--r--arch/tile/lib/exports.c2
-rw-r--r--arch/tile/mm/homecache.c1
-rw-r--r--arch/x86/include/asm/mce.h84
-rw-r--r--arch/x86/include/asm/pgtable.h5
-rw-r--r--arch/x86/include/uapi/asm/mce.h87
-rw-r--r--arch/x86/kernel/apic/x2apic_phys.c21
-rw-r--r--arch/x86/mm/fault.c8
-rw-r--r--arch/x86/mm/init_64.c3
27 files changed, 544 insertions, 503 deletions
diff --git a/arch/arm/include/asm/smp_scu.h b/arch/arm/include/asm/smp_scu.h
index 4eb6d005ffaa..86dff32a0737 100644
--- a/arch/arm/include/asm/smp_scu.h
+++ b/arch/arm/include/asm/smp_scu.h
@@ -7,8 +7,14 @@
7 7
8#ifndef __ASSEMBLER__ 8#ifndef __ASSEMBLER__
9unsigned int scu_get_core_count(void __iomem *); 9unsigned int scu_get_core_count(void __iomem *);
10void scu_enable(void __iomem *);
11int scu_power_mode(void __iomem *, unsigned int); 10int scu_power_mode(void __iomem *, unsigned int);
11
12#ifdef CONFIG_SMP
13void scu_enable(void __iomem *scu_base);
14#else
15static inline void scu_enable(void __iomem *scu_base) {}
16#endif
17
12#endif 18#endif
13 19
14#endif 20#endif
diff --git a/arch/arm/kernel/smp_scu.c b/arch/arm/kernel/smp_scu.c
index b9f015e843d8..45eac87ed66a 100644
--- a/arch/arm/kernel/smp_scu.c
+++ b/arch/arm/kernel/smp_scu.c
@@ -75,7 +75,7 @@ void scu_enable(void __iomem *scu_base)
75int scu_power_mode(void __iomem *scu_base, unsigned int mode) 75int scu_power_mode(void __iomem *scu_base, unsigned int mode)
76{ 76{
77 unsigned int val; 77 unsigned int val;
78 int cpu = cpu_logical_map(smp_processor_id()); 78 int cpu = MPIDR_AFFINITY_LEVEL(cpu_logical_map(smp_processor_id()), 0);
79 79
80 if (mode > 3 || mode == 1 || cpu > 3) 80 if (mode > 3 || mode == 1 || cpu > 3)
81 return -EINVAL; 81 return -EINVAL;
diff --git a/arch/arm/mach-highbank/highbank.c b/arch/arm/mach-highbank/highbank.c
index 981dc1e1da51..e6c061282939 100644
--- a/arch/arm/mach-highbank/highbank.c
+++ b/arch/arm/mach-highbank/highbank.c
@@ -28,6 +28,7 @@
28 28
29#include <asm/arch_timer.h> 29#include <asm/arch_timer.h>
30#include <asm/cacheflush.h> 30#include <asm/cacheflush.h>
31#include <asm/cputype.h>
31#include <asm/smp_plat.h> 32#include <asm/smp_plat.h>
32#include <asm/smp_twd.h> 33#include <asm/smp_twd.h>
33#include <asm/hardware/arm_timer.h> 34#include <asm/hardware/arm_timer.h>
@@ -59,7 +60,7 @@ static void __init highbank_scu_map_io(void)
59 60
60void highbank_set_cpu_jump(int cpu, void *jump_addr) 61void highbank_set_cpu_jump(int cpu, void *jump_addr)
61{ 62{
62 cpu = cpu_logical_map(cpu); 63 cpu = MPIDR_AFFINITY_LEVEL(cpu_logical_map(cpu), 0);
63 writel(virt_to_phys(jump_addr), HB_JUMP_TABLE_VIRT(cpu)); 64 writel(virt_to_phys(jump_addr), HB_JUMP_TABLE_VIRT(cpu));
64 __cpuc_flush_dcache_area(HB_JUMP_TABLE_VIRT(cpu), 16); 65 __cpuc_flush_dcache_area(HB_JUMP_TABLE_VIRT(cpu), 16);
65 outer_clean_range(HB_JUMP_TABLE_PHYS(cpu), 66 outer_clean_range(HB_JUMP_TABLE_PHYS(cpu),
diff --git a/arch/arm/mach-highbank/sysregs.h b/arch/arm/mach-highbank/sysregs.h
index 70af9d13fcef..5995df7f2622 100644
--- a/arch/arm/mach-highbank/sysregs.h
+++ b/arch/arm/mach-highbank/sysregs.h
@@ -37,7 +37,7 @@ extern void __iomem *sregs_base;
37 37
38static inline void highbank_set_core_pwr(void) 38static inline void highbank_set_core_pwr(void)
39{ 39{
40 int cpu = cpu_logical_map(smp_processor_id()); 40 int cpu = MPIDR_AFFINITY_LEVEL(cpu_logical_map(smp_processor_id()), 0);
41 if (scu_base_addr) 41 if (scu_base_addr)
42 scu_power_mode(scu_base_addr, SCU_PM_POWEROFF); 42 scu_power_mode(scu_base_addr, SCU_PM_POWEROFF);
43 else 43 else
@@ -46,7 +46,7 @@ static inline void highbank_set_core_pwr(void)
46 46
47static inline void highbank_clear_core_pwr(void) 47static inline void highbank_clear_core_pwr(void)
48{ 48{
49 int cpu = cpu_logical_map(smp_processor_id()); 49 int cpu = MPIDR_AFFINITY_LEVEL(cpu_logical_map(smp_processor_id()), 0);
50 if (scu_base_addr) 50 if (scu_base_addr)
51 scu_power_mode(scu_base_addr, SCU_PM_NORMAL); 51 scu_power_mode(scu_base_addr, SCU_PM_NORMAL);
52 else 52 else
diff --git a/arch/arm/net/bpf_jit_32.c b/arch/arm/net/bpf_jit_32.c
index a34f1e214116..6828ef6ce80e 100644
--- a/arch/arm/net/bpf_jit_32.c
+++ b/arch/arm/net/bpf_jit_32.c
@@ -341,10 +341,17 @@ static void emit_load_be16(u8 cond, u8 r_res, u8 r_addr, struct jit_ctx *ctx)
341 341
342static inline void emit_swap16(u8 r_dst, u8 r_src, struct jit_ctx *ctx) 342static inline void emit_swap16(u8 r_dst, u8 r_src, struct jit_ctx *ctx)
343{ 343{
344 emit(ARM_LSL_R(ARM_R1, r_src, 8), ctx); 344 /* r_dst = (r_src << 8) | (r_src >> 8) */
345 emit(ARM_ORR_S(r_dst, ARM_R1, r_src, SRTYPE_LSL, 8), ctx); 345 emit(ARM_LSL_I(ARM_R1, r_src, 8), ctx);
346 emit(ARM_LSL_I(r_dst, r_dst, 8), ctx); 346 emit(ARM_ORR_S(r_dst, ARM_R1, r_src, SRTYPE_LSR, 8), ctx);
347 emit(ARM_LSL_R(r_dst, r_dst, 8), ctx); 347
348 /*
349 * we need to mask out the bits set in r_dst[23:16] due to
350 * the first shift instruction.
351 *
352 * note that 0x8ff is the encoded immediate 0x00ff0000.
353 */
354 emit(ARM_BIC_I(r_dst, r_dst, 0x8ff), ctx);
348} 355}
349 356
350#else /* ARMv6+ */ 357#else /* ARMv6+ */
diff --git a/arch/m68k/include/asm/processor.h b/arch/m68k/include/asm/processor.h
index ae700f49e51d..b0768a657920 100644
--- a/arch/m68k/include/asm/processor.h
+++ b/arch/m68k/include/asm/processor.h
@@ -130,7 +130,6 @@ extern int handle_kernel_fault(struct pt_regs *regs);
130#define start_thread(_regs, _pc, _usp) \ 130#define start_thread(_regs, _pc, _usp) \
131do { \ 131do { \
132 (_regs)->pc = (_pc); \ 132 (_regs)->pc = (_pc); \
133 ((struct switch_stack *)(_regs))[-1].a6 = 0; \
134 setframeformat(_regs); \ 133 setframeformat(_regs); \
135 if (current->mm) \ 134 if (current->mm) \
136 (_regs)->d5 = current->mm->start_data; \ 135 (_regs)->d5 = current->mm->start_data; \
diff --git a/arch/s390/kernel/time.c b/arch/s390/kernel/time.c
index a5f4f5a1d24b..0aa98db8a80d 100644
--- a/arch/s390/kernel/time.c
+++ b/arch/s390/kernel/time.c
@@ -120,6 +120,9 @@ static int s390_next_ktime(ktime_t expires,
120 nsecs = ktime_to_ns(ktime_add(timespec_to_ktime(ts), expires)); 120 nsecs = ktime_to_ns(ktime_add(timespec_to_ktime(ts), expires));
121 do_div(nsecs, 125); 121 do_div(nsecs, 125);
122 S390_lowcore.clock_comparator = sched_clock_base_cc + (nsecs << 9); 122 S390_lowcore.clock_comparator = sched_clock_base_cc + (nsecs << 9);
123 /* Program the maximum value if we have an overflow (== year 2042) */
124 if (unlikely(S390_lowcore.clock_comparator < sched_clock_base_cc))
125 S390_lowcore.clock_comparator = -1ULL;
123 set_clock_comparator(S390_lowcore.clock_comparator); 126 set_clock_comparator(S390_lowcore.clock_comparator);
124 return 0; 127 return 0;
125} 128}
diff --git a/arch/tile/Kconfig b/arch/tile/Kconfig
index 875d008828b8..1bb7ad4aeff4 100644
--- a/arch/tile/Kconfig
+++ b/arch/tile/Kconfig
@@ -140,6 +140,8 @@ config ARCH_DEFCONFIG
140 140
141source "init/Kconfig" 141source "init/Kconfig"
142 142
143source "kernel/Kconfig.freezer"
144
143menu "Tilera-specific configuration" 145menu "Tilera-specific configuration"
144 146
145config NR_CPUS 147config NR_CPUS
diff --git a/arch/tile/include/asm/io.h b/arch/tile/include/asm/io.h
index 2a9b293fece6..31672918064c 100644
--- a/arch/tile/include/asm/io.h
+++ b/arch/tile/include/asm/io.h
@@ -250,7 +250,9 @@ static inline void writeq(u64 val, unsigned long addr)
250#define iowrite32 writel 250#define iowrite32 writel
251#define iowrite64 writeq 251#define iowrite64 writeq
252 252
253static inline void memset_io(void *dst, int val, size_t len) 253#if CHIP_HAS_MMIO() || defined(CONFIG_PCI)
254
255static inline void memset_io(volatile void *dst, int val, size_t len)
254{ 256{
255 int x; 257 int x;
256 BUG_ON((unsigned long)dst & 0x3); 258 BUG_ON((unsigned long)dst & 0x3);
@@ -277,6 +279,8 @@ static inline void memcpy_toio(volatile void __iomem *dst, const void *src,
277 writel(*(u32 *)(src + x), dst + x); 279 writel(*(u32 *)(src + x), dst + x);
278} 280}
279 281
282#endif
283
280/* 284/*
281 * The Tile architecture does not support IOPORT, even with PCI. 285 * The Tile architecture does not support IOPORT, even with PCI.
282 * Unfortunately we can't yet simply not declare these methods, 286 * Unfortunately we can't yet simply not declare these methods,
diff --git a/arch/tile/include/asm/irqflags.h b/arch/tile/include/asm/irqflags.h
index b4e96fef2cf8..241c0bb60b12 100644
--- a/arch/tile/include/asm/irqflags.h
+++ b/arch/tile/include/asm/irqflags.h
@@ -18,32 +18,20 @@
18#include <arch/interrupts.h> 18#include <arch/interrupts.h>
19#include <arch/chip.h> 19#include <arch/chip.h>
20 20
21#if !defined(__tilegx__) && defined(__ASSEMBLY__)
22
23/* 21/*
24 * The set of interrupts we want to allow when interrupts are nominally 22 * The set of interrupts we want to allow when interrupts are nominally
25 * disabled. The remainder are effectively "NMI" interrupts from 23 * disabled. The remainder are effectively "NMI" interrupts from
26 * the point of view of the generic Linux code. Note that synchronous 24 * the point of view of the generic Linux code. Note that synchronous
27 * interrupts (aka "non-queued") are not blocked by the mask in any case. 25 * interrupts (aka "non-queued") are not blocked by the mask in any case.
28 */ 26 */
29#if CHIP_HAS_AUX_PERF_COUNTERS()
30#define LINUX_MASKABLE_INTERRUPTS_HI \
31 (~(INT_MASK_HI(INT_PERF_COUNT) | INT_MASK_HI(INT_AUX_PERF_COUNT)))
32#else
33#define LINUX_MASKABLE_INTERRUPTS_HI \
34 (~(INT_MASK_HI(INT_PERF_COUNT)))
35#endif
36
37#else
38
39#if CHIP_HAS_AUX_PERF_COUNTERS()
40#define LINUX_MASKABLE_INTERRUPTS \
41 (~(INT_MASK(INT_PERF_COUNT) | INT_MASK(INT_AUX_PERF_COUNT)))
42#else
43#define LINUX_MASKABLE_INTERRUPTS \ 27#define LINUX_MASKABLE_INTERRUPTS \
44 (~(INT_MASK(INT_PERF_COUNT))) 28 (~((_AC(1,ULL) << INT_PERF_COUNT) | (_AC(1,ULL) << INT_AUX_PERF_COUNT)))
45#endif
46 29
30#if CHIP_HAS_SPLIT_INTR_MASK()
31/* The same macro, but for the two 32-bit SPRs separately. */
32#define LINUX_MASKABLE_INTERRUPTS_LO (-1)
33#define LINUX_MASKABLE_INTERRUPTS_HI \
34 (~((1 << (INT_PERF_COUNT - 32)) | (1 << (INT_AUX_PERF_COUNT - 32))))
47#endif 35#endif
48 36
49#ifndef __ASSEMBLY__ 37#ifndef __ASSEMBLY__
@@ -126,7 +114,7 @@
126 * to know our current state. 114 * to know our current state.
127 */ 115 */
128DECLARE_PER_CPU(unsigned long long, interrupts_enabled_mask); 116DECLARE_PER_CPU(unsigned long long, interrupts_enabled_mask);
129#define INITIAL_INTERRUPTS_ENABLED INT_MASK(INT_MEM_ERROR) 117#define INITIAL_INTERRUPTS_ENABLED (1ULL << INT_MEM_ERROR)
130 118
131/* Disable interrupts. */ 119/* Disable interrupts. */
132#define arch_local_irq_disable() \ 120#define arch_local_irq_disable() \
@@ -165,7 +153,7 @@ DECLARE_PER_CPU(unsigned long long, interrupts_enabled_mask);
165 153
166/* Prevent the given interrupt from being enabled next time we enable irqs. */ 154/* Prevent the given interrupt from being enabled next time we enable irqs. */
167#define arch_local_irq_mask(interrupt) \ 155#define arch_local_irq_mask(interrupt) \
168 (__get_cpu_var(interrupts_enabled_mask) &= ~INT_MASK(interrupt)) 156 (__get_cpu_var(interrupts_enabled_mask) &= ~(1ULL << (interrupt)))
169 157
170/* Prevent the given interrupt from being enabled immediately. */ 158/* Prevent the given interrupt from being enabled immediately. */
171#define arch_local_irq_mask_now(interrupt) do { \ 159#define arch_local_irq_mask_now(interrupt) do { \
@@ -175,7 +163,7 @@ DECLARE_PER_CPU(unsigned long long, interrupts_enabled_mask);
175 163
176/* Allow the given interrupt to be enabled next time we enable irqs. */ 164/* Allow the given interrupt to be enabled next time we enable irqs. */
177#define arch_local_irq_unmask(interrupt) \ 165#define arch_local_irq_unmask(interrupt) \
178 (__get_cpu_var(interrupts_enabled_mask) |= INT_MASK(interrupt)) 166 (__get_cpu_var(interrupts_enabled_mask) |= (1ULL << (interrupt)))
179 167
180/* Allow the given interrupt to be enabled immediately, if !irqs_disabled. */ 168/* Allow the given interrupt to be enabled immediately, if !irqs_disabled. */
181#define arch_local_irq_unmask_now(interrupt) do { \ 169#define arch_local_irq_unmask_now(interrupt) do { \
@@ -250,7 +238,7 @@ DECLARE_PER_CPU(unsigned long long, interrupts_enabled_mask);
250/* Disable interrupts. */ 238/* Disable interrupts. */
251#define IRQ_DISABLE(tmp0, tmp1) \ 239#define IRQ_DISABLE(tmp0, tmp1) \
252 { \ 240 { \
253 movei tmp0, -1; \ 241 movei tmp0, LINUX_MASKABLE_INTERRUPTS_LO; \
254 moveli tmp1, lo16(LINUX_MASKABLE_INTERRUPTS_HI) \ 242 moveli tmp1, lo16(LINUX_MASKABLE_INTERRUPTS_HI) \
255 }; \ 243 }; \
256 { \ 244 { \
diff --git a/arch/tile/include/uapi/arch/interrupts_32.h b/arch/tile/include/uapi/arch/interrupts_32.h
index 96b5710505b6..2efe3f68b2d6 100644
--- a/arch/tile/include/uapi/arch/interrupts_32.h
+++ b/arch/tile/include/uapi/arch/interrupts_32.h
@@ -15,6 +15,7 @@
15#ifndef __ARCH_INTERRUPTS_H__ 15#ifndef __ARCH_INTERRUPTS_H__
16#define __ARCH_INTERRUPTS_H__ 16#define __ARCH_INTERRUPTS_H__
17 17
18#ifndef __KERNEL__
18/** Mask for an interrupt. */ 19/** Mask for an interrupt. */
19/* Note: must handle breaking interrupts into high and low words manually. */ 20/* Note: must handle breaking interrupts into high and low words manually. */
20#define INT_MASK_LO(intno) (1 << (intno)) 21#define INT_MASK_LO(intno) (1 << (intno))
@@ -23,6 +24,7 @@
23#ifndef __ASSEMBLER__ 24#ifndef __ASSEMBLER__
24#define INT_MASK(intno) (1ULL << (intno)) 25#define INT_MASK(intno) (1ULL << (intno))
25#endif 26#endif
27#endif
26 28
27 29
28/** Where a given interrupt executes */ 30/** Where a given interrupt executes */
@@ -92,216 +94,216 @@
92 94
93#ifndef __ASSEMBLER__ 95#ifndef __ASSEMBLER__
94#define QUEUED_INTERRUPTS ( \ 96#define QUEUED_INTERRUPTS ( \
95 INT_MASK(INT_MEM_ERROR) | \ 97 (1ULL << INT_MEM_ERROR) | \
96 INT_MASK(INT_DMATLB_MISS) | \ 98 (1ULL << INT_DMATLB_MISS) | \
97 INT_MASK(INT_DMATLB_ACCESS) | \ 99 (1ULL << INT_DMATLB_ACCESS) | \
98 INT_MASK(INT_SNITLB_MISS) | \ 100 (1ULL << INT_SNITLB_MISS) | \
99 INT_MASK(INT_SN_NOTIFY) | \ 101 (1ULL << INT_SN_NOTIFY) | \
100 INT_MASK(INT_SN_FIREWALL) | \ 102 (1ULL << INT_SN_FIREWALL) | \
101 INT_MASK(INT_IDN_FIREWALL) | \ 103 (1ULL << INT_IDN_FIREWALL) | \
102 INT_MASK(INT_UDN_FIREWALL) | \ 104 (1ULL << INT_UDN_FIREWALL) | \
103 INT_MASK(INT_TILE_TIMER) | \ 105 (1ULL << INT_TILE_TIMER) | \
104 INT_MASK(INT_IDN_TIMER) | \ 106 (1ULL << INT_IDN_TIMER) | \
105 INT_MASK(INT_UDN_TIMER) | \ 107 (1ULL << INT_UDN_TIMER) | \
106 INT_MASK(INT_DMA_NOTIFY) | \ 108 (1ULL << INT_DMA_NOTIFY) | \
107 INT_MASK(INT_IDN_CA) | \ 109 (1ULL << INT_IDN_CA) | \
108 INT_MASK(INT_UDN_CA) | \ 110 (1ULL << INT_UDN_CA) | \
109 INT_MASK(INT_IDN_AVAIL) | \ 111 (1ULL << INT_IDN_AVAIL) | \
110 INT_MASK(INT_UDN_AVAIL) | \ 112 (1ULL << INT_UDN_AVAIL) | \
111 INT_MASK(INT_PERF_COUNT) | \ 113 (1ULL << INT_PERF_COUNT) | \
112 INT_MASK(INT_INTCTRL_3) | \ 114 (1ULL << INT_INTCTRL_3) | \
113 INT_MASK(INT_INTCTRL_2) | \ 115 (1ULL << INT_INTCTRL_2) | \
114 INT_MASK(INT_INTCTRL_1) | \ 116 (1ULL << INT_INTCTRL_1) | \
115 INT_MASK(INT_INTCTRL_0) | \ 117 (1ULL << INT_INTCTRL_0) | \
116 INT_MASK(INT_BOOT_ACCESS) | \ 118 (1ULL << INT_BOOT_ACCESS) | \
117 INT_MASK(INT_WORLD_ACCESS) | \ 119 (1ULL << INT_WORLD_ACCESS) | \
118 INT_MASK(INT_I_ASID) | \ 120 (1ULL << INT_I_ASID) | \
119 INT_MASK(INT_D_ASID) | \ 121 (1ULL << INT_D_ASID) | \
120 INT_MASK(INT_DMA_ASID) | \ 122 (1ULL << INT_DMA_ASID) | \
121 INT_MASK(INT_SNI_ASID) | \ 123 (1ULL << INT_SNI_ASID) | \
122 INT_MASK(INT_DMA_CPL) | \ 124 (1ULL << INT_DMA_CPL) | \
123 INT_MASK(INT_SN_CPL) | \ 125 (1ULL << INT_SN_CPL) | \
124 INT_MASK(INT_DOUBLE_FAULT) | \ 126 (1ULL << INT_DOUBLE_FAULT) | \
125 INT_MASK(INT_AUX_PERF_COUNT) | \ 127 (1ULL << INT_AUX_PERF_COUNT) | \
126 0) 128 0)
127#define NONQUEUED_INTERRUPTS ( \ 129#define NONQUEUED_INTERRUPTS ( \
128 INT_MASK(INT_ITLB_MISS) | \ 130 (1ULL << INT_ITLB_MISS) | \
129 INT_MASK(INT_ILL) | \ 131 (1ULL << INT_ILL) | \
130 INT_MASK(INT_GPV) | \ 132 (1ULL << INT_GPV) | \
131 INT_MASK(INT_SN_ACCESS) | \ 133 (1ULL << INT_SN_ACCESS) | \
132 INT_MASK(INT_IDN_ACCESS) | \ 134 (1ULL << INT_IDN_ACCESS) | \
133 INT_MASK(INT_UDN_ACCESS) | \ 135 (1ULL << INT_UDN_ACCESS) | \
134 INT_MASK(INT_IDN_REFILL) | \ 136 (1ULL << INT_IDN_REFILL) | \
135 INT_MASK(INT_UDN_REFILL) | \ 137 (1ULL << INT_UDN_REFILL) | \
136 INT_MASK(INT_IDN_COMPLETE) | \ 138 (1ULL << INT_IDN_COMPLETE) | \
137 INT_MASK(INT_UDN_COMPLETE) | \ 139 (1ULL << INT_UDN_COMPLETE) | \
138 INT_MASK(INT_SWINT_3) | \ 140 (1ULL << INT_SWINT_3) | \
139 INT_MASK(INT_SWINT_2) | \ 141 (1ULL << INT_SWINT_2) | \
140 INT_MASK(INT_SWINT_1) | \ 142 (1ULL << INT_SWINT_1) | \
141 INT_MASK(INT_SWINT_0) | \ 143 (1ULL << INT_SWINT_0) | \
142 INT_MASK(INT_UNALIGN_DATA) | \ 144 (1ULL << INT_UNALIGN_DATA) | \
143 INT_MASK(INT_DTLB_MISS) | \ 145 (1ULL << INT_DTLB_MISS) | \
144 INT_MASK(INT_DTLB_ACCESS) | \ 146 (1ULL << INT_DTLB_ACCESS) | \
145 INT_MASK(INT_SN_STATIC_ACCESS) | \ 147 (1ULL << INT_SN_STATIC_ACCESS) | \
146 0) 148 0)
147#define CRITICAL_MASKED_INTERRUPTS ( \ 149#define CRITICAL_MASKED_INTERRUPTS ( \
148 INT_MASK(INT_MEM_ERROR) | \ 150 (1ULL << INT_MEM_ERROR) | \
149 INT_MASK(INT_DMATLB_MISS) | \ 151 (1ULL << INT_DMATLB_MISS) | \
150 INT_MASK(INT_DMATLB_ACCESS) | \ 152 (1ULL << INT_DMATLB_ACCESS) | \
151 INT_MASK(INT_SNITLB_MISS) | \ 153 (1ULL << INT_SNITLB_MISS) | \
152 INT_MASK(INT_SN_NOTIFY) | \ 154 (1ULL << INT_SN_NOTIFY) | \
153 INT_MASK(INT_SN_FIREWALL) | \ 155 (1ULL << INT_SN_FIREWALL) | \
154 INT_MASK(INT_IDN_FIREWALL) | \ 156 (1ULL << INT_IDN_FIREWALL) | \
155 INT_MASK(INT_UDN_FIREWALL) | \ 157 (1ULL << INT_UDN_FIREWALL) | \
156 INT_MASK(INT_TILE_TIMER) | \ 158 (1ULL << INT_TILE_TIMER) | \
157 INT_MASK(INT_IDN_TIMER) | \ 159 (1ULL << INT_IDN_TIMER) | \
158 INT_MASK(INT_UDN_TIMER) | \ 160 (1ULL << INT_UDN_TIMER) | \
159 INT_MASK(INT_DMA_NOTIFY) | \ 161 (1ULL << INT_DMA_NOTIFY) | \
160 INT_MASK(INT_IDN_CA) | \ 162 (1ULL << INT_IDN_CA) | \
161 INT_MASK(INT_UDN_CA) | \ 163 (1ULL << INT_UDN_CA) | \
162 INT_MASK(INT_IDN_AVAIL) | \ 164 (1ULL << INT_IDN_AVAIL) | \
163 INT_MASK(INT_UDN_AVAIL) | \ 165 (1ULL << INT_UDN_AVAIL) | \
164 INT_MASK(INT_PERF_COUNT) | \ 166 (1ULL << INT_PERF_COUNT) | \
165 INT_MASK(INT_INTCTRL_3) | \ 167 (1ULL << INT_INTCTRL_3) | \
166 INT_MASK(INT_INTCTRL_2) | \ 168 (1ULL << INT_INTCTRL_2) | \
167 INT_MASK(INT_INTCTRL_1) | \ 169 (1ULL << INT_INTCTRL_1) | \
168 INT_MASK(INT_INTCTRL_0) | \ 170 (1ULL << INT_INTCTRL_0) | \
169 INT_MASK(INT_AUX_PERF_COUNT) | \ 171 (1ULL << INT_AUX_PERF_COUNT) | \
170 0) 172 0)
171#define CRITICAL_UNMASKED_INTERRUPTS ( \ 173#define CRITICAL_UNMASKED_INTERRUPTS ( \
172 INT_MASK(INT_ITLB_MISS) | \ 174 (1ULL << INT_ITLB_MISS) | \
173 INT_MASK(INT_ILL) | \ 175 (1ULL << INT_ILL) | \
174 INT_MASK(INT_GPV) | \ 176 (1ULL << INT_GPV) | \
175 INT_MASK(INT_SN_ACCESS) | \ 177 (1ULL << INT_SN_ACCESS) | \
176 INT_MASK(INT_IDN_ACCESS) | \ 178 (1ULL << INT_IDN_ACCESS) | \
177 INT_MASK(INT_UDN_ACCESS) | \ 179 (1ULL << INT_UDN_ACCESS) | \
178 INT_MASK(INT_IDN_REFILL) | \ 180 (1ULL << INT_IDN_REFILL) | \
179 INT_MASK(INT_UDN_REFILL) | \ 181 (1ULL << INT_UDN_REFILL) | \
180 INT_MASK(INT_IDN_COMPLETE) | \ 182 (1ULL << INT_IDN_COMPLETE) | \
181 INT_MASK(INT_UDN_COMPLETE) | \ 183 (1ULL << INT_UDN_COMPLETE) | \
182 INT_MASK(INT_SWINT_3) | \ 184 (1ULL << INT_SWINT_3) | \
183 INT_MASK(INT_SWINT_2) | \ 185 (1ULL << INT_SWINT_2) | \
184 INT_MASK(INT_SWINT_1) | \ 186 (1ULL << INT_SWINT_1) | \
185 INT_MASK(INT_SWINT_0) | \ 187 (1ULL << INT_SWINT_0) | \
186 INT_MASK(INT_UNALIGN_DATA) | \ 188 (1ULL << INT_UNALIGN_DATA) | \
187 INT_MASK(INT_DTLB_MISS) | \ 189 (1ULL << INT_DTLB_MISS) | \
188 INT_MASK(INT_DTLB_ACCESS) | \ 190 (1ULL << INT_DTLB_ACCESS) | \
189 INT_MASK(INT_BOOT_ACCESS) | \ 191 (1ULL << INT_BOOT_ACCESS) | \
190 INT_MASK(INT_WORLD_ACCESS) | \ 192 (1ULL << INT_WORLD_ACCESS) | \
191 INT_MASK(INT_I_ASID) | \ 193 (1ULL << INT_I_ASID) | \
192 INT_MASK(INT_D_ASID) | \ 194 (1ULL << INT_D_ASID) | \
193 INT_MASK(INT_DMA_ASID) | \ 195 (1ULL << INT_DMA_ASID) | \
194 INT_MASK(INT_SNI_ASID) | \ 196 (1ULL << INT_SNI_ASID) | \
195 INT_MASK(INT_DMA_CPL) | \ 197 (1ULL << INT_DMA_CPL) | \
196 INT_MASK(INT_SN_CPL) | \ 198 (1ULL << INT_SN_CPL) | \
197 INT_MASK(INT_DOUBLE_FAULT) | \ 199 (1ULL << INT_DOUBLE_FAULT) | \
198 INT_MASK(INT_SN_STATIC_ACCESS) | \ 200 (1ULL << INT_SN_STATIC_ACCESS) | \
199 0) 201 0)
200#define MASKABLE_INTERRUPTS ( \ 202#define MASKABLE_INTERRUPTS ( \
201 INT_MASK(INT_MEM_ERROR) | \ 203 (1ULL << INT_MEM_ERROR) | \
202 INT_MASK(INT_IDN_REFILL) | \ 204 (1ULL << INT_IDN_REFILL) | \
203 INT_MASK(INT_UDN_REFILL) | \ 205 (1ULL << INT_UDN_REFILL) | \
204 INT_MASK(INT_IDN_COMPLETE) | \ 206 (1ULL << INT_IDN_COMPLETE) | \
205 INT_MASK(INT_UDN_COMPLETE) | \ 207 (1ULL << INT_UDN_COMPLETE) | \
206 INT_MASK(INT_DMATLB_MISS) | \ 208 (1ULL << INT_DMATLB_MISS) | \
207 INT_MASK(INT_DMATLB_ACCESS) | \ 209 (1ULL << INT_DMATLB_ACCESS) | \
208 INT_MASK(INT_SNITLB_MISS) | \ 210 (1ULL << INT_SNITLB_MISS) | \
209 INT_MASK(INT_SN_NOTIFY) | \ 211 (1ULL << INT_SN_NOTIFY) | \
210 INT_MASK(INT_SN_FIREWALL) | \ 212 (1ULL << INT_SN_FIREWALL) | \
211 INT_MASK(INT_IDN_FIREWALL) | \ 213 (1ULL << INT_IDN_FIREWALL) | \
212 INT_MASK(INT_UDN_FIREWALL) | \ 214 (1ULL << INT_UDN_FIREWALL) | \
213 INT_MASK(INT_TILE_TIMER) | \ 215 (1ULL << INT_TILE_TIMER) | \
214 INT_MASK(INT_IDN_TIMER) | \ 216 (1ULL << INT_IDN_TIMER) | \
215 INT_MASK(INT_UDN_TIMER) | \ 217 (1ULL << INT_UDN_TIMER) | \
216 INT_MASK(INT_DMA_NOTIFY) | \ 218 (1ULL << INT_DMA_NOTIFY) | \
217 INT_MASK(INT_IDN_CA) | \ 219 (1ULL << INT_IDN_CA) | \
218 INT_MASK(INT_UDN_CA) | \ 220 (1ULL << INT_UDN_CA) | \
219 INT_MASK(INT_IDN_AVAIL) | \ 221 (1ULL << INT_IDN_AVAIL) | \
220 INT_MASK(INT_UDN_AVAIL) | \ 222 (1ULL << INT_UDN_AVAIL) | \
221 INT_MASK(INT_PERF_COUNT) | \ 223 (1ULL << INT_PERF_COUNT) | \
222 INT_MASK(INT_INTCTRL_3) | \ 224 (1ULL << INT_INTCTRL_3) | \
223 INT_MASK(INT_INTCTRL_2) | \ 225 (1ULL << INT_INTCTRL_2) | \
224 INT_MASK(INT_INTCTRL_1) | \ 226 (1ULL << INT_INTCTRL_1) | \
225 INT_MASK(INT_INTCTRL_0) | \ 227 (1ULL << INT_INTCTRL_0) | \
226 INT_MASK(INT_AUX_PERF_COUNT) | \ 228 (1ULL << INT_AUX_PERF_COUNT) | \
227 0) 229 0)
228#define UNMASKABLE_INTERRUPTS ( \ 230#define UNMASKABLE_INTERRUPTS ( \
229 INT_MASK(INT_ITLB_MISS) | \ 231 (1ULL << INT_ITLB_MISS) | \
230 INT_MASK(INT_ILL) | \ 232 (1ULL << INT_ILL) | \
231 INT_MASK(INT_GPV) | \ 233 (1ULL << INT_GPV) | \
232 INT_MASK(INT_SN_ACCESS) | \ 234 (1ULL << INT_SN_ACCESS) | \
233 INT_MASK(INT_IDN_ACCESS) | \ 235 (1ULL << INT_IDN_ACCESS) | \
234 INT_MASK(INT_UDN_ACCESS) | \ 236 (1ULL << INT_UDN_ACCESS) | \
235 INT_MASK(INT_SWINT_3) | \ 237 (1ULL << INT_SWINT_3) | \
236 INT_MASK(INT_SWINT_2) | \ 238 (1ULL << INT_SWINT_2) | \
237 INT_MASK(INT_SWINT_1) | \ 239 (1ULL << INT_SWINT_1) | \
238 INT_MASK(INT_SWINT_0) | \ 240 (1ULL << INT_SWINT_0) | \
239 INT_MASK(INT_UNALIGN_DATA) | \ 241 (1ULL << INT_UNALIGN_DATA) | \
240 INT_MASK(INT_DTLB_MISS) | \ 242 (1ULL << INT_DTLB_MISS) | \
241 INT_MASK(INT_DTLB_ACCESS) | \ 243 (1ULL << INT_DTLB_ACCESS) | \
242 INT_MASK(INT_BOOT_ACCESS) | \ 244 (1ULL << INT_BOOT_ACCESS) | \
243 INT_MASK(INT_WORLD_ACCESS) | \ 245 (1ULL << INT_WORLD_ACCESS) | \
244 INT_MASK(INT_I_ASID) | \ 246 (1ULL << INT_I_ASID) | \
245 INT_MASK(INT_D_ASID) | \ 247 (1ULL << INT_D_ASID) | \
246 INT_MASK(INT_DMA_ASID) | \ 248 (1ULL << INT_DMA_ASID) | \
247 INT_MASK(INT_SNI_ASID) | \ 249 (1ULL << INT_SNI_ASID) | \
248 INT_MASK(INT_DMA_CPL) | \ 250 (1ULL << INT_DMA_CPL) | \
249 INT_MASK(INT_SN_CPL) | \ 251 (1ULL << INT_SN_CPL) | \
250 INT_MASK(INT_DOUBLE_FAULT) | \ 252 (1ULL << INT_DOUBLE_FAULT) | \
251 INT_MASK(INT_SN_STATIC_ACCESS) | \ 253 (1ULL << INT_SN_STATIC_ACCESS) | \
252 0) 254 0)
253#define SYNC_INTERRUPTS ( \ 255#define SYNC_INTERRUPTS ( \
254 INT_MASK(INT_ITLB_MISS) | \ 256 (1ULL << INT_ITLB_MISS) | \
255 INT_MASK(INT_ILL) | \ 257 (1ULL << INT_ILL) | \
256 INT_MASK(INT_GPV) | \ 258 (1ULL << INT_GPV) | \
257 INT_MASK(INT_SN_ACCESS) | \ 259 (1ULL << INT_SN_ACCESS) | \
258 INT_MASK(INT_IDN_ACCESS) | \ 260 (1ULL << INT_IDN_ACCESS) | \
259 INT_MASK(INT_UDN_ACCESS) | \ 261 (1ULL << INT_UDN_ACCESS) | \
260 INT_MASK(INT_IDN_REFILL) | \ 262 (1ULL << INT_IDN_REFILL) | \
261 INT_MASK(INT_UDN_REFILL) | \ 263 (1ULL << INT_UDN_REFILL) | \
262 INT_MASK(INT_IDN_COMPLETE) | \ 264 (1ULL << INT_IDN_COMPLETE) | \
263 INT_MASK(INT_UDN_COMPLETE) | \ 265 (1ULL << INT_UDN_COMPLETE) | \
264 INT_MASK(INT_SWINT_3) | \ 266 (1ULL << INT_SWINT_3) | \
265 INT_MASK(INT_SWINT_2) | \ 267 (1ULL << INT_SWINT_2) | \
266 INT_MASK(INT_SWINT_1) | \ 268 (1ULL << INT_SWINT_1) | \
267 INT_MASK(INT_SWINT_0) | \ 269 (1ULL << INT_SWINT_0) | \
268 INT_MASK(INT_UNALIGN_DATA) | \ 270 (1ULL << INT_UNALIGN_DATA) | \
269 INT_MASK(INT_DTLB_MISS) | \ 271 (1ULL << INT_DTLB_MISS) | \
270 INT_MASK(INT_DTLB_ACCESS) | \ 272 (1ULL << INT_DTLB_ACCESS) | \
271 INT_MASK(INT_SN_STATIC_ACCESS) | \ 273 (1ULL << INT_SN_STATIC_ACCESS) | \
272 0) 274 0)
273#define NON_SYNC_INTERRUPTS ( \ 275#define NON_SYNC_INTERRUPTS ( \
274 INT_MASK(INT_MEM_ERROR) | \ 276 (1ULL << INT_MEM_ERROR) | \
275 INT_MASK(INT_DMATLB_MISS) | \ 277 (1ULL << INT_DMATLB_MISS) | \
276 INT_MASK(INT_DMATLB_ACCESS) | \ 278 (1ULL << INT_DMATLB_ACCESS) | \
277 INT_MASK(INT_SNITLB_MISS) | \ 279 (1ULL << INT_SNITLB_MISS) | \
278 INT_MASK(INT_SN_NOTIFY) | \ 280 (1ULL << INT_SN_NOTIFY) | \
279 INT_MASK(INT_SN_FIREWALL) | \ 281 (1ULL << INT_SN_FIREWALL) | \
280 INT_MASK(INT_IDN_FIREWALL) | \ 282 (1ULL << INT_IDN_FIREWALL) | \
281 INT_MASK(INT_UDN_FIREWALL) | \ 283 (1ULL << INT_UDN_FIREWALL) | \
282 INT_MASK(INT_TILE_TIMER) | \ 284 (1ULL << INT_TILE_TIMER) | \
283 INT_MASK(INT_IDN_TIMER) | \ 285 (1ULL << INT_IDN_TIMER) | \
284 INT_MASK(INT_UDN_TIMER) | \ 286 (1ULL << INT_UDN_TIMER) | \
285 INT_MASK(INT_DMA_NOTIFY) | \ 287 (1ULL << INT_DMA_NOTIFY) | \
286 INT_MASK(INT_IDN_CA) | \ 288 (1ULL << INT_IDN_CA) | \
287 INT_MASK(INT_UDN_CA) | \ 289 (1ULL << INT_UDN_CA) | \
288 INT_MASK(INT_IDN_AVAIL) | \ 290 (1ULL << INT_IDN_AVAIL) | \
289 INT_MASK(INT_UDN_AVAIL) | \ 291 (1ULL << INT_UDN_AVAIL) | \
290 INT_MASK(INT_PERF_COUNT) | \ 292 (1ULL << INT_PERF_COUNT) | \
291 INT_MASK(INT_INTCTRL_3) | \ 293 (1ULL << INT_INTCTRL_3) | \
292 INT_MASK(INT_INTCTRL_2) | \ 294 (1ULL << INT_INTCTRL_2) | \
293 INT_MASK(INT_INTCTRL_1) | \ 295 (1ULL << INT_INTCTRL_1) | \
294 INT_MASK(INT_INTCTRL_0) | \ 296 (1ULL << INT_INTCTRL_0) | \
295 INT_MASK(INT_BOOT_ACCESS) | \ 297 (1ULL << INT_BOOT_ACCESS) | \
296 INT_MASK(INT_WORLD_ACCESS) | \ 298 (1ULL << INT_WORLD_ACCESS) | \
297 INT_MASK(INT_I_ASID) | \ 299 (1ULL << INT_I_ASID) | \
298 INT_MASK(INT_D_ASID) | \ 300 (1ULL << INT_D_ASID) | \
299 INT_MASK(INT_DMA_ASID) | \ 301 (1ULL << INT_DMA_ASID) | \
300 INT_MASK(INT_SNI_ASID) | \ 302 (1ULL << INT_SNI_ASID) | \
301 INT_MASK(INT_DMA_CPL) | \ 303 (1ULL << INT_DMA_CPL) | \
302 INT_MASK(INT_SN_CPL) | \ 304 (1ULL << INT_SN_CPL) | \
303 INT_MASK(INT_DOUBLE_FAULT) | \ 305 (1ULL << INT_DOUBLE_FAULT) | \
304 INT_MASK(INT_AUX_PERF_COUNT) | \ 306 (1ULL << INT_AUX_PERF_COUNT) | \
305 0) 307 0)
306#endif /* !__ASSEMBLER__ */ 308#endif /* !__ASSEMBLER__ */
307#endif /* !__ARCH_INTERRUPTS_H__ */ 309#endif /* !__ARCH_INTERRUPTS_H__ */
diff --git a/arch/tile/include/uapi/arch/interrupts_64.h b/arch/tile/include/uapi/arch/interrupts_64.h
index 5bb58b2e4e6f..13c9f9182348 100644
--- a/arch/tile/include/uapi/arch/interrupts_64.h
+++ b/arch/tile/include/uapi/arch/interrupts_64.h
@@ -15,6 +15,7 @@
15#ifndef __ARCH_INTERRUPTS_H__ 15#ifndef __ARCH_INTERRUPTS_H__
16#define __ARCH_INTERRUPTS_H__ 16#define __ARCH_INTERRUPTS_H__
17 17
18#ifndef __KERNEL__
18/** Mask for an interrupt. */ 19/** Mask for an interrupt. */
19#ifdef __ASSEMBLER__ 20#ifdef __ASSEMBLER__
20/* Note: must handle breaking interrupts into high and low words manually. */ 21/* Note: must handle breaking interrupts into high and low words manually. */
@@ -22,6 +23,7 @@
22#else 23#else
23#define INT_MASK(intno) (1ULL << (intno)) 24#define INT_MASK(intno) (1ULL << (intno))
24#endif 25#endif
26#endif
25 27
26 28
27/** Where a given interrupt executes */ 29/** Where a given interrupt executes */
@@ -85,192 +87,192 @@
85 87
86#ifndef __ASSEMBLER__ 88#ifndef __ASSEMBLER__
87#define QUEUED_INTERRUPTS ( \ 89#define QUEUED_INTERRUPTS ( \
88 INT_MASK(INT_MEM_ERROR) | \ 90 (1ULL << INT_MEM_ERROR) | \
89 INT_MASK(INT_IDN_COMPLETE) | \ 91 (1ULL << INT_IDN_COMPLETE) | \
90 INT_MASK(INT_UDN_COMPLETE) | \ 92 (1ULL << INT_UDN_COMPLETE) | \
91 INT_MASK(INT_IDN_FIREWALL) | \ 93 (1ULL << INT_IDN_FIREWALL) | \
92 INT_MASK(INT_UDN_FIREWALL) | \ 94 (1ULL << INT_UDN_FIREWALL) | \
93 INT_MASK(INT_TILE_TIMER) | \ 95 (1ULL << INT_TILE_TIMER) | \
94 INT_MASK(INT_AUX_TILE_TIMER) | \ 96 (1ULL << INT_AUX_TILE_TIMER) | \
95 INT_MASK(INT_IDN_TIMER) | \ 97 (1ULL << INT_IDN_TIMER) | \
96 INT_MASK(INT_UDN_TIMER) | \ 98 (1ULL << INT_UDN_TIMER) | \
97 INT_MASK(INT_IDN_AVAIL) | \ 99 (1ULL << INT_IDN_AVAIL) | \
98 INT_MASK(INT_UDN_AVAIL) | \ 100 (1ULL << INT_UDN_AVAIL) | \
99 INT_MASK(INT_IPI_3) | \ 101 (1ULL << INT_IPI_3) | \
100 INT_MASK(INT_IPI_2) | \ 102 (1ULL << INT_IPI_2) | \
101 INT_MASK(INT_IPI_1) | \ 103 (1ULL << INT_IPI_1) | \
102 INT_MASK(INT_IPI_0) | \ 104 (1ULL << INT_IPI_0) | \
103 INT_MASK(INT_PERF_COUNT) | \ 105 (1ULL << INT_PERF_COUNT) | \
104 INT_MASK(INT_AUX_PERF_COUNT) | \ 106 (1ULL << INT_AUX_PERF_COUNT) | \
105 INT_MASK(INT_INTCTRL_3) | \ 107 (1ULL << INT_INTCTRL_3) | \
106 INT_MASK(INT_INTCTRL_2) | \ 108 (1ULL << INT_INTCTRL_2) | \
107 INT_MASK(INT_INTCTRL_1) | \ 109 (1ULL << INT_INTCTRL_1) | \
108 INT_MASK(INT_INTCTRL_0) | \ 110 (1ULL << INT_INTCTRL_0) | \
109 INT_MASK(INT_BOOT_ACCESS) | \ 111 (1ULL << INT_BOOT_ACCESS) | \
110 INT_MASK(INT_WORLD_ACCESS) | \ 112 (1ULL << INT_WORLD_ACCESS) | \
111 INT_MASK(INT_I_ASID) | \ 113 (1ULL << INT_I_ASID) | \
112 INT_MASK(INT_D_ASID) | \ 114 (1ULL << INT_D_ASID) | \
113 INT_MASK(INT_DOUBLE_FAULT) | \ 115 (1ULL << INT_DOUBLE_FAULT) | \
114 0) 116 0)
115#define NONQUEUED_INTERRUPTS ( \ 117#define NONQUEUED_INTERRUPTS ( \
116 INT_MASK(INT_SINGLE_STEP_3) | \ 118 (1ULL << INT_SINGLE_STEP_3) | \
117 INT_MASK(INT_SINGLE_STEP_2) | \ 119 (1ULL << INT_SINGLE_STEP_2) | \
118 INT_MASK(INT_SINGLE_STEP_1) | \ 120 (1ULL << INT_SINGLE_STEP_1) | \
119 INT_MASK(INT_SINGLE_STEP_0) | \ 121 (1ULL << INT_SINGLE_STEP_0) | \
120 INT_MASK(INT_ITLB_MISS) | \ 122 (1ULL << INT_ITLB_MISS) | \
121 INT_MASK(INT_ILL) | \ 123 (1ULL << INT_ILL) | \
122 INT_MASK(INT_GPV) | \ 124 (1ULL << INT_GPV) | \
123 INT_MASK(INT_IDN_ACCESS) | \ 125 (1ULL << INT_IDN_ACCESS) | \
124 INT_MASK(INT_UDN_ACCESS) | \ 126 (1ULL << INT_UDN_ACCESS) | \
125 INT_MASK(INT_SWINT_3) | \ 127 (1ULL << INT_SWINT_3) | \
126 INT_MASK(INT_SWINT_2) | \ 128 (1ULL << INT_SWINT_2) | \
127 INT_MASK(INT_SWINT_1) | \ 129 (1ULL << INT_SWINT_1) | \
128 INT_MASK(INT_SWINT_0) | \ 130 (1ULL << INT_SWINT_0) | \
129 INT_MASK(INT_ILL_TRANS) | \ 131 (1ULL << INT_ILL_TRANS) | \
130 INT_MASK(INT_UNALIGN_DATA) | \ 132 (1ULL << INT_UNALIGN_DATA) | \
131 INT_MASK(INT_DTLB_MISS) | \ 133 (1ULL << INT_DTLB_MISS) | \
132 INT_MASK(INT_DTLB_ACCESS) | \ 134 (1ULL << INT_DTLB_ACCESS) | \
133 0) 135 0)
134#define CRITICAL_MASKED_INTERRUPTS ( \ 136#define CRITICAL_MASKED_INTERRUPTS ( \
135 INT_MASK(INT_MEM_ERROR) | \ 137 (1ULL << INT_MEM_ERROR) | \
136 INT_MASK(INT_SINGLE_STEP_3) | \ 138 (1ULL << INT_SINGLE_STEP_3) | \
137 INT_MASK(INT_SINGLE_STEP_2) | \ 139 (1ULL << INT_SINGLE_STEP_2) | \
138 INT_MASK(INT_SINGLE_STEP_1) | \ 140 (1ULL << INT_SINGLE_STEP_1) | \
139 INT_MASK(INT_SINGLE_STEP_0) | \ 141 (1ULL << INT_SINGLE_STEP_0) | \
140 INT_MASK(INT_IDN_COMPLETE) | \ 142 (1ULL << INT_IDN_COMPLETE) | \
141 INT_MASK(INT_UDN_COMPLETE) | \ 143 (1ULL << INT_UDN_COMPLETE) | \
142 INT_MASK(INT_IDN_FIREWALL) | \ 144 (1ULL << INT_IDN_FIREWALL) | \
143 INT_MASK(INT_UDN_FIREWALL) | \ 145 (1ULL << INT_UDN_FIREWALL) | \
144 INT_MASK(INT_TILE_TIMER) | \ 146 (1ULL << INT_TILE_TIMER) | \
145 INT_MASK(INT_AUX_TILE_TIMER) | \ 147 (1ULL << INT_AUX_TILE_TIMER) | \
146 INT_MASK(INT_IDN_TIMER) | \ 148 (1ULL << INT_IDN_TIMER) | \
147 INT_MASK(INT_UDN_TIMER) | \ 149 (1ULL << INT_UDN_TIMER) | \
148 INT_MASK(INT_IDN_AVAIL) | \ 150 (1ULL << INT_IDN_AVAIL) | \
149 INT_MASK(INT_UDN_AVAIL) | \ 151 (1ULL << INT_UDN_AVAIL) | \
150 INT_MASK(INT_IPI_3) | \ 152 (1ULL << INT_IPI_3) | \
151 INT_MASK(INT_IPI_2) | \ 153 (1ULL << INT_IPI_2) | \
152 INT_MASK(INT_IPI_1) | \ 154 (1ULL << INT_IPI_1) | \
153 INT_MASK(INT_IPI_0) | \ 155 (1ULL << INT_IPI_0) | \
154 INT_MASK(INT_PERF_COUNT) | \ 156 (1ULL << INT_PERF_COUNT) | \
155 INT_MASK(INT_AUX_PERF_COUNT) | \ 157 (1ULL << INT_AUX_PERF_COUNT) | \
156 INT_MASK(INT_INTCTRL_3) | \ 158 (1ULL << INT_INTCTRL_3) | \
157 INT_MASK(INT_INTCTRL_2) | \ 159 (1ULL << INT_INTCTRL_2) | \
158 INT_MASK(INT_INTCTRL_1) | \ 160 (1ULL << INT_INTCTRL_1) | \
159 INT_MASK(INT_INTCTRL_0) | \ 161 (1ULL << INT_INTCTRL_0) | \
160 0) 162 0)
161#define CRITICAL_UNMASKED_INTERRUPTS ( \ 163#define CRITICAL_UNMASKED_INTERRUPTS ( \
162 INT_MASK(INT_ITLB_MISS) | \ 164 (1ULL << INT_ITLB_MISS) | \
163 INT_MASK(INT_ILL) | \ 165 (1ULL << INT_ILL) | \
164 INT_MASK(INT_GPV) | \ 166 (1ULL << INT_GPV) | \
165 INT_MASK(INT_IDN_ACCESS) | \ 167 (1ULL << INT_IDN_ACCESS) | \
166 INT_MASK(INT_UDN_ACCESS) | \ 168 (1ULL << INT_UDN_ACCESS) | \
167 INT_MASK(INT_SWINT_3) | \ 169 (1ULL << INT_SWINT_3) | \
168 INT_MASK(INT_SWINT_2) | \ 170 (1ULL << INT_SWINT_2) | \
169 INT_MASK(INT_SWINT_1) | \ 171 (1ULL << INT_SWINT_1) | \
170 INT_MASK(INT_SWINT_0) | \ 172 (1ULL << INT_SWINT_0) | \
171 INT_MASK(INT_ILL_TRANS) | \ 173 (1ULL << INT_ILL_TRANS) | \
172 INT_MASK(INT_UNALIGN_DATA) | \ 174 (1ULL << INT_UNALIGN_DATA) | \
173 INT_MASK(INT_DTLB_MISS) | \ 175 (1ULL << INT_DTLB_MISS) | \
174 INT_MASK(INT_DTLB_ACCESS) | \ 176 (1ULL << INT_DTLB_ACCESS) | \
175 INT_MASK(INT_BOOT_ACCESS) | \ 177 (1ULL << INT_BOOT_ACCESS) | \
176 INT_MASK(INT_WORLD_ACCESS) | \ 178 (1ULL << INT_WORLD_ACCESS) | \
177 INT_MASK(INT_I_ASID) | \ 179 (1ULL << INT_I_ASID) | \
178 INT_MASK(INT_D_ASID) | \ 180 (1ULL << INT_D_ASID) | \
179 INT_MASK(INT_DOUBLE_FAULT) | \ 181 (1ULL << INT_DOUBLE_FAULT) | \
180 0) 182 0)
181#define MASKABLE_INTERRUPTS ( \ 183#define MASKABLE_INTERRUPTS ( \
182 INT_MASK(INT_MEM_ERROR) | \ 184 (1ULL << INT_MEM_ERROR) | \
183 INT_MASK(INT_SINGLE_STEP_3) | \ 185 (1ULL << INT_SINGLE_STEP_3) | \
184 INT_MASK(INT_SINGLE_STEP_2) | \ 186 (1ULL << INT_SINGLE_STEP_2) | \
185 INT_MASK(INT_SINGLE_STEP_1) | \ 187 (1ULL << INT_SINGLE_STEP_1) | \
186 INT_MASK(INT_SINGLE_STEP_0) | \ 188 (1ULL << INT_SINGLE_STEP_0) | \
187 INT_MASK(INT_IDN_COMPLETE) | \ 189 (1ULL << INT_IDN_COMPLETE) | \
188 INT_MASK(INT_UDN_COMPLETE) | \ 190 (1ULL << INT_UDN_COMPLETE) | \
189 INT_MASK(INT_IDN_FIREWALL) | \ 191 (1ULL << INT_IDN_FIREWALL) | \
190 INT_MASK(INT_UDN_FIREWALL) | \ 192 (1ULL << INT_UDN_FIREWALL) | \
191 INT_MASK(INT_TILE_TIMER) | \ 193 (1ULL << INT_TILE_TIMER) | \
192 INT_MASK(INT_AUX_TILE_TIMER) | \ 194 (1ULL << INT_AUX_TILE_TIMER) | \
193 INT_MASK(INT_IDN_TIMER) | \ 195 (1ULL << INT_IDN_TIMER) | \
194 INT_MASK(INT_UDN_TIMER) | \ 196 (1ULL << INT_UDN_TIMER) | \
195 INT_MASK(INT_IDN_AVAIL) | \ 197 (1ULL << INT_IDN_AVAIL) | \
196 INT_MASK(INT_UDN_AVAIL) | \ 198 (1ULL << INT_UDN_AVAIL) | \
197 INT_MASK(INT_IPI_3) | \ 199 (1ULL << INT_IPI_3) | \
198 INT_MASK(INT_IPI_2) | \ 200 (1ULL << INT_IPI_2) | \
199 INT_MASK(INT_IPI_1) | \ 201 (1ULL << INT_IPI_1) | \
200 INT_MASK(INT_IPI_0) | \ 202 (1ULL << INT_IPI_0) | \
201 INT_MASK(INT_PERF_COUNT) | \ 203 (1ULL << INT_PERF_COUNT) | \
202 INT_MASK(INT_AUX_PERF_COUNT) | \ 204 (1ULL << INT_AUX_PERF_COUNT) | \
203 INT_MASK(INT_INTCTRL_3) | \ 205 (1ULL << INT_INTCTRL_3) | \
204 INT_MASK(INT_INTCTRL_2) | \ 206 (1ULL << INT_INTCTRL_2) | \
205 INT_MASK(INT_INTCTRL_1) | \ 207 (1ULL << INT_INTCTRL_1) | \
206 INT_MASK(INT_INTCTRL_0) | \ 208 (1ULL << INT_INTCTRL_0) | \
207 0) 209 0)
208#define UNMASKABLE_INTERRUPTS ( \ 210#define UNMASKABLE_INTERRUPTS ( \
209 INT_MASK(INT_ITLB_MISS) | \ 211 (1ULL << INT_ITLB_MISS) | \
210 INT_MASK(INT_ILL) | \ 212 (1ULL << INT_ILL) | \
211 INT_MASK(INT_GPV) | \ 213 (1ULL << INT_GPV) | \
212 INT_MASK(INT_IDN_ACCESS) | \ 214 (1ULL << INT_IDN_ACCESS) | \
213 INT_MASK(INT_UDN_ACCESS) | \ 215 (1ULL << INT_UDN_ACCESS) | \
214 INT_MASK(INT_SWINT_3) | \ 216 (1ULL << INT_SWINT_3) | \
215 INT_MASK(INT_SWINT_2) | \ 217 (1ULL << INT_SWINT_2) | \
216 INT_MASK(INT_SWINT_1) | \ 218 (1ULL << INT_SWINT_1) | \
217 INT_MASK(INT_SWINT_0) | \ 219 (1ULL << INT_SWINT_0) | \
218 INT_MASK(INT_ILL_TRANS) | \ 220 (1ULL << INT_ILL_TRANS) | \
219 INT_MASK(INT_UNALIGN_DATA) | \ 221 (1ULL << INT_UNALIGN_DATA) | \
220 INT_MASK(INT_DTLB_MISS) | \ 222 (1ULL << INT_DTLB_MISS) | \
221 INT_MASK(INT_DTLB_ACCESS) | \ 223 (1ULL << INT_DTLB_ACCESS) | \
222 INT_MASK(INT_BOOT_ACCESS) | \ 224 (1ULL << INT_BOOT_ACCESS) | \
223 INT_MASK(INT_WORLD_ACCESS) | \ 225 (1ULL << INT_WORLD_ACCESS) | \
224 INT_MASK(INT_I_ASID) | \ 226 (1ULL << INT_I_ASID) | \
225 INT_MASK(INT_D_ASID) | \ 227 (1ULL << INT_D_ASID) | \
226 INT_MASK(INT_DOUBLE_FAULT) | \ 228 (1ULL << INT_DOUBLE_FAULT) | \
227 0) 229 0)
228#define SYNC_INTERRUPTS ( \ 230#define SYNC_INTERRUPTS ( \
229 INT_MASK(INT_SINGLE_STEP_3) | \ 231 (1ULL << INT_SINGLE_STEP_3) | \
230 INT_MASK(INT_SINGLE_STEP_2) | \ 232 (1ULL << INT_SINGLE_STEP_2) | \
231 INT_MASK(INT_SINGLE_STEP_1) | \ 233 (1ULL << INT_SINGLE_STEP_1) | \
232 INT_MASK(INT_SINGLE_STEP_0) | \ 234 (1ULL << INT_SINGLE_STEP_0) | \
233 INT_MASK(INT_IDN_COMPLETE) | \ 235 (1ULL << INT_IDN_COMPLETE) | \
234 INT_MASK(INT_UDN_COMPLETE) | \ 236 (1ULL << INT_UDN_COMPLETE) | \
235 INT_MASK(INT_ITLB_MISS) | \ 237 (1ULL << INT_ITLB_MISS) | \
236 INT_MASK(INT_ILL) | \ 238 (1ULL << INT_ILL) | \
237 INT_MASK(INT_GPV) | \ 239 (1ULL << INT_GPV) | \
238 INT_MASK(INT_IDN_ACCESS) | \ 240 (1ULL << INT_IDN_ACCESS) | \
239 INT_MASK(INT_UDN_ACCESS) | \ 241 (1ULL << INT_UDN_ACCESS) | \
240 INT_MASK(INT_SWINT_3) | \ 242 (1ULL << INT_SWINT_3) | \
241 INT_MASK(INT_SWINT_2) | \ 243 (1ULL << INT_SWINT_2) | \
242 INT_MASK(INT_SWINT_1) | \ 244 (1ULL << INT_SWINT_1) | \
243 INT_MASK(INT_SWINT_0) | \ 245 (1ULL << INT_SWINT_0) | \
244 INT_MASK(INT_ILL_TRANS) | \ 246 (1ULL << INT_ILL_TRANS) | \
245 INT_MASK(INT_UNALIGN_DATA) | \ 247 (1ULL << INT_UNALIGN_DATA) | \
246 INT_MASK(INT_DTLB_MISS) | \ 248 (1ULL << INT_DTLB_MISS) | \
247 INT_MASK(INT_DTLB_ACCESS) | \ 249 (1ULL << INT_DTLB_ACCESS) | \
248 0) 250 0)
249#define NON_SYNC_INTERRUPTS ( \ 251#define NON_SYNC_INTERRUPTS ( \
250 INT_MASK(INT_MEM_ERROR) | \ 252 (1ULL << INT_MEM_ERROR) | \
251 INT_MASK(INT_IDN_FIREWALL) | \ 253 (1ULL << INT_IDN_FIREWALL) | \
252 INT_MASK(INT_UDN_FIREWALL) | \ 254 (1ULL << INT_UDN_FIREWALL) | \
253 INT_MASK(INT_TILE_TIMER) | \ 255 (1ULL << INT_TILE_TIMER) | \
254 INT_MASK(INT_AUX_TILE_TIMER) | \ 256 (1ULL << INT_AUX_TILE_TIMER) | \
255 INT_MASK(INT_IDN_TIMER) | \ 257 (1ULL << INT_IDN_TIMER) | \
256 INT_MASK(INT_UDN_TIMER) | \ 258 (1ULL << INT_UDN_TIMER) | \
257 INT_MASK(INT_IDN_AVAIL) | \ 259 (1ULL << INT_IDN_AVAIL) | \
258 INT_MASK(INT_UDN_AVAIL) | \ 260 (1ULL << INT_UDN_AVAIL) | \
259 INT_MASK(INT_IPI_3) | \ 261 (1ULL << INT_IPI_3) | \
260 INT_MASK(INT_IPI_2) | \ 262 (1ULL << INT_IPI_2) | \
261 INT_MASK(INT_IPI_1) | \ 263 (1ULL << INT_IPI_1) | \
262 INT_MASK(INT_IPI_0) | \ 264 (1ULL << INT_IPI_0) | \
263 INT_MASK(INT_PERF_COUNT) | \ 265 (1ULL << INT_PERF_COUNT) | \
264 INT_MASK(INT_AUX_PERF_COUNT) | \ 266 (1ULL << INT_AUX_PERF_COUNT) | \
265 INT_MASK(INT_INTCTRL_3) | \ 267 (1ULL << INT_INTCTRL_3) | \
266 INT_MASK(INT_INTCTRL_2) | \ 268 (1ULL << INT_INTCTRL_2) | \
267 INT_MASK(INT_INTCTRL_1) | \ 269 (1ULL << INT_INTCTRL_1) | \
268 INT_MASK(INT_INTCTRL_0) | \ 270 (1ULL << INT_INTCTRL_0) | \
269 INT_MASK(INT_BOOT_ACCESS) | \ 271 (1ULL << INT_BOOT_ACCESS) | \
270 INT_MASK(INT_WORLD_ACCESS) | \ 272 (1ULL << INT_WORLD_ACCESS) | \
271 INT_MASK(INT_I_ASID) | \ 273 (1ULL << INT_I_ASID) | \
272 INT_MASK(INT_D_ASID) | \ 274 (1ULL << INT_D_ASID) | \
273 INT_MASK(INT_DOUBLE_FAULT) | \ 275 (1ULL << INT_DOUBLE_FAULT) | \
274 0) 276 0)
275#endif /* !__ASSEMBLER__ */ 277#endif /* !__ASSEMBLER__ */
276#endif /* !__ARCH_INTERRUPTS_H__ */ 278#endif /* !__ARCH_INTERRUPTS_H__ */
diff --git a/arch/tile/kernel/intvec_64.S b/arch/tile/kernel/intvec_64.S
index 54bc9a6678e8..4ea080902654 100644
--- a/arch/tile/kernel/intvec_64.S
+++ b/arch/tile/kernel/intvec_64.S
@@ -1035,7 +1035,9 @@ handle_syscall:
1035 /* Ensure that the syscall number is within the legal range. */ 1035 /* Ensure that the syscall number is within the legal range. */
1036 { 1036 {
1037 moveli r20, hw2(sys_call_table) 1037 moveli r20, hw2(sys_call_table)
1038#ifdef CONFIG_COMPAT
1038 blbs r30, .Lcompat_syscall 1039 blbs r30, .Lcompat_syscall
1040#endif
1039 } 1041 }
1040 { 1042 {
1041 cmpltu r21, TREG_SYSCALL_NR_NAME, r21 1043 cmpltu r21, TREG_SYSCALL_NR_NAME, r21
@@ -1093,6 +1095,7 @@ handle_syscall:
1093 j .Lresume_userspace /* jump into middle of interrupt_return */ 1095 j .Lresume_userspace /* jump into middle of interrupt_return */
1094 } 1096 }
1095 1097
1098#ifdef CONFIG_COMPAT
1096.Lcompat_syscall: 1099.Lcompat_syscall:
1097 /* 1100 /*
1098 * Load the base of the compat syscall table in r20, and 1101 * Load the base of the compat syscall table in r20, and
@@ -1117,6 +1120,7 @@ handle_syscall:
1117 { move r15, r4; addxi r4, r4, 0 } 1120 { move r15, r4; addxi r4, r4, 0 }
1118 { move r16, r5; addxi r5, r5, 0 } 1121 { move r16, r5; addxi r5, r5, 0 }
1119 j .Lload_syscall_pointer 1122 j .Lload_syscall_pointer
1123#endif
1120 1124
1121.Linvalid_syscall: 1125.Linvalid_syscall:
1122 /* Report an invalid syscall back to the user program */ 1126 /* Report an invalid syscall back to the user program */
diff --git a/arch/tile/kernel/process.c b/arch/tile/kernel/process.c
index 0e5661e7d00d..caf93ae11793 100644
--- a/arch/tile/kernel/process.c
+++ b/arch/tile/kernel/process.c
@@ -159,7 +159,7 @@ static void save_arch_state(struct thread_struct *t);
159int copy_thread(unsigned long clone_flags, unsigned long sp, 159int copy_thread(unsigned long clone_flags, unsigned long sp,
160 unsigned long arg, struct task_struct *p) 160 unsigned long arg, struct task_struct *p)
161{ 161{
162 struct pt_regs *childregs = task_pt_regs(p), *regs = current_pt_regs(); 162 struct pt_regs *childregs = task_pt_regs(p);
163 unsigned long ksp; 163 unsigned long ksp;
164 unsigned long *callee_regs; 164 unsigned long *callee_regs;
165 165
diff --git a/arch/tile/kernel/reboot.c b/arch/tile/kernel/reboot.c
index baa3d905fee2..d1b5c913ae72 100644
--- a/arch/tile/kernel/reboot.c
+++ b/arch/tile/kernel/reboot.c
@@ -16,6 +16,7 @@
16#include <linux/reboot.h> 16#include <linux/reboot.h>
17#include <linux/smp.h> 17#include <linux/smp.h>
18#include <linux/pm.h> 18#include <linux/pm.h>
19#include <linux/export.h>
19#include <asm/page.h> 20#include <asm/page.h>
20#include <asm/setup.h> 21#include <asm/setup.h>
21#include <hv/hypervisor.h> 22#include <hv/hypervisor.h>
@@ -49,3 +50,4 @@ void machine_restart(char *cmd)
49 50
50/* No interesting distinction to be made here. */ 51/* No interesting distinction to be made here. */
51void (*pm_power_off)(void) = NULL; 52void (*pm_power_off)(void) = NULL;
53EXPORT_SYMBOL(pm_power_off);
diff --git a/arch/tile/kernel/setup.c b/arch/tile/kernel/setup.c
index 6a649a4462d3..d1e15f7b59c6 100644
--- a/arch/tile/kernel/setup.c
+++ b/arch/tile/kernel/setup.c
@@ -31,6 +31,7 @@
31#include <linux/timex.h> 31#include <linux/timex.h>
32#include <linux/hugetlb.h> 32#include <linux/hugetlb.h>
33#include <linux/start_kernel.h> 33#include <linux/start_kernel.h>
34#include <linux/screen_info.h>
34#include <asm/setup.h> 35#include <asm/setup.h>
35#include <asm/sections.h> 36#include <asm/sections.h>
36#include <asm/cacheflush.h> 37#include <asm/cacheflush.h>
@@ -49,6 +50,10 @@ static inline int ABS(int x) { return x >= 0 ? x : -x; }
49/* Chip information */ 50/* Chip information */
50char chip_model[64] __write_once; 51char chip_model[64] __write_once;
51 52
53#ifdef CONFIG_VT
54struct screen_info screen_info;
55#endif
56
52struct pglist_data node_data[MAX_NUMNODES] __read_mostly; 57struct pglist_data node_data[MAX_NUMNODES] __read_mostly;
53EXPORT_SYMBOL(node_data); 58EXPORT_SYMBOL(node_data);
54 59
diff --git a/arch/tile/kernel/stack.c b/arch/tile/kernel/stack.c
index b2f44c28dda6..ed258b8ae320 100644
--- a/arch/tile/kernel/stack.c
+++ b/arch/tile/kernel/stack.c
@@ -112,7 +112,7 @@ static struct pt_regs *valid_fault_handler(struct KBacktraceIterator* kbt)
112 p->pc, p->sp, p->ex1); 112 p->pc, p->sp, p->ex1);
113 p = NULL; 113 p = NULL;
114 } 114 }
115 if (!kbt->profile || (INT_MASK(p->faultnum) & QUEUED_INTERRUPTS) == 0) 115 if (!kbt->profile || ((1ULL << p->faultnum) & QUEUED_INTERRUPTS) == 0)
116 return p; 116 return p;
117 return NULL; 117 return NULL;
118} 118}
@@ -484,6 +484,7 @@ void save_stack_trace(struct stack_trace *trace)
484{ 484{
485 save_stack_trace_tsk(NULL, trace); 485 save_stack_trace_tsk(NULL, trace);
486} 486}
487EXPORT_SYMBOL_GPL(save_stack_trace);
487 488
488#endif 489#endif
489 490
diff --git a/arch/tile/lib/cacheflush.c b/arch/tile/lib/cacheflush.c
index db4fb89e12d8..8f8ad814b139 100644
--- a/arch/tile/lib/cacheflush.c
+++ b/arch/tile/lib/cacheflush.c
@@ -12,6 +12,7 @@
12 * more details. 12 * more details.
13 */ 13 */
14 14
15#include <linux/export.h>
15#include <asm/page.h> 16#include <asm/page.h>
16#include <asm/cacheflush.h> 17#include <asm/cacheflush.h>
17#include <arch/icache.h> 18#include <arch/icache.h>
@@ -165,3 +166,4 @@ void finv_buffer_remote(void *buffer, size_t size, int hfh)
165 __insn_mtspr(SPR_DSTREAM_PF, old_dstream_pf); 166 __insn_mtspr(SPR_DSTREAM_PF, old_dstream_pf);
166#endif 167#endif
167} 168}
169EXPORT_SYMBOL_GPL(finv_buffer_remote);
diff --git a/arch/tile/lib/cpumask.c b/arch/tile/lib/cpumask.c
index fdc403614d12..75947edccb26 100644
--- a/arch/tile/lib/cpumask.c
+++ b/arch/tile/lib/cpumask.c
@@ -16,6 +16,7 @@
16#include <linux/ctype.h> 16#include <linux/ctype.h>
17#include <linux/errno.h> 17#include <linux/errno.h>
18#include <linux/smp.h> 18#include <linux/smp.h>
19#include <linux/export.h>
19 20
20/* 21/*
21 * Allow cropping out bits beyond the end of the array. 22 * Allow cropping out bits beyond the end of the array.
@@ -50,3 +51,4 @@ int bitmap_parselist_crop(const char *bp, unsigned long *maskp, int nmaskbits)
50 } while (*bp != '\0' && *bp != '\n'); 51 } while (*bp != '\0' && *bp != '\n');
51 return 0; 52 return 0;
52} 53}
54EXPORT_SYMBOL(bitmap_parselist_crop);
diff --git a/arch/tile/lib/exports.c b/arch/tile/lib/exports.c
index dd5f0a33fdaf..4385cb6fa00a 100644
--- a/arch/tile/lib/exports.c
+++ b/arch/tile/lib/exports.c
@@ -55,6 +55,8 @@ EXPORT_SYMBOL(hv_dev_poll_cancel);
55EXPORT_SYMBOL(hv_dev_close); 55EXPORT_SYMBOL(hv_dev_close);
56EXPORT_SYMBOL(hv_sysconf); 56EXPORT_SYMBOL(hv_sysconf);
57EXPORT_SYMBOL(hv_confstr); 57EXPORT_SYMBOL(hv_confstr);
58EXPORT_SYMBOL(hv_get_rtc);
59EXPORT_SYMBOL(hv_set_rtc);
58 60
59/* libgcc.a */ 61/* libgcc.a */
60uint32_t __udivsi3(uint32_t dividend, uint32_t divisor); 62uint32_t __udivsi3(uint32_t dividend, uint32_t divisor);
diff --git a/arch/tile/mm/homecache.c b/arch/tile/mm/homecache.c
index 5f7868dcd6d4..1ae911939a18 100644
--- a/arch/tile/mm/homecache.c
+++ b/arch/tile/mm/homecache.c
@@ -408,6 +408,7 @@ void homecache_change_page_home(struct page *page, int order, int home)
408 __set_pte(ptep, pte_set_home(pteval, home)); 408 __set_pte(ptep, pte_set_home(pteval, home));
409 } 409 }
410} 410}
411EXPORT_SYMBOL(homecache_change_page_home);
411 412
412struct page *homecache_alloc_pages(gfp_t gfp_mask, 413struct page *homecache_alloc_pages(gfp_t gfp_mask,
413 unsigned int order, int home) 414 unsigned int order, int home)
diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h
index ecdfee60ee4a..f4076af1f4ed 100644
--- a/arch/x86/include/asm/mce.h
+++ b/arch/x86/include/asm/mce.h
@@ -3,6 +3,90 @@
3 3
4#include <uapi/asm/mce.h> 4#include <uapi/asm/mce.h>
5 5
6/*
7 * Machine Check support for x86
8 */
9
10/* MCG_CAP register defines */
11#define MCG_BANKCNT_MASK 0xff /* Number of Banks */
12#define MCG_CTL_P (1ULL<<8) /* MCG_CTL register available */
13#define MCG_EXT_P (1ULL<<9) /* Extended registers available */
14#define MCG_CMCI_P (1ULL<<10) /* CMCI supported */
15#define MCG_EXT_CNT_MASK 0xff0000 /* Number of Extended registers */
16#define MCG_EXT_CNT_SHIFT 16
17#define MCG_EXT_CNT(c) (((c) & MCG_EXT_CNT_MASK) >> MCG_EXT_CNT_SHIFT)
18#define MCG_SER_P (1ULL<<24) /* MCA recovery/new status bits */
19
20/* MCG_STATUS register defines */
21#define MCG_STATUS_RIPV (1ULL<<0) /* restart ip valid */
22#define MCG_STATUS_EIPV (1ULL<<1) /* ip points to correct instruction */
23#define MCG_STATUS_MCIP (1ULL<<2) /* machine check in progress */
24
25/* MCi_STATUS register defines */
26#define MCI_STATUS_VAL (1ULL<<63) /* valid error */
27#define MCI_STATUS_OVER (1ULL<<62) /* previous errors lost */
28#define MCI_STATUS_UC (1ULL<<61) /* uncorrected error */
29#define MCI_STATUS_EN (1ULL<<60) /* error enabled */
30#define MCI_STATUS_MISCV (1ULL<<59) /* misc error reg. valid */
31#define MCI_STATUS_ADDRV (1ULL<<58) /* addr reg. valid */
32#define MCI_STATUS_PCC (1ULL<<57) /* processor context corrupt */
33#define MCI_STATUS_S (1ULL<<56) /* Signaled machine check */
34#define MCI_STATUS_AR (1ULL<<55) /* Action required */
35#define MCACOD 0xffff /* MCA Error Code */
36
37/* Architecturally defined codes from SDM Vol. 3B Chapter 15 */
38#define MCACOD_SCRUB 0x00C0 /* 0xC0-0xCF Memory Scrubbing */
39#define MCACOD_SCRUBMSK 0xfff0
40#define MCACOD_L3WB 0x017A /* L3 Explicit Writeback */
41#define MCACOD_DATA 0x0134 /* Data Load */
42#define MCACOD_INSTR 0x0150 /* Instruction Fetch */
43
44/* MCi_MISC register defines */
45#define MCI_MISC_ADDR_LSB(m) ((m) & 0x3f)
46#define MCI_MISC_ADDR_MODE(m) (((m) >> 6) & 7)
47#define MCI_MISC_ADDR_SEGOFF 0 /* segment offset */
48#define MCI_MISC_ADDR_LINEAR 1 /* linear address */
49#define MCI_MISC_ADDR_PHYS 2 /* physical address */
50#define MCI_MISC_ADDR_MEM 3 /* memory address */
51#define MCI_MISC_ADDR_GENERIC 7 /* generic */
52
53/* CTL2 register defines */
54#define MCI_CTL2_CMCI_EN (1ULL << 30)
55#define MCI_CTL2_CMCI_THRESHOLD_MASK 0x7fffULL
56
57#define MCJ_CTX_MASK 3
58#define MCJ_CTX(flags) ((flags) & MCJ_CTX_MASK)
59#define MCJ_CTX_RANDOM 0 /* inject context: random */
60#define MCJ_CTX_PROCESS 0x1 /* inject context: process */
61#define MCJ_CTX_IRQ 0x2 /* inject context: IRQ */
62#define MCJ_NMI_BROADCAST 0x4 /* do NMI broadcasting */
63#define MCJ_EXCEPTION 0x8 /* raise as exception */
64#define MCJ_IRQ_BRAODCAST 0x10 /* do IRQ broadcasting */
65
66#define MCE_OVERFLOW 0 /* bit 0 in flags means overflow */
67
68/* Software defined banks */
69#define MCE_EXTENDED_BANK 128
70#define MCE_THERMAL_BANK (MCE_EXTENDED_BANK + 0)
71#define K8_MCE_THRESHOLD_BASE (MCE_EXTENDED_BANK + 1)
72
73#define MCE_LOG_LEN 32
74#define MCE_LOG_SIGNATURE "MACHINECHECK"
75
76/*
77 * This structure contains all data related to the MCE log. Also
78 * carries a signature to make it easier to find from external
79 * debugging tools. Each entry is only valid when its finished flag
80 * is set.
81 */
82struct mce_log {
83 char signature[12]; /* "MACHINECHECK" */
84 unsigned len; /* = MCE_LOG_LEN */
85 unsigned next;
86 unsigned flags;
87 unsigned recordlen; /* length of struct mce */
88 struct mce entry[MCE_LOG_LEN];
89};
6 90
7struct mca_config { 91struct mca_config {
8 bool dont_log_ce; 92 bool dont_log_ce;
diff --git a/arch/x86/include/asm/pgtable.h b/arch/x86/include/asm/pgtable.h
index 5199db2923d3..1c1a955e67c0 100644
--- a/arch/x86/include/asm/pgtable.h
+++ b/arch/x86/include/asm/pgtable.h
@@ -142,6 +142,11 @@ static inline unsigned long pmd_pfn(pmd_t pmd)
142 return (pmd_val(pmd) & PTE_PFN_MASK) >> PAGE_SHIFT; 142 return (pmd_val(pmd) & PTE_PFN_MASK) >> PAGE_SHIFT;
143} 143}
144 144
145static inline unsigned long pud_pfn(pud_t pud)
146{
147 return (pud_val(pud) & PTE_PFN_MASK) >> PAGE_SHIFT;
148}
149
145#define pte_page(pte) pfn_to_page(pte_pfn(pte)) 150#define pte_page(pte) pfn_to_page(pte_pfn(pte))
146 151
147static inline int pmd_large(pmd_t pte) 152static inline int pmd_large(pmd_t pte)
diff --git a/arch/x86/include/uapi/asm/mce.h b/arch/x86/include/uapi/asm/mce.h
index 58c829871c31..a0eab85ce7b8 100644
--- a/arch/x86/include/uapi/asm/mce.h
+++ b/arch/x86/include/uapi/asm/mce.h
@@ -4,66 +4,6 @@
4#include <linux/types.h> 4#include <linux/types.h>
5#include <asm/ioctls.h> 5#include <asm/ioctls.h>
6 6
7/*
8 * Machine Check support for x86
9 */
10
11/* MCG_CAP register defines */
12#define MCG_BANKCNT_MASK 0xff /* Number of Banks */
13#define MCG_CTL_P (1ULL<<8) /* MCG_CTL register available */
14#define MCG_EXT_P (1ULL<<9) /* Extended registers available */
15#define MCG_CMCI_P (1ULL<<10) /* CMCI supported */
16#define MCG_EXT_CNT_MASK 0xff0000 /* Number of Extended registers */
17#define MCG_EXT_CNT_SHIFT 16
18#define MCG_EXT_CNT(c) (((c) & MCG_EXT_CNT_MASK) >> MCG_EXT_CNT_SHIFT)
19#define MCG_SER_P (1ULL<<24) /* MCA recovery/new status bits */
20
21/* MCG_STATUS register defines */
22#define MCG_STATUS_RIPV (1ULL<<0) /* restart ip valid */
23#define MCG_STATUS_EIPV (1ULL<<1) /* ip points to correct instruction */
24#define MCG_STATUS_MCIP (1ULL<<2) /* machine check in progress */
25
26/* MCi_STATUS register defines */
27#define MCI_STATUS_VAL (1ULL<<63) /* valid error */
28#define MCI_STATUS_OVER (1ULL<<62) /* previous errors lost */
29#define MCI_STATUS_UC (1ULL<<61) /* uncorrected error */
30#define MCI_STATUS_EN (1ULL<<60) /* error enabled */
31#define MCI_STATUS_MISCV (1ULL<<59) /* misc error reg. valid */
32#define MCI_STATUS_ADDRV (1ULL<<58) /* addr reg. valid */
33#define MCI_STATUS_PCC (1ULL<<57) /* processor context corrupt */
34#define MCI_STATUS_S (1ULL<<56) /* Signaled machine check */
35#define MCI_STATUS_AR (1ULL<<55) /* Action required */
36#define MCACOD 0xffff /* MCA Error Code */
37
38/* Architecturally defined codes from SDM Vol. 3B Chapter 15 */
39#define MCACOD_SCRUB 0x00C0 /* 0xC0-0xCF Memory Scrubbing */
40#define MCACOD_SCRUBMSK 0xfff0
41#define MCACOD_L3WB 0x017A /* L3 Explicit Writeback */
42#define MCACOD_DATA 0x0134 /* Data Load */
43#define MCACOD_INSTR 0x0150 /* Instruction Fetch */
44
45/* MCi_MISC register defines */
46#define MCI_MISC_ADDR_LSB(m) ((m) & 0x3f)
47#define MCI_MISC_ADDR_MODE(m) (((m) >> 6) & 7)
48#define MCI_MISC_ADDR_SEGOFF 0 /* segment offset */
49#define MCI_MISC_ADDR_LINEAR 1 /* linear address */
50#define MCI_MISC_ADDR_PHYS 2 /* physical address */
51#define MCI_MISC_ADDR_MEM 3 /* memory address */
52#define MCI_MISC_ADDR_GENERIC 7 /* generic */
53
54/* CTL2 register defines */
55#define MCI_CTL2_CMCI_EN (1ULL << 30)
56#define MCI_CTL2_CMCI_THRESHOLD_MASK 0x7fffULL
57
58#define MCJ_CTX_MASK 3
59#define MCJ_CTX(flags) ((flags) & MCJ_CTX_MASK)
60#define MCJ_CTX_RANDOM 0 /* inject context: random */
61#define MCJ_CTX_PROCESS 0x1 /* inject context: process */
62#define MCJ_CTX_IRQ 0x2 /* inject context: IRQ */
63#define MCJ_NMI_BROADCAST 0x4 /* do NMI broadcasting */
64#define MCJ_EXCEPTION 0x8 /* raise as exception */
65#define MCJ_IRQ_BRAODCAST 0x10 /* do IRQ broadcasting */
66
67/* Fields are zero when not available */ 7/* Fields are zero when not available */
68struct mce { 8struct mce {
69 __u64 status; 9 __u64 status;
@@ -87,35 +27,8 @@ struct mce {
87 __u64 mcgcap; /* MCGCAP MSR: machine check capabilities of CPU */ 27 __u64 mcgcap; /* MCGCAP MSR: machine check capabilities of CPU */
88}; 28};
89 29
90/*
91 * This structure contains all data related to the MCE log. Also
92 * carries a signature to make it easier to find from external
93 * debugging tools. Each entry is only valid when its finished flag
94 * is set.
95 */
96
97#define MCE_LOG_LEN 32
98
99struct mce_log {
100 char signature[12]; /* "MACHINECHECK" */
101 unsigned len; /* = MCE_LOG_LEN */
102 unsigned next;
103 unsigned flags;
104 unsigned recordlen; /* length of struct mce */
105 struct mce entry[MCE_LOG_LEN];
106};
107
108#define MCE_OVERFLOW 0 /* bit 0 in flags means overflow */
109
110#define MCE_LOG_SIGNATURE "MACHINECHECK"
111
112#define MCE_GET_RECORD_LEN _IOR('M', 1, int) 30#define MCE_GET_RECORD_LEN _IOR('M', 1, int)
113#define MCE_GET_LOG_LEN _IOR('M', 2, int) 31#define MCE_GET_LOG_LEN _IOR('M', 2, int)
114#define MCE_GETCLEAR_FLAGS _IOR('M', 3, int) 32#define MCE_GETCLEAR_FLAGS _IOR('M', 3, int)
115 33
116/* Software defined banks */
117#define MCE_EXTENDED_BANK 128
118#define MCE_THERMAL_BANK MCE_EXTENDED_BANK + 0
119#define K8_MCE_THRESHOLD_BASE (MCE_EXTENDED_BANK + 1)
120
121#endif /* _UAPI_ASM_X86_MCE_H */ 34#endif /* _UAPI_ASM_X86_MCE_H */
diff --git a/arch/x86/kernel/apic/x2apic_phys.c b/arch/x86/kernel/apic/x2apic_phys.c
index e03a1e180e81..562a76d433c8 100644
--- a/arch/x86/kernel/apic/x2apic_phys.c
+++ b/arch/x86/kernel/apic/x2apic_phys.c
@@ -20,18 +20,19 @@ static int set_x2apic_phys_mode(char *arg)
20} 20}
21early_param("x2apic_phys", set_x2apic_phys_mode); 21early_param("x2apic_phys", set_x2apic_phys_mode);
22 22
23static int x2apic_acpi_madt_oem_check(char *oem_id, char *oem_table_id) 23static bool x2apic_fadt_phys(void)
24{ 24{
25 if (x2apic_phys) 25 if ((acpi_gbl_FADT.header.revision >= FADT2_REVISION_ID) &&
26 return x2apic_enabled(); 26 (acpi_gbl_FADT.flags & ACPI_FADT_APIC_PHYSICAL)) {
27 else if ((acpi_gbl_FADT.header.revision >= FADT2_REVISION_ID) &&
28 (acpi_gbl_FADT.flags & ACPI_FADT_APIC_PHYSICAL) &&
29 x2apic_enabled()) {
30 printk(KERN_DEBUG "System requires x2apic physical mode\n"); 27 printk(KERN_DEBUG "System requires x2apic physical mode\n");
31 return 1; 28 return true;
32 } 29 }
33 else 30 return false;
34 return 0; 31}
32
33static int x2apic_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
34{
35 return x2apic_enabled() && (x2apic_phys || x2apic_fadt_phys());
35} 36}
36 37
37static void 38static void
@@ -82,7 +83,7 @@ static void init_x2apic_ldr(void)
82 83
83static int x2apic_phys_probe(void) 84static int x2apic_phys_probe(void)
84{ 85{
85 if (x2apic_mode && x2apic_phys) 86 if (x2apic_mode && (x2apic_phys || x2apic_fadt_phys()))
86 return 1; 87 return 1;
87 88
88 return apic == &apic_x2apic_phys; 89 return apic == &apic_x2apic_phys;
diff --git a/arch/x86/mm/fault.c b/arch/x86/mm/fault.c
index 027088f2f7dd..fb674fd3fc22 100644
--- a/arch/x86/mm/fault.c
+++ b/arch/x86/mm/fault.c
@@ -748,13 +748,15 @@ __bad_area_nosemaphore(struct pt_regs *regs, unsigned long error_code,
748 return; 748 return;
749 } 749 }
750#endif 750#endif
751 /* Kernel addresses are always protection faults: */
752 if (address >= TASK_SIZE)
753 error_code |= PF_PROT;
751 754
752 if (unlikely(show_unhandled_signals)) 755 if (likely(show_unhandled_signals))
753 show_signal_msg(regs, error_code, address, tsk); 756 show_signal_msg(regs, error_code, address, tsk);
754 757
755 /* Kernel addresses are always protection faults: */
756 tsk->thread.cr2 = address; 758 tsk->thread.cr2 = address;
757 tsk->thread.error_code = error_code | (address >= TASK_SIZE); 759 tsk->thread.error_code = error_code;
758 tsk->thread.trap_nr = X86_TRAP_PF; 760 tsk->thread.trap_nr = X86_TRAP_PF;
759 761
760 force_sig_info_fault(SIGSEGV, si_code, address, tsk, 0); 762 force_sig_info_fault(SIGSEGV, si_code, address, tsk, 0);
diff --git a/arch/x86/mm/init_64.c b/arch/x86/mm/init_64.c
index 2ead3c8a4c84..75c9a6a59697 100644
--- a/arch/x86/mm/init_64.c
+++ b/arch/x86/mm/init_64.c
@@ -831,6 +831,9 @@ int kern_addr_valid(unsigned long addr)
831 if (pud_none(*pud)) 831 if (pud_none(*pud))
832 return 0; 832 return 0;
833 833
834 if (pud_large(*pud))
835 return pfn_valid(pud_pfn(*pud));
836
834 pmd = pmd_offset(pud, addr); 837 pmd = pmd_offset(pud, addr);
835 if (pmd_none(*pmd)) 838 if (pmd_none(*pmd))
836 return 0; 839 return 0;
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-15 12:16:08 -0500