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-rw-r--r--arch/xtensa/mm/misc.S2
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/xtensa/mm/misc.S b/arch/xtensa/mm/misc.S
index c885664211d1..b048406d8756 100644
--- a/arch/xtensa/mm/misc.S
+++ b/arch/xtensa/mm/misc.S
@@ -84,6 +84,7 @@ ENTRY(copy_page)
84 84
85 retw 85 retw
86 86
87#ifdef CONFIG_MMU
87/* 88/*
88 * If we have to deal with cache aliasing, we use temporary memory mappings 89 * If we have to deal with cache aliasing, we use temporary memory mappings
89 * to ensure that the source and destination pages have the same color as 90 * to ensure that the source and destination pages have the same color as
@@ -311,6 +312,7 @@ ENTRY(__invalidate_icache_page_alias)
311/* End of special treatment in tlb miss exception */ 312/* End of special treatment in tlb miss exception */
312 313
313ENTRY(__tlbtemp_mapping_end) 314ENTRY(__tlbtemp_mapping_end)
315#endif /* CONFIG_MMU
314 316
315/* 317/*
316 * void __invalidate_icache_page(ulong start) 318 * void __invalidate_icache_page(ulong start)