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-rw-r--r--arch/sh/kernel/cpu/clock.c10
-rw-r--r--arch/sh/kernel/cpu/init.c2
-rw-r--r--arch/sh/kernel/cpu/sh2a/Makefile3
-rw-r--r--arch/sh/kernel/cpu/sh2a/clock-sh7201.c85
-rw-r--r--arch/sh/kernel/cpu/sh2a/probe.c7
-rw-r--r--arch/sh/kernel/cpu/sh2a/setup-sh7201.c331
-rw-r--r--arch/sh/kernel/cpu/sh3/entry.S14
-rw-r--r--arch/sh/kernel/cpu/sh3/ex.S2
-rw-r--r--arch/sh/kernel/cpu/sh4/softfloat.c73
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7722.c310
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7343.c37
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7366.c19
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7722.c50
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7723.c19
14 files changed, 768 insertions, 194 deletions
diff --git a/arch/sh/kernel/cpu/clock.c b/arch/sh/kernel/cpu/clock.c
index b7e46d5bba43..7b17137536d6 100644
--- a/arch/sh/kernel/cpu/clock.c
+++ b/arch/sh/kernel/cpu/clock.c
@@ -117,6 +117,11 @@ int clk_enable(struct clk *clk)
117 unsigned long flags; 117 unsigned long flags;
118 int ret; 118 int ret;
119 119
120 if (!clk)
121 return -EINVAL;
122
123 clk_enable(clk->parent);
124
120 spin_lock_irqsave(&clock_lock, flags); 125 spin_lock_irqsave(&clock_lock, flags);
121 ret = __clk_enable(clk); 126 ret = __clk_enable(clk);
122 spin_unlock_irqrestore(&clock_lock, flags); 127 spin_unlock_irqrestore(&clock_lock, flags);
@@ -147,9 +152,14 @@ void clk_disable(struct clk *clk)
147{ 152{
148 unsigned long flags; 153 unsigned long flags;
149 154
155 if (!clk)
156 return;
157
150 spin_lock_irqsave(&clock_lock, flags); 158 spin_lock_irqsave(&clock_lock, flags);
151 __clk_disable(clk); 159 __clk_disable(clk);
152 spin_unlock_irqrestore(&clock_lock, flags); 160 spin_unlock_irqrestore(&clock_lock, flags);
161
162 clk_disable(clk->parent);
153} 163}
154EXPORT_SYMBOL_GPL(clk_disable); 164EXPORT_SYMBOL_GPL(clk_disable);
155 165
diff --git a/arch/sh/kernel/cpu/init.c b/arch/sh/kernel/cpu/init.c
index 75fb03d35670..d29e69c156f0 100644
--- a/arch/sh/kernel/cpu/init.c
+++ b/arch/sh/kernel/cpu/init.c
@@ -261,9 +261,11 @@ asmlinkage void __init sh_cpu_init(void)
261 cache_init(); 261 cache_init();
262 262
263 if (raw_smp_processor_id() == 0) { 263 if (raw_smp_processor_id() == 0) {
264#ifdef CONFIG_MMU
264 shm_align_mask = max_t(unsigned long, 265 shm_align_mask = max_t(unsigned long,
265 current_cpu_data.dcache.way_size - 1, 266 current_cpu_data.dcache.way_size - 1,
266 PAGE_SIZE - 1); 267 PAGE_SIZE - 1);
268#endif
267 269
268 /* Boot CPU sets the cache shape */ 270 /* Boot CPU sets the cache shape */
269 detect_cache_shape(); 271 detect_cache_shape();
diff --git a/arch/sh/kernel/cpu/sh2a/Makefile b/arch/sh/kernel/cpu/sh2a/Makefile
index 428450cc0809..45f85c77ef75 100644
--- a/arch/sh/kernel/cpu/sh2a/Makefile
+++ b/arch/sh/kernel/cpu/sh2a/Makefile
@@ -8,9 +8,10 @@ common-y += ex.o entry.o
8 8
9obj-$(CONFIG_SH_FPU) += fpu.o 9obj-$(CONFIG_SH_FPU) += fpu.o
10 10
11obj-$(CONFIG_CPU_SUBTYPE_SH7206) += setup-sh7206.o clock-sh7206.o 11obj-$(CONFIG_CPU_SUBTYPE_SH7201) += setup-sh7201.o clock-sh7201.o
12obj-$(CONFIG_CPU_SUBTYPE_SH7203) += setup-sh7203.o clock-sh7203.o 12obj-$(CONFIG_CPU_SUBTYPE_SH7203) += setup-sh7203.o clock-sh7203.o
13obj-$(CONFIG_CPU_SUBTYPE_SH7263) += setup-sh7203.o clock-sh7203.o 13obj-$(CONFIG_CPU_SUBTYPE_SH7263) += setup-sh7203.o clock-sh7203.o
14obj-$(CONFIG_CPU_SUBTYPE_SH7206) += setup-sh7206.o clock-sh7206.o
14obj-$(CONFIG_CPU_SUBTYPE_MXG) += setup-mxg.o clock-sh7206.o 15obj-$(CONFIG_CPU_SUBTYPE_MXG) += setup-mxg.o clock-sh7206.o
15 16
16# Pinmux setup 17# Pinmux setup
diff --git a/arch/sh/kernel/cpu/sh2a/clock-sh7201.c b/arch/sh/kernel/cpu/sh2a/clock-sh7201.c
new file mode 100644
index 000000000000..020a96fe961a
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh2a/clock-sh7201.c
@@ -0,0 +1,85 @@
1/*
2 * arch/sh/kernel/cpu/sh2a/clock-sh7201.c
3 *
4 * SH7201 support for the clock framework
5 *
6 * Copyright (C) 2008 Peter Griffin <pgriffin@mpc-data.co.uk>
7 *
8 * Based on clock-sh4.c
9 * Copyright (C) 2005 Paul Mundt
10 *
11 * This file is subject to the terms and conditions of the GNU General Public
12 * License. See the file "COPYING" in the main directory of this archive
13 * for more details.
14 */
15#include <linux/init.h>
16#include <linux/kernel.h>
17#include <asm/clock.h>
18#include <asm/freq.h>
19#include <asm/io.h>
20
21const static int pll1rate[]={1,2,3,4,6,8};
22const static int pfc_divisors[]={1,2,3,4,6,8,12};
23#define ifc_divisors pfc_divisors
24
25#if (CONFIG_SH_CLK_MD == 0)
26#define PLL2 (4)
27#elif (CONFIG_SH_CLK_MD == 2)
28#define PLL2 (2)
29#elif (CONFIG_SH_CLK_MD == 3)
30#define PLL2 (1)
31#else
32#error "Illegal Clock Mode!"
33#endif
34
35static void master_clk_init(struct clk *clk)
36{
37 clk->rate = 10000000 * PLL2 * pll1rate[(ctrl_inw(FREQCR) >> 8) & 0x0007];
38}
39
40static struct clk_ops sh7201_master_clk_ops = {
41 .init = master_clk_init,
42};
43
44static void module_clk_recalc(struct clk *clk)
45{
46 int idx = (ctrl_inw(FREQCR) & 0x0007);
47 clk->rate = clk->parent->rate / pfc_divisors[idx];
48}
49
50static struct clk_ops sh7201_module_clk_ops = {
51 .recalc = module_clk_recalc,
52};
53
54static void bus_clk_recalc(struct clk *clk)
55{
56 int idx = (ctrl_inw(FREQCR) & 0x0007);
57 clk->rate = clk->parent->rate / pfc_divisors[idx];
58}
59
60static struct clk_ops sh7201_bus_clk_ops = {
61 .recalc = bus_clk_recalc,
62};
63
64static void cpu_clk_recalc(struct clk *clk)
65{
66 int idx = ((ctrl_inw(FREQCR) >> 4) & 0x0007);
67 clk->rate = clk->parent->rate / ifc_divisors[idx];
68}
69
70static struct clk_ops sh7201_cpu_clk_ops = {
71 .recalc = cpu_clk_recalc,
72};
73
74static struct clk_ops *sh7201_clk_ops[] = {
75 &sh7201_master_clk_ops,
76 &sh7201_module_clk_ops,
77 &sh7201_bus_clk_ops,
78 &sh7201_cpu_clk_ops,
79};
80
81void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
82{
83 if (idx < ARRAY_SIZE(sh7201_clk_ops))
84 *ops = sh7201_clk_ops[idx];
85}
diff --git a/arch/sh/kernel/cpu/sh2a/probe.c b/arch/sh/kernel/cpu/sh2a/probe.c
index 6e79132f6f30..e098e2f6aa08 100644
--- a/arch/sh/kernel/cpu/sh2a/probe.c
+++ b/arch/sh/kernel/cpu/sh2a/probe.c
@@ -18,16 +18,17 @@ int __init detect_cpu_and_cache_system(void)
18 /* All SH-2A CPUs have support for 16 and 32-bit opcodes.. */ 18 /* All SH-2A CPUs have support for 16 and 32-bit opcodes.. */
19 boot_cpu_data.flags |= CPU_HAS_OP32; 19 boot_cpu_data.flags |= CPU_HAS_OP32;
20 20
21#if defined(CONFIG_CPU_SUBTYPE_SH7203) 21#if defined(CONFIG_CPU_SUBTYPE_SH7201)
22 boot_cpu_data.type = CPU_SH7201;
23 boot_cpu_data.flags |= CPU_HAS_FPU;
24#elif defined(CONFIG_CPU_SUBTYPE_SH7203)
22 boot_cpu_data.type = CPU_SH7203; 25 boot_cpu_data.type = CPU_SH7203;
23 /* SH7203 has an FPU.. */
24 boot_cpu_data.flags |= CPU_HAS_FPU; 26 boot_cpu_data.flags |= CPU_HAS_FPU;
25#elif defined(CONFIG_CPU_SUBTYPE_SH7263) 27#elif defined(CONFIG_CPU_SUBTYPE_SH7263)
26 boot_cpu_data.type = CPU_SH7263; 28 boot_cpu_data.type = CPU_SH7263;
27 boot_cpu_data.flags |= CPU_HAS_FPU; 29 boot_cpu_data.flags |= CPU_HAS_FPU;
28#elif defined(CONFIG_CPU_SUBTYPE_SH7206) 30#elif defined(CONFIG_CPU_SUBTYPE_SH7206)
29 boot_cpu_data.type = CPU_SH7206; 31 boot_cpu_data.type = CPU_SH7206;
30 /* While SH7206 has a DSP.. */
31 boot_cpu_data.flags |= CPU_HAS_DSP; 32 boot_cpu_data.flags |= CPU_HAS_DSP;
32#elif defined(CONFIG_CPU_SUBTYPE_MXG) 33#elif defined(CONFIG_CPU_SUBTYPE_MXG)
33 boot_cpu_data.type = CPU_MXG; 34 boot_cpu_data.type = CPU_MXG;
diff --git a/arch/sh/kernel/cpu/sh2a/setup-sh7201.c b/arch/sh/kernel/cpu/sh2a/setup-sh7201.c
new file mode 100644
index 000000000000..0631e421c022
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh2a/setup-sh7201.c
@@ -0,0 +1,331 @@
1/*
2 * SH7201 setup
3 *
4 * Copyright (C) 2008 Peter Griffin pgriffin@mpc-data.co.uk
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#include <linux/platform_device.h>
11#include <linux/init.h>
12#include <linux/serial.h>
13#include <linux/serial_sci.h>
14
15enum {
16 UNUSED = 0,
17
18 /* interrupt sources */
19 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
20 PINT0, PINT1, PINT2, PINT3, PINT4, PINT5, PINT6, PINT7,
21 ADC_ADI,
22 MTU2_TGI0A, MTU2_TGI0B, MTU2_TGI0C, MTU2_TGI0D,
23 MTU2_TCI0V, MTU2_TGI0E, MTU2_TGI0F,
24 MTU2_TGI1A, MTU2_TGI1B, MTU2_TCI1V, MTU2_TCI1U,
25 MTU2_TGI2A, MTU2_TGI2B, MTU2_TCI2V, MTU2_TCI2U,
26 MTU2_TGI3A, MTU2_TGI3B, MTU2_TGI3C, MTU2_TGI3D, MTU2_TCI3V,
27 MTU2_TGI4A, MTU2_TGI4B, MTU2_TGI4C, MTU2_TGI4D, MTU2_TCI4V,
28 MTU2_TGI5U, MTU2_TGI5V, MTU2_TGI5W,
29 RTC_ARM, RTC_PRD, RTC_CUP,
30 WDT,
31 IIC30_STPI, IIC30_NAKI, IIC30_RXI, IIC30_TXI, IIC30_TEI,
32 IIC31_STPI, IIC31_NAKI, IIC31_RXI, IIC31_TXI, IIC31_TEI,
33 IIC32_STPI, IIC32_NAKI, IIC32_RXI, IIC32_TXI, IIC32_TEI,
34
35 DMAC0_DMINT0, DMAC1_DMINT1,
36 DMAC2_DMINT2, DMAC3_DMINT3,
37
38 SCIF0_BRI, SCIF0_ERI, SCIF0_RXI, SCIF0_TXI,
39 SCIF1_BRI, SCIF1_ERI, SCIF1_RXI, SCIF1_TXI,
40 SCIF2_BRI, SCIF2_ERI, SCIF2_RXI, SCIF2_TXI,
41 SCIF3_BRI, SCIF3_ERI, SCIF3_RXI, SCIF3_TXI,
42 SCIF4_BRI, SCIF4_ERI, SCIF4_RXI, SCIF4_TXI,
43 SCIF5_BRI, SCIF5_ERI, SCIF5_RXI, SCIF5_TXI,
44 SCIF6_BRI, SCIF6_ERI, SCIF6_RXI, SCIF6_TXI,
45 SCIF7_BRI, SCIF7_ERI, SCIF7_RXI, SCIF7_TXI,
46
47 DMAC0_DMINTA, DMAC4_DMINT4, DMAC5_DMINT5, DMAC6_DMINT6,
48 DMAC7_DMINT7,
49
50 RCAN0_ERS, RCAN0_OVR,
51 RCAN0_SLE,
52 RCAN0_RM0, RCAN0_RM1,
53
54 RCAN1_ERS, RCAN1_OVR,
55 RCAN1_SLE,
56 RCAN1_RM0, RCAN1_RM1,
57
58 SSI0_SSII, SSI1_SSII,
59
60 TMR0_CMIA0, TMR0_CMIB0, TMR0_OVI0,
61 TMR1_CMIA1, TMR1_CMIB1, TMR1_OVI1,
62
63 /* interrupt groups */
64
65 IRQ, PINT, ADC,
66 MTU20_ABCD, MTU20_VEF, MTU21_AB, MTU21_VU, MTU22_AB, MTU22_VU,
67 MTU23_ABCD, MTU24_ABCD, MTU25_UVW,
68 RTC, IIC30, IIC31, IIC32,
69 SCIF0, SCIF1, SCIF2, SCIF3, SCIF4, SCIF5, SCIF6, SCIF7,
70 RCAN0, RCAN1, TMR0, TMR1
71
72};
73
74static struct intc_vect vectors[] __initdata = {
75 INTC_IRQ(IRQ0, 64), INTC_IRQ(IRQ1, 65),
76 INTC_IRQ(IRQ2, 66), INTC_IRQ(IRQ3, 67),
77 INTC_IRQ(IRQ4, 68), INTC_IRQ(IRQ5, 69),
78 INTC_IRQ(IRQ6, 70), INTC_IRQ(IRQ7, 71),
79 INTC_IRQ(PINT0, 80), INTC_IRQ(PINT1, 81),
80 INTC_IRQ(PINT2, 82), INTC_IRQ(PINT3, 83),
81 INTC_IRQ(PINT4, 84), INTC_IRQ(PINT5, 85),
82 INTC_IRQ(PINT6, 86), INTC_IRQ(PINT7, 87),
83
84 INTC_IRQ(ADC_ADI, 92),
85
86 INTC_IRQ(MTU2_TGI0A, 108), INTC_IRQ(MTU2_TGI0B, 109),
87 INTC_IRQ(MTU2_TGI0C, 110), INTC_IRQ(MTU2_TGI0D, 111),
88 INTC_IRQ(MTU2_TCI0V, 112),
89 INTC_IRQ(MTU2_TGI0E, 113), INTC_IRQ(MTU2_TGI0F, 114),
90
91 INTC_IRQ(MTU2_TGI1A, 116), INTC_IRQ(MTU2_TGI1B, 117),
92 INTC_IRQ(MTU2_TCI1V, 120), INTC_IRQ(MTU2_TCI1U, 121),
93
94 INTC_IRQ(MTU2_TGI2A, 124), INTC_IRQ(MTU2_TGI2B, 125),
95 INTC_IRQ(MTU2_TCI2V, 128), INTC_IRQ(MTU2_TCI2U, 129),
96
97 INTC_IRQ(MTU2_TGI3A, 132), INTC_IRQ(MTU2_TGI3B, 133),
98 INTC_IRQ(MTU2_TGI3C, 134), INTC_IRQ(MTU2_TGI3D, 135),
99 INTC_IRQ(MTU2_TCI3V, 136),
100
101 INTC_IRQ(MTU2_TGI4A, 140), INTC_IRQ(MTU2_TGI4B, 141),
102 INTC_IRQ(MTU2_TGI4C, 142), INTC_IRQ(MTU2_TGI4D, 143),
103 INTC_IRQ(MTU2_TCI4V, 144),
104
105 INTC_IRQ(MTU2_TGI5U, 148), INTC_IRQ(MTU2_TGI5V, 149),
106 INTC_IRQ(MTU2_TGI5W, 150),
107
108 INTC_IRQ(RTC_ARM, 152), INTC_IRQ(RTC_PRD, 153),
109 INTC_IRQ(RTC_CUP, 154), INTC_IRQ(WDT, 156),
110
111 INTC_IRQ(IIC30_STPI, 157), INTC_IRQ(IIC30_NAKI, 158),
112 INTC_IRQ(IIC30_RXI, 159), INTC_IRQ(IIC30_TXI, 160),
113 INTC_IRQ(IIC30_TEI, 161),
114
115 INTC_IRQ(IIC31_STPI, 164), INTC_IRQ(IIC31_NAKI, 165),
116 INTC_IRQ(IIC31_RXI, 166), INTC_IRQ(IIC31_TXI, 167),
117 INTC_IRQ(IIC31_TEI, 168),
118
119 INTC_IRQ(IIC32_STPI, 170), INTC_IRQ(IIC32_NAKI, 171),
120 INTC_IRQ(IIC32_RXI, 172), INTC_IRQ(IIC32_TXI, 173),
121 INTC_IRQ(IIC32_TEI, 174),
122
123 INTC_IRQ(DMAC0_DMINT0, 176), INTC_IRQ(DMAC1_DMINT1, 177),
124 INTC_IRQ(DMAC2_DMINT2, 178), INTC_IRQ(DMAC3_DMINT3, 179),
125
126 INTC_IRQ(SCIF0_BRI, 180), INTC_IRQ(SCIF0_ERI, 181),
127 INTC_IRQ(SCIF0_RXI, 182), INTC_IRQ(SCIF0_TXI, 183),
128 INTC_IRQ(SCIF1_BRI, 184), INTC_IRQ(SCIF1_ERI, 185),
129 INTC_IRQ(SCIF1_RXI, 186), INTC_IRQ(SCIF1_TXI, 187),
130 INTC_IRQ(SCIF2_BRI, 188), INTC_IRQ(SCIF2_ERI, 189),
131 INTC_IRQ(SCIF2_RXI, 190), INTC_IRQ(SCIF2_TXI, 191),
132 INTC_IRQ(SCIF3_BRI, 192), INTC_IRQ(SCIF3_ERI, 193),
133 INTC_IRQ(SCIF3_RXI, 194), INTC_IRQ(SCIF3_TXI, 195),
134 INTC_IRQ(SCIF4_BRI, 196), INTC_IRQ(SCIF4_ERI, 197),
135 INTC_IRQ(SCIF4_RXI, 198), INTC_IRQ(SCIF4_TXI, 199),
136 INTC_IRQ(SCIF5_BRI, 200), INTC_IRQ(SCIF5_ERI, 201),
137 INTC_IRQ(SCIF5_RXI, 202), INTC_IRQ(SCIF5_TXI, 203),
138 INTC_IRQ(SCIF6_BRI, 204), INTC_IRQ(SCIF6_ERI, 205),
139 INTC_IRQ(SCIF6_RXI, 206), INTC_IRQ(SCIF6_TXI, 207),
140 INTC_IRQ(SCIF7_BRI, 208), INTC_IRQ(SCIF7_ERI, 209),
141 INTC_IRQ(SCIF7_RXI, 210), INTC_IRQ(SCIF7_TXI, 211),
142
143 INTC_IRQ(DMAC0_DMINTA, 212), INTC_IRQ(DMAC4_DMINT4, 216),
144 INTC_IRQ(DMAC5_DMINT5, 217), INTC_IRQ(DMAC6_DMINT6, 218),
145 INTC_IRQ(DMAC7_DMINT7, 219),
146
147 INTC_IRQ(RCAN0_ERS, 228), INTC_IRQ(RCAN0_OVR, 229),
148 INTC_IRQ(RCAN0_SLE, 230),
149 INTC_IRQ(RCAN0_RM0, 231), INTC_IRQ(RCAN0_RM1, 232),
150
151 INTC_IRQ(RCAN1_ERS, 234), INTC_IRQ(RCAN1_OVR, 235),
152 INTC_IRQ(RCAN1_SLE, 236),
153 INTC_IRQ(RCAN1_RM0, 237), INTC_IRQ(RCAN1_RM1, 238),
154
155 INTC_IRQ(SSI0_SSII, 244), INTC_IRQ(SSI1_SSII, 245),
156
157 INTC_IRQ(TMR0_CMIA0, 246), INTC_IRQ(TMR0_CMIB0, 247),
158 INTC_IRQ(TMR0_OVI0, 248),
159
160 INTC_IRQ(TMR1_CMIA1, 252), INTC_IRQ(TMR1_CMIB1, 253),
161 INTC_IRQ(TMR1_OVI1, 254),
162
163};
164
165static struct intc_group groups[] __initdata = {
166 INTC_GROUP(PINT, PINT0, PINT1, PINT2, PINT3,
167 PINT4, PINT5, PINT6, PINT7),
168 INTC_GROUP(MTU20_ABCD, MTU2_TGI0A, MTU2_TGI0B, MTU2_TGI0C, MTU2_TGI0D),
169 INTC_GROUP(MTU20_VEF, MTU2_TCI0V, MTU2_TGI0E, MTU2_TGI0F),
170
171 INTC_GROUP(MTU21_AB, MTU2_TGI1A, MTU2_TGI1B),
172 INTC_GROUP(MTU21_VU, MTU2_TCI1V, MTU2_TCI1U),
173 INTC_GROUP(MTU22_AB, MTU2_TGI2A, MTU2_TGI2B),
174 INTC_GROUP(MTU22_VU, MTU2_TCI2V, MTU2_TCI2U),
175 INTC_GROUP(MTU23_ABCD, MTU2_TGI3A, MTU2_TGI3B, MTU2_TGI3C, MTU2_TGI3D),
176 INTC_GROUP(MTU24_ABCD, MTU2_TGI4A, MTU2_TGI4B, MTU2_TGI4C, MTU2_TGI4D),
177 INTC_GROUP(MTU25_UVW, MTU2_TGI5U, MTU2_TGI5V, MTU2_TGI5W),
178 INTC_GROUP(RTC, RTC_ARM, RTC_PRD, RTC_CUP ),
179
180 INTC_GROUP(IIC30, IIC30_STPI, IIC30_NAKI, IIC30_RXI, IIC30_TXI,
181 IIC30_TEI),
182 INTC_GROUP(IIC31, IIC31_STPI, IIC31_NAKI, IIC31_RXI, IIC31_TXI,
183 IIC31_TEI),
184 INTC_GROUP(IIC32, IIC32_STPI, IIC32_NAKI, IIC32_RXI, IIC32_TXI,
185 IIC32_TEI),
186
187 INTC_GROUP(SCIF0, SCIF0_BRI, SCIF0_ERI, SCIF0_RXI, SCIF0_TXI),
188 INTC_GROUP(SCIF1, SCIF1_BRI, SCIF1_ERI, SCIF1_RXI, SCIF1_TXI),
189 INTC_GROUP(SCIF2, SCIF2_BRI, SCIF2_ERI, SCIF2_RXI, SCIF2_TXI),
190 INTC_GROUP(SCIF3, SCIF3_BRI, SCIF3_ERI, SCIF3_RXI, SCIF3_TXI),
191 INTC_GROUP(SCIF4, SCIF4_BRI, SCIF4_ERI, SCIF4_RXI, SCIF4_TXI),
192 INTC_GROUP(SCIF5, SCIF5_BRI, SCIF5_ERI, SCIF5_RXI, SCIF5_TXI),
193 INTC_GROUP(SCIF6, SCIF6_BRI, SCIF6_ERI, SCIF6_RXI, SCIF6_TXI),
194 INTC_GROUP(SCIF7, SCIF7_BRI, SCIF7_ERI, SCIF7_RXI, SCIF7_TXI),
195
196 INTC_GROUP(RCAN0, RCAN0_ERS, RCAN0_OVR, RCAN0_RM0, RCAN0_RM1,
197 RCAN0_SLE),
198 INTC_GROUP(RCAN1, RCAN1_ERS, RCAN1_OVR, RCAN1_RM0, RCAN1_RM1,
199 RCAN1_SLE),
200
201 INTC_GROUP(TMR0, TMR0_CMIA0, TMR0_CMIB0, TMR0_OVI0),
202 INTC_GROUP(TMR1, TMR1_CMIA1, TMR1_CMIB1, TMR1_OVI1),
203};
204
205static struct intc_prio_reg prio_registers[] __initdata = {
206 { 0xfffe9418, 0, 16, 4, /* IPR01 */ { IRQ0, IRQ1, IRQ2, IRQ3 } },
207 { 0xfffe941a, 0, 16, 4, /* IPR02 */ { IRQ4, IRQ5, IRQ6, IRQ7 } },
208 { 0xfffe9420, 0, 16, 4, /* IPR05 */ { PINT, 0, ADC_ADI, 0 } },
209 { 0xfffe9800, 0, 16, 4, /* IPR06 */ { 0, MTU20_ABCD, MTU20_VEF, MTU21_AB } },
210 { 0xfffe9802, 0, 16, 4, /* IPR07 */ { MTU21_VU, MTU22_AB, MTU22_VU, MTU23_ABCD } },
211 { 0xfffe9804, 0, 16, 4, /* IPR08 */ { MTU2_TCI3V, MTU24_ABCD, MTU2_TCI4V, MTU25_UVW } },
212
213 { 0xfffe9806, 0, 16, 4, /* IPR09 */ { RTC, WDT, IIC30, 0 } },
214 { 0xfffe9808, 0, 16, 4, /* IPR10 */ { IIC31, IIC32, DMAC0_DMINT0, DMAC1_DMINT1 } },
215 { 0xfffe980a, 0, 16, 4, /* IPR11 */ { DMAC2_DMINT2, DMAC3_DMINT3, SCIF0 , SCIF1 } },
216 { 0xfffe980c, 0, 16, 4, /* IPR12 */ { SCIF2, SCIF3, SCIF4, SCIF5 } },
217 { 0xfffe980e, 0, 16, 4, /* IPR13 */ { SCIF6, SCIF7, DMAC0_DMINTA, DMAC4_DMINT4 } },
218 { 0xfffe9810, 0, 16, 4, /* IPR14 */ { DMAC5_DMINT5, DMAC6_DMINT6, DMAC7_DMINT7, 0 } },
219 { 0xfffe9812, 0, 16, 4, /* IPR15 */ { 0, RCAN0, RCAN1, 0 } },
220 { 0xfffe9814, 0, 16, 4, /* IPR16 */ { SSI0_SSII, SSI1_SSII, TMR0, TMR1 } },
221};
222
223static struct intc_mask_reg mask_registers[] __initdata = {
224 { 0xfffe9408, 0, 16, /* PINTER */
225 { 0, 0, 0, 0, 0, 0, 0, 0,
226 PINT7, PINT6, PINT5, PINT4, PINT3, PINT2, PINT1, PINT0 } },
227};
228
229static DECLARE_INTC_DESC(intc_desc, "sh7201", vectors, groups,
230 mask_registers, prio_registers, NULL);
231
232static struct plat_sci_port sci_platform_data[] = {
233 {
234 .mapbase = 0xfffe8000,
235 .flags = UPF_BOOT_AUTOCONF,
236 .type = PORT_SCIF,
237 .irqs = { 181, 182, 183, 180}
238 }, {
239 .mapbase = 0xfffe8800,
240 .flags = UPF_BOOT_AUTOCONF,
241 .type = PORT_SCIF,
242 .irqs = { 185, 186, 187, 184}
243 }, {
244 .mapbase = 0xfffe9000,
245 .flags = UPF_BOOT_AUTOCONF,
246 .type = PORT_SCIF,
247 .irqs = { 189, 186, 187, 188}
248 }, {
249 .mapbase = 0xfffe9800,
250 .flags = UPF_BOOT_AUTOCONF,
251 .type = PORT_SCIF,
252 .irqs = { 193, 194, 195, 192}
253 }, {
254 .mapbase = 0xfffea000,
255 .flags = UPF_BOOT_AUTOCONF,
256 .type = PORT_SCIF,
257 .irqs = { 196, 198, 199, 196}
258 }, {
259 .mapbase = 0xfffea800,
260 .flags = UPF_BOOT_AUTOCONF,
261 .type = PORT_SCIF,
262 .irqs = { 201, 202, 203, 200}
263 }, {
264 .mapbase = 0xfffeb000,
265 .flags = UPF_BOOT_AUTOCONF,
266 .type = PORT_SCIF,
267 .irqs = { 205, 206, 207, 204}
268 }, {
269 .mapbase = 0xfffeb800,
270 .flags = UPF_BOOT_AUTOCONF,
271 .type = PORT_SCIF,
272 .irqs = { 209, 210, 211, 208}
273 }, {
274 .flags = 0,
275 }
276};
277
278static struct platform_device sci_device = {
279 .name = "sh-sci",
280 .id = -1,
281 .dev = {
282 .platform_data = sci_platform_data,
283 },
284};
285
286static struct resource rtc_resources[] = {
287 [0] = {
288 .start = 0xffff0800,
289 .end = 0xffff2000 + 0x58 - 1,
290 .flags = IORESOURCE_IO,
291 },
292 [1] = {
293 /* Period IRQ */
294 .start = 153,
295 .flags = IORESOURCE_IRQ,
296 },
297 [2] = {
298 /* Carry IRQ */
299 .start = 154,
300 .flags = IORESOURCE_IRQ,
301 },
302 [3] = {
303 /* Alarm IRQ */
304 .start = 152,
305 .flags = IORESOURCE_IRQ,
306 },
307};
308
309static struct platform_device rtc_device = {
310 .name = "sh-rtc",
311 .id = -1,
312 .num_resources = ARRAY_SIZE(rtc_resources),
313 .resource = rtc_resources,
314};
315
316static struct platform_device *sh7201_devices[] __initdata = {
317 &sci_device,
318 &rtc_device,
319};
320
321static int __init sh7201_devices_setup(void)
322{
323 return platform_add_devices(sh7201_devices,
324 ARRAY_SIZE(sh7201_devices));
325}
326__initcall(sh7201_devices_setup);
327
328void __init plat_irq_setup(void)
329{
330 register_intc_controller(&intc_desc);
331}
diff --git a/arch/sh/kernel/cpu/sh3/entry.S b/arch/sh/kernel/cpu/sh3/entry.S
index 3fe482dd05c1..b4106d0c68ec 100644
--- a/arch/sh/kernel/cpu/sh3/entry.S
+++ b/arch/sh/kernel/cpu/sh3/entry.S
@@ -52,7 +52,7 @@
52 * syscall # 52 * syscall #
53 * 53 *
54 */ 54 */
55#if defined(CONFIG_KGDB_NMI) 55#if defined(CONFIG_KGDB)
56NMI_VEC = 0x1c0 ! Must catch early for debounce 56NMI_VEC = 0x1c0 ! Must catch early for debounce
57#endif 57#endif
58 58
@@ -307,7 +307,7 @@ skip_restore:
3076: or k0, k2 ! Set the IMASK-bits 3076: or k0, k2 ! Set the IMASK-bits
308 ldc k2, ssr 308 ldc k2, ssr
309 ! 309 !
310#if defined(CONFIG_KGDB_NMI) 310#if defined(CONFIG_KGDB)
311 ! Clear in_nmi 311 ! Clear in_nmi
312 mov.l 6f, k0 312 mov.l 6f, k0
313 mov #0, k1 313 mov #0, k1
@@ -320,7 +320,7 @@ skip_restore:
320 320
321 .align 2 321 .align 2
3225: .long 0x00001000 ! DSP 3225: .long 0x00001000 ! DSP
323#ifdef CONFIG_KGDB_NMI 323#ifdef CONFIG_KGDB
3246: .long in_nmi 3246: .long in_nmi
325#endif 325#endif
3267: .long 0x30000000 3267: .long 0x30000000
@@ -376,9 +376,9 @@ tlb_miss:
376! 376!
377 .balign 512,0,512 377 .balign 512,0,512
378interrupt: 378interrupt:
379 mov.l 2f, k2
380 mov.l 3f, k3 379 mov.l 3f, k3
381#if defined(CONFIG_KGDB_NMI) 380#if defined(CONFIG_KGDB)
381 mov.l 2f, k2
382 ! Debounce (filter nested NMI) 382 ! Debounce (filter nested NMI)
383 mov.l @k2, k0 383 mov.l @k2, k0
384 mov.l 5f, k1 384 mov.l 5f, k1
@@ -390,16 +390,16 @@ interrupt:
390 rte 390 rte
391 nop 391 nop
392 .align 2 392 .align 2
3932: .long INTEVT
3935: .long NMI_VEC 3945: .long NMI_VEC
3946: .long in_nmi 3956: .long in_nmi
3950: 3960:
396#endif /* defined(CONFIG_KGDB_NMI) */ 397#endif /* defined(CONFIG_KGDB) */
397 bra handle_exception 398 bra handle_exception
398 mov #-1, k2 ! interrupt exception marker 399 mov #-1, k2 ! interrupt exception marker
399 400
400 .align 2 401 .align 2
4011: .long EXPEVT 4021: .long EXPEVT
4022: .long INTEVT
4033: .long ret_from_irq 4033: .long ret_from_irq
4044: .long ret_from_exception 4044: .long ret_from_exception
405 405
diff --git a/arch/sh/kernel/cpu/sh3/ex.S b/arch/sh/kernel/cpu/sh3/ex.S
index dac429726899..e5a0de39a2db 100644
--- a/arch/sh/kernel/cpu/sh3/ex.S
+++ b/arch/sh/kernel/cpu/sh3/ex.S
@@ -26,7 +26,7 @@
26#define fpu_error_trap_handler exception_error 26#define fpu_error_trap_handler exception_error
27#endif 27#endif
28 28
29#if !defined(CONFIG_KGDB_NMI) 29#if !defined(CONFIG_KGDB)
30#define kgdb_handle_exception exception_error 30#define kgdb_handle_exception exception_error
31#endif 31#endif
32 32
diff --git a/arch/sh/kernel/cpu/sh4/softfloat.c b/arch/sh/kernel/cpu/sh4/softfloat.c
index 2b747f3b02bd..42edf2e54e85 100644
--- a/arch/sh/kernel/cpu/sh4/softfloat.c
+++ b/arch/sh/kernel/cpu/sh4/softfloat.c
@@ -37,6 +37,7 @@
37 */ 37 */
38#include <linux/kernel.h> 38#include <linux/kernel.h>
39#include <cpu/fpu.h> 39#include <cpu/fpu.h>
40#include <asm/div64.h>
40 41
41#define LIT64( a ) a##LL 42#define LIT64( a ) a##LL
42 43
@@ -67,16 +68,16 @@ typedef unsigned long long float64;
67extern void float_raise(unsigned int flags); /* in fpu.c */ 68extern void float_raise(unsigned int flags); /* in fpu.c */
68extern int float_rounding_mode(void); /* in fpu.c */ 69extern int float_rounding_mode(void); /* in fpu.c */
69 70
70inline bits64 extractFloat64Frac(float64 a); 71bits64 extractFloat64Frac(float64 a);
71inline flag extractFloat64Sign(float64 a); 72flag extractFloat64Sign(float64 a);
72inline int16 extractFloat64Exp(float64 a); 73int16 extractFloat64Exp(float64 a);
73inline int16 extractFloat32Exp(float32 a); 74int16 extractFloat32Exp(float32 a);
74inline flag extractFloat32Sign(float32 a); 75flag extractFloat32Sign(float32 a);
75inline bits32 extractFloat32Frac(float32 a); 76bits32 extractFloat32Frac(float32 a);
76inline float64 packFloat64(flag zSign, int16 zExp, bits64 zSig); 77float64 packFloat64(flag zSign, int16 zExp, bits64 zSig);
77inline void shift64RightJamming(bits64 a, int16 count, bits64 * zPtr); 78void shift64RightJamming(bits64 a, int16 count, bits64 * zPtr);
78inline float32 packFloat32(flag zSign, int16 zExp, bits32 zSig); 79float32 packFloat32(flag zSign, int16 zExp, bits32 zSig);
79inline void shift32RightJamming(bits32 a, int16 count, bits32 * zPtr); 80void shift32RightJamming(bits32 a, int16 count, bits32 * zPtr);
80float64 float64_sub(float64 a, float64 b); 81float64 float64_sub(float64 a, float64 b);
81float32 float32_sub(float32 a, float32 b); 82float32 float32_sub(float32 a, float32 b);
82float32 float32_add(float32 a, float32 b); 83float32 float32_add(float32 a, float32 b);
@@ -86,11 +87,11 @@ float32 float32_div(float32 a, float32 b);
86float32 float32_mul(float32 a, float32 b); 87float32 float32_mul(float32 a, float32 b);
87float64 float64_mul(float64 a, float64 b); 88float64 float64_mul(float64 a, float64 b);
88float32 float64_to_float32(float64 a); 89float32 float64_to_float32(float64 a);
89inline void add128(bits64 a0, bits64 a1, bits64 b0, bits64 b1, bits64 * z0Ptr, 90void add128(bits64 a0, bits64 a1, bits64 b0, bits64 b1, bits64 * z0Ptr,
90 bits64 * z1Ptr); 91 bits64 * z1Ptr);
91inline void sub128(bits64 a0, bits64 a1, bits64 b0, bits64 b1, bits64 * z0Ptr, 92void sub128(bits64 a0, bits64 a1, bits64 b0, bits64 b1, bits64 * z0Ptr,
92 bits64 * z1Ptr); 93 bits64 * z1Ptr);
93inline void mul64To128(bits64 a, bits64 b, bits64 * z0Ptr, bits64 * z1Ptr); 94void mul64To128(bits64 a, bits64 b, bits64 * z0Ptr, bits64 * z1Ptr);
94 95
95static int8 countLeadingZeros32(bits32 a); 96static int8 countLeadingZeros32(bits32 a);
96static int8 countLeadingZeros64(bits64 a); 97static int8 countLeadingZeros64(bits64 a);
@@ -110,42 +111,42 @@ static bits64 estimateDiv128To64(bits64 a0, bits64 a1, bits64 b);
110static void normalizeFloat32Subnormal(bits32 aSig, int16 * zExpPtr, 111static void normalizeFloat32Subnormal(bits32 aSig, int16 * zExpPtr,
111 bits32 * zSigPtr); 112 bits32 * zSigPtr);
112 113
113inline bits64 extractFloat64Frac(float64 a) 114bits64 extractFloat64Frac(float64 a)
114{ 115{
115 return a & LIT64(0x000FFFFFFFFFFFFF); 116 return a & LIT64(0x000FFFFFFFFFFFFF);
116} 117}
117 118
118inline flag extractFloat64Sign(float64 a) 119flag extractFloat64Sign(float64 a)
119{ 120{
120 return a >> 63; 121 return a >> 63;
121} 122}
122 123
123inline int16 extractFloat64Exp(float64 a) 124int16 extractFloat64Exp(float64 a)
124{ 125{
125 return (a >> 52) & 0x7FF; 126 return (a >> 52) & 0x7FF;
126} 127}
127 128
128inline int16 extractFloat32Exp(float32 a) 129int16 extractFloat32Exp(float32 a)
129{ 130{
130 return (a >> 23) & 0xFF; 131 return (a >> 23) & 0xFF;
131} 132}
132 133
133inline flag extractFloat32Sign(float32 a) 134flag extractFloat32Sign(float32 a)
134{ 135{
135 return a >> 31; 136 return a >> 31;
136} 137}
137 138
138inline bits32 extractFloat32Frac(float32 a) 139bits32 extractFloat32Frac(float32 a)
139{ 140{
140 return a & 0x007FFFFF; 141 return a & 0x007FFFFF;
141} 142}
142 143
143inline float64 packFloat64(flag zSign, int16 zExp, bits64 zSig) 144float64 packFloat64(flag zSign, int16 zExp, bits64 zSig)
144{ 145{
145 return (((bits64) zSign) << 63) + (((bits64) zExp) << 52) + zSig; 146 return (((bits64) zSign) << 63) + (((bits64) zExp) << 52) + zSig;
146} 147}
147 148
148inline void shift64RightJamming(bits64 a, int16 count, bits64 * zPtr) 149void shift64RightJamming(bits64 a, int16 count, bits64 * zPtr)
149{ 150{
150 bits64 z; 151 bits64 z;
151 152
@@ -338,12 +339,12 @@ static float64 addFloat64Sigs(float64 a, float64 b, flag zSign)
338 339
339} 340}
340 341
341inline float32 packFloat32(flag zSign, int16 zExp, bits32 zSig) 342float32 packFloat32(flag zSign, int16 zExp, bits32 zSig)
342{ 343{
343 return (((bits32) zSign) << 31) + (((bits32) zExp) << 23) + zSig; 344 return (((bits32) zSign) << 31) + (((bits32) zExp) << 23) + zSig;
344} 345}
345 346
346inline void shift32RightJamming(bits32 a, int16 count, bits32 * zPtr) 347void shift32RightJamming(bits32 a, int16 count, bits32 * zPtr)
347{ 348{
348 bits32 z; 349 bits32 z;
349 if (count == 0) { 350 if (count == 0) {
@@ -634,7 +635,7 @@ normalizeFloat64Subnormal(bits64 aSig, int16 * zExpPtr, bits64 * zSigPtr)
634 *zExpPtr = 1 - shiftCount; 635 *zExpPtr = 1 - shiftCount;
635} 636}
636 637
637inline void add128(bits64 a0, bits64 a1, bits64 b0, bits64 b1, bits64 * z0Ptr, 638void add128(bits64 a0, bits64 a1, bits64 b0, bits64 b1, bits64 * z0Ptr,
638 bits64 * z1Ptr) 639 bits64 * z1Ptr)
639{ 640{
640 bits64 z1; 641 bits64 z1;
@@ -644,7 +645,7 @@ inline void add128(bits64 a0, bits64 a1, bits64 b0, bits64 b1, bits64 * z0Ptr,
644 *z0Ptr = a0 + b0 + (z1 < a1); 645 *z0Ptr = a0 + b0 + (z1 < a1);
645} 646}
646 647
647inline void 648void
648sub128(bits64 a0, bits64 a1, bits64 b0, bits64 b1, bits64 * z0Ptr, 649sub128(bits64 a0, bits64 a1, bits64 b0, bits64 b1, bits64 * z0Ptr,
649 bits64 * z1Ptr) 650 bits64 * z1Ptr)
650{ 651{
@@ -656,11 +657,14 @@ static bits64 estimateDiv128To64(bits64 a0, bits64 a1, bits64 b)
656{ 657{
657 bits64 b0, b1; 658 bits64 b0, b1;
658 bits64 rem0, rem1, term0, term1; 659 bits64 rem0, rem1, term0, term1;
659 bits64 z; 660 bits64 z, tmp;
660 if (b <= a0) 661 if (b <= a0)
661 return LIT64(0xFFFFFFFFFFFFFFFF); 662 return LIT64(0xFFFFFFFFFFFFFFFF);
662 b0 = b >> 32; 663 b0 = b >> 32;
663 z = (b0 << 32 <= a0) ? LIT64(0xFFFFFFFF00000000) : (a0 / b0) << 32; 664 tmp = a0;
665 do_div(tmp, b0);
666
667 z = (b0 << 32 <= a0) ? LIT64(0xFFFFFFFF00000000) : tmp << 32;
664 mul64To128(b, z, &term0, &term1); 668 mul64To128(b, z, &term0, &term1);
665 sub128(a0, a1, term0, term1, &rem0, &rem1); 669 sub128(a0, a1, term0, term1, &rem0, &rem1);
666 while (((sbits64) rem0) < 0) { 670 while (((sbits64) rem0) < 0) {
@@ -669,11 +673,13 @@ static bits64 estimateDiv128To64(bits64 a0, bits64 a1, bits64 b)
669 add128(rem0, rem1, b0, b1, &rem0, &rem1); 673 add128(rem0, rem1, b0, b1, &rem0, &rem1);
670 } 674 }
671 rem0 = (rem0 << 32) | (rem1 >> 32); 675 rem0 = (rem0 << 32) | (rem1 >> 32);
672 z |= (b0 << 32 <= rem0) ? 0xFFFFFFFF : rem0 / b0; 676 tmp = rem0;
677 do_div(tmp, b0);
678 z |= (b0 << 32 <= rem0) ? 0xFFFFFFFF : tmp;
673 return z; 679 return z;
674} 680}
675 681
676inline void mul64To128(bits64 a, bits64 b, bits64 * z0Ptr, bits64 * z1Ptr) 682void mul64To128(bits64 a, bits64 b, bits64 * z0Ptr, bits64 * z1Ptr)
677{ 683{
678 bits32 aHigh, aLow, bHigh, bLow; 684 bits32 aHigh, aLow, bHigh, bLow;
679 bits64 z0, zMiddleA, zMiddleB, z1; 685 bits64 z0, zMiddleA, zMiddleB, z1;
@@ -769,7 +775,8 @@ float32 float32_div(float32 a, float32 b)
769{ 775{
770 flag aSign, bSign, zSign; 776 flag aSign, bSign, zSign;
771 int16 aExp, bExp, zExp; 777 int16 aExp, bExp, zExp;
772 bits32 aSig, bSig, zSig; 778 bits32 aSig, bSig;
779 uint64_t zSig;
773 780
774 aSig = extractFloat32Frac(a); 781 aSig = extractFloat32Frac(a);
775 aExp = extractFloat32Exp(a); 782 aExp = extractFloat32Exp(a);
@@ -804,11 +811,13 @@ float32 float32_div(float32 a, float32 b)
804 aSig >>= 1; 811 aSig >>= 1;
805 ++zExp; 812 ++zExp;
806 } 813 }
807 zSig = (((bits64) aSig) << 32) / bSig; 814 zSig = (((bits64) aSig) << 32);
815 do_div(zSig, bSig);
816
808 if ((zSig & 0x3F) == 0) { 817 if ((zSig & 0x3F) == 0) {
809 zSig |= (((bits64) bSig) * zSig != ((bits64) aSig) << 32); 818 zSig |= (((bits64) bSig) * zSig != ((bits64) aSig) << 32);
810 } 819 }
811 return roundAndPackFloat32(zSign, zExp, zSig); 820 return roundAndPackFloat32(zSign, zExp, (bits32)zSig);
812 821
813} 822}
814 823
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7722.c b/arch/sh/kernel/cpu/sh4a/clock-sh7722.c
index db913855c2fd..0e174af21874 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7722.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7722.c
@@ -229,7 +229,7 @@ struct frqcr_context sh7722_get_clk_context(const char *name)
229} 229}
230 230
231/** 231/**
232 * sh7722_find_divisors - find divisor for setting rate 232 * sh7722_find_div_index - find divisor for setting rate
233 * 233 *
234 * All sh7722 clocks use the same set of multipliers/divisors. This function 234 * All sh7722 clocks use the same set of multipliers/divisors. This function
235 * chooses correct divisor to set the rate of clock with parent clock that 235 * chooses correct divisor to set the rate of clock with parent clock that
@@ -238,7 +238,7 @@ struct frqcr_context sh7722_get_clk_context(const char *name)
238 * @parent_rate: rate of parent clock 238 * @parent_rate: rate of parent clock
239 * @rate: requested rate to be set 239 * @rate: requested rate to be set
240 */ 240 */
241static int sh7722_find_divisors(unsigned long parent_rate, unsigned rate) 241static int sh7722_find_div_index(unsigned long parent_rate, unsigned rate)
242{ 242{
243 unsigned div2 = parent_rate * 2 / rate; 243 unsigned div2 = parent_rate * 2 / rate;
244 int index; 244 int index;
@@ -247,12 +247,12 @@ static int sh7722_find_divisors(unsigned long parent_rate, unsigned rate)
247 return -EINVAL; 247 return -EINVAL;
248 248
249 for (index = 1; index < ARRAY_SIZE(divisors2); index++) { 249 for (index = 1; index < ARRAY_SIZE(divisors2); index++) {
250 if (div2 > divisors2[index] && div2 <= divisors2[index]) 250 if (div2 > divisors2[index - 1] && div2 <= divisors2[index])
251 break; 251 break;
252 } 252 }
253 if (index >= ARRAY_SIZE(divisors2)) 253 if (index >= ARRAY_SIZE(divisors2))
254 index = ARRAY_SIZE(divisors2) - 1; 254 index = ARRAY_SIZE(divisors2) - 1;
255 return divisors2[index]; 255 return index;
256} 256}
257 257
258static void sh7722_frqcr_recalc(struct clk *clk) 258static void sh7722_frqcr_recalc(struct clk *clk)
@@ -279,12 +279,12 @@ static int sh7722_frqcr_set_rate(struct clk *clk, unsigned long rate,
279 return -EINVAL; 279 return -EINVAL;
280 280
281 /* look for multiplier/divisor pair */ 281 /* look for multiplier/divisor pair */
282 div = sh7722_find_divisors(parent_rate, rate); 282 div = sh7722_find_div_index(parent_rate, rate);
283 if (div<0) 283 if (div<0)
284 return div; 284 return div;
285 285
286 /* calculate new value of clock rate */ 286 /* calculate new value of clock rate */
287 clk->rate = parent_rate * 2 / div; 287 clk->rate = parent_rate * 2 / divisors2[div];
288 frqcr = ctrl_inl(FRQCR); 288 frqcr = ctrl_inl(FRQCR);
289 289
290 /* FIXME: adjust as algo_id specifies */ 290 /* FIXME: adjust as algo_id specifies */
@@ -353,7 +353,7 @@ static int sh7722_frqcr_set_rate(struct clk *clk, unsigned long rate,
353 int part_div; 353 int part_div;
354 354
355 if (likely(!err)) { 355 if (likely(!err)) {
356 part_div = sh7722_find_divisors(parent_rate, 356 part_div = sh7722_find_div_index(parent_rate,
357 rate); 357 rate);
358 if (part_div > 0) { 358 if (part_div > 0) {
359 part_ctx = sh7722_get_clk_context( 359 part_ctx = sh7722_get_clk_context(
@@ -394,12 +394,12 @@ static long sh7722_frqcr_round_rate(struct clk *clk, unsigned long rate)
394 int div; 394 int div;
395 395
396 /* look for multiplier/divisor pair */ 396 /* look for multiplier/divisor pair */
397 div = sh7722_find_divisors(parent_rate, rate); 397 div = sh7722_find_div_index(parent_rate, rate);
398 if (div < 0) 398 if (div < 0)
399 return clk->rate; 399 return clk->rate;
400 400
401 /* calculate new value of clock rate */ 401 /* calculate new value of clock rate */
402 return parent_rate * 2 / div; 402 return parent_rate * 2 / divisors2[div];
403} 403}
404 404
405static struct clk_ops sh7722_frqcr_clk_ops = { 405static struct clk_ops sh7722_frqcr_clk_ops = {
@@ -421,7 +421,7 @@ static int sh7722_siu_set_rate(struct clk *clk, unsigned long rate, int algo_id)
421 int div; 421 int div;
422 422
423 r = ctrl_inl(clk->arch_flags); 423 r = ctrl_inl(clk->arch_flags);
424 div = sh7722_find_divisors(clk->parent->rate, rate); 424 div = sh7722_find_div_index(clk->parent->rate, rate);
425 if (div < 0) 425 if (div < 0)
426 return div; 426 return div;
427 r = (r & ~0xF) | div; 427 r = (r & ~0xF) | div;
@@ -516,16 +516,19 @@ static struct clk_ops sh7722_video_clk_ops = {
516static struct clk sh7722_umem_clock = { 516static struct clk sh7722_umem_clock = {
517 .name = "umem_clk", 517 .name = "umem_clk",
518 .ops = &sh7722_frqcr_clk_ops, 518 .ops = &sh7722_frqcr_clk_ops,
519 .flags = CLK_RATE_PROPAGATES,
519}; 520};
520 521
521static struct clk sh7722_sh_clock = { 522static struct clk sh7722_sh_clock = {
522 .name = "sh_clk", 523 .name = "sh_clk",
523 .ops = &sh7722_frqcr_clk_ops, 524 .ops = &sh7722_frqcr_clk_ops,
525 .flags = CLK_RATE_PROPAGATES,
524}; 526};
525 527
526static struct clk sh7722_peripheral_clock = { 528static struct clk sh7722_peripheral_clock = {
527 .name = "peripheral_clk", 529 .name = "peripheral_clk",
528 .ops = &sh7722_frqcr_clk_ops, 530 .ops = &sh7722_frqcr_clk_ops,
531 .flags = CLK_RATE_PROPAGATES,
529}; 532};
530 533
531static struct clk sh7722_sdram_clock = { 534static struct clk sh7722_sdram_clock = {
@@ -533,6 +536,11 @@ static struct clk sh7722_sdram_clock = {
533 .ops = &sh7722_frqcr_clk_ops, 536 .ops = &sh7722_frqcr_clk_ops,
534}; 537};
535 538
539static struct clk sh7722_r_clock = {
540 .name = "r_clk",
541 .rate = 32768,
542 .flags = CLK_RATE_PROPAGATES,
543};
536 544
537#ifndef CONFIG_CPU_SUBTYPE_SH7343 545#ifndef CONFIG_CPU_SUBTYPE_SH7343
538 546
@@ -567,12 +575,30 @@ static struct clk sh7722_video_clock = {
567 .ops = &sh7722_video_clk_ops, 575 .ops = &sh7722_video_clk_ops,
568}; 576};
569 577
570static int sh7722_mstpcr_start_stop(struct clk *clk, unsigned long reg, 578#define MSTPCR_ARCH_FLAGS(reg, bit) (((reg) << 8) | (bit))
571 int enable) 579#define MSTPCR_ARCH_FLAGS_REG(value) ((value) >> 8)
580#define MSTPCR_ARCH_FLAGS_BIT(value) ((value) & 0xff)
581
582static int sh7722_mstpcr_start_stop(struct clk *clk, int enable)
572{ 583{
573 unsigned long bit = clk->arch_flags; 584 unsigned long bit = MSTPCR_ARCH_FLAGS_BIT(clk->arch_flags);
585 unsigned long reg;
574 unsigned long r; 586 unsigned long r;
575 587
588 switch(MSTPCR_ARCH_FLAGS_REG(clk->arch_flags)) {
589 case 0:
590 reg = MSTPCR0;
591 break;
592 case 1:
593 reg = MSTPCR1;
594 break;
595 case 2:
596 reg = MSTPCR2;
597 break;
598 default:
599 return -EINVAL;
600 }
601
576 r = ctrl_inl(reg); 602 r = ctrl_inl(reg);
577 603
578 if (enable) 604 if (enable)
@@ -584,96 +610,175 @@ static int sh7722_mstpcr_start_stop(struct clk *clk, unsigned long reg,
584 return 0; 610 return 0;
585} 611}
586 612
587static void sh7722_mstpcr0_enable(struct clk *clk) 613static void sh7722_mstpcr_enable(struct clk *clk)
588{
589 sh7722_mstpcr_start_stop(clk, MSTPCR0, 1);
590}
591
592static void sh7722_mstpcr0_disable(struct clk *clk)
593{
594 sh7722_mstpcr_start_stop(clk, MSTPCR0, 0);
595}
596
597static void sh7722_mstpcr1_enable(struct clk *clk)
598{
599 sh7722_mstpcr_start_stop(clk, MSTPCR1, 1);
600}
601
602static void sh7722_mstpcr1_disable(struct clk *clk)
603{ 614{
604 sh7722_mstpcr_start_stop(clk, MSTPCR1, 0); 615 sh7722_mstpcr_start_stop(clk, 1);
605} 616}
606 617
607static void sh7722_mstpcr2_enable(struct clk *clk) 618static void sh7722_mstpcr_disable(struct clk *clk)
608{ 619{
609 sh7722_mstpcr_start_stop(clk, MSTPCR2, 1); 620 sh7722_mstpcr_start_stop(clk, 0);
610} 621}
611 622
612static void sh7722_mstpcr2_disable(struct clk *clk) 623static void sh7722_mstpcr_recalc(struct clk *clk)
613{ 624{
614 sh7722_mstpcr_start_stop(clk, MSTPCR2, 0); 625 if (clk->parent)
626 clk->rate = clk->parent->rate;
615} 627}
616 628
617static struct clk_ops sh7722_mstpcr0_clk_ops = { 629static struct clk_ops sh7722_mstpcr_clk_ops = {
618 .enable = sh7722_mstpcr0_enable, 630 .enable = sh7722_mstpcr_enable,
619 .disable = sh7722_mstpcr0_disable, 631 .disable = sh7722_mstpcr_disable,
620}; 632 .recalc = sh7722_mstpcr_recalc,
621
622static struct clk_ops sh7722_mstpcr1_clk_ops = {
623 .enable = sh7722_mstpcr1_enable,
624 .disable = sh7722_mstpcr1_disable,
625}; 633};
626 634
627static struct clk_ops sh7722_mstpcr2_clk_ops = { 635#define MSTPCR(_name, _parent, regnr, bitnr) \
628 .enable = sh7722_mstpcr2_enable, 636{ \
629 .disable = sh7722_mstpcr2_disable, 637 .name = _name, \
630}; 638 .arch_flags = MSTPCR_ARCH_FLAGS(regnr, bitnr), \
631 639 .ops = (void *)_parent, \
632#define DECLARE_MSTPCRN(regnr, bitnr, bitstr) \
633{ \
634 .name = "mstp" __stringify(regnr) bitstr, \
635 .arch_flags = bitnr, \
636 .ops = &sh7722_mstpcr ## regnr ## _clk_ops, \
637} 640}
638 641
639#define DECLARE_MSTPCR(regnr) \ 642static struct clk sh7722_mstpcr_clocks[] = {
640 DECLARE_MSTPCRN(regnr, 31, "31"), \ 643#if defined(CONFIG_CPU_SUBTYPE_SH7722)
641 DECLARE_MSTPCRN(regnr, 30, "30"), \ 644 MSTPCR("uram0", "umem_clk", 0, 28),
642 DECLARE_MSTPCRN(regnr, 29, "29"), \ 645 MSTPCR("xymem0", "bus_clk", 0, 26),
643 DECLARE_MSTPCRN(regnr, 28, "28"), \ 646 MSTPCR("tmu0", "peripheral_clk", 0, 15),
644 DECLARE_MSTPCRN(regnr, 27, "27"), \ 647 MSTPCR("cmt0", "r_clk", 0, 14),
645 DECLARE_MSTPCRN(regnr, 26, "26"), \ 648 MSTPCR("rwdt0", "r_clk", 0, 13),
646 DECLARE_MSTPCRN(regnr, 25, "25"), \ 649 MSTPCR("flctl0", "peripheral_clk", 0, 10),
647 DECLARE_MSTPCRN(regnr, 24, "24"), \ 650 MSTPCR("scif0", "peripheral_clk", 0, 7),
648 DECLARE_MSTPCRN(regnr, 23, "23"), \ 651 MSTPCR("scif1", "peripheral_clk", 0, 6),
649 DECLARE_MSTPCRN(regnr, 22, "22"), \ 652 MSTPCR("scif2", "peripheral_clk", 0, 5),
650 DECLARE_MSTPCRN(regnr, 21, "21"), \ 653 MSTPCR("i2c0", "peripheral_clk", 1, 9),
651 DECLARE_MSTPCRN(regnr, 20, "20"), \ 654 MSTPCR("rtc0", "r_clk", 1, 8),
652 DECLARE_MSTPCRN(regnr, 19, "19"), \ 655 MSTPCR("sdhi0", "peripheral_clk", 2, 18),
653 DECLARE_MSTPCRN(regnr, 18, "18"), \ 656 MSTPCR("keysc0", "r_clk", 2, 14),
654 DECLARE_MSTPCRN(regnr, 17, "17"), \ 657 MSTPCR("usbf0", "peripheral_clk", 2, 11),
655 DECLARE_MSTPCRN(regnr, 16, "16"), \ 658 MSTPCR("2dg0", "bus_clk", 2, 9),
656 DECLARE_MSTPCRN(regnr, 15, "15"), \ 659 MSTPCR("siu0", "bus_clk", 2, 8),
657 DECLARE_MSTPCRN(regnr, 14, "14"), \ 660 MSTPCR("vou0", "bus_clk", 2, 5),
658 DECLARE_MSTPCRN(regnr, 13, "13"), \ 661 MSTPCR("jpu0", "bus_clk", 2, 6),
659 DECLARE_MSTPCRN(regnr, 12, "12"), \ 662 MSTPCR("beu0", "bus_clk", 2, 4),
660 DECLARE_MSTPCRN(regnr, 11, "11"), \ 663 MSTPCR("ceu0", "bus_clk", 2, 3),
661 DECLARE_MSTPCRN(regnr, 10, "10"), \ 664 MSTPCR("veu0", "bus_clk", 2, 2),
662 DECLARE_MSTPCRN(regnr, 9, "09"), \ 665 MSTPCR("vpu0", "bus_clk", 2, 1),
663 DECLARE_MSTPCRN(regnr, 8, "08"), \ 666 MSTPCR("lcdc0", "bus_clk", 2, 0),
664 DECLARE_MSTPCRN(regnr, 7, "07"), \ 667#endif
665 DECLARE_MSTPCRN(regnr, 6, "06"), \ 668#if defined(CONFIG_CPU_SUBTYPE_SH7723)
666 DECLARE_MSTPCRN(regnr, 5, "05"), \ 669 /* See page 60 of Datasheet V1.0: Overview -> Block Diagram */
667 DECLARE_MSTPCRN(regnr, 4, "04"), \ 670 MSTPCR("tlb0", "cpu_clk", 0, 31),
668 DECLARE_MSTPCRN(regnr, 3, "03"), \ 671 MSTPCR("ic0", "cpu_clk", 0, 30),
669 DECLARE_MSTPCRN(regnr, 2, "02"), \ 672 MSTPCR("oc0", "cpu_clk", 0, 29),
670 DECLARE_MSTPCRN(regnr, 1, "01"), \ 673 MSTPCR("l2c0", "sh_clk", 0, 28),
671 DECLARE_MSTPCRN(regnr, 0, "00") 674 MSTPCR("ilmem0", "cpu_clk", 0, 27),
672 675 MSTPCR("fpu0", "cpu_clk", 0, 24),
673static struct clk sh7722_mstpcr[] = { 676 MSTPCR("intc0", "cpu_clk", 0, 22),
674 DECLARE_MSTPCR(0), 677 MSTPCR("dmac0", "bus_clk", 0, 21),
675 DECLARE_MSTPCR(1), 678 MSTPCR("sh0", "sh_clk", 0, 20),
676 DECLARE_MSTPCR(2), 679 MSTPCR("hudi0", "peripheral_clk", 0, 19),
680 MSTPCR("ubc0", "cpu_clk", 0, 17),
681 MSTPCR("tmu0", "peripheral_clk", 0, 15),
682 MSTPCR("cmt0", "r_clk", 0, 14),
683 MSTPCR("rwdt0", "r_clk", 0, 13),
684 MSTPCR("dmac1", "bus_clk", 0, 12),
685 MSTPCR("tmu1", "peripheral_clk", 0, 11),
686 MSTPCR("flctl0", "peripheral_clk", 0, 10),
687 MSTPCR("scif0", "peripheral_clk", 0, 9),
688 MSTPCR("scif1", "peripheral_clk", 0, 8),
689 MSTPCR("scif2", "peripheral_clk", 0, 7),
690 MSTPCR("scif3", "bus_clk", 0, 6),
691 MSTPCR("scif4", "bus_clk", 0, 5),
692 MSTPCR("scif5", "bus_clk", 0, 4),
693 MSTPCR("msiof0", "bus_clk", 0, 2),
694 MSTPCR("msiof1", "bus_clk", 0, 1),
695 MSTPCR("meram0", "sh_clk", 0, 0),
696 MSTPCR("i2c0", "peripheral_clk", 1, 9),
697 MSTPCR("rtc0", "r_clk", 1, 8),
698 MSTPCR("atapi0", "sh_clk", 2, 28),
699 MSTPCR("adc0", "peripheral_clk", 2, 28),
700 MSTPCR("tpu0", "bus_clk", 2, 25),
701 MSTPCR("irda0", "peripheral_clk", 2, 24),
702 MSTPCR("tsif0", "bus_clk", 2, 22),
703 MSTPCR("icb0", "bus_clk", 2, 21),
704 MSTPCR("sdhi0", "bus_clk", 2, 18),
705 MSTPCR("sdhi1", "bus_clk", 2, 17),
706 MSTPCR("keysc0", "r_clk", 2, 14),
707 MSTPCR("usb0", "bus_clk", 2, 11),
708 MSTPCR("2dg0", "bus_clk", 2, 10),
709 MSTPCR("siu0", "bus_clk", 2, 8),
710 MSTPCR("veu1", "bus_clk", 2, 6),
711 MSTPCR("vou0", "bus_clk", 2, 5),
712 MSTPCR("beu0", "bus_clk", 2, 4),
713 MSTPCR("ceu0", "bus_clk", 2, 3),
714 MSTPCR("veu0", "bus_clk", 2, 2),
715 MSTPCR("vpu0", "bus_clk", 2, 1),
716 MSTPCR("lcdc0", "bus_clk", 2, 0),
717#endif
718#if defined(CONFIG_CPU_SUBTYPE_SH7343)
719 MSTPCR("uram0", "umem_clk", 0, 28),
720 MSTPCR("xymem0", "bus_clk", 0, 26),
721 MSTPCR("tmu0", "peripheral_clk", 0, 15),
722 MSTPCR("cmt0", "r_clk", 0, 14),
723 MSTPCR("rwdt0", "r_clk", 0, 13),
724 MSTPCR("scif0", "peripheral_clk", 0, 7),
725 MSTPCR("scif1", "peripheral_clk", 0, 6),
726 MSTPCR("scif2", "peripheral_clk", 0, 5),
727 MSTPCR("scif3", "peripheral_clk", 0, 4),
728 MSTPCR("i2c0", "peripheral_clk", 1, 9),
729 MSTPCR("i2c1", "peripheral_clk", 1, 8),
730 MSTPCR("sdhi0", "peripheral_clk", 2, 18),
731 MSTPCR("keysc0", "r_clk", 2, 14),
732 MSTPCR("usbf0", "peripheral_clk", 2, 11),
733 MSTPCR("siu0", "bus_clk", 2, 8),
734 MSTPCR("jpu0", "bus_clk", 2, 6),
735 MSTPCR("vou0", "bus_clk", 2, 5),
736 MSTPCR("beu0", "bus_clk", 2, 4),
737 MSTPCR("ceu0", "bus_clk", 2, 3),
738 MSTPCR("veu0", "bus_clk", 2, 2),
739 MSTPCR("vpu0", "bus_clk", 2, 1),
740 MSTPCR("lcdc0", "bus_clk", 2, 0),
741#endif
742#if defined(CONFIG_CPU_SUBTYPE_SH7366)
743 /* See page 52 of Datasheet V0.40: Overview -> Block Diagram */
744 MSTPCR("tlb0", "cpu_clk", 0, 31),
745 MSTPCR("ic0", "cpu_clk", 0, 30),
746 MSTPCR("oc0", "cpu_clk", 0, 29),
747 MSTPCR("rsmem0", "sh_clk", 0, 28),
748 MSTPCR("xymem0", "cpu_clk", 0, 26),
749 MSTPCR("intc30", "peripheral_clk", 0, 23),
750 MSTPCR("intc0", "peripheral_clk", 0, 22),
751 MSTPCR("dmac0", "bus_clk", 0, 21),
752 MSTPCR("sh0", "sh_clk", 0, 20),
753 MSTPCR("hudi0", "peripheral_clk", 0, 19),
754 MSTPCR("ubc0", "cpu_clk", 0, 17),
755 MSTPCR("tmu0", "peripheral_clk", 0, 15),
756 MSTPCR("cmt0", "r_clk", 0, 14),
757 MSTPCR("rwdt0", "r_clk", 0, 13),
758 MSTPCR("flctl0", "peripheral_clk", 0, 10),
759 MSTPCR("scif0", "peripheral_clk", 0, 7),
760 MSTPCR("scif1", "bus_clk", 0, 6),
761 MSTPCR("scif2", "bus_clk", 0, 5),
762 MSTPCR("msiof0", "peripheral_clk", 0, 2),
763 MSTPCR("sbr0", "peripheral_clk", 0, 1),
764 MSTPCR("i2c0", "peripheral_clk", 1, 9),
765 MSTPCR("icb0", "bus_clk", 2, 27),
766 MSTPCR("meram0", "sh_clk", 2, 26),
767 MSTPCR("dacc0", "peripheral_clk", 2, 24),
768 MSTPCR("dacy0", "peripheral_clk", 2, 23),
769 MSTPCR("tsif0", "bus_clk", 2, 22),
770 MSTPCR("sdhi0", "bus_clk", 2, 18),
771 MSTPCR("mmcif0", "bus_clk", 2, 17),
772 MSTPCR("usb0", "bus_clk", 2, 11),
773 MSTPCR("siu0", "bus_clk", 2, 8),
774 MSTPCR("veu1", "bus_clk", 2, 7),
775 MSTPCR("vou0", "bus_clk", 2, 5),
776 MSTPCR("beu0", "bus_clk", 2, 4),
777 MSTPCR("ceu0", "bus_clk", 2, 3),
778 MSTPCR("veu0", "bus_clk", 2, 2),
779 MSTPCR("vpu0", "bus_clk", 2, 1),
780 MSTPCR("lcdc0", "bus_clk", 2, 0),
781#endif
677}; 782};
678 783
679static struct clk *sh7722_clocks[] = { 784static struct clk *sh7722_clocks[] = {
@@ -710,21 +815,30 @@ arch_init_clk_ops(struct clk_ops **ops, int type)
710 815
711int __init arch_clk_init(void) 816int __init arch_clk_init(void)
712{ 817{
713 struct clk *master; 818 struct clk *clk;
714 int i; 819 int i;
715 820
716 master = clk_get(NULL, "master_clk"); 821 clk = clk_get(NULL, "master_clk");
717 for (i = 0; i < ARRAY_SIZE(sh7722_clocks); i++) { 822 for (i = 0; i < ARRAY_SIZE(sh7722_clocks); i++) {
718 pr_debug( "Registering clock '%s'\n", sh7722_clocks[i]->name); 823 pr_debug( "Registering clock '%s'\n", sh7722_clocks[i]->name);
719 sh7722_clocks[i]->parent = master; 824 sh7722_clocks[i]->parent = clk;
720 clk_register(sh7722_clocks[i]); 825 clk_register(sh7722_clocks[i]);
721 } 826 }
722 clk_put(master); 827 clk_put(clk);
723 828
724 for (i = 0; i < ARRAY_SIZE(sh7722_mstpcr); i++) { 829 clk_register(&sh7722_r_clock);
725 pr_debug( "Registering mstpcr '%s'\n", sh7722_mstpcr[i].name); 830
726 clk_register(&sh7722_mstpcr[i]); 831 for (i = 0; i < ARRAY_SIZE(sh7722_mstpcr_clocks); i++) {
832 pr_debug( "Registering mstpcr clock '%s'\n",
833 sh7722_mstpcr_clocks[i].name);
834 clk = clk_get(NULL, (void *) sh7722_mstpcr_clocks[i].ops);
835 sh7722_mstpcr_clocks[i].parent = clk;
836 sh7722_mstpcr_clocks[i].ops = &sh7722_mstpcr_clk_ops;
837 clk_register(&sh7722_mstpcr_clocks[i]);
838 clk_put(clk);
727 } 839 }
728 840
841 clk_recalc_rate(&sh7722_r_clock); /* make sure rate gets propagated */
842
729 return 0; 843 return 0;
730} 844}
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7343.c b/arch/sh/kernel/cpu/sh4a/setup-sh7343.c
index 78881b4214da..0623e377f488 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7343.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7343.c
@@ -30,6 +30,7 @@ static struct resource iic0_resources[] = {
30 30
31static struct platform_device iic0_device = { 31static struct platform_device iic0_device = {
32 .name = "i2c-sh_mobile", 32 .name = "i2c-sh_mobile",
33 .id = 0, /* "i2c0" clock */
33 .num_resources = ARRAY_SIZE(iic0_resources), 34 .num_resources = ARRAY_SIZE(iic0_resources),
34 .resource = iic0_resources, 35 .resource = iic0_resources,
35}; 36};
@@ -50,6 +51,7 @@ static struct resource iic1_resources[] = {
50 51
51static struct platform_device iic1_device = { 52static struct platform_device iic1_device = {
52 .name = "i2c-sh_mobile", 53 .name = "i2c-sh_mobile",
54 .id = 1, /* "i2c1" clock */
53 .num_resources = ARRAY_SIZE(iic1_resources), 55 .num_resources = ARRAY_SIZE(iic1_resources),
54 .resource = iic1_resources, 56 .resource = iic1_resources,
55}; 57};
@@ -115,7 +117,22 @@ static struct plat_sci_port sci_platform_data[] = {
115 .mapbase = 0xffe00000, 117 .mapbase = 0xffe00000,
116 .flags = UPF_BOOT_AUTOCONF, 118 .flags = UPF_BOOT_AUTOCONF,
117 .type = PORT_SCIF, 119 .type = PORT_SCIF,
118 .irqs = { 80, 81, 83, 82 }, 120 .irqs = { 80, 80, 80, 80 },
121 }, {
122 .mapbase = 0xffe10000,
123 .flags = UPF_BOOT_AUTOCONF,
124 .type = PORT_SCIF,
125 .irqs = { 81, 81, 81, 81 },
126 }, {
127 .mapbase = 0xffe20000,
128 .flags = UPF_BOOT_AUTOCONF,
129 .type = PORT_SCIF,
130 .irqs = { 82, 82, 82, 82 },
131 }, {
132 .mapbase = 0xffe30000,
133 .flags = UPF_BOOT_AUTOCONF,
134 .type = PORT_SCIF,
135 .irqs = { 83, 83, 83, 83 },
119 }, { 136 }, {
120 .flags = 0, 137 .flags = 0,
121 } 138 }
@@ -139,18 +156,10 @@ static struct platform_device *sh7343_devices[] __initdata = {
139 156
140static int __init sh7343_devices_setup(void) 157static int __init sh7343_devices_setup(void)
141{ 158{
142 clk_always_enable("mstp031"); /* TLB */ 159 clk_always_enable("uram0"); /* URAM */
143 clk_always_enable("mstp030"); /* IC */ 160 clk_always_enable("xymem0"); /* XYMEM */
144 clk_always_enable("mstp029"); /* OC */ 161 clk_always_enable("veu0"); /* VEU */
145 clk_always_enable("mstp028"); /* URAM */ 162 clk_always_enable("vpu0"); /* VPU */
146 clk_always_enable("mstp026"); /* XYMEM */
147 clk_always_enable("mstp023"); /* INTC3 */
148 clk_always_enable("mstp022"); /* INTC */
149 clk_always_enable("mstp020"); /* SuperHyway */
150 clk_always_enable("mstp109"); /* I2C0 */
151 clk_always_enable("mstp108"); /* I2C1 */
152 clk_always_enable("mstp202"); /* VEU */
153 clk_always_enable("mstp201"); /* VPU */
154 163
155 platform_resource_setup_memory(&vpu_device, "vpu", 1 << 20); 164 platform_resource_setup_memory(&vpu_device, "vpu", 1 << 20);
156 platform_resource_setup_memory(&veu_device, "veu", 2 << 20); 165 platform_resource_setup_memory(&veu_device, "veu", 2 << 20);
@@ -171,7 +180,7 @@ enum {
171 MMC_ERR, MMC_TRAN, MMC_FSTAT, MMC_FRDY, 180 MMC_ERR, MMC_TRAN, MMC_FSTAT, MMC_FRDY,
172 DMAC4, DMAC5, DMAC_DADERR, 181 DMAC4, DMAC5, DMAC_DADERR,
173 KEYSC, 182 KEYSC,
174 SCIF, SCIF1, SCIF2, SCIF3, SCIF4, 183 SCIF, SCIF1, SCIF2, SCIF3,
175 SIOF0, SIOF1, SIO, 184 SIOF0, SIOF1, SIO,
176 FLCTL_FLSTEI, FLCTL_FLENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I, 185 FLCTL_FLSTEI, FLCTL_FLENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,
177 I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI, 186 I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI,
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7366.c b/arch/sh/kernel/cpu/sh4a/setup-sh7366.c
index e17db39b97aa..839ae97a7fd2 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7366.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7366.c
@@ -32,6 +32,7 @@ static struct resource iic_resources[] = {
32 32
33static struct platform_device iic_device = { 33static struct platform_device iic_device = {
34 .name = "i2c-sh_mobile", 34 .name = "i2c-sh_mobile",
35 .id = 0, /* "i2c0" clock */
35 .num_resources = ARRAY_SIZE(iic_resources), 36 .num_resources = ARRAY_SIZE(iic_resources),
36 .resource = iic_resources, 37 .resource = iic_resources,
37}; 38};
@@ -176,19 +177,11 @@ static struct platform_device *sh7366_devices[] __initdata = {
176 177
177static int __init sh7366_devices_setup(void) 178static int __init sh7366_devices_setup(void)
178{ 179{
179 clk_always_enable("mstp031"); /* TLB */ 180 clk_always_enable("rsmem0"); /* RSMEM */
180 clk_always_enable("mstp030"); /* IC */ 181 clk_always_enable("xymem0"); /* XYMEM */
181 clk_always_enable("mstp029"); /* OC */ 182 clk_always_enable("veu1"); /* VEU-2 */
182 clk_always_enable("mstp028"); /* RSMEM */ 183 clk_always_enable("veu0"); /* VEU-1 */
183 clk_always_enable("mstp026"); /* XYMEM */ 184 clk_always_enable("vpu0"); /* VPU */
184 clk_always_enable("mstp023"); /* INTC3 */
185 clk_always_enable("mstp022"); /* INTC */
186 clk_always_enable("mstp020"); /* SuperHyway */
187 clk_always_enable("mstp109"); /* I2C */
188 clk_always_enable("mstp211"); /* USB */
189 clk_always_enable("mstp207"); /* VEU-2 */
190 clk_always_enable("mstp202"); /* VEU-1 */
191 clk_always_enable("mstp201"); /* VPU */
192 185
193 platform_resource_setup_memory(&vpu_device, "vpu", 2 << 20); 186 platform_resource_setup_memory(&vpu_device, "vpu", 2 << 20);
194 platform_resource_setup_memory(&veu0_device, "veu0", 2 << 20); 187 platform_resource_setup_memory(&veu0_device, "veu0", 2 << 20);
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
index ef77ee1d9f53..50cf6838ec41 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
@@ -62,7 +62,7 @@ static struct resource usbf_resources[] = {
62 62
63static struct platform_device usbf_device = { 63static struct platform_device usbf_device = {
64 .name = "m66592_udc", 64 .name = "m66592_udc",
65 .id = -1, 65 .id = 0, /* "usbf0" clock */
66 .dev = { 66 .dev = {
67 .dma_mask = NULL, 67 .dma_mask = NULL,
68 .coherent_dma_mask = 0xffffffff, 68 .coherent_dma_mask = 0xffffffff,
@@ -87,6 +87,7 @@ static struct resource iic_resources[] = {
87 87
88static struct platform_device iic_device = { 88static struct platform_device iic_device = {
89 .name = "i2c-sh_mobile", 89 .name = "i2c-sh_mobile",
90 .id = 0, /* "i2c0" clock */
90 .num_resources = ARRAY_SIZE(iic_resources), 91 .num_resources = ARRAY_SIZE(iic_resources),
91 .resource = iic_resources, 92 .resource = iic_resources,
92}; 93};
@@ -147,6 +148,34 @@ static struct platform_device veu_device = {
147 .num_resources = ARRAY_SIZE(veu_resources), 148 .num_resources = ARRAY_SIZE(veu_resources),
148}; 149};
149 150
151static struct uio_info jpu_platform_data = {
152 .name = "JPU",
153 .version = "0",
154 .irq = 27,
155};
156
157static struct resource jpu_resources[] = {
158 [0] = {
159 .name = "JPU",
160 .start = 0xfea00000,
161 .end = 0xfea102d0,
162 .flags = IORESOURCE_MEM,
163 },
164 [1] = {
165 /* place holder for contiguous memory */
166 },
167};
168
169static struct platform_device jpu_device = {
170 .name = "uio_pdrv_genirq",
171 .id = 2,
172 .dev = {
173 .platform_data = &jpu_platform_data,
174 },
175 .resource = jpu_resources,
176 .num_resources = ARRAY_SIZE(jpu_resources),
177};
178
150static struct plat_sci_port sci_platform_data[] = { 179static struct plat_sci_port sci_platform_data[] = {
151 { 180 {
152 .mapbase = 0xffe00000, 181 .mapbase = 0xffe00000,
@@ -186,24 +215,21 @@ static struct platform_device *sh7722_devices[] __initdata = {
186 &sci_device, 215 &sci_device,
187 &vpu_device, 216 &vpu_device,
188 &veu_device, 217 &veu_device,
218 &jpu_device,
189}; 219};
190 220
191static int __init sh7722_devices_setup(void) 221static int __init sh7722_devices_setup(void)
192{ 222{
193 clk_always_enable("mstp031"); /* TLB */ 223 clk_always_enable("uram0"); /* URAM */
194 clk_always_enable("mstp030"); /* IC */ 224 clk_always_enable("xymem0"); /* XYMEM */
195 clk_always_enable("mstp029"); /* OC */ 225 clk_always_enable("rtc0"); /* RTC */
196 clk_always_enable("mstp028"); /* URAM */ 226 clk_always_enable("veu0"); /* VEU */
197 clk_always_enable("mstp026"); /* XYMEM */ 227 clk_always_enable("vpu0"); /* VPU */
198 clk_always_enable("mstp022"); /* INTC */ 228 clk_always_enable("jpu0"); /* JPU */
199 clk_always_enable("mstp020"); /* SuperHyway */
200 clk_always_enable("mstp109"); /* I2C */
201 clk_always_enable("mstp211"); /* USB */
202 clk_always_enable("mstp202"); /* VEU */
203 clk_always_enable("mstp201"); /* VPU */
204 229
205 platform_resource_setup_memory(&vpu_device, "vpu", 1 << 20); 230 platform_resource_setup_memory(&vpu_device, "vpu", 1 << 20);
206 platform_resource_setup_memory(&veu_device, "veu", 2 << 20); 231 platform_resource_setup_memory(&veu_device, "veu", 2 << 20);
232 platform_resource_setup_memory(&jpu_device, "jpu", 2 << 20);
207 233
208 return platform_add_devices(sh7722_devices, 234 return platform_add_devices(sh7722_devices,
209 ARRAY_SIZE(sh7722_devices)); 235 ARRAY_SIZE(sh7722_devices));
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7723.c b/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
index 6d9e6972cfc9..849770d780ae 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
@@ -215,6 +215,7 @@ static struct resource iic_resources[] = {
215 215
216static struct platform_device iic_device = { 216static struct platform_device iic_device = {
217 .name = "i2c-sh_mobile", 217 .name = "i2c-sh_mobile",
218 .id = 0, /* "i2c0" clock */
218 .num_resources = ARRAY_SIZE(iic_resources), 219 .num_resources = ARRAY_SIZE(iic_resources),
219 .resource = iic_resources, 220 .resource = iic_resources,
220}; 221};
@@ -231,19 +232,11 @@ static struct platform_device *sh7723_devices[] __initdata = {
231 232
232static int __init sh7723_devices_setup(void) 233static int __init sh7723_devices_setup(void)
233{ 234{
234 clk_always_enable("mstp031"); /* TLB */ 235 clk_always_enable("meram0"); /* MERAM */
235 clk_always_enable("mstp030"); /* IC */ 236 clk_always_enable("rtc0"); /* RTC */
236 clk_always_enable("mstp029"); /* OC */ 237 clk_always_enable("veu1"); /* VEU2H1 */
237 clk_always_enable("mstp024"); /* FPU */ 238 clk_always_enable("veu0"); /* VEU2H0 */
238 clk_always_enable("mstp022"); /* INTC */ 239 clk_always_enable("vpu0"); /* VPU */
239 clk_always_enable("mstp020"); /* SuperHyway */
240 clk_always_enable("mstp000"); /* MERAM */
241 clk_always_enable("mstp109"); /* I2C */
242 clk_always_enable("mstp108"); /* RTC */
243 clk_always_enable("mstp211"); /* USB */
244 clk_always_enable("mstp206"); /* VEU2H1 */
245 clk_always_enable("mstp202"); /* VEU2H0 */
246 clk_always_enable("mstp201"); /* VPU */
247 240
248 platform_resource_setup_memory(&vpu_device, "vpu", 2 << 20); 241 platform_resource_setup_memory(&vpu_device, "vpu", 2 << 20);
249 platform_resource_setup_memory(&veu0_device, "veu0", 2 << 20); 242 platform_resource_setup_memory(&veu0_device, "veu0", 2 << 20);
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-27 01:12:17 -0500