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-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7723.c300
1 files changed, 300 insertions, 0 deletions
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7723.c b/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
new file mode 100644
index 000000000000..16925cf28db8
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
@@ -0,0 +1,300 @@
1/*
2 * SH7723 Setup
3 *
4 * Copyright (C) 2008 Paul Mundt
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#include <linux/platform_device.h>
11#include <linux/init.h>
12#include <linux/serial.h>
13#include <linux/mm.h>
14#include <linux/serial_sci.h>
15#include <asm/mmzone.h>
16
17static struct plat_sci_port sci_platform_data[] = {
18 {
19 .mapbase = 0xa4e30000,
20 .flags = UPF_BOOT_AUTOCONF,
21 .type = PORT_SCI,
22 .irqs = { 56, 56, 56, 56 },
23 },{
24 .mapbase = 0xa4e40000,
25 .flags = UPF_BOOT_AUTOCONF,
26 .type = PORT_SCI,
27 .irqs = { 88, 88, 88, 88 },
28 },{
29 .mapbase = 0xa4e50000,
30 .flags = UPF_BOOT_AUTOCONF,
31 .type = PORT_SCI,
32 .irqs = { 109, 109, 109, 109 },
33 }, {
34 .flags = 0,
35 }
36};
37
38static struct platform_device sci_device = {
39 .name = "sh-sci",
40 .id = -1,
41 .dev = {
42 .platform_data = sci_platform_data,
43 },
44};
45
46static struct resource rtc_resources[] = {
47 [0] = {
48 .start = 0xa465fec0,
49 .end = 0xa465fec0 + 0x58 - 1,
50 .flags = IORESOURCE_IO,
51 },
52 [1] = {
53 /* Period IRQ */
54 .start = 69,
55 .flags = IORESOURCE_IRQ,
56 },
57 [2] = {
58 /* Carry IRQ */
59 .start = 70,
60 .flags = IORESOURCE_IRQ,
61 },
62 [3] = {
63 /* Alarm IRQ */
64 .start = 68,
65 .flags = IORESOURCE_IRQ,
66 },
67};
68
69static struct platform_device rtc_device = {
70 .name = "sh-rtc",
71 .id = -1,
72 .num_resources = ARRAY_SIZE(rtc_resources),
73 .resource = rtc_resources,
74};
75
76static struct platform_device *sh7723_devices[] __initdata = {
77 &sci_device,
78 &rtc_device,
79};
80
81static int __init sh7723_devices_setup(void)
82{
83 return platform_add_devices(sh7723_devices,
84 ARRAY_SIZE(sh7723_devices));
85}
86__initcall(sh7723_devices_setup);
87
88enum {
89 UNUSED=0,
90
91 /* interrupt sources */
92 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
93 HUDI,
94 DMAC1A_DEI0,DMAC1A_DEI1,DMAC1A_DEI2,DMAC1A_DEI3,
95 _2DG_TRI,_2DG_INI,_2DG_CEI,
96 DMAC0A_DEI0,DMAC0A_DEI1,DMAC0A_DEI2,DMAC0A_DEI3,
97 VIO_CEUI,VIO_BEUI,VIO_VEU2HI,VIO_VOUI,
98 SCIFA_SCIFA0,
99 VPU_VPUI,
100 TPU_TPUI,
101 ADC_ADI,
102 USB_USI0,
103 RTC_ATI,RTC_PRI,RTC_CUI,
104 DMAC1B_DEI4,DMAC1B_DEI5,DMAC1B_DADERR,
105 DMAC0B_DEI4,DMAC0B_DEI5,DMAC0B_DADERR,
106 KEYSC_KEYI,
107 SCIF_SCIF0,SCIF_SCIF1,SCIF_SCIF2,
108 MSIOF_MSIOFI0,MSIOF_MSIOFI1,
109 SCIFA_SCIFA1,
110 FLCTL_FLSTEI,FLCTL_FLTENDI,FLCTL_FLTREQ0I,FLCTL_FLTREQ1I,
111 I2C_ALI,I2C_TACKI,I2C_WAITI,I2C_DTEI,
112 SDHI0_SDHII0,SDHI0_SDHII1,SDHI0_SDHII2,
113 CMT_CMTI,
114 TSIF_TSIFI,
115 SIU_SIUI,
116 SCIFA_SCIFA2,
117 TMU0_TUNI0, TMU0_TUNI1, TMU0_TUNI2,
118 IRDA_IRDAI,
119 ATAPI_ATAPII,
120 SDHI1_SDHII0,SDHI1_SDHII1,SDHI1_SDHII2,
121 VEU2H1_VEU2HI,
122 LCDC_LCDCI,
123 TMU1_TUNI0,TMU1_TUNI1,TMU1_TUNI2,
124
125 /* interrupt groups */
126 DMAC1A, DMAC0A, VIO, DMAC0B, FLCTL, I2C, _2DG,
127 SDHI1, RTC, DMAC1B, SDHI0,
128};
129
130static struct intc_vect vectors[] __initdata = {
131 INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
132 INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
133 INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
134 INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0),
135
136 INTC_VECT(DMAC1A_DEI0,0x700),
137 INTC_VECT(DMAC1A_DEI1,0x720),
138 INTC_VECT(DMAC1A_DEI2,0x740),
139 INTC_VECT(DMAC1A_DEI3,0x760),
140
141 INTC_VECT(_2DG_TRI, 0x780),
142 INTC_VECT(_2DG_INI, 0x7A0),
143 INTC_VECT(_2DG_CEI, 0x7C0),
144
145 INTC_VECT(DMAC0A_DEI0,0x800),
146 INTC_VECT(DMAC0A_DEI1,0x820),
147 INTC_VECT(DMAC0A_DEI2,0x840),
148 INTC_VECT(DMAC0A_DEI3,0x860),
149
150 INTC_VECT(VIO_CEUI,0x880),
151 INTC_VECT(VIO_BEUI,0x8A0),
152 INTC_VECT(VIO_VEU2HI,0x8C0),
153 INTC_VECT(VIO_VOUI,0x8E0),
154
155 INTC_VECT(SCIFA_SCIFA0,0x900),
156 INTC_VECT(VPU_VPUI,0x920),
157 INTC_VECT(TPU_TPUI,0x9A0),
158 INTC_VECT(ADC_ADI,0x9E0),
159 INTC_VECT(USB_USI0,0xA20),
160
161 INTC_VECT(RTC_ATI,0xA80),
162 INTC_VECT(RTC_PRI,0xAA0),
163 INTC_VECT(RTC_CUI,0xAC0),
164
165 INTC_VECT(DMAC1B_DEI4,0xB00),
166 INTC_VECT(DMAC1B_DEI5,0xB20),
167 INTC_VECT(DMAC1B_DADERR,0xB40),
168
169 INTC_VECT(DMAC0B_DEI4,0xB80),
170 INTC_VECT(DMAC0B_DEI5,0xBA0),
171 INTC_VECT(DMAC0B_DADERR,0xBC0),
172
173 INTC_VECT(KEYSC_KEYI,0xBE0),
174 INTC_VECT(SCIF_SCIF0,0xC00),
175 INTC_VECT(SCIF_SCIF1,0xC20),
176 INTC_VECT(SCIF_SCIF2,0xC40),
177 INTC_VECT(MSIOF_MSIOFI0,0xC80),
178 INTC_VECT(MSIOF_MSIOFI1,0xCA0),
179 INTC_VECT(SCIFA_SCIFA1,0xD00),
180
181 INTC_VECT(FLCTL_FLSTEI,0xD80),
182 INTC_VECT(FLCTL_FLTENDI,0xDA0),
183 INTC_VECT(FLCTL_FLTREQ0I,0xDC0),
184 INTC_VECT(FLCTL_FLTREQ1I,0xDE0),
185
186 INTC_VECT(I2C_ALI,0xE00),
187 INTC_VECT(I2C_TACKI,0xE20),
188 INTC_VECT(I2C_WAITI,0xE40),
189 INTC_VECT(I2C_DTEI,0xE60),
190
191 INTC_VECT(SDHI0_SDHII0,0xE80),
192 INTC_VECT(SDHI0_SDHII1,0xEA0),
193 INTC_VECT(SDHI0_SDHII2,0xEC0),
194
195 INTC_VECT(CMT_CMTI,0xF00),
196 INTC_VECT(TSIF_TSIFI,0xF20),
197 INTC_VECT(SIU_SIUI,0xF80),
198 INTC_VECT(SCIFA_SCIFA2,0xFA0),
199
200 INTC_VECT(TMU0_TUNI0,0x400),
201 INTC_VECT(TMU0_TUNI1,0x420),
202 INTC_VECT(TMU0_TUNI2,0x440),
203
204 INTC_VECT(IRDA_IRDAI,0x480),
205 INTC_VECT(ATAPI_ATAPII,0x4A0),
206
207 INTC_VECT(SDHI1_SDHII0,0x4E0),
208 INTC_VECT(SDHI1_SDHII1,0x500),
209 INTC_VECT(SDHI1_SDHII2,0x520),
210
211 INTC_VECT(VEU2H1_VEU2HI,0x560),
212 INTC_VECT(LCDC_LCDCI,0x580),
213
214 INTC_VECT(TMU1_TUNI0,0x920),
215 INTC_VECT(TMU1_TUNI1,0x940),
216 INTC_VECT(TMU1_TUNI2,0x960),
217
218};
219
220static struct intc_group groups[] __initdata = {
221 INTC_GROUP(DMAC1A,DMAC1A_DEI0,DMAC1A_DEI1,DMAC1A_DEI2,DMAC1A_DEI3),
222 INTC_GROUP(DMAC0A,DMAC0A_DEI0,DMAC0A_DEI1,DMAC0A_DEI2,DMAC0A_DEI3),
223 INTC_GROUP(VIO, VIO_CEUI,VIO_BEUI,VIO_VEU2HI,VIO_VOUI),
224 INTC_GROUP(DMAC0B, DMAC0B_DEI4,DMAC0B_DEI5,DMAC0B_DADERR),
225 INTC_GROUP(FLCTL,FLCTL_FLSTEI,FLCTL_FLTENDI,FLCTL_FLTREQ0I,FLCTL_FLTREQ1I),
226 INTC_GROUP(I2C,I2C_ALI,I2C_TACKI,I2C_WAITI,I2C_DTEI),
227 INTC_GROUP(_2DG, _2DG_TRI,_2DG_INI,_2DG_CEI),
228 INTC_GROUP(SDHI1, SDHI1_SDHII0,SDHI1_SDHII1,SDHI1_SDHII2),
229 INTC_GROUP(RTC, RTC_ATI,RTC_PRI,RTC_CUI),
230 INTC_GROUP(DMAC1B, DMAC1B_DEI4,DMAC1B_DEI5,DMAC1B_DADERR),
231 INTC_GROUP(SDHI0,SDHI0_SDHII0,SDHI0_SDHII1,SDHI0_SDHII2),
232};
233
234static struct intc_mask_reg mask_registers[] __initdata = {
235 { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */
236 { 0, TMU1_TUNI2,TMU1_TUNI1,TMU1_TUNI0,0,SDHI1_SDHII2,SDHI1_SDHII1,SDHI1_SDHII0} },
237 { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
238 { VIO_VOUI, VIO_VEU2HI,VIO_BEUI,VIO_CEUI,DMAC0A_DEI3,DMAC0A_DEI2,DMAC0A_DEI1,DMAC0A_DEI0 } },
239 { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */
240 { 0, 0, 0, VPU_VPUI,0,0,0,SCIFA_SCIFA0 } },
241 { 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */
242 { DMAC1A_DEI3,DMAC1A_DEI2,DMAC1A_DEI1,DMAC1A_DEI0,0,0,0,IRDA_IRDAI } },
243 { 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */
244 { 0,TMU0_TUNI2,TMU0_TUNI1,TMU0_TUNI0,VEU2H1_VEU2HI,0,0,LCDC_LCDCI } },
245 { 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */
246 { KEYSC_KEYI,DMAC0B_DADERR,DMAC0B_DEI5,DMAC0B_DEI4,0,SCIF_SCIF2,SCIF_SCIF1,SCIF_SCIF0 } },
247 { 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */
248 { 0,0,0,SCIFA_SCIFA1,ADC_ADI,0,MSIOF_MSIOFI1,MSIOF_MSIOFI0 } },
249 { 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */
250 { I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI,
251 FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } },
252 { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
253 { 0,SDHI0_SDHII2,SDHI0_SDHII1,SDHI0_SDHII0,0,0,SCIFA_SCIFA2,SIU_SIUI } },
254 { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
255 { 0, 0, 0, CMT_CMTI, 0, 0, USB_USI0,0 } },
256 { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
257 { 0, DMAC1B_DADERR,DMAC1B_DEI5,DMAC1B_DEI4,0,RTC_ATI,RTC_PRI,RTC_CUI } },
258 { 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */
259 { 0,_2DG_CEI,_2DG_INI,_2DG_TRI,0,TPU_TPUI,0,TSIF_TSIFI } },
260 { 0xa40800b0, 0xa40800f0, 8, /* IMR12 / IMCR12 */
261 { 0,0,0,0,0,0,0,ATAPI_ATAPII } },
262 { 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */
263 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
264};
265
266static struct intc_prio_reg prio_registers[] __initdata = {
267 { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0_TUNI0, TMU0_TUNI1, TMU0_TUNI2, IRDA_IRDAI } },
268 { 0xa4080004, 0, 16, 4, /* IPRB */ { VEU2H1_VEU2HI, LCDC_LCDCI, DMAC1A, 0} },
269 { 0xa4080008, 0, 16, 4, /* IPRC */ { TMU1_TUNI0, TMU1_TUNI1, TMU1_TUNI2, 0} },
270 { 0xa408000c, 0, 16, 4, /* IPRD */ { } },
271 { 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0A, VIO, SCIFA_SCIFA0, VPU_VPUI } },
272 { 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC_KEYI, DMAC0B, USB_USI0, CMT_CMTI } },
273 { 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF_SCIF0, SCIF_SCIF1, SCIF_SCIF2,0 } },
274 { 0xa408001c, 0, 16, 4, /* IPRH */ { MSIOF_MSIOFI0,MSIOF_MSIOFI1, FLCTL, I2C } },
275 { 0xa4080020, 0, 16, 4, /* IPRI */ { SCIFA_SCIFA1,0,TSIF_TSIFI,_2DG } },
276 { 0xa4080024, 0, 16, 4, /* IPRJ */ { ADC_ADI,0,SIU_SIUI,SDHI1 } },
277 { 0xa4080028, 0, 16, 4, /* IPRK */ { RTC,DMAC1B,0,SDHI0 } },
278 { 0xa408002c, 0, 16, 4, /* IPRL */ { SCIFA_SCIFA2,0,TPU_TPUI,ATAPI_ATAPII } },
279 { 0xa4140010, 0, 32, 4, /* INTPRI00 */
280 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
281};
282
283static struct intc_sense_reg sense_registers[] __initdata = {
284 { 0xa414001c, 16, 2, /* ICR1 */
285 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
286};
287
288static DECLARE_INTC_DESC(intc_desc, "sh7723", vectors, groups,
289 mask_registers, prio_registers, sense_registers);
290
291void __init plat_irq_setup(void)
292{
293 register_intc_controller(&intc_desc);
294}
295
296void __init plat_mem_setup(void)
297{
298 /* Register the URAM space as Node 1 */
299 setup_bootmem_node(1, 0x055f0000, 0x05610000);
300}
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