diff options
Diffstat (limited to 'arch/sh/kernel/cpu/sh4a/clock-sh7763.c')
-rw-r--r-- | arch/sh/kernel/cpu/sh4a/clock-sh7763.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7763.c b/arch/sh/kernel/cpu/sh4a/clock-sh7763.c index 370cd47642ef..9f401163e71e 100644 --- a/arch/sh/kernel/cpu/sh4a/clock-sh7763.c +++ b/arch/sh/kernel/cpu/sh4a/clock-sh7763.c | |||
@@ -22,7 +22,7 @@ static int cfc_divisors[] = { 1, 1, 4, 1, 1, 1, 1, 1 }; | |||
22 | 22 | ||
23 | static void master_clk_init(struct clk *clk) | 23 | static void master_clk_init(struct clk *clk) |
24 | { | 24 | { |
25 | clk->rate *= p0fc_divisors[(ctrl_inl(FRQCR) >> 4) & 0x07]; | 25 | clk->rate *= p0fc_divisors[(__raw_readl(FRQCR) >> 4) & 0x07]; |
26 | } | 26 | } |
27 | 27 | ||
28 | static struct clk_ops sh7763_master_clk_ops = { | 28 | static struct clk_ops sh7763_master_clk_ops = { |
@@ -31,7 +31,7 @@ static struct clk_ops sh7763_master_clk_ops = { | |||
31 | 31 | ||
32 | static unsigned long module_clk_recalc(struct clk *clk) | 32 | static unsigned long module_clk_recalc(struct clk *clk) |
33 | { | 33 | { |
34 | int idx = ((ctrl_inl(FRQCR) >> 4) & 0x07); | 34 | int idx = ((__raw_readl(FRQCR) >> 4) & 0x07); |
35 | return clk->parent->rate / p0fc_divisors[idx]; | 35 | return clk->parent->rate / p0fc_divisors[idx]; |
36 | } | 36 | } |
37 | 37 | ||
@@ -41,7 +41,7 @@ static struct clk_ops sh7763_module_clk_ops = { | |||
41 | 41 | ||
42 | static unsigned long bus_clk_recalc(struct clk *clk) | 42 | static unsigned long bus_clk_recalc(struct clk *clk) |
43 | { | 43 | { |
44 | int idx = ((ctrl_inl(FRQCR) >> 16) & 0x07); | 44 | int idx = ((__raw_readl(FRQCR) >> 16) & 0x07); |
45 | return clk->parent->rate / bfc_divisors[idx]; | 45 | return clk->parent->rate / bfc_divisors[idx]; |
46 | } | 46 | } |
47 | 47 | ||
@@ -68,7 +68,7 @@ void __init arch_init_clk_ops(struct clk_ops **ops, int idx) | |||
68 | 68 | ||
69 | static unsigned long shyway_clk_recalc(struct clk *clk) | 69 | static unsigned long shyway_clk_recalc(struct clk *clk) |
70 | { | 70 | { |
71 | int idx = ((ctrl_inl(FRQCR) >> 20) & 0x07); | 71 | int idx = ((__raw_readl(FRQCR) >> 20) & 0x07); |
72 | return clk->parent->rate / cfc_divisors[idx]; | 72 | return clk->parent->rate / cfc_divisors[idx]; |
73 | } | 73 | } |
74 | 74 | ||