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-rw-r--r--arch/sh/kernel/cpu/init.c10
1 files changed, 5 insertions, 5 deletions
diff --git a/arch/sh/kernel/cpu/init.c b/arch/sh/kernel/cpu/init.c
index 05a7d2a373b6..6311b0b1789d 100644
--- a/arch/sh/kernel/cpu/init.c
+++ b/arch/sh/kernel/cpu/init.c
@@ -61,10 +61,10 @@ onchip_setup(dsp);
61static void __init speculative_execution_init(void) 61static void __init speculative_execution_init(void)
62{ 62{
63 /* Clear RABD */ 63 /* Clear RABD */
64 ctrl_outl(ctrl_inl(CPUOPM) & ~CPUOPM_RABD, CPUOPM); 64 __raw_writel(__raw_readl(CPUOPM) & ~CPUOPM_RABD, CPUOPM);
65 65
66 /* Flush the update */ 66 /* Flush the update */
67 (void)ctrl_inl(CPUOPM); 67 (void)__raw_readl(CPUOPM);
68 ctrl_barrier(); 68 ctrl_barrier();
69} 69}
70#else 70#else
@@ -111,7 +111,7 @@ static void cache_init(void)
111 unsigned long ccr, flags; 111 unsigned long ccr, flags;
112 112
113 jump_to_uncached(); 113 jump_to_uncached();
114 ccr = ctrl_inl(CCR); 114 ccr = __raw_readl(CCR);
115 115
116 /* 116 /*
117 * At this point we don't know whether the cache is enabled or not - a 117 * At this point we don't know whether the cache is enabled or not - a
@@ -155,7 +155,7 @@ static void cache_init(void)
155 for (addr = addrstart; 155 for (addr = addrstart;
156 addr < addrstart + waysize; 156 addr < addrstart + waysize;
157 addr += current_cpu_data.dcache.linesz) 157 addr += current_cpu_data.dcache.linesz)
158 ctrl_outl(0, addr); 158 __raw_writel(0, addr);
159 159
160 addrstart += current_cpu_data.dcache.way_incr; 160 addrstart += current_cpu_data.dcache.way_incr;
161 } while (--ways); 161 } while (--ways);
@@ -188,7 +188,7 @@ static void cache_init(void)
188 188
189 l2_cache_init(); 189 l2_cache_init();
190 190
191 ctrl_outl(flags, CCR); 191 __raw_writel(flags, CCR);
192 back_to_cached(); 192 back_to_cached();
193} 193}
194#else 194#else