diff options
Diffstat (limited to 'arch/sh/include/asm')
-rw-r--r-- | arch/sh/include/asm/dma-sh.h | 12 | ||||
-rw-r--r-- | arch/sh/include/asm/mmu_context.h | 6 | ||||
-rw-r--r-- | arch/sh/include/asm/mmu_context_32.h | 4 | ||||
-rw-r--r-- | arch/sh/include/asm/watchdog.h | 18 |
4 files changed, 20 insertions, 20 deletions
diff --git a/arch/sh/include/asm/dma-sh.h b/arch/sh/include/asm/dma-sh.h index 78eed3e0bdf5..47de10976991 100644 --- a/arch/sh/include/asm/dma-sh.h +++ b/arch/sh/include/asm/dma-sh.h | |||
@@ -20,14 +20,14 @@ | |||
20 | defined(CONFIG_CPU_SUBTYPE_SH7780) || \ | 20 | defined(CONFIG_CPU_SUBTYPE_SH7780) || \ |
21 | defined(CONFIG_CPU_SUBTYPE_SH7785) | 21 | defined(CONFIG_CPU_SUBTYPE_SH7785) |
22 | #define dmaor_read_reg(n) \ | 22 | #define dmaor_read_reg(n) \ |
23 | (n ? ctrl_inw(SH_DMAC_BASE1 + DMAOR) \ | 23 | (n ? __raw_readw(SH_DMAC_BASE1 + DMAOR) \ |
24 | : ctrl_inw(SH_DMAC_BASE0 + DMAOR)) | 24 | : __raw_readw(SH_DMAC_BASE0 + DMAOR)) |
25 | #define dmaor_write_reg(n, data) \ | 25 | #define dmaor_write_reg(n, data) \ |
26 | (n ? ctrl_outw(data, SH_DMAC_BASE1 + DMAOR) \ | 26 | (n ? __raw_writew(data, SH_DMAC_BASE1 + DMAOR) \ |
27 | : ctrl_outw(data, SH_DMAC_BASE0 + DMAOR)) | 27 | : __raw_writew(data, SH_DMAC_BASE0 + DMAOR)) |
28 | #else /* Other CPU */ | 28 | #else /* Other CPU */ |
29 | #define dmaor_read_reg(n) ctrl_inw(SH_DMAC_BASE0 + DMAOR) | 29 | #define dmaor_read_reg(n) __raw_readw(SH_DMAC_BASE0 + DMAOR) |
30 | #define dmaor_write_reg(n, data) ctrl_outw(data, SH_DMAC_BASE0 + DMAOR) | 30 | #define dmaor_write_reg(n, data) __raw_writew(data, SH_DMAC_BASE0 + DMAOR) |
31 | #endif | 31 | #endif |
32 | 32 | ||
33 | static int dmte_irq_map[] __maybe_unused = { | 33 | static int dmte_irq_map[] __maybe_unused = { |
diff --git a/arch/sh/include/asm/mmu_context.h b/arch/sh/include/asm/mmu_context.h index 41080b173a7a..384c7471a374 100644 --- a/arch/sh/include/asm/mmu_context.h +++ b/arch/sh/include/asm/mmu_context.h | |||
@@ -158,7 +158,7 @@ static inline void enable_mmu(void) | |||
158 | unsigned int cpu = smp_processor_id(); | 158 | unsigned int cpu = smp_processor_id(); |
159 | 159 | ||
160 | /* Enable MMU */ | 160 | /* Enable MMU */ |
161 | ctrl_outl(MMU_CONTROL_INIT, MMUCR); | 161 | __raw_writel(MMU_CONTROL_INIT, MMUCR); |
162 | ctrl_barrier(); | 162 | ctrl_barrier(); |
163 | 163 | ||
164 | if (asid_cache(cpu) == NO_CONTEXT) | 164 | if (asid_cache(cpu) == NO_CONTEXT) |
@@ -171,9 +171,9 @@ static inline void disable_mmu(void) | |||
171 | { | 171 | { |
172 | unsigned long cr; | 172 | unsigned long cr; |
173 | 173 | ||
174 | cr = ctrl_inl(MMUCR); | 174 | cr = __raw_readl(MMUCR); |
175 | cr &= ~MMU_CONTROL_INIT; | 175 | cr &= ~MMU_CONTROL_INIT; |
176 | ctrl_outl(cr, MMUCR); | 176 | __raw_writel(cr, MMUCR); |
177 | 177 | ||
178 | ctrl_barrier(); | 178 | ctrl_barrier(); |
179 | } | 179 | } |
diff --git a/arch/sh/include/asm/mmu_context_32.h b/arch/sh/include/asm/mmu_context_32.h index 8ef800c549ab..10e2e17210d2 100644 --- a/arch/sh/include/asm/mmu_context_32.h +++ b/arch/sh/include/asm/mmu_context_32.h | |||
@@ -49,11 +49,11 @@ static inline unsigned long get_asid(void) | |||
49 | /* MMU_TTB is used for optimizing the fault handling. */ | 49 | /* MMU_TTB is used for optimizing the fault handling. */ |
50 | static inline void set_TTB(pgd_t *pgd) | 50 | static inline void set_TTB(pgd_t *pgd) |
51 | { | 51 | { |
52 | ctrl_outl((unsigned long)pgd, MMU_TTB); | 52 | __raw_writel((unsigned long)pgd, MMU_TTB); |
53 | } | 53 | } |
54 | 54 | ||
55 | static inline pgd_t *get_TTB(void) | 55 | static inline pgd_t *get_TTB(void) |
56 | { | 56 | { |
57 | return (pgd_t *)ctrl_inl(MMU_TTB); | 57 | return (pgd_t *)__raw_readl(MMU_TTB); |
58 | } | 58 | } |
59 | #endif /* __ASM_SH_MMU_CONTEXT_32_H */ | 59 | #endif /* __ASM_SH_MMU_CONTEXT_32_H */ |
diff --git a/arch/sh/include/asm/watchdog.h b/arch/sh/include/asm/watchdog.h index 19dfff5c8511..85a7aca7fb8f 100644 --- a/arch/sh/include/asm/watchdog.h +++ b/arch/sh/include/asm/watchdog.h | |||
@@ -70,7 +70,7 @@ | |||
70 | */ | 70 | */ |
71 | static inline __u32 sh_wdt_read_cnt(void) | 71 | static inline __u32 sh_wdt_read_cnt(void) |
72 | { | 72 | { |
73 | return ctrl_inl(WTCNT_R); | 73 | return __raw_readl(WTCNT_R); |
74 | } | 74 | } |
75 | 75 | ||
76 | /** | 76 | /** |
@@ -82,7 +82,7 @@ static inline __u32 sh_wdt_read_cnt(void) | |||
82 | */ | 82 | */ |
83 | static inline void sh_wdt_write_cnt(__u32 val) | 83 | static inline void sh_wdt_write_cnt(__u32 val) |
84 | { | 84 | { |
85 | ctrl_outl((WTCNT_HIGH << 24) | (__u32)val, WTCNT); | 85 | __raw_writel((WTCNT_HIGH << 24) | (__u32)val, WTCNT); |
86 | } | 86 | } |
87 | 87 | ||
88 | /** | 88 | /** |
@@ -94,7 +94,7 @@ static inline void sh_wdt_write_cnt(__u32 val) | |||
94 | */ | 94 | */ |
95 | static inline void sh_wdt_write_bst(__u32 val) | 95 | static inline void sh_wdt_write_bst(__u32 val) |
96 | { | 96 | { |
97 | ctrl_outl((WTBST_HIGH << 24) | (__u32)val, WTBST); | 97 | __raw_writel((WTBST_HIGH << 24) | (__u32)val, WTBST); |
98 | } | 98 | } |
99 | /** | 99 | /** |
100 | * sh_wdt_read_csr - Read from Control/Status Register | 100 | * sh_wdt_read_csr - Read from Control/Status Register |
@@ -103,7 +103,7 @@ static inline void sh_wdt_write_bst(__u32 val) | |||
103 | */ | 103 | */ |
104 | static inline __u32 sh_wdt_read_csr(void) | 104 | static inline __u32 sh_wdt_read_csr(void) |
105 | { | 105 | { |
106 | return ctrl_inl(WTCSR_R); | 106 | return __raw_readl(WTCSR_R); |
107 | } | 107 | } |
108 | 108 | ||
109 | /** | 109 | /** |
@@ -115,7 +115,7 @@ static inline __u32 sh_wdt_read_csr(void) | |||
115 | */ | 115 | */ |
116 | static inline void sh_wdt_write_csr(__u32 val) | 116 | static inline void sh_wdt_write_csr(__u32 val) |
117 | { | 117 | { |
118 | ctrl_outl((WTCSR_HIGH << 24) | (__u32)val, WTCSR); | 118 | __raw_writel((WTCSR_HIGH << 24) | (__u32)val, WTCSR); |
119 | } | 119 | } |
120 | #else | 120 | #else |
121 | /** | 121 | /** |
@@ -124,7 +124,7 @@ static inline void sh_wdt_write_csr(__u32 val) | |||
124 | */ | 124 | */ |
125 | static inline __u8 sh_wdt_read_cnt(void) | 125 | static inline __u8 sh_wdt_read_cnt(void) |
126 | { | 126 | { |
127 | return ctrl_inb(WTCNT_R); | 127 | return __raw_readb(WTCNT_R); |
128 | } | 128 | } |
129 | 129 | ||
130 | /** | 130 | /** |
@@ -136,7 +136,7 @@ static inline __u8 sh_wdt_read_cnt(void) | |||
136 | */ | 136 | */ |
137 | static inline void sh_wdt_write_cnt(__u8 val) | 137 | static inline void sh_wdt_write_cnt(__u8 val) |
138 | { | 138 | { |
139 | ctrl_outw((WTCNT_HIGH << 8) | (__u16)val, WTCNT); | 139 | __raw_writew((WTCNT_HIGH << 8) | (__u16)val, WTCNT); |
140 | } | 140 | } |
141 | 141 | ||
142 | /** | 142 | /** |
@@ -146,7 +146,7 @@ static inline void sh_wdt_write_cnt(__u8 val) | |||
146 | */ | 146 | */ |
147 | static inline __u8 sh_wdt_read_csr(void) | 147 | static inline __u8 sh_wdt_read_csr(void) |
148 | { | 148 | { |
149 | return ctrl_inb(WTCSR_R); | 149 | return __raw_readb(WTCSR_R); |
150 | } | 150 | } |
151 | 151 | ||
152 | /** | 152 | /** |
@@ -158,7 +158,7 @@ static inline __u8 sh_wdt_read_csr(void) | |||
158 | */ | 158 | */ |
159 | static inline void sh_wdt_write_csr(__u8 val) | 159 | static inline void sh_wdt_write_csr(__u8 val) |
160 | { | 160 | { |
161 | ctrl_outw((WTCSR_HIGH << 8) | (__u16)val, WTCSR); | 161 | __raw_writew((WTCSR_HIGH << 8) | (__u16)val, WTCSR); |
162 | } | 162 | } |
163 | #endif /* CONFIG_CPU_SUBTYPE_SH7785 || CONFIG_CPU_SUBTYPE_SH7780 */ | 163 | #endif /* CONFIG_CPU_SUBTYPE_SH7785 || CONFIG_CPU_SUBTYPE_SH7780 */ |
164 | #endif /* __KERNEL__ */ | 164 | #endif /* __KERNEL__ */ |