diff options
Diffstat (limited to 'arch/sh/drivers/dma/dma-sh.c')
-rw-r--r-- | arch/sh/drivers/dma/dma-sh.c | 26 |
1 files changed, 13 insertions, 13 deletions
diff --git a/arch/sh/drivers/dma/dma-sh.c b/arch/sh/drivers/dma/dma-sh.c index 37fb5b8bbc3f..565cc1a4cbba 100644 --- a/arch/sh/drivers/dma/dma-sh.c +++ b/arch/sh/drivers/dma/dma-sh.c | |||
@@ -54,7 +54,7 @@ static inline unsigned int get_dmte_irq(unsigned int chan) | |||
54 | */ | 54 | */ |
55 | static inline unsigned int calc_xmit_shift(struct dma_channel *chan) | 55 | static inline unsigned int calc_xmit_shift(struct dma_channel *chan) |
56 | { | 56 | { |
57 | u32 chcr = ctrl_inl(dma_base_addr[chan->chan] + CHCR); | 57 | u32 chcr = __raw_readl(dma_base_addr[chan->chan] + CHCR); |
58 | 58 | ||
59 | return ts_shift[(chcr & CHCR_TS_MASK)>>CHCR_TS_SHIFT]; | 59 | return ts_shift[(chcr & CHCR_TS_MASK)>>CHCR_TS_SHIFT]; |
60 | } | 60 | } |
@@ -70,13 +70,13 @@ static irqreturn_t dma_tei(int irq, void *dev_id) | |||
70 | struct dma_channel *chan = dev_id; | 70 | struct dma_channel *chan = dev_id; |
71 | u32 chcr; | 71 | u32 chcr; |
72 | 72 | ||
73 | chcr = ctrl_inl(dma_base_addr[chan->chan] + CHCR); | 73 | chcr = __raw_readl(dma_base_addr[chan->chan] + CHCR); |
74 | 74 | ||
75 | if (!(chcr & CHCR_TE)) | 75 | if (!(chcr & CHCR_TE)) |
76 | return IRQ_NONE; | 76 | return IRQ_NONE; |
77 | 77 | ||
78 | chcr &= ~(CHCR_IE | CHCR_DE); | 78 | chcr &= ~(CHCR_IE | CHCR_DE); |
79 | ctrl_outl(chcr, (dma_base_addr[chan->chan] + CHCR)); | 79 | __raw_writel(chcr, (dma_base_addr[chan->chan] + CHCR)); |
80 | 80 | ||
81 | wake_up(&chan->wait_queue); | 81 | wake_up(&chan->wait_queue); |
82 | 82 | ||
@@ -115,7 +115,7 @@ sh_dmac_configure_channel(struct dma_channel *chan, unsigned long chcr) | |||
115 | chan->flags &= ~DMA_TEI_CAPABLE; | 115 | chan->flags &= ~DMA_TEI_CAPABLE; |
116 | } | 116 | } |
117 | 117 | ||
118 | ctrl_outl(chcr, (dma_base_addr[chan->chan] + CHCR)); | 118 | __raw_writel(chcr, (dma_base_addr[chan->chan] + CHCR)); |
119 | 119 | ||
120 | chan->flags |= DMA_CONFIGURED; | 120 | chan->flags |= DMA_CONFIGURED; |
121 | return 0; | 121 | return 0; |
@@ -126,13 +126,13 @@ static void sh_dmac_enable_dma(struct dma_channel *chan) | |||
126 | int irq; | 126 | int irq; |
127 | u32 chcr; | 127 | u32 chcr; |
128 | 128 | ||
129 | chcr = ctrl_inl(dma_base_addr[chan->chan] + CHCR); | 129 | chcr = __raw_readl(dma_base_addr[chan->chan] + CHCR); |
130 | chcr |= CHCR_DE; | 130 | chcr |= CHCR_DE; |
131 | 131 | ||
132 | if (chan->flags & DMA_TEI_CAPABLE) | 132 | if (chan->flags & DMA_TEI_CAPABLE) |
133 | chcr |= CHCR_IE; | 133 | chcr |= CHCR_IE; |
134 | 134 | ||
135 | ctrl_outl(chcr, (dma_base_addr[chan->chan] + CHCR)); | 135 | __raw_writel(chcr, (dma_base_addr[chan->chan] + CHCR)); |
136 | 136 | ||
137 | if (chan->flags & DMA_TEI_CAPABLE) { | 137 | if (chan->flags & DMA_TEI_CAPABLE) { |
138 | irq = get_dmte_irq(chan->chan); | 138 | irq = get_dmte_irq(chan->chan); |
@@ -150,9 +150,9 @@ static void sh_dmac_disable_dma(struct dma_channel *chan) | |||
150 | disable_irq(irq); | 150 | disable_irq(irq); |
151 | } | 151 | } |
152 | 152 | ||
153 | chcr = ctrl_inl(dma_base_addr[chan->chan] + CHCR); | 153 | chcr = __raw_readl(dma_base_addr[chan->chan] + CHCR); |
154 | chcr &= ~(CHCR_DE | CHCR_TE | CHCR_IE); | 154 | chcr &= ~(CHCR_DE | CHCR_TE | CHCR_IE); |
155 | ctrl_outl(chcr, (dma_base_addr[chan->chan] + CHCR)); | 155 | __raw_writel(chcr, (dma_base_addr[chan->chan] + CHCR)); |
156 | } | 156 | } |
157 | 157 | ||
158 | static int sh_dmac_xfer_dma(struct dma_channel *chan) | 158 | static int sh_dmac_xfer_dma(struct dma_channel *chan) |
@@ -183,12 +183,12 @@ static int sh_dmac_xfer_dma(struct dma_channel *chan) | |||
183 | */ | 183 | */ |
184 | if (chan->sar || (mach_is_dreamcast() && | 184 | if (chan->sar || (mach_is_dreamcast() && |
185 | chan->chan == PVR2_CASCADE_CHAN)) | 185 | chan->chan == PVR2_CASCADE_CHAN)) |
186 | ctrl_outl(chan->sar, (dma_base_addr[chan->chan]+SAR)); | 186 | __raw_writel(chan->sar, (dma_base_addr[chan->chan]+SAR)); |
187 | if (chan->dar || (mach_is_dreamcast() && | 187 | if (chan->dar || (mach_is_dreamcast() && |
188 | chan->chan == PVR2_CASCADE_CHAN)) | 188 | chan->chan == PVR2_CASCADE_CHAN)) |
189 | ctrl_outl(chan->dar, (dma_base_addr[chan->chan] + DAR)); | 189 | __raw_writel(chan->dar, (dma_base_addr[chan->chan] + DAR)); |
190 | 190 | ||
191 | ctrl_outl(chan->count >> calc_xmit_shift(chan), | 191 | __raw_writel(chan->count >> calc_xmit_shift(chan), |
192 | (dma_base_addr[chan->chan] + TCR)); | 192 | (dma_base_addr[chan->chan] + TCR)); |
193 | 193 | ||
194 | sh_dmac_enable_dma(chan); | 194 | sh_dmac_enable_dma(chan); |
@@ -198,10 +198,10 @@ static int sh_dmac_xfer_dma(struct dma_channel *chan) | |||
198 | 198 | ||
199 | static int sh_dmac_get_dma_residue(struct dma_channel *chan) | 199 | static int sh_dmac_get_dma_residue(struct dma_channel *chan) |
200 | { | 200 | { |
201 | if (!(ctrl_inl(dma_base_addr[chan->chan] + CHCR) & CHCR_DE)) | 201 | if (!(__raw_readl(dma_base_addr[chan->chan] + CHCR) & CHCR_DE)) |
202 | return 0; | 202 | return 0; |
203 | 203 | ||
204 | return ctrl_inl(dma_base_addr[chan->chan] + TCR) | 204 | return __raw_readl(dma_base_addr[chan->chan] + TCR) |
205 | << calc_xmit_shift(chan); | 205 | << calc_xmit_shift(chan); |
206 | } | 206 | } |
207 | 207 | ||