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Diffstat (limited to 'arch/ppc/platforms/4xx/ibm440gx.c')
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diff --git a/arch/ppc/platforms/4xx/ibm440gx.c b/arch/ppc/platforms/4xx/ibm440gx.c
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1/*
2 * arch/ppc/platforms/4xx/ibm440gx.c
3 *
4 * PPC440GX I/O descriptions
5 *
6 * Matt Porter <mporter@mvista.com>
7 * Copyright 2002-2004 MontaVista Software Inc.
8 *
9 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
10 * Copyright (c) 2003, 2004 Zultys Technologies
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 *
17 */
18#include <linux/init.h>
19#include <linux/module.h>
20#include <platforms/4xx/ibm440gx.h>
21#include <asm/ocp.h>
22#include <asm/ppc4xx_pic.h>
23
24static struct ocp_func_emac_data ibm440gx_emac0_def = {
25 .rgmii_idx = -1, /* No RGMII */
26 .rgmii_mux = -1, /* No RGMII */
27 .zmii_idx = 0, /* ZMII device index */
28 .zmii_mux = 0, /* ZMII input of this EMAC */
29 .mal_idx = 0, /* MAL device index */
30 .mal_rx_chan = 0, /* MAL rx channel number */
31 .mal_tx_chan = 0, /* MAL tx channel number */
32 .wol_irq = 61, /* WOL interrupt number */
33 .mdio_idx = -1, /* No shared MDIO */
34 .tah_idx = -1, /* No TAH */
35};
36
37static struct ocp_func_emac_data ibm440gx_emac1_def = {
38 .rgmii_idx = -1, /* No RGMII */
39 .rgmii_mux = -1, /* No RGMII */
40 .zmii_idx = 0, /* ZMII device index */
41 .zmii_mux = 1, /* ZMII input of this EMAC */
42 .mal_idx = 0, /* MAL device index */
43 .mal_rx_chan = 1, /* MAL rx channel number */
44 .mal_tx_chan = 1, /* MAL tx channel number */
45 .wol_irq = 63, /* WOL interrupt number */
46 .mdio_idx = -1, /* No shared MDIO */
47 .tah_idx = -1, /* No TAH */
48};
49
50static struct ocp_func_emac_data ibm440gx_emac2_def = {
51 .rgmii_idx = 0, /* RGMII device index */
52 .rgmii_mux = 0, /* RGMII input of this EMAC */
53 .zmii_idx = 0, /* ZMII device index */
54 .zmii_mux = 2, /* ZMII input of this EMAC */
55 .mal_idx = 0, /* MAL device index */
56 .mal_rx_chan = 2, /* MAL rx channel number */
57 .mal_tx_chan = 2, /* MAL tx channel number */
58 .wol_irq = 65, /* WOL interrupt number */
59 .mdio_idx = -1, /* No shared MDIO */
60 .tah_idx = 0, /* TAH device index */
61 .jumbo = 1, /* Jumbo frames supported */
62};
63
64static struct ocp_func_emac_data ibm440gx_emac3_def = {
65 .rgmii_idx = 0, /* RGMII device index */
66 .rgmii_mux = 1, /* RGMII input of this EMAC */
67 .zmii_idx = 0, /* ZMII device index */
68 .zmii_mux = 3, /* ZMII input of this EMAC */
69 .mal_idx = 0, /* MAL device index */
70 .mal_rx_chan = 3, /* MAL rx channel number */
71 .mal_tx_chan = 3, /* MAL tx channel number */
72 .wol_irq = 67, /* WOL interrupt number */
73 .mdio_idx = -1, /* No shared MDIO */
74 .tah_idx = 1, /* TAH device index */
75 .jumbo = 1, /* Jumbo frames supported */
76};
77OCP_SYSFS_EMAC_DATA()
78
79static struct ocp_func_mal_data ibm440gx_mal0_def = {
80 .num_tx_chans = 4, /* Number of TX channels */
81 .num_rx_chans = 4, /* Number of RX channels */
82 .txeob_irq = 10, /* TX End Of Buffer IRQ */
83 .rxeob_irq = 11, /* RX End Of Buffer IRQ */
84 .txde_irq = 33, /* TX Descriptor Error IRQ */
85 .rxde_irq = 34, /* RX Descriptor Error IRQ */
86 .serr_irq = 32, /* MAL System Error IRQ */
87};
88OCP_SYSFS_MAL_DATA()
89
90static struct ocp_func_iic_data ibm440gx_iic0_def = {
91 .fast_mode = 0, /* Use standad mode (100Khz) */
92};
93
94static struct ocp_func_iic_data ibm440gx_iic1_def = {
95 .fast_mode = 0, /* Use standad mode (100Khz) */
96};
97OCP_SYSFS_IIC_DATA()
98
99struct ocp_def core_ocp[] = {
100 { .vendor = OCP_VENDOR_IBM,
101 .function = OCP_FUNC_OPB,
102 .index = 0,
103 .paddr = 0x0000000140000000ULL,
104 .irq = OCP_IRQ_NA,
105 .pm = OCP_CPM_NA,
106 },
107 { .vendor = OCP_VENDOR_IBM,
108 .function = OCP_FUNC_16550,
109 .index = 0,
110 .paddr = PPC440GX_UART0_ADDR,
111 .irq = UART0_INT,
112 .pm = IBM_CPM_UART0,
113 },
114 { .vendor = OCP_VENDOR_IBM,
115 .function = OCP_FUNC_16550,
116 .index = 1,
117 .paddr = PPC440GX_UART1_ADDR,
118 .irq = UART1_INT,
119 .pm = IBM_CPM_UART1,
120 },
121 { .vendor = OCP_VENDOR_IBM,
122 .function = OCP_FUNC_IIC,
123 .index = 0,
124 .paddr = 0x0000000140000400ULL,
125 .irq = 2,
126 .pm = IBM_CPM_IIC0,
127 .additions = &ibm440gx_iic0_def,
128 .show = &ocp_show_iic_data
129 },
130 { .vendor = OCP_VENDOR_IBM,
131 .function = OCP_FUNC_IIC,
132 .index = 1,
133 .paddr = 0x0000000140000500ULL,
134 .irq = 3,
135 .pm = IBM_CPM_IIC1,
136 .additions = &ibm440gx_iic1_def,
137 .show = &ocp_show_iic_data
138 },
139 { .vendor = OCP_VENDOR_IBM,
140 .function = OCP_FUNC_GPIO,
141 .index = 0,
142 .paddr = 0x0000000140000700ULL,
143 .irq = OCP_IRQ_NA,
144 .pm = IBM_CPM_GPIO0,
145 },
146 { .vendor = OCP_VENDOR_IBM,
147 .function = OCP_FUNC_MAL,
148 .paddr = OCP_PADDR_NA,
149 .irq = OCP_IRQ_NA,
150 .pm = OCP_CPM_NA,
151 .additions = &ibm440gx_mal0_def,
152 .show = &ocp_show_mal_data,
153 },
154 { .vendor = OCP_VENDOR_IBM,
155 .function = OCP_FUNC_EMAC,
156 .index = 0,
157 .paddr = 0x0000000140000800ULL,
158 .irq = 60,
159 .pm = OCP_CPM_NA,
160 .additions = &ibm440gx_emac0_def,
161 .show = &ocp_show_emac_data,
162 },
163 { .vendor = OCP_VENDOR_IBM,
164 .function = OCP_FUNC_EMAC,
165 .index = 1,
166 .paddr = 0x0000000140000900ULL,
167 .irq = 62,
168 .pm = OCP_CPM_NA,
169 .additions = &ibm440gx_emac1_def,
170 .show = &ocp_show_emac_data,
171 },
172 { .vendor = OCP_VENDOR_IBM,
173 .function = OCP_FUNC_EMAC,
174 .index = 2,
175 .paddr = 0x0000000140000C00ULL,
176 .irq = 64,
177 .pm = OCP_CPM_NA,
178 .additions = &ibm440gx_emac2_def,
179 .show = &ocp_show_emac_data,
180 },
181 { .vendor = OCP_VENDOR_IBM,
182 .function = OCP_FUNC_EMAC,
183 .index = 3,
184 .paddr = 0x0000000140000E00ULL,
185 .irq = 66,
186 .pm = OCP_CPM_NA,
187 .additions = &ibm440gx_emac3_def,
188 .show = &ocp_show_emac_data,
189 },
190 { .vendor = OCP_VENDOR_IBM,
191 .function = OCP_FUNC_RGMII,
192 .paddr = 0x0000000140000790ULL,
193 .irq = OCP_IRQ_NA,
194 .pm = OCP_CPM_NA,
195 },
196 { .vendor = OCP_VENDOR_IBM,
197 .function = OCP_FUNC_ZMII,
198 .paddr = 0x0000000140000780ULL,
199 .irq = OCP_IRQ_NA,
200 .pm = OCP_CPM_NA,
201 },
202 { .vendor = OCP_VENDOR_IBM,
203 .function = OCP_FUNC_TAH,
204 .index = 0,
205 .paddr = 0x0000000140000b50ULL,
206 .irq = 68,
207 .pm = OCP_CPM_NA,
208 },
209 { .vendor = OCP_VENDOR_IBM,
210 .function = OCP_FUNC_TAH,
211 .index = 1,
212 .paddr = 0x0000000140000d50ULL,
213 .irq = 69,
214 .pm = OCP_CPM_NA,
215 },
216 { .vendor = OCP_VENDOR_INVALID
217 }
218};
219
220/* Polarity and triggering settings for internal interrupt sources */
221struct ppc4xx_uic_settings ppc4xx_core_uic_cfg[] __initdata = {
222 { .polarity = 0xfffffe03,
223 .triggering = 0x01c00000,
224 .ext_irq_mask = 0x000001fc, /* IRQ0 - IRQ6 */
225 },
226 { .polarity = 0xffffc0ff,
227 .triggering = 0x00ff8000,
228 .ext_irq_mask = 0x00003f00, /* IRQ7 - IRQ12 */
229 },
230 { .polarity = 0xffff83ff,
231 .triggering = 0x000f83c0,
232 .ext_irq_mask = 0x00007c00, /* IRQ13 - IRQ17 */
233 },
234};
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-19 15:37:54 -0500