1 files changed, 143 insertions, 0 deletions

diff --git a/arch/ppc/platforms/4xx/ibm405ep.c b/arch/ppc/platforms/4xx/ibm405ep.c
new file mode 100644
index 000000000000..6d44567f4dd2
--- /dev/null
+++ b/arch/ppc/platforms/4xx/ibm405ep.c
@@ -0,0 +1,143 @@
+/*
+ * arch/ppc/platforms/ibm405ep.c
+ *
+ * Support for IBM PPC 405EP processors.
+ *
+ * Author: SAW (IBM), derived from ibmnp405l.c.
+ *         Maintained by MontaVista Software <source@mvista.com>
+ *
+ * 2003 (c) MontaVista Softare Inc.  This file is licensed under the
+ * terms of the GNU General Public License version 2. This program is
+ * licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+
+#include <linux/config.h>
+#include <linux/init.h>
+#include <linux/smp.h>
+#include <linux/threads.h>
+#include <linux/param.h>
+#include <linux/string.h>
+
+#include <asm/ibm4xx.h>
+#include <asm/ocp.h>
+#include <asm/ppc4xx_pic.h>
+
+#include <platforms/4xx/ibm405ep.h>
+
+static struct ocp_func_mal_data ibm405ep_mal0_def = {
+        .num_tx_chans   = 4,            /* Number of TX channels */
+        .num_rx_chans   = 2,            /* Number of RX channels */
+        .txeob_irq      = 11,           /* TX End Of Buffer IRQ  */
+        .rxeob_irq      = 12,           /* RX End Of Buffer IRQ  */
+        .txde_irq       = 13,           /* TX Descriptor Error IRQ */
+        .rxde_irq       = 14,           /* RX Descriptor Error IRQ */
+        .serr_irq       = 10,           /* MAL System Error IRQ    */
+};
+OCP_SYSFS_MAL_DATA()
+
+static struct ocp_func_emac_data ibm405ep_emac0_def = {
+        .rgmii_idx      = -1,           /* No RGMII */
+        .rgmii_mux      = -1,           /* No RGMII */
+        .zmii_idx       = -1,           /* ZMII device index */
+        .zmii_mux       = 0,            /* ZMII input of this EMAC */
+        .mal_idx        = 0,            /* MAL device index */
+        .mal_rx_chan    = 0,            /* MAL rx channel number */
+        .mal_tx_chan    = 0,            /* MAL tx channel number */
+        .wol_irq        = 9,            /* WOL interrupt number */
+        .mdio_idx       = 0,            /* MDIO via EMAC0 */
+        .tah_idx        = -1,           /* No TAH */
+};
+
+static struct ocp_func_emac_data ibm405ep_emac1_def = {
+        .rgmii_idx      = -1,           /* No RGMII */
+        .rgmii_mux      = -1,           /* No RGMII */
+        .zmii_idx       = -1,           /* ZMII device index */
+        .zmii_mux       = 0,            /* ZMII input of this EMAC */
+        .mal_idx        = 0,            /* MAL device index */
+        .mal_rx_chan    = 1,            /* MAL rx channel number */
+        .mal_tx_chan    = 2,            /* MAL tx channel number */
+        .wol_irq        = 9,            /* WOL interrupt number */
+        .mdio_idx       = 0,            /* MDIO via EMAC0 */
+        .tah_idx        = -1,           /* No TAH */
+};
+OCP_SYSFS_EMAC_DATA()
+
+static struct ocp_func_iic_data ibm405ep_iic0_def = {
+        .fast_mode      = 0,            /* Use standad mode (100Khz) */
+};
+OCP_SYSFS_IIC_DATA()
+
+struct ocp_def core_ocp[] = {
+        { .vendor       = OCP_VENDOR_IBM,
+          .function     = OCP_FUNC_OPB,
+          .index        = 0,
+          .paddr        = 0xEF600000,
+          .irq          = OCP_IRQ_NA,
+          .pm           = OCP_CPM_NA,
+        },
+        { .vendor       = OCP_VENDOR_IBM,
+          .function     = OCP_FUNC_16550,
+          .index        = 0,
+          .paddr        = UART0_IO_BASE,
+          .irq          = UART0_INT,
+          .pm           = IBM_CPM_UART0
+        },
+        { .vendor       = OCP_VENDOR_IBM,
+          .function     = OCP_FUNC_16550,
+          .index        = 1,
+          .paddr        = UART1_IO_BASE,
+          .irq          = UART1_INT,
+          .pm           = IBM_CPM_UART1
+        },
+        { .vendor       = OCP_VENDOR_IBM,
+          .function     = OCP_FUNC_IIC,
+          .paddr        = 0xEF600500,
+          .irq          = 2,
+          .pm           = IBM_CPM_IIC0,
+          .additions    = &ibm405ep_iic0_def,
+          .show         = &ocp_show_iic_data
+        },
+        { .vendor       = OCP_VENDOR_IBM,
+          .function     = OCP_FUNC_GPIO,
+          .paddr        = 0xEF600700,
+          .irq          = OCP_IRQ_NA,
+          .pm           = IBM_CPM_GPIO0
+        },
+        { .vendor       = OCP_VENDOR_IBM,
+          .function     = OCP_FUNC_MAL,
+          .paddr        = OCP_PADDR_NA,
+          .irq          = OCP_IRQ_NA,
+          .pm           = OCP_CPM_NA,
+          .additions    = &ibm405ep_mal0_def,
+          .show         = &ocp_show_mal_data
+        },
+        { .vendor       = OCP_VENDOR_IBM,
+          .function     = OCP_FUNC_EMAC,
+          .index        = 0,
+          .paddr        = EMAC0_BASE,
+          .irq          = 15,
+          .pm           = OCP_CPM_NA,
+          .additions    = &ibm405ep_emac0_def,
+          .show         = &ocp_show_emac_data
+        },
+        { .vendor       = OCP_VENDOR_IBM,
+          .function     = OCP_FUNC_EMAC,
+          .index        = 1,
+          .paddr        = 0xEF600900,
+          .irq          = 17,
+          .pm           = OCP_CPM_NA,
+          .additions    = &ibm405ep_emac1_def,
+          .show         = &ocp_show_emac_data
+        },
+        { .vendor       = OCP_VENDOR_INVALID
+        }
+};
+
+/* Polarity and triggering settings for internal interrupt sources */
+struct ppc4xx_uic_settings ppc4xx_core_uic_cfg[] __initdata = {
+        { .polarity     = 0xffff7f80,
+          .triggering   = 0x00000000,
+          .ext_irq_mask = 0x0000007f,   /* IRQ0 - IRQ6 */
+        }
+};