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-rw-r--r--arch/powerpc/boot/dts/katmai.dts210
1 files changed, 106 insertions, 104 deletions
diff --git a/arch/powerpc/boot/dts/katmai.dts b/arch/powerpc/boot/dts/katmai.dts
index cc2873a531d2..077819bc3cbd 100644
--- a/arch/powerpc/boot/dts/katmai.dts
+++ b/arch/powerpc/boot/dts/katmai.dts
@@ -12,12 +12,14 @@
12 * any warranty of any kind, whether express or implied. 12 * any warranty of any kind, whether express or implied.
13 */ 13 */
14 14
15/dts-v1/;
16
15/ { 17/ {
16 #address-cells = <2>; 18 #address-cells = <2>;
17 #size-cells = <1>; 19 #size-cells = <1>;
18 model = "amcc,katmai"; 20 model = "amcc,katmai";
19 compatible = "amcc,katmai"; 21 compatible = "amcc,katmai";
20 dcr-parent = <&/cpus/cpu@0>; 22 dcr-parent = <&{/cpus/cpu@0}>;
21 23
22 aliases { 24 aliases {
23 ethernet0 = &EMAC0; 25 ethernet0 = &EMAC0;
@@ -33,13 +35,13 @@
33 cpu@0 { 35 cpu@0 {
34 device_type = "cpu"; 36 device_type = "cpu";
35 model = "PowerPC,440SPe"; 37 model = "PowerPC,440SPe";
36 reg = <0>; 38 reg = <0x00000000>;
37 clock-frequency = <0>; /* Filled in by zImage */ 39 clock-frequency = <0>; /* Filled in by zImage */
38 timebase-frequency = <0>; /* Filled in by zImage */ 40 timebase-frequency = <0>; /* Filled in by zImage */
39 i-cache-line-size = <20>; 41 i-cache-line-size = <32>;
40 d-cache-line-size = <20>; 42 d-cache-line-size = <32>;
41 i-cache-size = <8000>; 43 i-cache-size = <32768>;
42 d-cache-size = <8000>; 44 d-cache-size = <32768>;
43 dcr-controller; 45 dcr-controller;
44 dcr-access-method = "native"; 46 dcr-access-method = "native";
45 }; 47 };
@@ -47,14 +49,14 @@
47 49
48 memory { 50 memory {
49 device_type = "memory"; 51 device_type = "memory";
50 reg = <0 0 0>; /* Filled in by zImage */ 52 reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by zImage */
51 }; 53 };
52 54
53 UIC0: interrupt-controller0 { 55 UIC0: interrupt-controller0 {
54 compatible = "ibm,uic-440spe","ibm,uic"; 56 compatible = "ibm,uic-440spe","ibm,uic";
55 interrupt-controller; 57 interrupt-controller;
56 cell-index = <0>; 58 cell-index = <0>;
57 dcr-reg = <0c0 009>; 59 dcr-reg = <0x0c0 0x009>;
58 #address-cells = <0>; 60 #address-cells = <0>;
59 #size-cells = <0>; 61 #size-cells = <0>;
60 #interrupt-cells = <2>; 62 #interrupt-cells = <2>;
@@ -64,11 +66,11 @@
64 compatible = "ibm,uic-440spe","ibm,uic"; 66 compatible = "ibm,uic-440spe","ibm,uic";
65 interrupt-controller; 67 interrupt-controller;
66 cell-index = <1>; 68 cell-index = <1>;
67 dcr-reg = <0d0 009>; 69 dcr-reg = <0x0d0 0x009>;
68 #address-cells = <0>; 70 #address-cells = <0>;
69 #size-cells = <0>; 71 #size-cells = <0>;
70 #interrupt-cells = <2>; 72 #interrupt-cells = <2>;
71 interrupts = <1e 4 1f 4>; /* cascade */ 73 interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
72 interrupt-parent = <&UIC0>; 74 interrupt-parent = <&UIC0>;
73 }; 75 };
74 76
@@ -76,11 +78,11 @@
76 compatible = "ibm,uic-440spe","ibm,uic"; 78 compatible = "ibm,uic-440spe","ibm,uic";
77 interrupt-controller; 79 interrupt-controller;
78 cell-index = <2>; 80 cell-index = <2>;
79 dcr-reg = <0e0 009>; 81 dcr-reg = <0x0e0 0x009>;
80 #address-cells = <0>; 82 #address-cells = <0>;
81 #size-cells = <0>; 83 #size-cells = <0>;
82 #interrupt-cells = <2>; 84 #interrupt-cells = <2>;
83 interrupts = <a 4 b 4>; /* cascade */ 85 interrupts = <0xa 0x4 0xb 0x4>; /* cascade */
84 interrupt-parent = <&UIC0>; 86 interrupt-parent = <&UIC0>;
85 }; 87 };
86 88
@@ -88,22 +90,22 @@
88 compatible = "ibm,uic-440spe","ibm,uic"; 90 compatible = "ibm,uic-440spe","ibm,uic";
89 interrupt-controller; 91 interrupt-controller;
90 cell-index = <3>; 92 cell-index = <3>;
91 dcr-reg = <0f0 009>; 93 dcr-reg = <0x0f0 0x009>;
92 #address-cells = <0>; 94 #address-cells = <0>;
93 #size-cells = <0>; 95 #size-cells = <0>;
94 #interrupt-cells = <2>; 96 #interrupt-cells = <2>;
95 interrupts = <10 4 11 4>; /* cascade */ 97 interrupts = <0x10 0x4 0x11 0x4>; /* cascade */
96 interrupt-parent = <&UIC0>; 98 interrupt-parent = <&UIC0>;
97 }; 99 };
98 100
99 SDR0: sdr { 101 SDR0: sdr {
100 compatible = "ibm,sdr-440spe"; 102 compatible = "ibm,sdr-440spe";
101 dcr-reg = <00e 002>; 103 dcr-reg = <0x00e 0x002>;
102 }; 104 };
103 105
104 CPR0: cpr { 106 CPR0: cpr {
105 compatible = "ibm,cpr-440spe"; 107 compatible = "ibm,cpr-440spe";
106 dcr-reg = <00c 002>; 108 dcr-reg = <0x00c 0x002>;
107 }; 109 };
108 110
109 plb { 111 plb {
@@ -115,108 +117,108 @@
115 117
116 SDRAM0: sdram { 118 SDRAM0: sdram {
117 compatible = "ibm,sdram-440spe", "ibm,sdram-405gp"; 119 compatible = "ibm,sdram-440spe", "ibm,sdram-405gp";
118 dcr-reg = <010 2>; 120 dcr-reg = <0x010 0x002>;
119 }; 121 };
120 122
121 MAL0: mcmal { 123 MAL0: mcmal {
122 compatible = "ibm,mcmal-440spe", "ibm,mcmal2"; 124 compatible = "ibm,mcmal-440spe", "ibm,mcmal2";
123 dcr-reg = <180 62>; 125 dcr-reg = <0x180 0x062>;
124 num-tx-chans = <2>; 126 num-tx-chans = <2>;
125 num-rx-chans = <1>; 127 num-rx-chans = <1>;
126 interrupt-parent = <&MAL0>; 128 interrupt-parent = <&MAL0>;
127 interrupts = <0 1 2 3 4>; 129 interrupts = <0x0 0x1 0x2 0x3 0x4>;
128 #interrupt-cells = <1>; 130 #interrupt-cells = <1>;
129 #address-cells = <0>; 131 #address-cells = <0>;
130 #size-cells = <0>; 132 #size-cells = <0>;
131 interrupt-map = </*TXEOB*/ 0 &UIC1 6 4 133 interrupt-map = </*TXEOB*/ 0x0 &UIC1 0x6 0x4
132 /*RXEOB*/ 1 &UIC1 7 4 134 /*RXEOB*/ 0x1 &UIC1 0x7 0x4
133 /*SERR*/ 2 &UIC1 1 4 135 /*SERR*/ 0x2 &UIC1 0x1 0x4
134 /*TXDE*/ 3 &UIC1 2 4 136 /*TXDE*/ 0x3 &UIC1 0x2 0x4
135 /*RXDE*/ 4 &UIC1 3 4>; 137 /*RXDE*/ 0x4 &UIC1 0x3 0x4>;
136 }; 138 };
137 139
138 POB0: opb { 140 POB0: opb {
139 compatible = "ibm,opb-440spe", "ibm,opb-440gp", "ibm,opb"; 141 compatible = "ibm,opb-440spe", "ibm,opb-440gp", "ibm,opb";
140 #address-cells = <1>; 142 #address-cells = <1>;
141 #size-cells = <1>; 143 #size-cells = <1>;
142 ranges = <00000000 4 e0000000 20000000>; 144 ranges = <0x00000000 0x00000004 0xe0000000 0x20000000>;
143 clock-frequency = <0>; /* Filled in by zImage */ 145 clock-frequency = <0>; /* Filled in by zImage */
144 146
145 EBC0: ebc { 147 EBC0: ebc {
146 compatible = "ibm,ebc-440spe", "ibm,ebc-440gp", "ibm,ebc"; 148 compatible = "ibm,ebc-440spe", "ibm,ebc-440gp", "ibm,ebc";
147 dcr-reg = <012 2>; 149 dcr-reg = <0x012 0x002>;
148 #address-cells = <2>; 150 #address-cells = <2>;
149 #size-cells = <1>; 151 #size-cells = <1>;
150 clock-frequency = <0>; /* Filled in by zImage */ 152 clock-frequency = <0>; /* Filled in by zImage */
151 interrupts = <5 1>; 153 interrupts = <0x5 0x1>;
152 interrupt-parent = <&UIC1>; 154 interrupt-parent = <&UIC1>;
153 }; 155 };
154 156
155 UART0: serial@10000200 { 157 UART0: serial@10000200 {
156 device_type = "serial"; 158 device_type = "serial";
157 compatible = "ns16550"; 159 compatible = "ns16550";
158 reg = <10000200 8>; 160 reg = <0x10000200 0x00000008>;
159 virtual-reg = <a0000200>; 161 virtual-reg = <0xa0000200>;
160 clock-frequency = <0>; /* Filled in by zImage */ 162 clock-frequency = <0>; /* Filled in by zImage */
161 current-speed = <1c200>; 163 current-speed = <115200>;
162 interrupt-parent = <&UIC0>; 164 interrupt-parent = <&UIC0>;
163 interrupts = <0 4>; 165 interrupts = <0x0 0x4>;
164 }; 166 };
165 167
166 UART1: serial@10000300 { 168 UART1: serial@10000300 {
167 device_type = "serial"; 169 device_type = "serial";
168 compatible = "ns16550"; 170 compatible = "ns16550";
169 reg = <10000300 8>; 171 reg = <0x10000300 0x00000008>;
170 virtual-reg = <a0000300>; 172 virtual-reg = <0xa0000300>;
171 clock-frequency = <0>; 173 clock-frequency = <0>;
172 current-speed = <0>; 174 current-speed = <0>;
173 interrupt-parent = <&UIC0>; 175 interrupt-parent = <&UIC0>;
174 interrupts = <1 4>; 176 interrupts = <0x1 0x4>;
175 }; 177 };
176 178
177 179
178 UART2: serial@10000600 { 180 UART2: serial@10000600 {
179 device_type = "serial"; 181 device_type = "serial";
180 compatible = "ns16550"; 182 compatible = "ns16550";
181 reg = <10000600 8>; 183 reg = <0x10000600 0x00000008>;
182 virtual-reg = <a0000600>; 184 virtual-reg = <0xa0000600>;
183 clock-frequency = <0>; 185 clock-frequency = <0>;
184 current-speed = <0>; 186 current-speed = <0>;
185 interrupt-parent = <&UIC1>; 187 interrupt-parent = <&UIC1>;
186 interrupts = <5 4>; 188 interrupts = <0x5 0x4>;
187 }; 189 };
188 190
189 IIC0: i2c@10000400 { 191 IIC0: i2c@10000400 {
190 compatible = "ibm,iic-440spe", "ibm,iic-440gp", "ibm,iic"; 192 compatible = "ibm,iic-440spe", "ibm,iic-440gp", "ibm,iic";
191 reg = <10000400 14>; 193 reg = <0x10000400 0x00000014>;
192 interrupt-parent = <&UIC0>; 194 interrupt-parent = <&UIC0>;
193 interrupts = <2 4>; 195 interrupts = <0x2 0x4>;
194 }; 196 };
195 197
196 IIC1: i2c@10000500 { 198 IIC1: i2c@10000500 {
197 compatible = "ibm,iic-440spe", "ibm,iic-440gp", "ibm,iic"; 199 compatible = "ibm,iic-440spe", "ibm,iic-440gp", "ibm,iic";
198 reg = <10000500 14>; 200 reg = <0x10000500 0x00000014>;
199 interrupt-parent = <&UIC0>; 201 interrupt-parent = <&UIC0>;
200 interrupts = <3 4>; 202 interrupts = <0x3 0x4>;
201 }; 203 };
202 204
203 EMAC0: ethernet@10000800 { 205 EMAC0: ethernet@10000800 {
204 linux,network-index = <0>; 206 linux,network-index = <0x0>;
205 device_type = "network"; 207 device_type = "network";
206 compatible = "ibm,emac-440spe", "ibm,emac4"; 208 compatible = "ibm,emac-440spe", "ibm,emac4";
207 interrupt-parent = <&UIC1>; 209 interrupt-parent = <&UIC1>;
208 interrupts = <1c 4 1d 4>; 210 interrupts = <0x1c 0x4 0x1d 0x4>;
209 reg = <10000800 70>; 211 reg = <0x10000800 0x00000074>;
210 local-mac-address = [000000000000]; 212 local-mac-address = [000000000000];
211 mal-device = <&MAL0>; 213 mal-device = <&MAL0>;
212 mal-tx-channel = <0>; 214 mal-tx-channel = <0>;
213 mal-rx-channel = <0>; 215 mal-rx-channel = <0>;
214 cell-index = <0>; 216 cell-index = <0>;
215 max-frame-size = <2328>; 217 max-frame-size = <9000>;
216 rx-fifo-size = <1000>; 218 rx-fifo-size = <4096>;
217 tx-fifo-size = <800>; 219 tx-fifo-size = <2048>;
218 phy-mode = "gmii"; 220 phy-mode = "gmii";
219 phy-map = <00000000>; 221 phy-map = <0x00000000>;
220 has-inverted-stacr-oc; 222 has-inverted-stacr-oc;
221 has-new-stacr-staopc; 223 has-new-stacr-staopc;
222 }; 224 };
@@ -231,23 +233,23 @@
231 primary; 233 primary;
232 large-inbound-windows; 234 large-inbound-windows;
233 enable-msi-hole; 235 enable-msi-hole;
234 reg = <c 0ec00000 8 /* Config space access */ 236 reg = <0x0000000c 0x0ec00000 0x00000008 /* Config space access */
235 0 0 0 /* no IACK cycles */ 237 0x00000000 0x00000000 0x00000000 /* no IACK cycles */
236 c 0ed00000 4 /* Special cycles */ 238 0x0000000c 0x0ed00000 0x00000004 /* Special cycles */
237 c 0ec80000 100 /* Internal registers */ 239 0x0000000c 0x0ec80000 0x00000100 /* Internal registers */
238 c 0ec80100 fc>; /* Internal messaging registers */ 240 0x0000000c 0x0ec80100 0x000000fc>; /* Internal messaging registers */
239 241
240 /* Outbound ranges, one memory and one IO, 242 /* Outbound ranges, one memory and one IO,
241 * later cannot be changed 243 * later cannot be changed
242 */ 244 */
243 ranges = <02000000 0 80000000 0000000d 80000000 0 80000000 245 ranges = <0x02000000 0x00000000 0x80000000 0x0000000d 0x80000000 0x00000000 0x80000000
244 01000000 0 00000000 0000000c 08000000 0 00010000>; 246 0x01000000 0x00000000 0x00000000 0x0000000c 0x08000000 0x00000000 0x00010000>;
245 247
246 /* Inbound 2GB range starting at 0 */ 248 /* Inbound 2GB range starting at 0 */
247 dma-ranges = <42000000 0 0 0 0 0 80000000>; 249 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
248 250
249 /* This drives busses 0 to 0xf */ 251 /* This drives busses 0 to 0xf */
250 bus-range = <0 f>; 252 bus-range = <0x0 0xf>;
251 253
252 /* 254 /*
253 * On Katmai, the following PCI-X interrupts signals 255 * On Katmai, the following PCI-X interrupts signals
@@ -258,13 +260,13 @@
258 * INTC: J2: 1-2 260 * INTC: J2: 1-2
259 * INTD: J1: 1-2 261 * INTD: J1: 1-2
260 */ 262 */
261 interrupt-map-mask = <f800 0 0 7>; 263 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
262 interrupt-map = < 264 interrupt-map = <
263 /* IDSEL 1 */ 265 /* IDSEL 1 */
264 0800 0 0 1 &UIC1 14 8 266 0x800 0x0 0x0 0x1 &UIC1 0x14 0x8
265 0800 0 0 2 &UIC1 13 8 267 0x800 0x0 0x0 0x2 &UIC1 0x13 0x8
266 0800 0 0 3 &UIC1 12 8 268 0x800 0x0 0x0 0x3 &UIC1 0x12 0x8
267 0800 0 0 4 &UIC1 11 8 269 0x800 0x0 0x0 0x4 &UIC1 0x11 0x8
268 >; 270 >;
269 }; 271 };
270 272
@@ -275,23 +277,23 @@
275 #address-cells = <3>; 277 #address-cells = <3>;
276 compatible = "ibm,plb-pciex-440spe", "ibm,plb-pciex"; 278 compatible = "ibm,plb-pciex-440spe", "ibm,plb-pciex";
277 primary; 279 primary;
278 port = <0>; /* port number */ 280 port = <0x0>; /* port number */
279 reg = <d 00000000 20000000 /* Config space access */ 281 reg = <0x0000000d 0x00000000 0x20000000 /* Config space access */
280 c 10000000 00001000>; /* Registers */ 282 0x0000000c 0x10000000 0x00001000>; /* Registers */
281 dcr-reg = <100 020>; 283 dcr-reg = <0x100 0x020>;
282 sdr-base = <300>; 284 sdr-base = <0x300>;
283 285
284 /* Outbound ranges, one memory and one IO, 286 /* Outbound ranges, one memory and one IO,
285 * later cannot be changed 287 * later cannot be changed
286 */ 288 */
287 ranges = <02000000 0 80000000 0000000e 00000000 0 80000000 289 ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000
288 01000000 0 00000000 0000000f 80000000 0 00010000>; 290 0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>;
289 291
290 /* Inbound 2GB range starting at 0 */ 292 /* Inbound 2GB range starting at 0 */
291 dma-ranges = <42000000 0 0 0 0 0 80000000>; 293 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
292 294
293 /* This drives busses 10 to 0x1f */ 295 /* This drives busses 10 to 0x1f */
294 bus-range = <10 1f>; 296 bus-range = <0x10 0x1f>;
295 297
296 /* Legacy interrupts (note the weird polarity, the bridge seems 298 /* Legacy interrupts (note the weird polarity, the bridge seems
297 * to invert PCIe legacy interrupts). 299 * to invert PCIe legacy interrupts).
@@ -301,12 +303,12 @@
301 * below are basically de-swizzled numbers. 303 * below are basically de-swizzled numbers.
302 * The real slot is on idsel 0, so the swizzling is 1:1 304 * The real slot is on idsel 0, so the swizzling is 1:1
303 */ 305 */
304 interrupt-map-mask = <0000 0 0 7>; 306 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
305 interrupt-map = < 307 interrupt-map = <
306 0000 0 0 1 &UIC3 0 4 /* swizzled int A */ 308 0x0 0x0 0x0 0x1 &UIC3 0x0 0x4 /* swizzled int A */
307 0000 0 0 2 &UIC3 1 4 /* swizzled int B */ 309 0x0 0x0 0x0 0x2 &UIC3 0x1 0x4 /* swizzled int B */
308 0000 0 0 3 &UIC3 2 4 /* swizzled int C */ 310 0x0 0x0 0x0 0x3 &UIC3 0x2 0x4 /* swizzled int C */
309 0000 0 0 4 &UIC3 3 4 /* swizzled int D */>; 311 0x0 0x0 0x0 0x4 &UIC3 0x3 0x4 /* swizzled int D */>;
310 }; 312 };
311 313
312 PCIE1: pciex@d20000000 { 314 PCIE1: pciex@d20000000 {
@@ -316,23 +318,23 @@
316 #address-cells = <3>; 318 #address-cells = <3>;
317 compatible = "ibm,plb-pciex-440spe", "ibm,plb-pciex"; 319 compatible = "ibm,plb-pciex-440spe", "ibm,plb-pciex";
318 primary; 320 primary;
319 port = <1>; /* port number */ 321 port = <0x1>; /* port number */
320 reg = <d 20000000 20000000 /* Config space access */ 322 reg = <0x0000000d 0x20000000 0x20000000 /* Config space access */
321 c 10001000 00001000>; /* Registers */ 323 0x0000000c 0x10001000 0x00001000>; /* Registers */
322 dcr-reg = <120 020>; 324 dcr-reg = <0x120 0x020>;
323 sdr-base = <340>; 325 sdr-base = <0x340>;
324 326
325 /* Outbound ranges, one memory and one IO, 327 /* Outbound ranges, one memory and one IO,
326 * later cannot be changed 328 * later cannot be changed
327 */ 329 */
328 ranges = <02000000 0 80000000 0000000e 80000000 0 80000000 330 ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x80000000 0x00000000 0x80000000
329 01000000 0 00000000 0000000f 80010000 0 00010000>; 331 0x01000000 0x00000000 0x00000000 0x0000000f 0x80010000 0x00000000 0x00010000>;
330 332
331 /* Inbound 2GB range starting at 0 */ 333 /* Inbound 2GB range starting at 0 */
332 dma-ranges = <42000000 0 0 0 0 0 80000000>; 334 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
333 335
334 /* This drives busses 10 to 0x1f */ 336 /* This drives busses 10 to 0x1f */
335 bus-range = <20 2f>; 337 bus-range = <0x20 0x2f>;
336 338
337 /* Legacy interrupts (note the weird polarity, the bridge seems 339 /* Legacy interrupts (note the weird polarity, the bridge seems
338 * to invert PCIe legacy interrupts). 340 * to invert PCIe legacy interrupts).
@@ -342,12 +344,12 @@
342 * below are basically de-swizzled numbers. 344 * below are basically de-swizzled numbers.
343 * The real slot is on idsel 0, so the swizzling is 1:1 345 * The real slot is on idsel 0, so the swizzling is 1:1
344 */ 346 */
345 interrupt-map-mask = <0000 0 0 7>; 347 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
346 interrupt-map = < 348 interrupt-map = <
347 0000 0 0 1 &UIC3 4 4 /* swizzled int A */ 349 0x0 0x0 0x0 0x1 &UIC3 0x4 0x4 /* swizzled int A */
348 0000 0 0 2 &UIC3 5 4 /* swizzled int B */ 350 0x0 0x0 0x0 0x2 &UIC3 0x5 0x4 /* swizzled int B */
349 0000 0 0 3 &UIC3 6 4 /* swizzled int C */ 351 0x0 0x0 0x0 0x3 &UIC3 0x6 0x4 /* swizzled int C */
350 0000 0 0 4 &UIC3 7 4 /* swizzled int D */>; 352 0x0 0x0 0x0 0x4 &UIC3 0x7 0x4 /* swizzled int D */>;
351 }; 353 };
352 354
353 PCIE2: pciex@d40000000 { 355 PCIE2: pciex@d40000000 {
@@ -357,23 +359,23 @@
357 #address-cells = <3>; 359 #address-cells = <3>;
358 compatible = "ibm,plb-pciex-440spe", "ibm,plb-pciex"; 360 compatible = "ibm,plb-pciex-440spe", "ibm,plb-pciex";
359 primary; 361 primary;
360 port = <2>; /* port number */ 362 port = <0x2>; /* port number */
361 reg = <d 40000000 20000000 /* Config space access */ 363 reg = <0x0000000d 0x40000000 0x20000000 /* Config space access */
362 c 10002000 00001000>; /* Registers */ 364 0x0000000c 0x10002000 0x00001000>; /* Registers */
363 dcr-reg = <140 020>; 365 dcr-reg = <0x140 0x020>;
364 sdr-base = <370>; 366 sdr-base = <0x370>;
365 367
366 /* Outbound ranges, one memory and one IO, 368 /* Outbound ranges, one memory and one IO,
367 * later cannot be changed 369 * later cannot be changed
368 */ 370 */
369 ranges = <02000000 0 80000000 0000000f 00000000 0 80000000 371 ranges = <0x02000000 0x00000000 0x80000000 0x0000000f 0x00000000 0x00000000 0x80000000
370 01000000 0 00000000 0000000f 80020000 0 00010000>; 372 0x01000000 0x00000000 0x00000000 0x0000000f 0x80020000 0x00000000 0x00010000>;
371 373
372 /* Inbound 2GB range starting at 0 */ 374 /* Inbound 2GB range starting at 0 */
373 dma-ranges = <42000000 0 0 0 0 0 80000000>; 375 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
374 376
375 /* This drives busses 10 to 0x1f */ 377 /* This drives busses 10 to 0x1f */
376 bus-range = <30 3f>; 378 bus-range = <0x30 0x3f>;
377 379
378 /* Legacy interrupts (note the weird polarity, the bridge seems 380 /* Legacy interrupts (note the weird polarity, the bridge seems
379 * to invert PCIe legacy interrupts). 381 * to invert PCIe legacy interrupts).
@@ -383,12 +385,12 @@
383 * below are basically de-swizzled numbers. 385 * below are basically de-swizzled numbers.
384 * The real slot is on idsel 0, so the swizzling is 1:1 386 * The real slot is on idsel 0, so the swizzling is 1:1
385 */ 387 */
386 interrupt-map-mask = <0000 0 0 7>; 388 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
387 interrupt-map = < 389 interrupt-map = <
388 0000 0 0 1 &UIC3 8 4 /* swizzled int A */ 390 0x0 0x0 0x0 0x1 &UIC3 0x8 0x4 /* swizzled int A */
389 0000 0 0 2 &UIC3 9 4 /* swizzled int B */ 391 0x0 0x0 0x0 0x2 &UIC3 0x9 0x4 /* swizzled int B */
390 0000 0 0 3 &UIC3 a 4 /* swizzled int C */ 392 0x0 0x0 0x0 0x3 &UIC3 0xa 0x4 /* swizzled int C */
391 0000 0 0 4 &UIC3 b 4 /* swizzled int D */>; 393 0x0 0x0 0x0 0x4 &UIC3 0xb 0x4 /* swizzled int D */>;
392 }; 394 };
393 }; 395 };
394 396
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-09 23:43:40 -0500