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Diffstat (limited to 'arch/mips/include/asm/octeon/cvmx-sriox-defs.h')
-rw-r--r--arch/mips/include/asm/octeon/cvmx-sriox-defs.h703
1 files changed, 702 insertions, 1 deletions
diff --git a/arch/mips/include/asm/octeon/cvmx-sriox-defs.h b/arch/mips/include/asm/octeon/cvmx-sriox-defs.h
index 7be7e9ed7465..5140f2d2ad1c 100644
--- a/arch/mips/include/asm/octeon/cvmx-sriox-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-sriox-defs.h
@@ -4,7 +4,7 @@
4 * Contact: support@caviumnetworks.com 4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK 5 * This file is part of the OCTEON SDK
6 * 6 *
7 * Copyright (c) 2003-2011 Cavium Networks 7 * Copyright (c) 2003-2012 Cavium Networks
8 * 8 *
9 * This file is free software; you can redistribute it and/or modify 9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as 10 * it under the terms of the GNU General Public License, Version 2, as
@@ -79,6 +79,7 @@
79union cvmx_sriox_acc_ctrl { 79union cvmx_sriox_acc_ctrl {
80 uint64_t u64; 80 uint64_t u64;
81 struct cvmx_sriox_acc_ctrl_s { 81 struct cvmx_sriox_acc_ctrl_s {
82#ifdef __BIG_ENDIAN_BITFIELD
82 uint64_t reserved_7_63:57; 83 uint64_t reserved_7_63:57;
83 uint64_t deny_adr2:1; 84 uint64_t deny_adr2:1;
84 uint64_t deny_adr1:1; 85 uint64_t deny_adr1:1;
@@ -87,12 +88,29 @@ union cvmx_sriox_acc_ctrl {
87 uint64_t deny_bar2:1; 88 uint64_t deny_bar2:1;
88 uint64_t deny_bar1:1; 89 uint64_t deny_bar1:1;
89 uint64_t deny_bar0:1; 90 uint64_t deny_bar0:1;
91#else
92 uint64_t deny_bar0:1;
93 uint64_t deny_bar1:1;
94 uint64_t deny_bar2:1;
95 uint64_t reserved_3_3:1;
96 uint64_t deny_adr0:1;
97 uint64_t deny_adr1:1;
98 uint64_t deny_adr2:1;
99 uint64_t reserved_7_63:57;
100#endif
90 } s; 101 } s;
91 struct cvmx_sriox_acc_ctrl_cn63xx { 102 struct cvmx_sriox_acc_ctrl_cn63xx {
103#ifdef __BIG_ENDIAN_BITFIELD
92 uint64_t reserved_3_63:61; 104 uint64_t reserved_3_63:61;
93 uint64_t deny_bar2:1; 105 uint64_t deny_bar2:1;
94 uint64_t deny_bar1:1; 106 uint64_t deny_bar1:1;
95 uint64_t deny_bar0:1; 107 uint64_t deny_bar0:1;
108#else
109 uint64_t deny_bar0:1;
110 uint64_t deny_bar1:1;
111 uint64_t deny_bar2:1;
112 uint64_t reserved_3_63:61;
113#endif
96 } cn63xx; 114 } cn63xx;
97 struct cvmx_sriox_acc_ctrl_cn63xx cn63xxp1; 115 struct cvmx_sriox_acc_ctrl_cn63xx cn63xxp1;
98 struct cvmx_sriox_acc_ctrl_s cn66xx; 116 struct cvmx_sriox_acc_ctrl_s cn66xx;
@@ -101,9 +119,15 @@ union cvmx_sriox_acc_ctrl {
101union cvmx_sriox_asmbly_id { 119union cvmx_sriox_asmbly_id {
102 uint64_t u64; 120 uint64_t u64;
103 struct cvmx_sriox_asmbly_id_s { 121 struct cvmx_sriox_asmbly_id_s {
122#ifdef __BIG_ENDIAN_BITFIELD
104 uint64_t reserved_32_63:32; 123 uint64_t reserved_32_63:32;
105 uint64_t assy_id:16; 124 uint64_t assy_id:16;
106 uint64_t assy_ven:16; 125 uint64_t assy_ven:16;
126#else
127 uint64_t assy_ven:16;
128 uint64_t assy_id:16;
129 uint64_t reserved_32_63:32;
130#endif
107 } s; 131 } s;
108 struct cvmx_sriox_asmbly_id_s cn63xx; 132 struct cvmx_sriox_asmbly_id_s cn63xx;
109 struct cvmx_sriox_asmbly_id_s cn63xxp1; 133 struct cvmx_sriox_asmbly_id_s cn63xxp1;
@@ -113,9 +137,15 @@ union cvmx_sriox_asmbly_id {
113union cvmx_sriox_asmbly_info { 137union cvmx_sriox_asmbly_info {
114 uint64_t u64; 138 uint64_t u64;
115 struct cvmx_sriox_asmbly_info_s { 139 struct cvmx_sriox_asmbly_info_s {
140#ifdef __BIG_ENDIAN_BITFIELD
116 uint64_t reserved_32_63:32; 141 uint64_t reserved_32_63:32;
117 uint64_t assy_rev:16; 142 uint64_t assy_rev:16;
118 uint64_t reserved_0_15:16; 143 uint64_t reserved_0_15:16;
144#else
145 uint64_t reserved_0_15:16;
146 uint64_t assy_rev:16;
147 uint64_t reserved_32_63:32;
148#endif
119 } s; 149 } s;
120 struct cvmx_sriox_asmbly_info_s cn63xx; 150 struct cvmx_sriox_asmbly_info_s cn63xx;
121 struct cvmx_sriox_asmbly_info_s cn63xxp1; 151 struct cvmx_sriox_asmbly_info_s cn63xxp1;
@@ -125,11 +155,19 @@ union cvmx_sriox_asmbly_info {
125union cvmx_sriox_bell_resp_ctrl { 155union cvmx_sriox_bell_resp_ctrl {
126 uint64_t u64; 156 uint64_t u64;
127 struct cvmx_sriox_bell_resp_ctrl_s { 157 struct cvmx_sriox_bell_resp_ctrl_s {
158#ifdef __BIG_ENDIAN_BITFIELD
128 uint64_t reserved_6_63:58; 159 uint64_t reserved_6_63:58;
129 uint64_t rp1_sid:1; 160 uint64_t rp1_sid:1;
130 uint64_t rp0_sid:2; 161 uint64_t rp0_sid:2;
131 uint64_t rp1_pid:1; 162 uint64_t rp1_pid:1;
132 uint64_t rp0_pid:2; 163 uint64_t rp0_pid:2;
164#else
165 uint64_t rp0_pid:2;
166 uint64_t rp1_pid:1;
167 uint64_t rp0_sid:2;
168 uint64_t rp1_sid:1;
169 uint64_t reserved_6_63:58;
170#endif
133 } s; 171 } s;
134 struct cvmx_sriox_bell_resp_ctrl_s cn63xx; 172 struct cvmx_sriox_bell_resp_ctrl_s cn63xx;
135 struct cvmx_sriox_bell_resp_ctrl_s cn63xxp1; 173 struct cvmx_sriox_bell_resp_ctrl_s cn63xxp1;
@@ -139,6 +177,7 @@ union cvmx_sriox_bell_resp_ctrl {
139union cvmx_sriox_bist_status { 177union cvmx_sriox_bist_status {
140 uint64_t u64; 178 uint64_t u64;
141 struct cvmx_sriox_bist_status_s { 179 struct cvmx_sriox_bist_status_s {
180#ifdef __BIG_ENDIAN_BITFIELD
142 uint64_t reserved_45_63:19; 181 uint64_t reserved_45_63:19;
143 uint64_t lram:1; 182 uint64_t lram:1;
144 uint64_t mram:2; 183 uint64_t mram:2;
@@ -159,8 +198,31 @@ union cvmx_sriox_bist_status {
159 uint64_t rxbuf:2; 198 uint64_t rxbuf:2;
160 uint64_t imsg:5; 199 uint64_t imsg:5;
161 uint64_t omsg:7; 200 uint64_t omsg:7;
201#else
202 uint64_t omsg:7;
203 uint64_t imsg:5;
204 uint64_t rxbuf:2;
205 uint64_t txbuf:2;
206 uint64_t ospf:1;
207 uint64_t ispf:1;
208 uint64_t oarb:2;
209 uint64_t rxbuf2:2;
210 uint64_t oarb2:2;
211 uint64_t optrs:4;
212 uint64_t obulk:4;
213 uint64_t rtn:2;
214 uint64_t ofree:1;
215 uint64_t itag:1;
216 uint64_t otag:2;
217 uint64_t bell:2;
218 uint64_t cram:2;
219 uint64_t mram:2;
220 uint64_t lram:1;
221 uint64_t reserved_45_63:19;
222#endif
162 } s; 223 } s;
163 struct cvmx_sriox_bist_status_cn63xx { 224 struct cvmx_sriox_bist_status_cn63xx {
225#ifdef __BIG_ENDIAN_BITFIELD
164 uint64_t reserved_44_63:20; 226 uint64_t reserved_44_63:20;
165 uint64_t mram:2; 227 uint64_t mram:2;
166 uint64_t cram:2; 228 uint64_t cram:2;
@@ -180,8 +242,30 @@ union cvmx_sriox_bist_status {
180 uint64_t rxbuf:2; 242 uint64_t rxbuf:2;
181 uint64_t imsg:5; 243 uint64_t imsg:5;
182 uint64_t omsg:7; 244 uint64_t omsg:7;
245#else
246 uint64_t omsg:7;
247 uint64_t imsg:5;
248 uint64_t rxbuf:2;
249 uint64_t txbuf:2;
250 uint64_t ospf:1;
251 uint64_t ispf:1;
252 uint64_t oarb:2;
253 uint64_t rxbuf2:2;
254 uint64_t oarb2:2;
255 uint64_t optrs:4;
256 uint64_t obulk:4;
257 uint64_t rtn:2;
258 uint64_t ofree:1;
259 uint64_t itag:1;
260 uint64_t otag:2;
261 uint64_t bell:2;
262 uint64_t cram:2;
263 uint64_t mram:2;
264 uint64_t reserved_44_63:20;
265#endif
183 } cn63xx; 266 } cn63xx;
184 struct cvmx_sriox_bist_status_cn63xxp1 { 267 struct cvmx_sriox_bist_status_cn63xxp1 {
268#ifdef __BIG_ENDIAN_BITFIELD
185 uint64_t reserved_44_63:20; 269 uint64_t reserved_44_63:20;
186 uint64_t mram:2; 270 uint64_t mram:2;
187 uint64_t cram:2; 271 uint64_t cram:2;
@@ -200,6 +284,26 @@ union cvmx_sriox_bist_status {
200 uint64_t rxbuf:2; 284 uint64_t rxbuf:2;
201 uint64_t imsg:5; 285 uint64_t imsg:5;
202 uint64_t omsg:7; 286 uint64_t omsg:7;
287#else
288 uint64_t omsg:7;
289 uint64_t imsg:5;
290 uint64_t rxbuf:2;
291 uint64_t txbuf:2;
292 uint64_t ospf:1;
293 uint64_t ispf:1;
294 uint64_t oarb:2;
295 uint64_t reserved_20_23:4;
296 uint64_t optrs:4;
297 uint64_t obulk:4;
298 uint64_t rtn:2;
299 uint64_t ofree:1;
300 uint64_t itag:1;
301 uint64_t otag:2;
302 uint64_t bell:2;
303 uint64_t cram:2;
304 uint64_t mram:2;
305 uint64_t reserved_44_63:20;
306#endif
203 } cn63xxp1; 307 } cn63xxp1;
204 struct cvmx_sriox_bist_status_s cn66xx; 308 struct cvmx_sriox_bist_status_s cn66xx;
205}; 309};
@@ -207,6 +311,7 @@ union cvmx_sriox_bist_status {
207union cvmx_sriox_imsg_ctrl { 311union cvmx_sriox_imsg_ctrl {
208 uint64_t u64; 312 uint64_t u64;
209 struct cvmx_sriox_imsg_ctrl_s { 313 struct cvmx_sriox_imsg_ctrl_s {
314#ifdef __BIG_ENDIAN_BITFIELD
210 uint64_t reserved_32_63:32; 315 uint64_t reserved_32_63:32;
211 uint64_t to_mode:1; 316 uint64_t to_mode:1;
212 uint64_t reserved_30_30:1; 317 uint64_t reserved_30_30:1;
@@ -221,6 +326,22 @@ union cvmx_sriox_imsg_ctrl {
221 uint64_t lttr:4; 326 uint64_t lttr:4;
222 uint64_t prio:4; 327 uint64_t prio:4;
223 uint64_t mbox:4; 328 uint64_t mbox:4;
329#else
330 uint64_t mbox:4;
331 uint64_t prio:4;
332 uint64_t lttr:4;
333 uint64_t prt_sel:3;
334 uint64_t reserved_15_15:1;
335 uint64_t rp0_pid:2;
336 uint64_t rp1_pid:1;
337 uint64_t rp0_sid:2;
338 uint64_t rp1_sid:1;
339 uint64_t reserved_22_23:2;
340 uint64_t rsp_thr:6;
341 uint64_t reserved_30_30:1;
342 uint64_t to_mode:1;
343 uint64_t reserved_32_63:32;
344#endif
224 } s; 345 } s;
225 struct cvmx_sriox_imsg_ctrl_s cn63xx; 346 struct cvmx_sriox_imsg_ctrl_s cn63xx;
226 struct cvmx_sriox_imsg_ctrl_s cn63xxp1; 347 struct cvmx_sriox_imsg_ctrl_s cn63xxp1;
@@ -230,6 +351,7 @@ union cvmx_sriox_imsg_ctrl {
230union cvmx_sriox_imsg_inst_hdrx { 351union cvmx_sriox_imsg_inst_hdrx {
231 uint64_t u64; 352 uint64_t u64;
232 struct cvmx_sriox_imsg_inst_hdrx_s { 353 struct cvmx_sriox_imsg_inst_hdrx_s {
354#ifdef __BIG_ENDIAN_BITFIELD
233 uint64_t r:1; 355 uint64_t r:1;
234 uint64_t reserved_58_62:5; 356 uint64_t reserved_58_62:5;
235 uint64_t pm:2; 357 uint64_t pm:2;
@@ -244,6 +366,22 @@ union cvmx_sriox_imsg_inst_hdrx {
244 uint64_t rs:1; 366 uint64_t rs:1;
245 uint64_t tt:2; 367 uint64_t tt:2;
246 uint64_t tag:32; 368 uint64_t tag:32;
369#else
370 uint64_t tag:32;
371 uint64_t tt:2;
372 uint64_t rs:1;
373 uint64_t reserved_35_41:7;
374 uint64_t ntag:1;
375 uint64_t ntt:1;
376 uint64_t ngrp:1;
377 uint64_t nqos:1;
378 uint64_t reserved_46_47:2;
379 uint64_t sl:7;
380 uint64_t reserved_55_55:1;
381 uint64_t pm:2;
382 uint64_t reserved_58_62:5;
383 uint64_t r:1;
384#endif
247 } s; 385 } s;
248 struct cvmx_sriox_imsg_inst_hdrx_s cn63xx; 386 struct cvmx_sriox_imsg_inst_hdrx_s cn63xx;
249 struct cvmx_sriox_imsg_inst_hdrx_s cn63xxp1; 387 struct cvmx_sriox_imsg_inst_hdrx_s cn63xxp1;
@@ -253,6 +391,7 @@ union cvmx_sriox_imsg_inst_hdrx {
253union cvmx_sriox_imsg_qos_grpx { 391union cvmx_sriox_imsg_qos_grpx {
254 uint64_t u64; 392 uint64_t u64;
255 struct cvmx_sriox_imsg_qos_grpx_s { 393 struct cvmx_sriox_imsg_qos_grpx_s {
394#ifdef __BIG_ENDIAN_BITFIELD
256 uint64_t reserved_63_63:1; 395 uint64_t reserved_63_63:1;
257 uint64_t qos7:3; 396 uint64_t qos7:3;
258 uint64_t grp7:4; 397 uint64_t grp7:4;
@@ -277,6 +416,32 @@ union cvmx_sriox_imsg_qos_grpx {
277 uint64_t reserved_7_7:1; 416 uint64_t reserved_7_7:1;
278 uint64_t qos0:3; 417 uint64_t qos0:3;
279 uint64_t grp0:4; 418 uint64_t grp0:4;
419#else
420 uint64_t grp0:4;
421 uint64_t qos0:3;
422 uint64_t reserved_7_7:1;
423 uint64_t grp1:4;
424 uint64_t qos1:3;
425 uint64_t reserved_15_15:1;
426 uint64_t grp2:4;
427 uint64_t qos2:3;
428 uint64_t reserved_23_23:1;
429 uint64_t grp3:4;
430 uint64_t qos3:3;
431 uint64_t reserved_31_31:1;
432 uint64_t grp4:4;
433 uint64_t qos4:3;
434 uint64_t reserved_39_39:1;
435 uint64_t grp5:4;
436 uint64_t qos5:3;
437 uint64_t reserved_47_47:1;
438 uint64_t grp6:4;
439 uint64_t qos6:3;
440 uint64_t reserved_55_55:1;
441 uint64_t grp7:4;
442 uint64_t qos7:3;
443 uint64_t reserved_63_63:1;
444#endif
280 } s; 445 } s;
281 struct cvmx_sriox_imsg_qos_grpx_s cn63xx; 446 struct cvmx_sriox_imsg_qos_grpx_s cn63xx;
282 struct cvmx_sriox_imsg_qos_grpx_s cn63xxp1; 447 struct cvmx_sriox_imsg_qos_grpx_s cn63xxp1;
@@ -286,6 +451,7 @@ union cvmx_sriox_imsg_qos_grpx {
286union cvmx_sriox_imsg_statusx { 451union cvmx_sriox_imsg_statusx {
287 uint64_t u64; 452 uint64_t u64;
288 struct cvmx_sriox_imsg_statusx_s { 453 struct cvmx_sriox_imsg_statusx_s {
454#ifdef __BIG_ENDIAN_BITFIELD
289 uint64_t val1:1; 455 uint64_t val1:1;
290 uint64_t err1:1; 456 uint64_t err1:1;
291 uint64_t toe1:1; 457 uint64_t toe1:1;
@@ -310,6 +476,32 @@ union cvmx_sriox_imsg_statusx {
310 uint64_t mbox0:2; 476 uint64_t mbox0:2;
311 uint64_t lttr0:2; 477 uint64_t lttr0:2;
312 uint64_t sid0:16; 478 uint64_t sid0:16;
479#else
480 uint64_t sid0:16;
481 uint64_t lttr0:2;
482 uint64_t mbox0:2;
483 uint64_t seg0:4;
484 uint64_t dis0:1;
485 uint64_t tt0:1;
486 uint64_t reserved_26_26:1;
487 uint64_t prt0:1;
488 uint64_t toc0:1;
489 uint64_t toe0:1;
490 uint64_t err0:1;
491 uint64_t val0:1;
492 uint64_t sid1:16;
493 uint64_t lttr1:2;
494 uint64_t mbox1:2;
495 uint64_t seg1:4;
496 uint64_t dis1:1;
497 uint64_t tt1:1;
498 uint64_t reserved_58_58:1;
499 uint64_t prt1:1;
500 uint64_t toc1:1;
501 uint64_t toe1:1;
502 uint64_t err1:1;
503 uint64_t val1:1;
504#endif
313 } s; 505 } s;
314 struct cvmx_sriox_imsg_statusx_s cn63xx; 506 struct cvmx_sriox_imsg_statusx_s cn63xx;
315 struct cvmx_sriox_imsg_statusx_s cn63xxp1; 507 struct cvmx_sriox_imsg_statusx_s cn63xxp1;
@@ -319,6 +511,7 @@ union cvmx_sriox_imsg_statusx {
319union cvmx_sriox_imsg_vport_thr { 511union cvmx_sriox_imsg_vport_thr {
320 uint64_t u64; 512 uint64_t u64;
321 struct cvmx_sriox_imsg_vport_thr_s { 513 struct cvmx_sriox_imsg_vport_thr_s {
514#ifdef __BIG_ENDIAN_BITFIELD
322 uint64_t reserved_54_63:10; 515 uint64_t reserved_54_63:10;
323 uint64_t max_tot:6; 516 uint64_t max_tot:6;
324 uint64_t reserved_46_47:2; 517 uint64_t reserved_46_47:2;
@@ -332,6 +525,21 @@ union cvmx_sriox_imsg_vport_thr {
332 uint64_t max_p1:6; 525 uint64_t max_p1:6;
333 uint64_t reserved_6_7:2; 526 uint64_t reserved_6_7:2;
334 uint64_t max_p0:6; 527 uint64_t max_p0:6;
528#else
529 uint64_t max_p0:6;
530 uint64_t reserved_6_7:2;
531 uint64_t max_p1:6;
532 uint64_t reserved_14_15:2;
533 uint64_t buf_thr:4;
534 uint64_t reserved_20_30:11;
535 uint64_t sp_vport:1;
536 uint64_t max_s0:6;
537 uint64_t reserved_38_39:2;
538 uint64_t max_s1:6;
539 uint64_t reserved_46_47:2;
540 uint64_t max_tot:6;
541 uint64_t reserved_54_63:10;
542#endif
335 } s; 543 } s;
336 struct cvmx_sriox_imsg_vport_thr_s cn63xx; 544 struct cvmx_sriox_imsg_vport_thr_s cn63xx;
337 struct cvmx_sriox_imsg_vport_thr_s cn63xxp1; 545 struct cvmx_sriox_imsg_vport_thr_s cn63xxp1;
@@ -341,11 +549,19 @@ union cvmx_sriox_imsg_vport_thr {
341union cvmx_sriox_imsg_vport_thr2 { 549union cvmx_sriox_imsg_vport_thr2 {
342 uint64_t u64; 550 uint64_t u64;
343 struct cvmx_sriox_imsg_vport_thr2_s { 551 struct cvmx_sriox_imsg_vport_thr2_s {
552#ifdef __BIG_ENDIAN_BITFIELD
344 uint64_t reserved_46_63:18; 553 uint64_t reserved_46_63:18;
345 uint64_t max_s3:6; 554 uint64_t max_s3:6;
346 uint64_t reserved_38_39:2; 555 uint64_t reserved_38_39:2;
347 uint64_t max_s2:6; 556 uint64_t max_s2:6;
348 uint64_t reserved_0_31:32; 557 uint64_t reserved_0_31:32;
558#else
559 uint64_t reserved_0_31:32;
560 uint64_t max_s2:6;
561 uint64_t reserved_38_39:2;
562 uint64_t max_s3:6;
563 uint64_t reserved_46_63:18;
564#endif
349 } s; 565 } s;
350 struct cvmx_sriox_imsg_vport_thr2_s cn66xx; 566 struct cvmx_sriox_imsg_vport_thr2_s cn66xx;
351}; 567};
@@ -353,8 +569,13 @@ union cvmx_sriox_imsg_vport_thr2 {
353union cvmx_sriox_int2_enable { 569union cvmx_sriox_int2_enable {
354 uint64_t u64; 570 uint64_t u64;
355 struct cvmx_sriox_int2_enable_s { 571 struct cvmx_sriox_int2_enable_s {
572#ifdef __BIG_ENDIAN_BITFIELD
356 uint64_t reserved_1_63:63; 573 uint64_t reserved_1_63:63;
357 uint64_t pko_rst:1; 574 uint64_t pko_rst:1;
575#else
576 uint64_t pko_rst:1;
577 uint64_t reserved_1_63:63;
578#endif
358 } s; 579 } s;
359 struct cvmx_sriox_int2_enable_s cn63xx; 580 struct cvmx_sriox_int2_enable_s cn63xx;
360 struct cvmx_sriox_int2_enable_s cn66xx; 581 struct cvmx_sriox_int2_enable_s cn66xx;
@@ -363,10 +584,17 @@ union cvmx_sriox_int2_enable {
363union cvmx_sriox_int2_reg { 584union cvmx_sriox_int2_reg {
364 uint64_t u64; 585 uint64_t u64;
365 struct cvmx_sriox_int2_reg_s { 586 struct cvmx_sriox_int2_reg_s {
587#ifdef __BIG_ENDIAN_BITFIELD
366 uint64_t reserved_32_63:32; 588 uint64_t reserved_32_63:32;
367 uint64_t int_sum:1; 589 uint64_t int_sum:1;
368 uint64_t reserved_1_30:30; 590 uint64_t reserved_1_30:30;
369 uint64_t pko_rst:1; 591 uint64_t pko_rst:1;
592#else
593 uint64_t pko_rst:1;
594 uint64_t reserved_1_30:30;
595 uint64_t int_sum:1;
596 uint64_t reserved_32_63:32;
597#endif
370 } s; 598 } s;
371 struct cvmx_sriox_int2_reg_s cn63xx; 599 struct cvmx_sriox_int2_reg_s cn63xx;
372 struct cvmx_sriox_int2_reg_s cn66xx; 600 struct cvmx_sriox_int2_reg_s cn66xx;
@@ -375,6 +603,7 @@ union cvmx_sriox_int2_reg {
375union cvmx_sriox_int_enable { 603union cvmx_sriox_int_enable {
376 uint64_t u64; 604 uint64_t u64;
377 struct cvmx_sriox_int_enable_s { 605 struct cvmx_sriox_int_enable_s {
606#ifdef __BIG_ENDIAN_BITFIELD
378 uint64_t reserved_27_63:37; 607 uint64_t reserved_27_63:37;
379 uint64_t zero_pkt:1; 608 uint64_t zero_pkt:1;
380 uint64_t ttl_tout:1; 609 uint64_t ttl_tout:1;
@@ -403,9 +632,40 @@ union cvmx_sriox_int_enable {
403 uint64_t rxbell:1; 632 uint64_t rxbell:1;
404 uint64_t bell_err:1; 633 uint64_t bell_err:1;
405 uint64_t txbell:1; 634 uint64_t txbell:1;
635#else
636 uint64_t txbell:1;
637 uint64_t bell_err:1;
638 uint64_t rxbell:1;
639 uint64_t maint_op:1;
640 uint64_t bar_err:1;
641 uint64_t deny_wr:1;
642 uint64_t sli_err:1;
643 uint64_t wr_done:1;
644 uint64_t mce_tx:1;
645 uint64_t mce_rx:1;
646 uint64_t soft_tx:1;
647 uint64_t soft_rx:1;
648 uint64_t log_erb:1;
649 uint64_t phy_erb:1;
650 uint64_t link_dwn:1;
651 uint64_t link_up:1;
652 uint64_t omsg0:1;
653 uint64_t omsg1:1;
654 uint64_t omsg_err:1;
655 uint64_t pko_err:1;
656 uint64_t rtry_err:1;
657 uint64_t f_error:1;
658 uint64_t mac_buf:1;
659 uint64_t degrade:1;
660 uint64_t fail:1;
661 uint64_t ttl_tout:1;
662 uint64_t zero_pkt:1;
663 uint64_t reserved_27_63:37;
664#endif
406 } s; 665 } s;
407 struct cvmx_sriox_int_enable_s cn63xx; 666 struct cvmx_sriox_int_enable_s cn63xx;
408 struct cvmx_sriox_int_enable_cn63xxp1 { 667 struct cvmx_sriox_int_enable_cn63xxp1 {
668#ifdef __BIG_ENDIAN_BITFIELD
409 uint64_t reserved_22_63:42; 669 uint64_t reserved_22_63:42;
410 uint64_t f_error:1; 670 uint64_t f_error:1;
411 uint64_t rtry_err:1; 671 uint64_t rtry_err:1;
@@ -429,6 +689,31 @@ union cvmx_sriox_int_enable {
429 uint64_t rxbell:1; 689 uint64_t rxbell:1;
430 uint64_t bell_err:1; 690 uint64_t bell_err:1;
431 uint64_t txbell:1; 691 uint64_t txbell:1;
692#else
693 uint64_t txbell:1;
694 uint64_t bell_err:1;
695 uint64_t rxbell:1;
696 uint64_t maint_op:1;
697 uint64_t bar_err:1;
698 uint64_t deny_wr:1;
699 uint64_t sli_err:1;
700 uint64_t wr_done:1;
701 uint64_t mce_tx:1;
702 uint64_t mce_rx:1;
703 uint64_t soft_tx:1;
704 uint64_t soft_rx:1;
705 uint64_t log_erb:1;
706 uint64_t phy_erb:1;
707 uint64_t link_dwn:1;
708 uint64_t link_up:1;
709 uint64_t omsg0:1;
710 uint64_t omsg1:1;
711 uint64_t omsg_err:1;
712 uint64_t pko_err:1;
713 uint64_t rtry_err:1;
714 uint64_t f_error:1;
715 uint64_t reserved_22_63:42;
716#endif
432 } cn63xxp1; 717 } cn63xxp1;
433 struct cvmx_sriox_int_enable_s cn66xx; 718 struct cvmx_sriox_int_enable_s cn66xx;
434}; 719};
@@ -436,6 +721,7 @@ union cvmx_sriox_int_enable {
436union cvmx_sriox_int_info0 { 721union cvmx_sriox_int_info0 {
437 uint64_t u64; 722 uint64_t u64;
438 struct cvmx_sriox_int_info0_s { 723 struct cvmx_sriox_int_info0_s {
724#ifdef __BIG_ENDIAN_BITFIELD
439 uint64_t cmd:4; 725 uint64_t cmd:4;
440 uint64_t type:4; 726 uint64_t type:4;
441 uint64_t tag:8; 727 uint64_t tag:8;
@@ -445,6 +731,17 @@ union cvmx_sriox_int_info0 {
445 uint64_t reserved_16_28:13; 731 uint64_t reserved_16_28:13;
446 uint64_t be0:8; 732 uint64_t be0:8;
447 uint64_t be1:8; 733 uint64_t be1:8;
734#else
735 uint64_t be1:8;
736 uint64_t be0:8;
737 uint64_t reserved_16_28:13;
738 uint64_t status:3;
739 uint64_t length:10;
740 uint64_t reserved_42_47:6;
741 uint64_t tag:8;
742 uint64_t type:4;
743 uint64_t cmd:4;
744#endif
448 } s; 745 } s;
449 struct cvmx_sriox_int_info0_s cn63xx; 746 struct cvmx_sriox_int_info0_s cn63xx;
450 struct cvmx_sriox_int_info0_s cn63xxp1; 747 struct cvmx_sriox_int_info0_s cn63xxp1;
@@ -454,7 +751,11 @@ union cvmx_sriox_int_info0 {
454union cvmx_sriox_int_info1 { 751union cvmx_sriox_int_info1 {
455 uint64_t u64; 752 uint64_t u64;
456 struct cvmx_sriox_int_info1_s { 753 struct cvmx_sriox_int_info1_s {
754#ifdef __BIG_ENDIAN_BITFIELD
457 uint64_t info1:64; 755 uint64_t info1:64;
756#else
757 uint64_t info1:64;
758#endif
458 } s; 759 } s;
459 struct cvmx_sriox_int_info1_s cn63xx; 760 struct cvmx_sriox_int_info1_s cn63xx;
460 struct cvmx_sriox_int_info1_s cn63xxp1; 761 struct cvmx_sriox_int_info1_s cn63xxp1;
@@ -464,6 +765,7 @@ union cvmx_sriox_int_info1 {
464union cvmx_sriox_int_info2 { 765union cvmx_sriox_int_info2 {
465 uint64_t u64; 766 uint64_t u64;
466 struct cvmx_sriox_int_info2_s { 767 struct cvmx_sriox_int_info2_s {
768#ifdef __BIG_ENDIAN_BITFIELD
467 uint64_t prio:2; 769 uint64_t prio:2;
468 uint64_t tt:1; 770 uint64_t tt:1;
469 uint64_t sis:1; 771 uint64_t sis:1;
@@ -475,6 +777,19 @@ union cvmx_sriox_int_info2 {
475 uint64_t rsrvd:30; 777 uint64_t rsrvd:30;
476 uint64_t lns:1; 778 uint64_t lns:1;
477 uint64_t intr:1; 779 uint64_t intr:1;
780#else
781 uint64_t intr:1;
782 uint64_t lns:1;
783 uint64_t rsrvd:30;
784 uint64_t letter:2;
785 uint64_t mbox:2;
786 uint64_t xmbox:4;
787 uint64_t did:16;
788 uint64_t ssize:4;
789 uint64_t sis:1;
790 uint64_t tt:1;
791 uint64_t prio:2;
792#endif
478 } s; 793 } s;
479 struct cvmx_sriox_int_info2_s cn63xx; 794 struct cvmx_sriox_int_info2_s cn63xx;
480 struct cvmx_sriox_int_info2_s cn63xxp1; 795 struct cvmx_sriox_int_info2_s cn63xxp1;
@@ -484,11 +799,19 @@ union cvmx_sriox_int_info2 {
484union cvmx_sriox_int_info3 { 799union cvmx_sriox_int_info3 {
485 uint64_t u64; 800 uint64_t u64;
486 struct cvmx_sriox_int_info3_s { 801 struct cvmx_sriox_int_info3_s {
802#ifdef __BIG_ENDIAN_BITFIELD
487 uint64_t prio:2; 803 uint64_t prio:2;
488 uint64_t tt:2; 804 uint64_t tt:2;
489 uint64_t type:4; 805 uint64_t type:4;
490 uint64_t other:48; 806 uint64_t other:48;
491 uint64_t reserved_0_7:8; 807 uint64_t reserved_0_7:8;
808#else
809 uint64_t reserved_0_7:8;
810 uint64_t other:48;
811 uint64_t type:4;
812 uint64_t tt:2;
813 uint64_t prio:2;
814#endif
492 } s; 815 } s;
493 struct cvmx_sriox_int_info3_s cn63xx; 816 struct cvmx_sriox_int_info3_s cn63xx;
494 struct cvmx_sriox_int_info3_s cn63xxp1; 817 struct cvmx_sriox_int_info3_s cn63xxp1;
@@ -498,6 +821,7 @@ union cvmx_sriox_int_info3 {
498union cvmx_sriox_int_reg { 821union cvmx_sriox_int_reg {
499 uint64_t u64; 822 uint64_t u64;
500 struct cvmx_sriox_int_reg_s { 823 struct cvmx_sriox_int_reg_s {
824#ifdef __BIG_ENDIAN_BITFIELD
501 uint64_t reserved_32_63:32; 825 uint64_t reserved_32_63:32;
502 uint64_t int2_sum:1; 826 uint64_t int2_sum:1;
503 uint64_t reserved_27_30:4; 827 uint64_t reserved_27_30:4;
@@ -528,9 +852,42 @@ union cvmx_sriox_int_reg {
528 uint64_t rxbell:1; 852 uint64_t rxbell:1;
529 uint64_t bell_err:1; 853 uint64_t bell_err:1;
530 uint64_t txbell:1; 854 uint64_t txbell:1;
855#else
856 uint64_t txbell:1;
857 uint64_t bell_err:1;
858 uint64_t rxbell:1;
859 uint64_t maint_op:1;
860 uint64_t bar_err:1;
861 uint64_t deny_wr:1;
862 uint64_t sli_err:1;
863 uint64_t wr_done:1;
864 uint64_t mce_tx:1;
865 uint64_t mce_rx:1;
866 uint64_t soft_tx:1;
867 uint64_t soft_rx:1;
868 uint64_t log_erb:1;
869 uint64_t phy_erb:1;
870 uint64_t link_dwn:1;
871 uint64_t link_up:1;
872 uint64_t omsg0:1;
873 uint64_t omsg1:1;
874 uint64_t omsg_err:1;
875 uint64_t pko_err:1;
876 uint64_t rtry_err:1;
877 uint64_t f_error:1;
878 uint64_t mac_buf:1;
879 uint64_t degrad:1;
880 uint64_t fail:1;
881 uint64_t ttl_tout:1;
882 uint64_t zero_pkt:1;
883 uint64_t reserved_27_30:4;
884 uint64_t int2_sum:1;
885 uint64_t reserved_32_63:32;
886#endif
531 } s; 887 } s;
532 struct cvmx_sriox_int_reg_s cn63xx; 888 struct cvmx_sriox_int_reg_s cn63xx;
533 struct cvmx_sriox_int_reg_cn63xxp1 { 889 struct cvmx_sriox_int_reg_cn63xxp1 {
890#ifdef __BIG_ENDIAN_BITFIELD
534 uint64_t reserved_22_63:42; 891 uint64_t reserved_22_63:42;
535 uint64_t f_error:1; 892 uint64_t f_error:1;
536 uint64_t rtry_err:1; 893 uint64_t rtry_err:1;
@@ -554,6 +911,31 @@ union cvmx_sriox_int_reg {
554 uint64_t rxbell:1; 911 uint64_t rxbell:1;
555 uint64_t bell_err:1; 912 uint64_t bell_err:1;
556 uint64_t txbell:1; 913 uint64_t txbell:1;
914#else
915 uint64_t txbell:1;
916 uint64_t bell_err:1;
917 uint64_t rxbell:1;
918 uint64_t maint_op:1;
919 uint64_t bar_err:1;
920 uint64_t deny_wr:1;
921 uint64_t sli_err:1;
922 uint64_t wr_done:1;
923 uint64_t mce_tx:1;
924 uint64_t mce_rx:1;
925 uint64_t soft_tx:1;
926 uint64_t soft_rx:1;
927 uint64_t log_erb:1;
928 uint64_t phy_erb:1;
929 uint64_t link_dwn:1;
930 uint64_t link_up:1;
931 uint64_t omsg0:1;
932 uint64_t omsg1:1;
933 uint64_t omsg_err:1;
934 uint64_t pko_err:1;
935 uint64_t rtry_err:1;
936 uint64_t f_error:1;
937 uint64_t reserved_22_63:42;
938#endif
557 } cn63xxp1; 939 } cn63xxp1;
558 struct cvmx_sriox_int_reg_s cn66xx; 940 struct cvmx_sriox_int_reg_s cn66xx;
559}; 941};
@@ -561,6 +943,7 @@ union cvmx_sriox_int_reg {
561union cvmx_sriox_ip_feature { 943union cvmx_sriox_ip_feature {
562 uint64_t u64; 944 uint64_t u64;
563 struct cvmx_sriox_ip_feature_s { 945 struct cvmx_sriox_ip_feature_s {
946#ifdef __BIG_ENDIAN_BITFIELD
564 uint64_t ops:32; 947 uint64_t ops:32;
565 uint64_t reserved_15_31:17; 948 uint64_t reserved_15_31:17;
566 uint64_t no_vmin:1; 949 uint64_t no_vmin:1;
@@ -571,8 +954,21 @@ union cvmx_sriox_ip_feature {
571 uint64_t pt_width:2; 954 uint64_t pt_width:2;
572 uint64_t tx_pol:4; 955 uint64_t tx_pol:4;
573 uint64_t rx_pol:4; 956 uint64_t rx_pol:4;
957#else
958 uint64_t rx_pol:4;
959 uint64_t tx_pol:4;
960 uint64_t pt_width:2;
961 uint64_t tx_flow:1;
962 uint64_t reserved_11_11:1;
963 uint64_t a50:1;
964 uint64_t a66:1;
965 uint64_t no_vmin:1;
966 uint64_t reserved_15_31:17;
967 uint64_t ops:32;
968#endif
574 } s; 969 } s;
575 struct cvmx_sriox_ip_feature_cn63xx { 970 struct cvmx_sriox_ip_feature_cn63xx {
971#ifdef __BIG_ENDIAN_BITFIELD
576 uint64_t ops:32; 972 uint64_t ops:32;
577 uint64_t reserved_14_31:18; 973 uint64_t reserved_14_31:18;
578 uint64_t a66:1; 974 uint64_t a66:1;
@@ -582,6 +978,17 @@ union cvmx_sriox_ip_feature {
582 uint64_t pt_width:2; 978 uint64_t pt_width:2;
583 uint64_t tx_pol:4; 979 uint64_t tx_pol:4;
584 uint64_t rx_pol:4; 980 uint64_t rx_pol:4;
981#else
982 uint64_t rx_pol:4;
983 uint64_t tx_pol:4;
984 uint64_t pt_width:2;
985 uint64_t tx_flow:1;
986 uint64_t reserved_11_11:1;
987 uint64_t a50:1;
988 uint64_t a66:1;
989 uint64_t reserved_14_31:18;
990 uint64_t ops:32;
991#endif
585 } cn63xx; 992 } cn63xx;
586 struct cvmx_sriox_ip_feature_cn63xx cn63xxp1; 993 struct cvmx_sriox_ip_feature_cn63xx cn63xxp1;
587 struct cvmx_sriox_ip_feature_s cn66xx; 994 struct cvmx_sriox_ip_feature_s cn66xx;
@@ -590,6 +997,7 @@ union cvmx_sriox_ip_feature {
590union cvmx_sriox_mac_buffers { 997union cvmx_sriox_mac_buffers {
591 uint64_t u64; 998 uint64_t u64;
592 struct cvmx_sriox_mac_buffers_s { 999 struct cvmx_sriox_mac_buffers_s {
1000#ifdef __BIG_ENDIAN_BITFIELD
593 uint64_t reserved_56_63:8; 1001 uint64_t reserved_56_63:8;
594 uint64_t tx_enb:8; 1002 uint64_t tx_enb:8;
595 uint64_t reserved_44_47:4; 1003 uint64_t reserved_44_47:4;
@@ -600,6 +1008,18 @@ union cvmx_sriox_mac_buffers {
600 uint64_t reserved_12_15:4; 1008 uint64_t reserved_12_15:4;
601 uint64_t rx_inuse:4; 1009 uint64_t rx_inuse:4;
602 uint64_t rx_stat:8; 1010 uint64_t rx_stat:8;
1011#else
1012 uint64_t rx_stat:8;
1013 uint64_t rx_inuse:4;
1014 uint64_t reserved_12_15:4;
1015 uint64_t rx_enb:8;
1016 uint64_t reserved_24_31:8;
1017 uint64_t tx_stat:8;
1018 uint64_t tx_inuse:4;
1019 uint64_t reserved_44_47:4;
1020 uint64_t tx_enb:8;
1021 uint64_t reserved_56_63:8;
1022#endif
603 } s; 1023 } s;
604 struct cvmx_sriox_mac_buffers_s cn63xx; 1024 struct cvmx_sriox_mac_buffers_s cn63xx;
605 struct cvmx_sriox_mac_buffers_s cn66xx; 1025 struct cvmx_sriox_mac_buffers_s cn66xx;
@@ -608,12 +1028,21 @@ union cvmx_sriox_mac_buffers {
608union cvmx_sriox_maint_op { 1028union cvmx_sriox_maint_op {
609 uint64_t u64; 1029 uint64_t u64;
610 struct cvmx_sriox_maint_op_s { 1030 struct cvmx_sriox_maint_op_s {
1031#ifdef __BIG_ENDIAN_BITFIELD
611 uint64_t wr_data:32; 1032 uint64_t wr_data:32;
612 uint64_t reserved_27_31:5; 1033 uint64_t reserved_27_31:5;
613 uint64_t fail:1; 1034 uint64_t fail:1;
614 uint64_t pending:1; 1035 uint64_t pending:1;
615 uint64_t op:1; 1036 uint64_t op:1;
616 uint64_t addr:24; 1037 uint64_t addr:24;
1038#else
1039 uint64_t addr:24;
1040 uint64_t op:1;
1041 uint64_t pending:1;
1042 uint64_t fail:1;
1043 uint64_t reserved_27_31:5;
1044 uint64_t wr_data:32;
1045#endif
617 } s; 1046 } s;
618 struct cvmx_sriox_maint_op_s cn63xx; 1047 struct cvmx_sriox_maint_op_s cn63xx;
619 struct cvmx_sriox_maint_op_s cn63xxp1; 1048 struct cvmx_sriox_maint_op_s cn63xxp1;
@@ -623,9 +1052,15 @@ union cvmx_sriox_maint_op {
623union cvmx_sriox_maint_rd_data { 1052union cvmx_sriox_maint_rd_data {
624 uint64_t u64; 1053 uint64_t u64;
625 struct cvmx_sriox_maint_rd_data_s { 1054 struct cvmx_sriox_maint_rd_data_s {
1055#ifdef __BIG_ENDIAN_BITFIELD
626 uint64_t reserved_33_63:31; 1056 uint64_t reserved_33_63:31;
627 uint64_t valid:1; 1057 uint64_t valid:1;
628 uint64_t rd_data:32; 1058 uint64_t rd_data:32;
1059#else
1060 uint64_t rd_data:32;
1061 uint64_t valid:1;
1062 uint64_t reserved_33_63:31;
1063#endif
629 } s; 1064 } s;
630 struct cvmx_sriox_maint_rd_data_s cn63xx; 1065 struct cvmx_sriox_maint_rd_data_s cn63xx;
631 struct cvmx_sriox_maint_rd_data_s cn63xxp1; 1066 struct cvmx_sriox_maint_rd_data_s cn63xxp1;
@@ -635,8 +1070,13 @@ union cvmx_sriox_maint_rd_data {
635union cvmx_sriox_mce_tx_ctl { 1070union cvmx_sriox_mce_tx_ctl {
636 uint64_t u64; 1071 uint64_t u64;
637 struct cvmx_sriox_mce_tx_ctl_s { 1072 struct cvmx_sriox_mce_tx_ctl_s {
1073#ifdef __BIG_ENDIAN_BITFIELD
638 uint64_t reserved_1_63:63; 1074 uint64_t reserved_1_63:63;
639 uint64_t mce:1; 1075 uint64_t mce:1;
1076#else
1077 uint64_t mce:1;
1078 uint64_t reserved_1_63:63;
1079#endif
640 } s; 1080 } s;
641 struct cvmx_sriox_mce_tx_ctl_s cn63xx; 1081 struct cvmx_sriox_mce_tx_ctl_s cn63xx;
642 struct cvmx_sriox_mce_tx_ctl_s cn63xxp1; 1082 struct cvmx_sriox_mce_tx_ctl_s cn63xxp1;
@@ -646,6 +1086,7 @@ union cvmx_sriox_mce_tx_ctl {
646union cvmx_sriox_mem_op_ctrl { 1086union cvmx_sriox_mem_op_ctrl {
647 uint64_t u64; 1087 uint64_t u64;
648 struct cvmx_sriox_mem_op_ctrl_s { 1088 struct cvmx_sriox_mem_op_ctrl_s {
1089#ifdef __BIG_ENDIAN_BITFIELD
649 uint64_t reserved_10_63:54; 1090 uint64_t reserved_10_63:54;
650 uint64_t rr_ro:1; 1091 uint64_t rr_ro:1;
651 uint64_t w_ro:1; 1092 uint64_t w_ro:1;
@@ -654,6 +1095,16 @@ union cvmx_sriox_mem_op_ctrl {
654 uint64_t rp0_sid:2; 1095 uint64_t rp0_sid:2;
655 uint64_t rp1_pid:1; 1096 uint64_t rp1_pid:1;
656 uint64_t rp0_pid:2; 1097 uint64_t rp0_pid:2;
1098#else
1099 uint64_t rp0_pid:2;
1100 uint64_t rp1_pid:1;
1101 uint64_t rp0_sid:2;
1102 uint64_t rp1_sid:1;
1103 uint64_t reserved_6_7:2;
1104 uint64_t w_ro:1;
1105 uint64_t rr_ro:1;
1106 uint64_t reserved_10_63:54;
1107#endif
657 } s; 1108 } s;
658 struct cvmx_sriox_mem_op_ctrl_s cn63xx; 1109 struct cvmx_sriox_mem_op_ctrl_s cn63xx;
659 struct cvmx_sriox_mem_op_ctrl_s cn63xxp1; 1110 struct cvmx_sriox_mem_op_ctrl_s cn63xxp1;
@@ -663,6 +1114,7 @@ union cvmx_sriox_mem_op_ctrl {
663union cvmx_sriox_omsg_ctrlx { 1114union cvmx_sriox_omsg_ctrlx {
664 uint64_t u64; 1115 uint64_t u64;
665 struct cvmx_sriox_omsg_ctrlx_s { 1116 struct cvmx_sriox_omsg_ctrlx_s {
1117#ifdef __BIG_ENDIAN_BITFIELD
666 uint64_t testmode:1; 1118 uint64_t testmode:1;
667 uint64_t reserved_37_62:26; 1119 uint64_t reserved_37_62:26;
668 uint64_t silo_max:5; 1120 uint64_t silo_max:5;
@@ -674,9 +1126,23 @@ union cvmx_sriox_omsg_ctrlx {
674 uint64_t idm_did:1; 1126 uint64_t idm_did:1;
675 uint64_t lttr_sp:4; 1127 uint64_t lttr_sp:4;
676 uint64_t lttr_mp:4; 1128 uint64_t lttr_mp:4;
1129#else
1130 uint64_t lttr_mp:4;
1131 uint64_t lttr_sp:4;
1132 uint64_t idm_did:1;
1133 uint64_t idm_sis:1;
1134 uint64_t idm_tt:1;
1135 uint64_t reserved_11_14:4;
1136 uint64_t rtry_en:1;
1137 uint64_t rtry_thr:16;
1138 uint64_t silo_max:5;
1139 uint64_t reserved_37_62:26;
1140 uint64_t testmode:1;
1141#endif
677 } s; 1142 } s;
678 struct cvmx_sriox_omsg_ctrlx_s cn63xx; 1143 struct cvmx_sriox_omsg_ctrlx_s cn63xx;
679 struct cvmx_sriox_omsg_ctrlx_cn63xxp1 { 1144 struct cvmx_sriox_omsg_ctrlx_cn63xxp1 {
1145#ifdef __BIG_ENDIAN_BITFIELD
680 uint64_t testmode:1; 1146 uint64_t testmode:1;
681 uint64_t reserved_32_62:31; 1147 uint64_t reserved_32_62:31;
682 uint64_t rtry_thr:16; 1148 uint64_t rtry_thr:16;
@@ -687,6 +1153,18 @@ union cvmx_sriox_omsg_ctrlx {
687 uint64_t idm_did:1; 1153 uint64_t idm_did:1;
688 uint64_t lttr_sp:4; 1154 uint64_t lttr_sp:4;
689 uint64_t lttr_mp:4; 1155 uint64_t lttr_mp:4;
1156#else
1157 uint64_t lttr_mp:4;
1158 uint64_t lttr_sp:4;
1159 uint64_t idm_did:1;
1160 uint64_t idm_sis:1;
1161 uint64_t idm_tt:1;
1162 uint64_t reserved_11_14:4;
1163 uint64_t rtry_en:1;
1164 uint64_t rtry_thr:16;
1165 uint64_t reserved_32_62:31;
1166 uint64_t testmode:1;
1167#endif
690 } cn63xxp1; 1168 } cn63xxp1;
691 struct cvmx_sriox_omsg_ctrlx_s cn66xx; 1169 struct cvmx_sriox_omsg_ctrlx_s cn66xx;
692}; 1170};
@@ -694,9 +1172,15 @@ union cvmx_sriox_omsg_ctrlx {
694union cvmx_sriox_omsg_done_countsx { 1172union cvmx_sriox_omsg_done_countsx {
695 uint64_t u64; 1173 uint64_t u64;
696 struct cvmx_sriox_omsg_done_countsx_s { 1174 struct cvmx_sriox_omsg_done_countsx_s {
1175#ifdef __BIG_ENDIAN_BITFIELD
697 uint64_t reserved_32_63:32; 1176 uint64_t reserved_32_63:32;
698 uint64_t bad:16; 1177 uint64_t bad:16;
699 uint64_t good:16; 1178 uint64_t good:16;
1179#else
1180 uint64_t good:16;
1181 uint64_t bad:16;
1182 uint64_t reserved_32_63:32;
1183#endif
700 } s; 1184 } s;
701 struct cvmx_sriox_omsg_done_countsx_s cn63xx; 1185 struct cvmx_sriox_omsg_done_countsx_s cn63xx;
702 struct cvmx_sriox_omsg_done_countsx_s cn66xx; 1186 struct cvmx_sriox_omsg_done_countsx_s cn66xx;
@@ -705,6 +1189,7 @@ union cvmx_sriox_omsg_done_countsx {
705union cvmx_sriox_omsg_fmp_mrx { 1189union cvmx_sriox_omsg_fmp_mrx {
706 uint64_t u64; 1190 uint64_t u64;
707 struct cvmx_sriox_omsg_fmp_mrx_s { 1191 struct cvmx_sriox_omsg_fmp_mrx_s {
1192#ifdef __BIG_ENDIAN_BITFIELD
708 uint64_t reserved_15_63:49; 1193 uint64_t reserved_15_63:49;
709 uint64_t ctlr_sp:1; 1194 uint64_t ctlr_sp:1;
710 uint64_t ctlr_fmp:1; 1195 uint64_t ctlr_fmp:1;
@@ -721,6 +1206,24 @@ union cvmx_sriox_omsg_fmp_mrx {
721 uint64_t all_fmp:1; 1206 uint64_t all_fmp:1;
722 uint64_t all_nmp:1; 1207 uint64_t all_nmp:1;
723 uint64_t all_psd:1; 1208 uint64_t all_psd:1;
1209#else
1210 uint64_t all_psd:1;
1211 uint64_t all_nmp:1;
1212 uint64_t all_fmp:1;
1213 uint64_t all_sp:1;
1214 uint64_t mbox_psd:1;
1215 uint64_t mbox_nmp:1;
1216 uint64_t mbox_fmp:1;
1217 uint64_t mbox_sp:1;
1218 uint64_t id_psd:1;
1219 uint64_t id_nmp:1;
1220 uint64_t id_fmp:1;
1221 uint64_t id_sp:1;
1222 uint64_t ctlr_nmp:1;
1223 uint64_t ctlr_fmp:1;
1224 uint64_t ctlr_sp:1;
1225 uint64_t reserved_15_63:49;
1226#endif
724 } s; 1227 } s;
725 struct cvmx_sriox_omsg_fmp_mrx_s cn63xx; 1228 struct cvmx_sriox_omsg_fmp_mrx_s cn63xx;
726 struct cvmx_sriox_omsg_fmp_mrx_s cn63xxp1; 1229 struct cvmx_sriox_omsg_fmp_mrx_s cn63xxp1;
@@ -730,6 +1233,7 @@ union cvmx_sriox_omsg_fmp_mrx {
730union cvmx_sriox_omsg_nmp_mrx { 1233union cvmx_sriox_omsg_nmp_mrx {
731 uint64_t u64; 1234 uint64_t u64;
732 struct cvmx_sriox_omsg_nmp_mrx_s { 1235 struct cvmx_sriox_omsg_nmp_mrx_s {
1236#ifdef __BIG_ENDIAN_BITFIELD
733 uint64_t reserved_15_63:49; 1237 uint64_t reserved_15_63:49;
734 uint64_t ctlr_sp:1; 1238 uint64_t ctlr_sp:1;
735 uint64_t ctlr_fmp:1; 1239 uint64_t ctlr_fmp:1;
@@ -746,6 +1250,24 @@ union cvmx_sriox_omsg_nmp_mrx {
746 uint64_t all_fmp:1; 1250 uint64_t all_fmp:1;
747 uint64_t all_nmp:1; 1251 uint64_t all_nmp:1;
748 uint64_t reserved_0_0:1; 1252 uint64_t reserved_0_0:1;
1253#else
1254 uint64_t reserved_0_0:1;
1255 uint64_t all_nmp:1;
1256 uint64_t all_fmp:1;
1257 uint64_t all_sp:1;
1258 uint64_t reserved_4_4:1;
1259 uint64_t mbox_nmp:1;
1260 uint64_t mbox_fmp:1;
1261 uint64_t mbox_sp:1;
1262 uint64_t reserved_8_8:1;
1263 uint64_t id_nmp:1;
1264 uint64_t id_fmp:1;
1265 uint64_t id_sp:1;
1266 uint64_t ctlr_nmp:1;
1267 uint64_t ctlr_fmp:1;
1268 uint64_t ctlr_sp:1;
1269 uint64_t reserved_15_63:49;
1270#endif
749 } s; 1271 } s;
750 struct cvmx_sriox_omsg_nmp_mrx_s cn63xx; 1272 struct cvmx_sriox_omsg_nmp_mrx_s cn63xx;
751 struct cvmx_sriox_omsg_nmp_mrx_s cn63xxp1; 1273 struct cvmx_sriox_omsg_nmp_mrx_s cn63xxp1;
@@ -755,16 +1277,30 @@ union cvmx_sriox_omsg_nmp_mrx {
755union cvmx_sriox_omsg_portx { 1277union cvmx_sriox_omsg_portx {
756 uint64_t u64; 1278 uint64_t u64;
757 struct cvmx_sriox_omsg_portx_s { 1279 struct cvmx_sriox_omsg_portx_s {
1280#ifdef __BIG_ENDIAN_BITFIELD
758 uint64_t reserved_32_63:32; 1281 uint64_t reserved_32_63:32;
759 uint64_t enable:1; 1282 uint64_t enable:1;
760 uint64_t reserved_3_30:28; 1283 uint64_t reserved_3_30:28;
761 uint64_t port:3; 1284 uint64_t port:3;
1285#else
1286 uint64_t port:3;
1287 uint64_t reserved_3_30:28;
1288 uint64_t enable:1;
1289 uint64_t reserved_32_63:32;
1290#endif
762 } s; 1291 } s;
763 struct cvmx_sriox_omsg_portx_cn63xx { 1292 struct cvmx_sriox_omsg_portx_cn63xx {
1293#ifdef __BIG_ENDIAN_BITFIELD
764 uint64_t reserved_32_63:32; 1294 uint64_t reserved_32_63:32;
765 uint64_t enable:1; 1295 uint64_t enable:1;
766 uint64_t reserved_2_30:29; 1296 uint64_t reserved_2_30:29;
767 uint64_t port:2; 1297 uint64_t port:2;
1298#else
1299 uint64_t port:2;
1300 uint64_t reserved_2_30:29;
1301 uint64_t enable:1;
1302 uint64_t reserved_32_63:32;
1303#endif
768 } cn63xx; 1304 } cn63xx;
769 struct cvmx_sriox_omsg_portx_cn63xx cn63xxp1; 1305 struct cvmx_sriox_omsg_portx_cn63xx cn63xxp1;
770 struct cvmx_sriox_omsg_portx_s cn66xx; 1306 struct cvmx_sriox_omsg_portx_s cn66xx;
@@ -773,8 +1309,13 @@ union cvmx_sriox_omsg_portx {
773union cvmx_sriox_omsg_silo_thr { 1309union cvmx_sriox_omsg_silo_thr {
774 uint64_t u64; 1310 uint64_t u64;
775 struct cvmx_sriox_omsg_silo_thr_s { 1311 struct cvmx_sriox_omsg_silo_thr_s {
1312#ifdef __BIG_ENDIAN_BITFIELD
776 uint64_t reserved_5_63:59; 1313 uint64_t reserved_5_63:59;
777 uint64_t tot_silo:5; 1314 uint64_t tot_silo:5;
1315#else
1316 uint64_t tot_silo:5;
1317 uint64_t reserved_5_63:59;
1318#endif
778 } s; 1319 } s;
779 struct cvmx_sriox_omsg_silo_thr_s cn63xx; 1320 struct cvmx_sriox_omsg_silo_thr_s cn63xx;
780 struct cvmx_sriox_omsg_silo_thr_s cn66xx; 1321 struct cvmx_sriox_omsg_silo_thr_s cn66xx;
@@ -783,6 +1324,7 @@ union cvmx_sriox_omsg_silo_thr {
783union cvmx_sriox_omsg_sp_mrx { 1324union cvmx_sriox_omsg_sp_mrx {
784 uint64_t u64; 1325 uint64_t u64;
785 struct cvmx_sriox_omsg_sp_mrx_s { 1326 struct cvmx_sriox_omsg_sp_mrx_s {
1327#ifdef __BIG_ENDIAN_BITFIELD
786 uint64_t reserved_16_63:48; 1328 uint64_t reserved_16_63:48;
787 uint64_t xmbox_sp:1; 1329 uint64_t xmbox_sp:1;
788 uint64_t ctlr_sp:1; 1330 uint64_t ctlr_sp:1;
@@ -800,6 +1342,25 @@ union cvmx_sriox_omsg_sp_mrx {
800 uint64_t all_fmp:1; 1342 uint64_t all_fmp:1;
801 uint64_t all_nmp:1; 1343 uint64_t all_nmp:1;
802 uint64_t all_psd:1; 1344 uint64_t all_psd:1;
1345#else
1346 uint64_t all_psd:1;
1347 uint64_t all_nmp:1;
1348 uint64_t all_fmp:1;
1349 uint64_t all_sp:1;
1350 uint64_t mbox_psd:1;
1351 uint64_t mbox_nmp:1;
1352 uint64_t mbox_fmp:1;
1353 uint64_t mbox_sp:1;
1354 uint64_t id_psd:1;
1355 uint64_t id_nmp:1;
1356 uint64_t id_fmp:1;
1357 uint64_t id_sp:1;
1358 uint64_t ctlr_nmp:1;
1359 uint64_t ctlr_fmp:1;
1360 uint64_t ctlr_sp:1;
1361 uint64_t xmbox_sp:1;
1362 uint64_t reserved_16_63:48;
1363#endif
803 } s; 1364 } s;
804 struct cvmx_sriox_omsg_sp_mrx_s cn63xx; 1365 struct cvmx_sriox_omsg_sp_mrx_s cn63xx;
805 struct cvmx_sriox_omsg_sp_mrx_s cn63xxp1; 1366 struct cvmx_sriox_omsg_sp_mrx_s cn63xxp1;
@@ -809,9 +1370,15 @@ union cvmx_sriox_omsg_sp_mrx {
809union cvmx_sriox_priox_in_use { 1370union cvmx_sriox_priox_in_use {
810 uint64_t u64; 1371 uint64_t u64;
811 struct cvmx_sriox_priox_in_use_s { 1372 struct cvmx_sriox_priox_in_use_s {
1373#ifdef __BIG_ENDIAN_BITFIELD
812 uint64_t reserved_32_63:32; 1374 uint64_t reserved_32_63:32;
813 uint64_t end_cnt:16; 1375 uint64_t end_cnt:16;
814 uint64_t start_cnt:16; 1376 uint64_t start_cnt:16;
1377#else
1378 uint64_t start_cnt:16;
1379 uint64_t end_cnt:16;
1380 uint64_t reserved_32_63:32;
1381#endif
815 } s; 1382 } s;
816 struct cvmx_sriox_priox_in_use_s cn63xx; 1383 struct cvmx_sriox_priox_in_use_s cn63xx;
817 struct cvmx_sriox_priox_in_use_s cn66xx; 1384 struct cvmx_sriox_priox_in_use_s cn66xx;
@@ -820,6 +1387,7 @@ union cvmx_sriox_priox_in_use {
820union cvmx_sriox_rx_bell { 1387union cvmx_sriox_rx_bell {
821 uint64_t u64; 1388 uint64_t u64;
822 struct cvmx_sriox_rx_bell_s { 1389 struct cvmx_sriox_rx_bell_s {
1390#ifdef __BIG_ENDIAN_BITFIELD
823 uint64_t reserved_48_63:16; 1391 uint64_t reserved_48_63:16;
824 uint64_t data:16; 1392 uint64_t data:16;
825 uint64_t src_id:16; 1393 uint64_t src_id:16;
@@ -829,6 +1397,17 @@ union cvmx_sriox_rx_bell {
829 uint64_t id16:1; 1397 uint64_t id16:1;
830 uint64_t reserved_2_2:1; 1398 uint64_t reserved_2_2:1;
831 uint64_t priority:2; 1399 uint64_t priority:2;
1400#else
1401 uint64_t priority:2;
1402 uint64_t reserved_2_2:1;
1403 uint64_t id16:1;
1404 uint64_t dest_id:1;
1405 uint64_t reserved_5_7:3;
1406 uint64_t count:8;
1407 uint64_t src_id:16;
1408 uint64_t data:16;
1409 uint64_t reserved_48_63:16;
1410#endif
832 } s; 1411 } s;
833 struct cvmx_sriox_rx_bell_s cn63xx; 1412 struct cvmx_sriox_rx_bell_s cn63xx;
834 struct cvmx_sriox_rx_bell_s cn63xxp1; 1413 struct cvmx_sriox_rx_bell_s cn63xxp1;
@@ -838,9 +1417,15 @@ union cvmx_sriox_rx_bell {
838union cvmx_sriox_rx_bell_seq { 1417union cvmx_sriox_rx_bell_seq {
839 uint64_t u64; 1418 uint64_t u64;
840 struct cvmx_sriox_rx_bell_seq_s { 1419 struct cvmx_sriox_rx_bell_seq_s {
1420#ifdef __BIG_ENDIAN_BITFIELD
841 uint64_t reserved_40_63:24; 1421 uint64_t reserved_40_63:24;
842 uint64_t count:8; 1422 uint64_t count:8;
843 uint64_t seq:32; 1423 uint64_t seq:32;
1424#else
1425 uint64_t seq:32;
1426 uint64_t count:8;
1427 uint64_t reserved_40_63:24;
1428#endif
844 } s; 1429 } s;
845 struct cvmx_sriox_rx_bell_seq_s cn63xx; 1430 struct cvmx_sriox_rx_bell_seq_s cn63xx;
846 struct cvmx_sriox_rx_bell_seq_s cn63xxp1; 1431 struct cvmx_sriox_rx_bell_seq_s cn63xxp1;
@@ -850,6 +1435,7 @@ union cvmx_sriox_rx_bell_seq {
850union cvmx_sriox_rx_status { 1435union cvmx_sriox_rx_status {
851 uint64_t u64; 1436 uint64_t u64;
852 struct cvmx_sriox_rx_status_s { 1437 struct cvmx_sriox_rx_status_s {
1438#ifdef __BIG_ENDIAN_BITFIELD
853 uint64_t rtn_pr3:8; 1439 uint64_t rtn_pr3:8;
854 uint64_t rtn_pr2:8; 1440 uint64_t rtn_pr2:8;
855 uint64_t rtn_pr1:8; 1441 uint64_t rtn_pr1:8;
@@ -859,6 +1445,17 @@ union cvmx_sriox_rx_status {
859 uint64_t reserved_13_15:3; 1445 uint64_t reserved_13_15:3;
860 uint64_t n_post:5; 1446 uint64_t n_post:5;
861 uint64_t post:8; 1447 uint64_t post:8;
1448#else
1449 uint64_t post:8;
1450 uint64_t n_post:5;
1451 uint64_t reserved_13_15:3;
1452 uint64_t comp:8;
1453 uint64_t mbox:4;
1454 uint64_t reserved_28_39:12;
1455 uint64_t rtn_pr1:8;
1456 uint64_t rtn_pr2:8;
1457 uint64_t rtn_pr3:8;
1458#endif
862 } s; 1459 } s;
863 struct cvmx_sriox_rx_status_s cn63xx; 1460 struct cvmx_sriox_rx_status_s cn63xx;
864 struct cvmx_sriox_rx_status_s cn63xxp1; 1461 struct cvmx_sriox_rx_status_s cn63xxp1;
@@ -868,6 +1465,7 @@ union cvmx_sriox_rx_status {
868union cvmx_sriox_s2m_typex { 1465union cvmx_sriox_s2m_typex {
869 uint64_t u64; 1466 uint64_t u64;
870 struct cvmx_sriox_s2m_typex_s { 1467 struct cvmx_sriox_s2m_typex_s {
1468#ifdef __BIG_ENDIAN_BITFIELD
871 uint64_t reserved_19_63:45; 1469 uint64_t reserved_19_63:45;
872 uint64_t wr_op:3; 1470 uint64_t wr_op:3;
873 uint64_t reserved_15_15:1; 1471 uint64_t reserved_15_15:1;
@@ -879,6 +1477,19 @@ union cvmx_sriox_s2m_typex {
879 uint64_t id16:1; 1477 uint64_t id16:1;
880 uint64_t reserved_2_3:2; 1478 uint64_t reserved_2_3:2;
881 uint64_t iaow_sel:2; 1479 uint64_t iaow_sel:2;
1480#else
1481 uint64_t iaow_sel:2;
1482 uint64_t reserved_2_3:2;
1483 uint64_t id16:1;
1484 uint64_t src_id:1;
1485 uint64_t reserved_6_7:2;
1486 uint64_t rd_prior:2;
1487 uint64_t wr_prior:2;
1488 uint64_t rd_op:3;
1489 uint64_t reserved_15_15:1;
1490 uint64_t wr_op:3;
1491 uint64_t reserved_19_63:45;
1492#endif
882 } s; 1493 } s;
883 struct cvmx_sriox_s2m_typex_s cn63xx; 1494 struct cvmx_sriox_s2m_typex_s cn63xx;
884 struct cvmx_sriox_s2m_typex_s cn63xxp1; 1495 struct cvmx_sriox_s2m_typex_s cn63xxp1;
@@ -888,8 +1499,13 @@ union cvmx_sriox_s2m_typex {
888union cvmx_sriox_seq { 1499union cvmx_sriox_seq {
889 uint64_t u64; 1500 uint64_t u64;
890 struct cvmx_sriox_seq_s { 1501 struct cvmx_sriox_seq_s {
1502#ifdef __BIG_ENDIAN_BITFIELD
891 uint64_t reserved_32_63:32; 1503 uint64_t reserved_32_63:32;
892 uint64_t seq:32; 1504 uint64_t seq:32;
1505#else
1506 uint64_t seq:32;
1507 uint64_t reserved_32_63:32;
1508#endif
893 } s; 1509 } s;
894 struct cvmx_sriox_seq_s cn63xx; 1510 struct cvmx_sriox_seq_s cn63xx;
895 struct cvmx_sriox_seq_s cn63xxp1; 1511 struct cvmx_sriox_seq_s cn63xxp1;
@@ -899,9 +1515,15 @@ union cvmx_sriox_seq {
899union cvmx_sriox_status_reg { 1515union cvmx_sriox_status_reg {
900 uint64_t u64; 1516 uint64_t u64;
901 struct cvmx_sriox_status_reg_s { 1517 struct cvmx_sriox_status_reg_s {
1518#ifdef __BIG_ENDIAN_BITFIELD
902 uint64_t reserved_2_63:62; 1519 uint64_t reserved_2_63:62;
903 uint64_t access:1; 1520 uint64_t access:1;
904 uint64_t srio:1; 1521 uint64_t srio:1;
1522#else
1523 uint64_t srio:1;
1524 uint64_t access:1;
1525 uint64_t reserved_2_63:62;
1526#endif
905 } s; 1527 } s;
906 struct cvmx_sriox_status_reg_s cn63xx; 1528 struct cvmx_sriox_status_reg_s cn63xx;
907 struct cvmx_sriox_status_reg_s cn63xxp1; 1529 struct cvmx_sriox_status_reg_s cn63xxp1;
@@ -911,12 +1533,21 @@ union cvmx_sriox_status_reg {
911union cvmx_sriox_tag_ctrl { 1533union cvmx_sriox_tag_ctrl {
912 uint64_t u64; 1534 uint64_t u64;
913 struct cvmx_sriox_tag_ctrl_s { 1535 struct cvmx_sriox_tag_ctrl_s {
1536#ifdef __BIG_ENDIAN_BITFIELD
914 uint64_t reserved_17_63:47; 1537 uint64_t reserved_17_63:47;
915 uint64_t o_clr:1; 1538 uint64_t o_clr:1;
916 uint64_t reserved_13_15:3; 1539 uint64_t reserved_13_15:3;
917 uint64_t otag:5; 1540 uint64_t otag:5;
918 uint64_t reserved_5_7:3; 1541 uint64_t reserved_5_7:3;
919 uint64_t itag:5; 1542 uint64_t itag:5;
1543#else
1544 uint64_t itag:5;
1545 uint64_t reserved_5_7:3;
1546 uint64_t otag:5;
1547 uint64_t reserved_13_15:3;
1548 uint64_t o_clr:1;
1549 uint64_t reserved_17_63:47;
1550#endif
920 } s; 1551 } s;
921 struct cvmx_sriox_tag_ctrl_s cn63xx; 1552 struct cvmx_sriox_tag_ctrl_s cn63xx;
922 struct cvmx_sriox_tag_ctrl_s cn63xxp1; 1553 struct cvmx_sriox_tag_ctrl_s cn63xxp1;
@@ -926,12 +1557,21 @@ union cvmx_sriox_tag_ctrl {
926union cvmx_sriox_tlp_credits { 1557union cvmx_sriox_tlp_credits {
927 uint64_t u64; 1558 uint64_t u64;
928 struct cvmx_sriox_tlp_credits_s { 1559 struct cvmx_sriox_tlp_credits_s {
1560#ifdef __BIG_ENDIAN_BITFIELD
929 uint64_t reserved_28_63:36; 1561 uint64_t reserved_28_63:36;
930 uint64_t mbox:4; 1562 uint64_t mbox:4;
931 uint64_t comp:8; 1563 uint64_t comp:8;
932 uint64_t reserved_13_15:3; 1564 uint64_t reserved_13_15:3;
933 uint64_t n_post:5; 1565 uint64_t n_post:5;
934 uint64_t post:8; 1566 uint64_t post:8;
1567#else
1568 uint64_t post:8;
1569 uint64_t n_post:5;
1570 uint64_t reserved_13_15:3;
1571 uint64_t comp:8;
1572 uint64_t mbox:4;
1573 uint64_t reserved_28_63:36;
1574#endif
935 } s; 1575 } s;
936 struct cvmx_sriox_tlp_credits_s cn63xx; 1576 struct cvmx_sriox_tlp_credits_s cn63xx;
937 struct cvmx_sriox_tlp_credits_s cn63xxp1; 1577 struct cvmx_sriox_tlp_credits_s cn63xxp1;
@@ -941,6 +1581,7 @@ union cvmx_sriox_tlp_credits {
941union cvmx_sriox_tx_bell { 1581union cvmx_sriox_tx_bell {
942 uint64_t u64; 1582 uint64_t u64;
943 struct cvmx_sriox_tx_bell_s { 1583 struct cvmx_sriox_tx_bell_s {
1584#ifdef __BIG_ENDIAN_BITFIELD
944 uint64_t reserved_48_63:16; 1585 uint64_t reserved_48_63:16;
945 uint64_t data:16; 1586 uint64_t data:16;
946 uint64_t dest_id:16; 1587 uint64_t dest_id:16;
@@ -951,6 +1592,18 @@ union cvmx_sriox_tx_bell {
951 uint64_t id16:1; 1592 uint64_t id16:1;
952 uint64_t reserved_2_2:1; 1593 uint64_t reserved_2_2:1;
953 uint64_t priority:2; 1594 uint64_t priority:2;
1595#else
1596 uint64_t priority:2;
1597 uint64_t reserved_2_2:1;
1598 uint64_t id16:1;
1599 uint64_t src_id:1;
1600 uint64_t reserved_5_7:3;
1601 uint64_t pending:1;
1602 uint64_t reserved_9_15:7;
1603 uint64_t dest_id:16;
1604 uint64_t data:16;
1605 uint64_t reserved_48_63:16;
1606#endif
954 } s; 1607 } s;
955 struct cvmx_sriox_tx_bell_s cn63xx; 1608 struct cvmx_sriox_tx_bell_s cn63xx;
956 struct cvmx_sriox_tx_bell_s cn63xxp1; 1609 struct cvmx_sriox_tx_bell_s cn63xxp1;
@@ -960,6 +1613,7 @@ union cvmx_sriox_tx_bell {
960union cvmx_sriox_tx_bell_info { 1613union cvmx_sriox_tx_bell_info {
961 uint64_t u64; 1614 uint64_t u64;
962 struct cvmx_sriox_tx_bell_info_s { 1615 struct cvmx_sriox_tx_bell_info_s {
1616#ifdef __BIG_ENDIAN_BITFIELD
963 uint64_t reserved_48_63:16; 1617 uint64_t reserved_48_63:16;
964 uint64_t data:16; 1618 uint64_t data:16;
965 uint64_t dest_id:16; 1619 uint64_t dest_id:16;
@@ -971,6 +1625,19 @@ union cvmx_sriox_tx_bell_info {
971 uint64_t id16:1; 1625 uint64_t id16:1;
972 uint64_t reserved_2_2:1; 1626 uint64_t reserved_2_2:1;
973 uint64_t priority:2; 1627 uint64_t priority:2;
1628#else
1629 uint64_t priority:2;
1630 uint64_t reserved_2_2:1;
1631 uint64_t id16:1;
1632 uint64_t src_id:1;
1633 uint64_t retry:1;
1634 uint64_t error:1;
1635 uint64_t timeout:1;
1636 uint64_t reserved_8_15:8;
1637 uint64_t dest_id:16;
1638 uint64_t data:16;
1639 uint64_t reserved_48_63:16;
1640#endif
974 } s; 1641 } s;
975 struct cvmx_sriox_tx_bell_info_s cn63xx; 1642 struct cvmx_sriox_tx_bell_info_s cn63xx;
976 struct cvmx_sriox_tx_bell_info_s cn63xxp1; 1643 struct cvmx_sriox_tx_bell_info_s cn63xxp1;
@@ -980,6 +1647,7 @@ union cvmx_sriox_tx_bell_info {
980union cvmx_sriox_tx_ctrl { 1647union cvmx_sriox_tx_ctrl {
981 uint64_t u64; 1648 uint64_t u64;
982 struct cvmx_sriox_tx_ctrl_s { 1649 struct cvmx_sriox_tx_ctrl_s {
1650#ifdef __BIG_ENDIAN_BITFIELD
983 uint64_t reserved_53_63:11; 1651 uint64_t reserved_53_63:11;
984 uint64_t tag_th2:5; 1652 uint64_t tag_th2:5;
985 uint64_t reserved_45_47:3; 1653 uint64_t reserved_45_47:3;
@@ -992,6 +1660,20 @@ union cvmx_sriox_tx_ctrl {
992 uint64_t tx_th1:4; 1660 uint64_t tx_th1:4;
993 uint64_t reserved_4_7:4; 1661 uint64_t reserved_4_7:4;
994 uint64_t tx_th0:4; 1662 uint64_t tx_th0:4;
1663#else
1664 uint64_t tx_th0:4;
1665 uint64_t reserved_4_7:4;
1666 uint64_t tx_th1:4;
1667 uint64_t reserved_12_15:4;
1668 uint64_t tx_th2:4;
1669 uint64_t reserved_20_31:12;
1670 uint64_t tag_th0:5;
1671 uint64_t reserved_37_39:3;
1672 uint64_t tag_th1:5;
1673 uint64_t reserved_45_47:3;
1674 uint64_t tag_th2:5;
1675 uint64_t reserved_53_63:11;
1676#endif
995 } s; 1677 } s;
996 struct cvmx_sriox_tx_ctrl_s cn63xx; 1678 struct cvmx_sriox_tx_ctrl_s cn63xx;
997 struct cvmx_sriox_tx_ctrl_s cn63xxp1; 1679 struct cvmx_sriox_tx_ctrl_s cn63xxp1;
@@ -1001,8 +1683,13 @@ union cvmx_sriox_tx_ctrl {
1001union cvmx_sriox_tx_emphasis { 1683union cvmx_sriox_tx_emphasis {
1002 uint64_t u64; 1684 uint64_t u64;
1003 struct cvmx_sriox_tx_emphasis_s { 1685 struct cvmx_sriox_tx_emphasis_s {
1686#ifdef __BIG_ENDIAN_BITFIELD
1004 uint64_t reserved_4_63:60; 1687 uint64_t reserved_4_63:60;
1005 uint64_t emph:4; 1688 uint64_t emph:4;
1689#else
1690 uint64_t emph:4;
1691 uint64_t reserved_4_63:60;
1692#endif
1006 } s; 1693 } s;
1007 struct cvmx_sriox_tx_emphasis_s cn63xx; 1694 struct cvmx_sriox_tx_emphasis_s cn63xx;
1008 struct cvmx_sriox_tx_emphasis_s cn66xx; 1695 struct cvmx_sriox_tx_emphasis_s cn66xx;
@@ -1011,11 +1698,19 @@ union cvmx_sriox_tx_emphasis {
1011union cvmx_sriox_tx_status { 1698union cvmx_sriox_tx_status {
1012 uint64_t u64; 1699 uint64_t u64;
1013 struct cvmx_sriox_tx_status_s { 1700 struct cvmx_sriox_tx_status_s {
1701#ifdef __BIG_ENDIAN_BITFIELD
1014 uint64_t reserved_32_63:32; 1702 uint64_t reserved_32_63:32;
1015 uint64_t s2m_pr3:8; 1703 uint64_t s2m_pr3:8;
1016 uint64_t s2m_pr2:8; 1704 uint64_t s2m_pr2:8;
1017 uint64_t s2m_pr1:8; 1705 uint64_t s2m_pr1:8;
1018 uint64_t s2m_pr0:8; 1706 uint64_t s2m_pr0:8;
1707#else
1708 uint64_t s2m_pr0:8;
1709 uint64_t s2m_pr1:8;
1710 uint64_t s2m_pr2:8;
1711 uint64_t s2m_pr3:8;
1712 uint64_t reserved_32_63:32;
1713#endif
1019 } s; 1714 } s;
1020 struct cvmx_sriox_tx_status_s cn63xx; 1715 struct cvmx_sriox_tx_status_s cn63xx;
1021 struct cvmx_sriox_tx_status_s cn63xxp1; 1716 struct cvmx_sriox_tx_status_s cn63xxp1;
@@ -1025,9 +1720,15 @@ union cvmx_sriox_tx_status {
1025union cvmx_sriox_wr_done_counts { 1720union cvmx_sriox_wr_done_counts {
1026 uint64_t u64; 1721 uint64_t u64;
1027 struct cvmx_sriox_wr_done_counts_s { 1722 struct cvmx_sriox_wr_done_counts_s {
1723#ifdef __BIG_ENDIAN_BITFIELD
1028 uint64_t reserved_32_63:32; 1724 uint64_t reserved_32_63:32;
1029 uint64_t bad:16; 1725 uint64_t bad:16;
1030 uint64_t good:16; 1726 uint64_t good:16;
1727#else
1728 uint64_t good:16;
1729 uint64_t bad:16;
1730 uint64_t reserved_32_63:32;
1731#endif
1031 } s; 1732 } s;
1032 struct cvmx_sriox_wr_done_counts_s cn63xx; 1733 struct cvmx_sriox_wr_done_counts_s cn63xx;
1033 struct cvmx_sriox_wr_done_counts_s cn66xx; 1734 struct cvmx_sriox_wr_done_counts_s cn66xx;
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-22 20:05:12 -0500