1 files changed, 166 insertions, 2 deletions

diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
index 61f2a2a5099d..12963d05da86 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
@@ -161,6 +161,7 @@
 /* External Interrupt Configuration register */
 #define PERF_EXTIRQ_CFG_REG_6328        0x18
 #define PERF_EXTIRQ_CFG_REG_6338        0x14
+#define PERF_EXTIRQ_CFG_REG_6345        0x14
 #define PERF_EXTIRQ_CFG_REG_6348        0x14
 #define PERF_EXTIRQ_CFG_REG_6358        0x14
 #define PERF_EXTIRQ_CFG_REG_6368        0x18
@@ -543,6 +544,12 @@
 #define GPIO_MODE_6368_SPI_SSN5         (1 << 31)
 
 
+#define GPIO_PINMUX_OTHR_REG            0x24
+#define GPIO_PINMUX_OTHR_6328_USB_SHIFT 12
+#define GPIO_PINMUX_OTHR_6328_USB_MASK  (3 << GPIO_PINMUX_OTHR_6328_USB_SHIFT)
+#define GPIO_PINMUX_OTHR_6328_USB_HOST  (1 << GPIO_PINMUX_OTHR_6328_USB_SHIFT)
+#define GPIO_PINMUX_OTHR_6328_USB_DEV   (2 << GPIO_PINMUX_OTHR_6328_USB_SHIFT)
+
 #define GPIO_BASEMODE_6368_REG          0x38
 #define GPIO_BASEMODE_6368_UART2        0x1
 #define GPIO_BASEMODE_6368_GPIO         0x0
@@ -670,6 +677,12 @@
 #define ENETDMA_BUFALLOC_FORCE_SHIFT    31
 #define ENETDMA_BUFALLOC_FORCE_MASK     (1 << ENETDMA_BUFALLOC_FORCE_SHIFT)
 
+/* Global interrupt status */
+#define ENETDMA_GLB_IRQSTAT_REG         (0x40)
+
+/* Global interrupt mask */
+#define ENETDMA_GLB_IRQMASK_REG         (0x44)
+
 /* Channel Configuration register */
 #define ENETDMA_CHANCFG_REG(x)          (0x100 + (x) * 0x10)
 #define ENETDMA_CHANCFG_EN_SHIFT        0
@@ -709,9 +722,11 @@
 /* Channel Configuration register */
 #define ENETDMAC_CHANCFG_REG(x)         ((x) * 0x10)
 #define ENETDMAC_CHANCFG_EN_SHIFT       0
-#define ENETDMAC_CHANCFG_EN_MASK        (1 << ENETDMA_CHANCFG_EN_SHIFT)
+#define ENETDMAC_CHANCFG_EN_MASK        (1 << ENETDMAC_CHANCFG_EN_SHIFT)
 #define ENETDMAC_CHANCFG_PKTHALT_SHIFT  1
-#define ENETDMAC_CHANCFG_PKTHALT_MASK   (1 << ENETDMA_CHANCFG_PKTHALT_SHIFT)
+#define ENETDMAC_CHANCFG_PKTHALT_MASK   (1 << ENETDMAC_CHANCFG_PKTHALT_SHIFT)
+#define ENETDMAC_CHANCFG_BUFHALT_SHIFT  2
+#define ENETDMAC_CHANCFG_BUFHALT_MASK   (1 << ENETDMAC_CHANCFG_BUFHALT_SHIFT)
 
 /* Interrupt Control/Status register */
 #define ENETDMAC_IR_REG(x)              (0x4 + (x) * 0x10)
@@ -770,6 +785,8 @@
 #define USBH_PRIV_SWAP_6358_REG         0x0
 #define USBH_PRIV_SWAP_6368_REG         0x1c
 
+#define USBH_PRIV_SWAP_USBD_SHIFT       6
+#define USBH_PRIV_SWAP_USBD_MASK        (1 << USBH_PRIV_SWAP_USBD_SHIFT)
 #define USBH_PRIV_SWAP_EHCI_ENDN_SHIFT  4
 #define USBH_PRIV_SWAP_EHCI_ENDN_MASK   (1 << USBH_PRIV_SWAP_EHCI_ENDN_SHIFT)
 #define USBH_PRIV_SWAP_EHCI_DATA_SHIFT  3
@@ -779,6 +796,12 @@
 #define USBH_PRIV_SWAP_OHCI_DATA_SHIFT  0
 #define USBH_PRIV_SWAP_OHCI_DATA_MASK   (1 << USBH_PRIV_SWAP_OHCI_DATA_SHIFT)
 
+#define USBH_PRIV_UTMI_CTL_6368_REG     0x10
+#define USBH_PRIV_UTMI_CTL_NODRIV_SHIFT 12
+#define USBH_PRIV_UTMI_CTL_NODRIV_MASK  (0xf << USBH_PRIV_UTMI_CTL_NODRIV_SHIFT)
+#define USBH_PRIV_UTMI_CTL_HOSTB_SHIFT  0
+#define USBH_PRIV_UTMI_CTL_HOSTB_MASK   (0xf << USBH_PRIV_UTMI_CTL_HOSTB_SHIFT)
+
 #define USBH_PRIV_TEST_6358_REG         0x24
 #define USBH_PRIV_TEST_6368_REG         0x14
 
@@ -787,6 +810,147 @@
 #define USBH_PRIV_SETUP_IOC_MASK        (1 << USBH_PRIV_SETUP_IOC_SHIFT)
 
 
+/*************************************************************************
+ * _REG relative to RSET_USBD
+ *************************************************************************/
+
+/* General control */
+#define USBD_CONTROL_REG                0x00
+#define USBD_CONTROL_TXZLENINS_SHIFT    14
+#define USBD_CONTROL_TXZLENINS_MASK     (1 << USBD_CONTROL_TXZLENINS_SHIFT)
+#define USBD_CONTROL_AUTO_CSRS_SHIFT    13
+#define USBD_CONTROL_AUTO_CSRS_MASK     (1 << USBD_CONTROL_AUTO_CSRS_SHIFT)
+#define USBD_CONTROL_RXZSCFG_SHIFT      12
+#define USBD_CONTROL_RXZSCFG_MASK       (1 << USBD_CONTROL_RXZSCFG_SHIFT)
+#define USBD_CONTROL_INIT_SEL_SHIFT     8
+#define USBD_CONTROL_INIT_SEL_MASK      (0xf << USBD_CONTROL_INIT_SEL_SHIFT)
+#define USBD_CONTROL_FIFO_RESET_SHIFT   6
+#define USBD_CONTROL_FIFO_RESET_MASK    (3 << USBD_CONTROL_FIFO_RESET_SHIFT)
+#define USBD_CONTROL_SETUPERRLOCK_SHIFT 5
+#define USBD_CONTROL_SETUPERRLOCK_MASK  (1 << USBD_CONTROL_SETUPERRLOCK_SHIFT)
+#define USBD_CONTROL_DONE_CSRS_SHIFT    0
+#define USBD_CONTROL_DONE_CSRS_MASK     (1 << USBD_CONTROL_DONE_CSRS_SHIFT)
+
+/* Strap options */
+#define USBD_STRAPS_REG                 0x04
+#define USBD_STRAPS_APP_SELF_PWR_SHIFT  10
+#define USBD_STRAPS_APP_SELF_PWR_MASK   (1 << USBD_STRAPS_APP_SELF_PWR_SHIFT)
+#define USBD_STRAPS_APP_DISCON_SHIFT    9
+#define USBD_STRAPS_APP_DISCON_MASK     (1 << USBD_STRAPS_APP_DISCON_SHIFT)
+#define USBD_STRAPS_APP_CSRPRGSUP_SHIFT 8
+#define USBD_STRAPS_APP_CSRPRGSUP_MASK  (1 << USBD_STRAPS_APP_CSRPRGSUP_SHIFT)
+#define USBD_STRAPS_APP_RMTWKUP_SHIFT   6
+#define USBD_STRAPS_APP_RMTWKUP_MASK    (1 << USBD_STRAPS_APP_RMTWKUP_SHIFT)
+#define USBD_STRAPS_APP_RAM_IF_SHIFT    7
+#define USBD_STRAPS_APP_RAM_IF_MASK     (1 << USBD_STRAPS_APP_RAM_IF_SHIFT)
+#define USBD_STRAPS_APP_8BITPHY_SHIFT   2
+#define USBD_STRAPS_APP_8BITPHY_MASK    (1 << USBD_STRAPS_APP_8BITPHY_SHIFT)
+#define USBD_STRAPS_SPEED_SHIFT         0
+#define USBD_STRAPS_SPEED_MASK          (3 << USBD_STRAPS_SPEED_SHIFT)
+
+/* Stall control */
+#define USBD_STALL_REG                  0x08
+#define USBD_STALL_UPDATE_SHIFT         7
+#define USBD_STALL_UPDATE_MASK          (1 << USBD_STALL_UPDATE_SHIFT)
+#define USBD_STALL_ENABLE_SHIFT         6
+#define USBD_STALL_ENABLE_MASK          (1 << USBD_STALL_ENABLE_SHIFT)
+#define USBD_STALL_EPNUM_SHIFT          0
+#define USBD_STALL_EPNUM_MASK           (0xf << USBD_STALL_EPNUM_SHIFT)
+
+/* General status */
+#define USBD_STATUS_REG                 0x0c
+#define USBD_STATUS_SOF_SHIFT           16
+#define USBD_STATUS_SOF_MASK            (0x7ff << USBD_STATUS_SOF_SHIFT)
+#define USBD_STATUS_SPD_SHIFT           12
+#define USBD_STATUS_SPD_MASK            (3 << USBD_STATUS_SPD_SHIFT)
+#define USBD_STATUS_ALTINTF_SHIFT       8
+#define USBD_STATUS_ALTINTF_MASK        (0xf << USBD_STATUS_ALTINTF_SHIFT)
+#define USBD_STATUS_INTF_SHIFT          4
+#define USBD_STATUS_INTF_MASK           (0xf << USBD_STATUS_INTF_SHIFT)
+#define USBD_STATUS_CFG_SHIFT           0
+#define USBD_STATUS_CFG_MASK            (0xf << USBD_STATUS_CFG_SHIFT)
+
+/* Other events */
+#define USBD_EVENTS_REG                 0x10
+#define USBD_EVENTS_USB_LINK_SHIFT      10
+#define USBD_EVENTS_USB_LINK_MASK       (1 << USBD_EVENTS_USB_LINK_SHIFT)
+
+/* IRQ status */
+#define USBD_EVENT_IRQ_STATUS_REG       0x14
+
+/* IRQ level (2 bits per IRQ event) */
+#define USBD_EVENT_IRQ_CFG_HI_REG       0x18
+
+#define USBD_EVENT_IRQ_CFG_LO_REG       0x1c
+
+#define USBD_EVENT_IRQ_CFG_SHIFT(x)     ((x & 0xf) << 1)
+#define USBD_EVENT_IRQ_CFG_MASK(x)      (3 << USBD_EVENT_IRQ_CFG_SHIFT(x))
+#define USBD_EVENT_IRQ_CFG_RISING(x)    (0 << USBD_EVENT_IRQ_CFG_SHIFT(x))
+#define USBD_EVENT_IRQ_CFG_FALLING(x)   (1 << USBD_EVENT_IRQ_CFG_SHIFT(x))
+
+/* IRQ mask (1=unmasked) */
+#define USBD_EVENT_IRQ_MASK_REG         0x20
+
+/* IRQ bits */
+#define USBD_EVENT_IRQ_USB_LINK         10
+#define USBD_EVENT_IRQ_SETCFG           9
+#define USBD_EVENT_IRQ_SETINTF          8
+#define USBD_EVENT_IRQ_ERRATIC_ERR      7
+#define USBD_EVENT_IRQ_SET_CSRS         6
+#define USBD_EVENT_IRQ_SUSPEND          5
+#define USBD_EVENT_IRQ_EARLY_SUSPEND    4
+#define USBD_EVENT_IRQ_SOF              3
+#define USBD_EVENT_IRQ_ENUM_ON          2
+#define USBD_EVENT_IRQ_SETUP            1
+#define USBD_EVENT_IRQ_USB_RESET        0
+
+/* TX FIFO partitioning */
+#define USBD_TXFIFO_CONFIG_REG          0x40
+#define USBD_TXFIFO_CONFIG_END_SHIFT    16
+#define USBD_TXFIFO_CONFIG_END_MASK     (0xff << USBD_TXFIFO_CONFIG_END_SHIFT)
+#define USBD_TXFIFO_CONFIG_START_SHIFT  0
+#define USBD_TXFIFO_CONFIG_START_MASK   (0xff << USBD_TXFIFO_CONFIG_START_SHIFT)
+
+/* RX FIFO partitioning */
+#define USBD_RXFIFO_CONFIG_REG          0x44
+#define USBD_RXFIFO_CONFIG_END_SHIFT    16
+#define USBD_RXFIFO_CONFIG_END_MASK     (0xff << USBD_TXFIFO_CONFIG_END_SHIFT)
+#define USBD_RXFIFO_CONFIG_START_SHIFT  0
+#define USBD_RXFIFO_CONFIG_START_MASK   (0xff << USBD_TXFIFO_CONFIG_START_SHIFT)
+
+/* TX FIFO/endpoint configuration */
+#define USBD_TXFIFO_EPSIZE_REG          0x48
+
+/* RX FIFO/endpoint configuration */
+#define USBD_RXFIFO_EPSIZE_REG          0x4c
+
+/* Endpoint<->DMA mappings */
+#define USBD_EPNUM_TYPEMAP_REG          0x50
+#define USBD_EPNUM_TYPEMAP_TYPE_SHIFT   8
+#define USBD_EPNUM_TYPEMAP_TYPE_MASK    (0x3 << USBD_EPNUM_TYPEMAP_TYPE_SHIFT)
+#define USBD_EPNUM_TYPEMAP_DMA_CH_SHIFT 0
+#define USBD_EPNUM_TYPEMAP_DMA_CH_MASK  (0xf << USBD_EPNUM_TYPEMAP_DMACH_SHIFT)
+
+/* Misc per-endpoint settings */
+#define USBD_CSR_SETUPADDR_REG          0x80
+#define USBD_CSR_SETUPADDR_DEF          0xb550
+
+#define USBD_CSR_EP_REG(x)              (0x84 + (x) * 4)
+#define USBD_CSR_EP_MAXPKT_SHIFT        19
+#define USBD_CSR_EP_MAXPKT_MASK         (0x7ff << USBD_CSR_EP_MAXPKT_SHIFT)
+#define USBD_CSR_EP_ALTIFACE_SHIFT      15
+#define USBD_CSR_EP_ALTIFACE_MASK       (0xf << USBD_CSR_EP_ALTIFACE_SHIFT)
+#define USBD_CSR_EP_IFACE_SHIFT         11
+#define USBD_CSR_EP_IFACE_MASK          (0xf << USBD_CSR_EP_IFACE_SHIFT)
+#define USBD_CSR_EP_CFG_SHIFT           7
+#define USBD_CSR_EP_CFG_MASK            (0xf << USBD_CSR_EP_CFG_SHIFT)
+#define USBD_CSR_EP_TYPE_SHIFT          5
+#define USBD_CSR_EP_TYPE_MASK           (3 << USBD_CSR_EP_TYPE_SHIFT)
+#define USBD_CSR_EP_DIR_SHIFT           4
+#define USBD_CSR_EP_DIR_MASK            (1 << USBD_CSR_EP_DIR_SHIFT)
+#define USBD_CSR_EP_LOG_SHIFT           0
+#define USBD_CSR_EP_LOG_MASK            (0xf << USBD_CSR_EP_LOG_SHIFT)
+
 
 /*************************************************************************
  * _REG relative to RSET_MPI