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-rw-r--r--arch/mips/au1000/common/dbg_io.c122
1 files changed, 122 insertions, 0 deletions
diff --git a/arch/mips/au1000/common/dbg_io.c b/arch/mips/au1000/common/dbg_io.c
new file mode 100644
index 000000000000..7bc768e558db
--- /dev/null
+++ b/arch/mips/au1000/common/dbg_io.c
@@ -0,0 +1,122 @@
1
2#include <linux/config.h>
3#include <asm/io.h>
4#include <asm/mach-au1x00/au1000.h>
5
6#ifdef CONFIG_KGDB
7
8/*
9 * FIXME the user should be able to select the
10 * uart to be used for debugging.
11 */
12#define DEBUG_BASE UART_DEBUG_BASE
13/**/
14
15/* we need uint32 uint8 */
16/* #include "types.h" */
17typedef unsigned char uint8;
18typedef unsigned int uint32;
19
20#define UART16550_BAUD_2400 2400
21#define UART16550_BAUD_4800 4800
22#define UART16550_BAUD_9600 9600
23#define UART16550_BAUD_19200 19200
24#define UART16550_BAUD_38400 38400
25#define UART16550_BAUD_57600 57600
26#define UART16550_BAUD_115200 115200
27
28#define UART16550_PARITY_NONE 0
29#define UART16550_PARITY_ODD 0x08
30#define UART16550_PARITY_EVEN 0x18
31#define UART16550_PARITY_MARK 0x28
32#define UART16550_PARITY_SPACE 0x38
33
34#define UART16550_DATA_5BIT 0x0
35#define UART16550_DATA_6BIT 0x1
36#define UART16550_DATA_7BIT 0x2
37#define UART16550_DATA_8BIT 0x3
38
39#define UART16550_STOP_1BIT 0x0
40#define UART16550_STOP_2BIT 0x4
41
42
43#define UART_RX 0 /* Receive buffer */
44#define UART_TX 4 /* Transmit buffer */
45#define UART_IER 8 /* Interrupt Enable Register */
46#define UART_IIR 0xC /* Interrupt ID Register */
47#define UART_FCR 0x10 /* FIFO Control Register */
48#define UART_LCR 0x14 /* Line Control Register */
49#define UART_MCR 0x18 /* Modem Control Register */
50#define UART_LSR 0x1C /* Line Status Register */
51#define UART_MSR 0x20 /* Modem Status Register */
52#define UART_CLK 0x28 /* Baud Rat4e Clock Divider */
53#define UART_MOD_CNTRL 0x100 /* Module Control */
54
55/* memory-mapped read/write of the port */
56#define UART16550_READ(y) (au_readl(DEBUG_BASE + y) & 0xff)
57#define UART16550_WRITE(y,z) (au_writel(z&0xff, DEBUG_BASE + y))
58
59extern unsigned long get_au1x00_uart_baud_base(void);
60extern unsigned long cal_r4koff(void);
61
62void debugInit(uint32 baud, uint8 data, uint8 parity, uint8 stop)
63{
64
65 if (UART16550_READ(UART_MOD_CNTRL) != 0x3) {
66 UART16550_WRITE(UART_MOD_CNTRL, 3);
67 }
68 cal_r4koff();
69
70 /* disable interrupts */
71 UART16550_WRITE(UART_IER, 0);
72
73 /* set up baud rate */
74 {
75 uint32 divisor;
76
77 /* set divisor */
78 divisor = get_au1x00_uart_baud_base() / baud;
79 UART16550_WRITE(UART_CLK, divisor & 0xffff);
80 }
81
82 /* set data format */
83 UART16550_WRITE(UART_LCR, (data | parity | stop));
84}
85
86static int remoteDebugInitialized = 0;
87
88uint8 getDebugChar(void)
89{
90 if (!remoteDebugInitialized) {
91 remoteDebugInitialized = 1;
92 debugInit(UART16550_BAUD_115200,
93 UART16550_DATA_8BIT,
94 UART16550_PARITY_NONE,
95 UART16550_STOP_1BIT);
96 }
97
98 while((UART16550_READ(UART_LSR) & 0x1) == 0);
99 return UART16550_READ(UART_RX);
100}
101
102
103int putDebugChar(uint8 byte)
104{
105// int i;
106
107 if (!remoteDebugInitialized) {
108 remoteDebugInitialized = 1;
109 debugInit(UART16550_BAUD_115200,
110 UART16550_DATA_8BIT,
111 UART16550_PARITY_NONE,
112 UART16550_STOP_1BIT);
113 }
114
115 while ((UART16550_READ(UART_LSR)&0x40) == 0);
116 UART16550_WRITE(UART_TX, byte);
117 //for (i=0;i<0xfff;i++);
118
119 return 1;
120}
121
122#endif