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Diffstat (limited to 'arch/m32r/platforms/mappi3/setup.c')
-rw-r--r--arch/m32r/platforms/mappi3/setup.c50
1 files changed, 10 insertions, 40 deletions
diff --git a/arch/m32r/platforms/mappi3/setup.c b/arch/m32r/platforms/mappi3/setup.c
index 882de25c6e8c..74098142cb2c 100644
--- a/arch/m32r/platforms/mappi3/setup.c
+++ b/arch/m32r/platforms/mappi3/setup.c
@@ -85,89 +85,59 @@ void __init init_IRQ(void)
85{ 85{
86#if defined(CONFIG_SMC91X) 86#if defined(CONFIG_SMC91X)
87 /* INT0 : LAN controller (SMC91111) */ 87 /* INT0 : LAN controller (SMC91111) */
88 irq_desc[M32R_IRQ_INT0].status = IRQ_DISABLED; 88 set_irq_chip(M32R_IRQ_INT0, &mappi3_irq_type);
89 irq_desc[M32R_IRQ_INT0].chip = &mappi3_irq_type;
90 irq_desc[M32R_IRQ_INT0].action = 0;
91 irq_desc[M32R_IRQ_INT0].depth = 1;
92 icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; 89 icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
93 disable_mappi3_irq(M32R_IRQ_INT0); 90 disable_mappi3_irq(M32R_IRQ_INT0);
94#endif /* CONFIG_SMC91X */ 91#endif /* CONFIG_SMC91X */
95 92
96 /* MFT2 : system timer */ 93 /* MFT2 : system timer */
97 irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED; 94 set_irq_chip(M32R_IRQ_MFT2, &mappi3_irq_type);
98 irq_desc[M32R_IRQ_MFT2].chip = &mappi3_irq_type;
99 irq_desc[M32R_IRQ_MFT2].action = 0;
100 irq_desc[M32R_IRQ_MFT2].depth = 1;
101 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; 95 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
102 disable_mappi3_irq(M32R_IRQ_MFT2); 96 disable_mappi3_irq(M32R_IRQ_MFT2);
103 97
104#ifdef CONFIG_SERIAL_M32R_SIO 98#ifdef CONFIG_SERIAL_M32R_SIO
105 /* SIO0_R : uart receive data */ 99 /* SIO0_R : uart receive data */
106 irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED; 100 set_irq_chip(M32R_IRQ_SIO0_R, &mappi3_irq_type);
107 irq_desc[M32R_IRQ_SIO0_R].chip = &mappi3_irq_type;
108 irq_desc[M32R_IRQ_SIO0_R].action = 0;
109 irq_desc[M32R_IRQ_SIO0_R].depth = 1;
110 icu_data[M32R_IRQ_SIO0_R].icucr = 0; 101 icu_data[M32R_IRQ_SIO0_R].icucr = 0;
111 disable_mappi3_irq(M32R_IRQ_SIO0_R); 102 disable_mappi3_irq(M32R_IRQ_SIO0_R);
112 103
113 /* SIO0_S : uart send data */ 104 /* SIO0_S : uart send data */
114 irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED; 105 set_irq_chip(M32R_IRQ_SIO0_S, &mappi3_irq_type);
115 irq_desc[M32R_IRQ_SIO0_S].chip = &mappi3_irq_type;
116 irq_desc[M32R_IRQ_SIO0_S].action = 0;
117 irq_desc[M32R_IRQ_SIO0_S].depth = 1;
118 icu_data[M32R_IRQ_SIO0_S].icucr = 0; 106 icu_data[M32R_IRQ_SIO0_S].icucr = 0;
119 disable_mappi3_irq(M32R_IRQ_SIO0_S); 107 disable_mappi3_irq(M32R_IRQ_SIO0_S);
120 /* SIO1_R : uart receive data */ 108 /* SIO1_R : uart receive data */
121 irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED; 109 set_irq_chip(M32R_IRQ_SIO1_R, &mappi3_irq_type);
122 irq_desc[M32R_IRQ_SIO1_R].chip = &mappi3_irq_type;
123 irq_desc[M32R_IRQ_SIO1_R].action = 0;
124 irq_desc[M32R_IRQ_SIO1_R].depth = 1;
125 icu_data[M32R_IRQ_SIO1_R].icucr = 0; 110 icu_data[M32R_IRQ_SIO1_R].icucr = 0;
126 disable_mappi3_irq(M32R_IRQ_SIO1_R); 111 disable_mappi3_irq(M32R_IRQ_SIO1_R);
127 112
128 /* SIO1_S : uart send data */ 113 /* SIO1_S : uart send data */
129 irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED; 114 set_irq_chip(M32R_IRQ_SIO1_S, &mappi3_irq_type);
130 irq_desc[M32R_IRQ_SIO1_S].chip = &mappi3_irq_type;
131 irq_desc[M32R_IRQ_SIO1_S].action = 0;
132 irq_desc[M32R_IRQ_SIO1_S].depth = 1;
133 icu_data[M32R_IRQ_SIO1_S].icucr = 0; 115 icu_data[M32R_IRQ_SIO1_S].icucr = 0;
134 disable_mappi3_irq(M32R_IRQ_SIO1_S); 116 disable_mappi3_irq(M32R_IRQ_SIO1_S);
135#endif /* CONFIG_M32R_USE_DBG_CONSOLE */ 117#endif /* CONFIG_M32R_USE_DBG_CONSOLE */
136 118
137#if defined(CONFIG_USB) 119#if defined(CONFIG_USB)
138 /* INT1 : USB Host controller interrupt */ 120 /* INT1 : USB Host controller interrupt */
139 irq_desc[M32R_IRQ_INT1].status = IRQ_DISABLED; 121 set_irq_chip(M32R_IRQ_INT1, &mappi3_irq_type);
140 irq_desc[M32R_IRQ_INT1].chip = &mappi3_irq_type;
141 irq_desc[M32R_IRQ_INT1].action = 0;
142 irq_desc[M32R_IRQ_INT1].depth = 1;
143 icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_ISMOD01; 122 icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_ISMOD01;
144 disable_mappi3_irq(M32R_IRQ_INT1); 123 disable_mappi3_irq(M32R_IRQ_INT1);
145#endif /* CONFIG_USB */ 124#endif /* CONFIG_USB */
146 125
147 /* CFC IREQ */ 126 /* CFC IREQ */
148 irq_desc[PLD_IRQ_CFIREQ].status = IRQ_DISABLED; 127 set_irq_chip(PLD_IRQ_CFIREQ, &mappi3_irq_type);
149 irq_desc[PLD_IRQ_CFIREQ].chip = &mappi3_irq_type;
150 irq_desc[PLD_IRQ_CFIREQ].action = 0;
151 irq_desc[PLD_IRQ_CFIREQ].depth = 1; /* disable nested irq */
152 icu_data[PLD_IRQ_CFIREQ].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD01; 128 icu_data[PLD_IRQ_CFIREQ].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD01;
153 disable_mappi3_irq(PLD_IRQ_CFIREQ); 129 disable_mappi3_irq(PLD_IRQ_CFIREQ);
154 130
155#if defined(CONFIG_M32R_CFC) 131#if defined(CONFIG_M32R_CFC)
156 /* ICUCR41: CFC Insert & eject */ 132 /* ICUCR41: CFC Insert & eject */
157 irq_desc[PLD_IRQ_CFC_INSERT].status = IRQ_DISABLED; 133 set_irq_chip(PLD_IRQ_CFC_INSERT, &mappi3_irq_type);
158 irq_desc[PLD_IRQ_CFC_INSERT].chip = &mappi3_irq_type;
159 irq_desc[PLD_IRQ_CFC_INSERT].action = 0;
160 irq_desc[PLD_IRQ_CFC_INSERT].depth = 1; /* disable nested irq */
161 icu_data[PLD_IRQ_CFC_INSERT].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD00; 134 icu_data[PLD_IRQ_CFC_INSERT].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD00;
162 disable_mappi3_irq(PLD_IRQ_CFC_INSERT); 135 disable_mappi3_irq(PLD_IRQ_CFC_INSERT);
163 136
164#endif /* CONFIG_M32R_CFC */ 137#endif /* CONFIG_M32R_CFC */
165 138
166 /* IDE IREQ */ 139 /* IDE IREQ */
167 irq_desc[PLD_IRQ_IDEIREQ].status = IRQ_DISABLED; 140 set_irq_chip(PLD_IRQ_IDEIREQ, &mappi3_irq_type);
168 irq_desc[PLD_IRQ_IDEIREQ].chip = &mappi3_irq_type;
169 irq_desc[PLD_IRQ_IDEIREQ].action = 0;
170 irq_desc[PLD_IRQ_IDEIREQ].depth = 1; /* disable nested irq */
171 icu_data[PLD_IRQ_IDEIREQ].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; 141 icu_data[PLD_IRQ_IDEIREQ].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
172 disable_mappi3_irq(PLD_IRQ_IDEIREQ); 142 disable_mappi3_irq(PLD_IRQ_IDEIREQ);
173 143