aboutsummaryrefslogtreecommitdiffstats
path: root/arch/m32r/platforms/mappi/setup.c
diff options
context:
space:
mode:
Diffstat (limited to 'arch/m32r/platforms/mappi/setup.c')
-rw-r--r--arch/m32r/platforms/mappi/setup.c41
1 files changed, 8 insertions, 33 deletions
diff --git a/arch/m32r/platforms/mappi/setup.c b/arch/m32r/platforms/mappi/setup.c
index ea00c84d6b1b..bc3fdaf21ca2 100644
--- a/arch/m32r/platforms/mappi/setup.c
+++ b/arch/m32r/platforms/mappi/setup.c
@@ -45,7 +45,6 @@ static void mask_and_ack_mappi(unsigned int irq)
45 45
46static void end_mappi_irq(unsigned int irq) 46static void end_mappi_irq(unsigned int irq)
47{ 47{
48 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
49 enable_mappi_irq(irq); 48 enable_mappi_irq(irq);
50} 49}
51 50
@@ -85,70 +84,46 @@ void __init init_IRQ(void)
85 84
86#ifdef CONFIG_NE2000 85#ifdef CONFIG_NE2000
87 /* INT0 : LAN controller (RTL8019AS) */ 86 /* INT0 : LAN controller (RTL8019AS) */
88 irq_desc[M32R_IRQ_INT0].status = IRQ_DISABLED; 87 set_irq_chip(M32R_IRQ_INT0, &mappi_irq_type);
89 irq_desc[M32R_IRQ_INT0].chip = &mappi_irq_type;
90 irq_desc[M32R_IRQ_INT0].action = NULL;
91 irq_desc[M32R_IRQ_INT0].depth = 1;
92 icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD11; 88 icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD11;
93 disable_mappi_irq(M32R_IRQ_INT0); 89 disable_mappi_irq(M32R_IRQ_INT0);
94#endif /* CONFIG_M32R_NE2000 */ 90#endif /* CONFIG_M32R_NE2000 */
95 91
96 /* MFT2 : system timer */ 92 /* MFT2 : system timer */
97 irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED; 93 set_irq_chip(M32R_IRQ_MFT2, &mappi_irq_type);
98 irq_desc[M32R_IRQ_MFT2].chip = &mappi_irq_type;
99 irq_desc[M32R_IRQ_MFT2].action = NULL;
100 irq_desc[M32R_IRQ_MFT2].depth = 1;
101 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; 94 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
102 disable_mappi_irq(M32R_IRQ_MFT2); 95 disable_mappi_irq(M32R_IRQ_MFT2);
103 96
104#ifdef CONFIG_SERIAL_M32R_SIO 97#ifdef CONFIG_SERIAL_M32R_SIO
105 /* SIO0_R : uart receive data */ 98 /* SIO0_R : uart receive data */
106 irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED; 99 set_irq_chip(M32R_IRQ_SIO0_R, &mappi_irq_type);
107 irq_desc[M32R_IRQ_SIO0_R].chip = &mappi_irq_type;
108 irq_desc[M32R_IRQ_SIO0_R].action = NULL;
109 irq_desc[M32R_IRQ_SIO0_R].depth = 1;
110 icu_data[M32R_IRQ_SIO0_R].icucr = 0; 100 icu_data[M32R_IRQ_SIO0_R].icucr = 0;
111 disable_mappi_irq(M32R_IRQ_SIO0_R); 101 disable_mappi_irq(M32R_IRQ_SIO0_R);
112 102
113 /* SIO0_S : uart send data */ 103 /* SIO0_S : uart send data */
114 irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED; 104 set_irq_chip(M32R_IRQ_SIO0_S, &mappi_irq_type);
115 irq_desc[M32R_IRQ_SIO0_S].chip = &mappi_irq_type;
116 irq_desc[M32R_IRQ_SIO0_S].action = NULL;
117 irq_desc[M32R_IRQ_SIO0_S].depth = 1;
118 icu_data[M32R_IRQ_SIO0_S].icucr = 0; 105 icu_data[M32R_IRQ_SIO0_S].icucr = 0;
119 disable_mappi_irq(M32R_IRQ_SIO0_S); 106 disable_mappi_irq(M32R_IRQ_SIO0_S);
120 107
121 /* SIO1_R : uart receive data */ 108 /* SIO1_R : uart receive data */
122 irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED; 109 set_irq_chip(M32R_IRQ_SIO1_R, &mappi_irq_type);
123 irq_desc[M32R_IRQ_SIO1_R].chip = &mappi_irq_type;
124 irq_desc[M32R_IRQ_SIO1_R].action = NULL;
125 irq_desc[M32R_IRQ_SIO1_R].depth = 1;
126 icu_data[M32R_IRQ_SIO1_R].icucr = 0; 110 icu_data[M32R_IRQ_SIO1_R].icucr = 0;
127 disable_mappi_irq(M32R_IRQ_SIO1_R); 111 disable_mappi_irq(M32R_IRQ_SIO1_R);
128 112
129 /* SIO1_S : uart send data */ 113 /* SIO1_S : uart send data */
130 irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED; 114 set_irq_chip(M32R_IRQ_SIO1_S, &mappi_irq_type);
131 irq_desc[M32R_IRQ_SIO1_S].chip = &mappi_irq_type;
132 irq_desc[M32R_IRQ_SIO1_S].action = NULL;
133 irq_desc[M32R_IRQ_SIO1_S].depth = 1;
134 icu_data[M32R_IRQ_SIO1_S].icucr = 0; 115 icu_data[M32R_IRQ_SIO1_S].icucr = 0;
135 disable_mappi_irq(M32R_IRQ_SIO1_S); 116 disable_mappi_irq(M32R_IRQ_SIO1_S);
136#endif /* CONFIG_SERIAL_M32R_SIO */ 117#endif /* CONFIG_SERIAL_M32R_SIO */
137 118
138#if defined(CONFIG_M32R_PCC) 119#if defined(CONFIG_M32R_PCC)
139 /* INT1 : pccard0 interrupt */ 120 /* INT1 : pccard0 interrupt */
140 irq_desc[M32R_IRQ_INT1].status = IRQ_DISABLED; 121 set_irq_chip(M32R_IRQ_INT1, &mappi_irq_type);
141 irq_desc[M32R_IRQ_INT1].chip = &mappi_irq_type;
142 irq_desc[M32R_IRQ_INT1].action = NULL;
143 irq_desc[M32R_IRQ_INT1].depth = 1;
144 icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_IEN | M32R_ICUCR_ISMOD00; 122 icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_IEN | M32R_ICUCR_ISMOD00;
145 disable_mappi_irq(M32R_IRQ_INT1); 123 disable_mappi_irq(M32R_IRQ_INT1);
146 124
147 /* INT2 : pccard1 interrupt */ 125 /* INT2 : pccard1 interrupt */
148 irq_desc[M32R_IRQ_INT2].status = IRQ_DISABLED; 126 set_irq_chip(M32R_IRQ_INT2, &mappi_irq_type);
149 irq_desc[M32R_IRQ_INT2].chip = &mappi_irq_type;
150 irq_desc[M32R_IRQ_INT2].action = NULL;
151 irq_desc[M32R_IRQ_INT2].depth = 1;
152 icu_data[M32R_IRQ_INT2].icucr = M32R_ICUCR_IEN | M32R_ICUCR_ISMOD00; 127 icu_data[M32R_IRQ_INT2].icucr = M32R_ICUCR_IEN | M32R_ICUCR_ISMOD00;
153 disable_mappi_irq(M32R_IRQ_INT2); 128 disable_mappi_irq(M32R_IRQ_INT2);
154#endif /* CONFIG_M32RPCC */ 129#endif /* CONFIG_M32RPCC */