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-rw-r--r--arch/cris/arch-v10/kernel/time.c9
1 files changed, 0 insertions, 9 deletions
diff --git a/arch/cris/arch-v10/kernel/time.c b/arch/cris/arch-v10/kernel/time.c
index 20c85b5dc7d0..bcffcb6a9415 100644
--- a/arch/cris/arch-v10/kernel/time.c
+++ b/arch/cris/arch-v10/kernel/time.c
@@ -19,16 +19,12 @@
19#include <asm/signal.h> 19#include <asm/signal.h>
20#include <asm/io.h> 20#include <asm/io.h>
21#include <asm/delay.h> 21#include <asm/delay.h>
22#include <asm/rtc.h>
23#include <asm/irq_regs.h> 22#include <asm/irq_regs.h>
24 23
25/* define this if you need to use print_timestamp */ 24/* define this if you need to use print_timestamp */
26/* it will make jiffies at 96 hz instead of 100 hz though */ 25/* it will make jiffies at 96 hz instead of 100 hz though */
27#undef USE_CASCADE_TIMERS 26#undef USE_CASCADE_TIMERS
28 27
29extern int set_rtc_mmss(unsigned long nowtime);
30extern int have_rtc;
31
32unsigned long get_ns_in_jiffie(void) 28unsigned long get_ns_in_jiffie(void)
33{ 29{
34 unsigned char timer_count, t1; 30 unsigned char timer_count, t1;
@@ -203,11 +199,6 @@ time_init(void)
203 */ 199 */
204 loops_per_usec = 50; 200 loops_per_usec = 50;
205 201
206 if(RTC_INIT() < 0)
207 have_rtc = 0;
208 else
209 have_rtc = 1;
210
211 /* Setup the etrax timers 202 /* Setup the etrax timers
212 * Base frequency is 25000 hz, divider 250 -> 100 HZ 203 * Base frequency is 25000 hz, divider 250 -> 100 HZ
213 * In normal mode, we use timer0, so timer1 is free. In cascade 204 * In normal mode, we use timer0, so timer1 is free. In cascade