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-rw-r--r--arch/arm/mach-omap2/omap_l3_noc.c130
-rw-r--r--arch/arm/mach-omap2/omap_l3_noc.h224
-rw-r--r--arch/arm/mach-omap2/omap_l3_smx.c91
-rw-r--r--arch/arm/mach-omap2/omap_l3_smx.h164
-rw-r--r--arch/arm/plat-omap/include/plat/io.h4
5 files changed, 322 insertions, 291 deletions
diff --git a/arch/arm/mach-omap2/omap_l3_noc.c b/arch/arm/mach-omap2/omap_l3_noc.c
index 7b9f1909ddb2..07a3d3ede768 100644
--- a/arch/arm/mach-omap2/omap_l3_noc.c
+++ b/arch/arm/mach-omap2/omap_l3_noc.c
@@ -1,25 +1,25 @@
1/* 1/*
2 * OMAP4XXX L3 Interconnect error handling driver 2 * OMAP4XXX L3 Interconnect error handling driver
3 * 3 *
4 * Copyright (C) 2011 Texas Corporation 4 * Copyright (C) 2011 Texas Corporation
5 * Santosh Shilimkar <santosh.shilimkar@ti.com> 5 * Santosh Shilimkar <santosh.shilimkar@ti.com>
6 * Sricharan <r.sricharan@ti.com> 6 * Sricharan <r.sricharan@ti.com>
7 * 7 *
8 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by 9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or 10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version. 11 * (at your option) any later version.
12 * 12 *
13 * This program is distributed in the hope that it will be useful, 13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details. 16 * GNU General Public License for more details.
17 * 17 *
18 * You should have received a copy of the GNU General Public License 18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software 19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
21 * USA 21 * USA
22 */ 22 */
23#include <linux/init.h> 23#include <linux/init.h>
24#include <linux/io.h> 24#include <linux/io.h>
25#include <linux/platform_device.h> 25#include <linux/platform_device.h>
@@ -55,12 +55,12 @@
55static irqreturn_t l3_interrupt_handler(int irq, void *_l3) 55static irqreturn_t l3_interrupt_handler(int irq, void *_l3)
56{ 56{
57 57
58 struct omap4_l3 *l3 = _l3; 58 struct omap4_l3 *l3 = _l3;
59 int inttype, i, j; 59 int inttype, i, k;
60 int err_src = 0; 60 int err_src = 0;
61 u32 std_err_main_addr, std_err_main, err_reg; 61 u32 std_err_main, err_reg, clear, masterid;
62 u32 base, slave_addr, clear; 62 void __iomem *base, *l3_targ_base;
63 char *source_name; 63 char *target_name, *master_name = "UN IDENTIFIED";
64 64
65 /* Get the Type of interrupt */ 65 /* Get the Type of interrupt */
66 inttype = irq == l3->app_irq ? L3_APPLICATION_ERROR : L3_DEBUG_ERROR; 66 inttype = irq == l3->app_irq ? L3_APPLICATION_ERROR : L3_DEBUG_ERROR;
@@ -70,43 +70,50 @@ static irqreturn_t l3_interrupt_handler(int irq, void *_l3)
70 * Read the regerr register of the clock domain 70 * Read the regerr register of the clock domain
71 * to determine the source 71 * to determine the source
72 */ 72 */
73 base = (u32)l3->l3_base[i]; 73 base = l3->l3_base[i];
74 err_reg = readl(base + l3_flagmux[i] + (inttype << 3)); 74 err_reg = __raw_readl(base + l3_flagmux[i] +
75 + L3_FLAGMUX_REGERR0 + (inttype << 3));
75 76
76 /* Get the corresponding error and analyse */ 77 /* Get the corresponding error and analyse */
77 if (err_reg) { 78 if (err_reg) {
78 /* Identify the source from control status register */ 79 /* Identify the source from control status register */
79 for (j = 0; !(err_reg & (1 << j)); j++) 80 err_src = __ffs(err_reg);
80 ;
81 81
82 err_src = j;
83 /* Read the stderrlog_main_source from clk domain */ 82 /* Read the stderrlog_main_source from clk domain */
84 std_err_main_addr = base + *(l3_targ[i] + err_src); 83 l3_targ_base = base + *(l3_targ[i] + err_src);
85 std_err_main = readl(std_err_main_addr); 84 std_err_main = __raw_readl(l3_targ_base +
85 L3_TARG_STDERRLOG_MAIN);
86 masterid = __raw_readl(l3_targ_base +
87 L3_TARG_STDERRLOG_MSTADDR);
86 88
87 switch (std_err_main & CUSTOM_ERROR) { 89 switch (std_err_main & CUSTOM_ERROR) {
88 case STANDARD_ERROR: 90 case STANDARD_ERROR:
89 source_name = 91 target_name =
90 l3_targ_stderrlog_main_name[i][err_src]; 92 l3_targ_inst_name[i][err_src];
91 93 WARN(true, "L3 standard error: TARGET:%s at address 0x%x\n",
92 slave_addr = std_err_main_addr + 94 target_name,
93 L3_SLAVE_ADDRESS_OFFSET; 95 __raw_readl(l3_targ_base +
94 WARN(true, "L3 standard error: SOURCE:%s at address 0x%x\n", 96 L3_TARG_STDERRLOG_SLVOFSLSB));
95 source_name, readl(slave_addr));
96 /* clear the std error log*/ 97 /* clear the std error log*/
97 clear = std_err_main | CLEAR_STDERR_LOG; 98 clear = std_err_main | CLEAR_STDERR_LOG;
98 writel(clear, std_err_main_addr); 99 writel(clear, l3_targ_base +
100 L3_TARG_STDERRLOG_MAIN);
99 break; 101 break;
100 102
101 case CUSTOM_ERROR: 103 case CUSTOM_ERROR:
102 source_name = 104 target_name =
103 l3_targ_stderrlog_main_name[i][err_src]; 105 l3_targ_inst_name[i][err_src];
104 106 for (k = 0; k < NUM_OF_L3_MASTERS; k++) {
105 WARN(true, "CUSTOM SRESP error with SOURCE:%s\n", 107 if (masterid == l3_masters[k].id)
106 source_name); 108 master_name =
109 l3_masters[k].name;
110 }
111 WARN(true, "L3 custom error: MASTER:%s TARGET:%s\n",
112 master_name, target_name);
107 /* clear the std error log*/ 113 /* clear the std error log*/
108 clear = std_err_main | CLEAR_STDERR_LOG; 114 clear = std_err_main | CLEAR_STDERR_LOG;
109 writel(clear, std_err_main_addr); 115 writel(clear, l3_targ_base +
116 L3_TARG_STDERRLOG_MAIN);
110 break; 117 break;
111 118
112 default: 119 default:
@@ -122,10 +129,9 @@ static irqreturn_t l3_interrupt_handler(int irq, void *_l3)
122 129
123static int __init omap4_l3_probe(struct platform_device *pdev) 130static int __init omap4_l3_probe(struct platform_device *pdev)
124{ 131{
125 static struct omap4_l3 *l3; 132 static struct omap4_l3 *l3;
126 struct resource *res; 133 struct resource *res;
127 int ret; 134 int ret;
128 int irq;
129 135
130 l3 = kzalloc(sizeof(*l3), GFP_KERNEL); 136 l3 = kzalloc(sizeof(*l3), GFP_KERNEL);
131 if (!l3) 137 if (!l3)
@@ -177,27 +183,25 @@ static int __init omap4_l3_probe(struct platform_device *pdev)
177 /* 183 /*
178 * Setup interrupt Handlers 184 * Setup interrupt Handlers
179 */ 185 */
180 irq = platform_get_irq(pdev, 0); 186 l3->debug_irq = platform_get_irq(pdev, 0);
181 ret = request_irq(irq, 187 ret = request_irq(l3->debug_irq,
182 l3_interrupt_handler, 188 l3_interrupt_handler,
183 IRQF_DISABLED, "l3-dbg-irq", l3); 189 IRQF_DISABLED, "l3-dbg-irq", l3);
184 if (ret) { 190 if (ret) {
185 pr_crit("L3: request_irq failed to register for 0x%x\n", 191 pr_crit("L3: request_irq failed to register for 0x%x\n",
186 OMAP44XX_IRQ_L3_DBG); 192 OMAP44XX_IRQ_L3_DBG);
187 goto err3; 193 goto err3;
188 } 194 }
189 l3->debug_irq = irq;
190 195
191 irq = platform_get_irq(pdev, 1); 196 l3->app_irq = platform_get_irq(pdev, 1);
192 ret = request_irq(irq, 197 ret = request_irq(l3->app_irq,
193 l3_interrupt_handler, 198 l3_interrupt_handler,
194 IRQF_DISABLED, "l3-app-irq", l3); 199 IRQF_DISABLED, "l3-app-irq", l3);
195 if (ret) { 200 if (ret) {
196 pr_crit("L3: request_irq failed to register for 0x%x\n", 201 pr_crit("L3: request_irq failed to register for 0x%x\n",
197 OMAP44XX_IRQ_L3_APP); 202 OMAP44XX_IRQ_L3_APP);
198 goto err4; 203 goto err4;
199 } 204 }
200 l3->app_irq = irq;
201 205
202 return 0; 206 return 0;
203 207
@@ -216,7 +220,7 @@ err0:
216 220
217static int __exit omap4_l3_remove(struct platform_device *pdev) 221static int __exit omap4_l3_remove(struct platform_device *pdev)
218{ 222{
219 struct omap4_l3 *l3 = platform_get_drvdata(pdev); 223 struct omap4_l3 *l3 = platform_get_drvdata(pdev);
220 224
221 free_irq(l3->app_irq, l3); 225 free_irq(l3->app_irq, l3);
222 free_irq(l3->debug_irq, l3); 226 free_irq(l3->debug_irq, l3);
@@ -229,9 +233,9 @@ static int __exit omap4_l3_remove(struct platform_device *pdev)
229} 233}
230 234
231static struct platform_driver omap4_l3_driver = { 235static struct platform_driver omap4_l3_driver = {
232 .remove = __exit_p(omap4_l3_remove), 236 .remove = __exit_p(omap4_l3_remove),
233 .driver = { 237 .driver = {
234 .name = "omap_l3_noc", 238 .name = "omap_l3_noc",
235 }, 239 },
236}; 240};
237 241
diff --git a/arch/arm/mach-omap2/omap_l3_noc.h b/arch/arm/mach-omap2/omap_l3_noc.h
index 359b83348aed..90b50984cd2e 100644
--- a/arch/arm/mach-omap2/omap_l3_noc.h
+++ b/arch/arm/mach-omap2/omap_l3_noc.h
@@ -1,132 +1,162 @@
1 /* 1/*
2 * OMAP4XXX L3 Interconnect error handling driver header 2 * OMAP4XXX L3 Interconnect error handling driver header
3 * 3 *
4 * Copyright (C) 2011 Texas Corporation 4 * Copyright (C) 2011 Texas Corporation
5 * Santosh Shilimkar <santosh.shilimkar@ti.com> 5 * Santosh Shilimkar <santosh.shilimkar@ti.com>
6 * sricharan <r.sricharan@ti.com> 6 * sricharan <r.sricharan@ti.com>
7 * 7 *
8 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by 9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or 10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version. 11 * (at your option) any later version.
12 * 12 *
13 * This program is distributed in the hope that it will be useful, 13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details. 16 * GNU General Public License for more details.
17 * 17 *
18 * You should have received a copy of the GNU General Public License 18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software 19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
21 * USA 21 * USA
22 */ 22 */
23#ifndef __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H 23#ifndef __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H
24#define __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H 24#define __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H
25 25
26/*
27 * L3 register offsets
28 */
29#define L3_MODULES 3 26#define L3_MODULES 3
30#define CLEAR_STDERR_LOG (1 << 31) 27#define CLEAR_STDERR_LOG (1 << 31)
31#define CUSTOM_ERROR 0x2 28#define CUSTOM_ERROR 0x2
32#define STANDARD_ERROR 0x0 29#define STANDARD_ERROR 0x0
33#define INBAND_ERROR 0x0 30#define INBAND_ERROR 0x0
34#define EMIF_KERRLOG_OFFSET 0x10
35#define L3_SLAVE_ADDRESS_OFFSET 0x14
36#define LOGICAL_ADDR_ERRORLOG 0x4
37#define L3_APPLICATION_ERROR 0x0 31#define L3_APPLICATION_ERROR 0x0
38#define L3_DEBUG_ERROR 0x1 32#define L3_DEBUG_ERROR 0x1
39 33
40u32 l3_flagmux[L3_MODULES] = { 34/* L3 TARG register offsets */
41 0x50C, 35#define L3_TARG_STDERRLOG_MAIN 0x48
42 0x100C, 36#define L3_TARG_STDERRLOG_SLVOFSLSB 0x5c
43 0X020C 37#define L3_TARG_STDERRLOG_MSTADDR 0x68
38#define L3_FLAGMUX_REGERR0 0xc
39
40#define NUM_OF_L3_MASTERS (sizeof(l3_masters)/sizeof(l3_masters[0]))
41
42static u32 l3_flagmux[L3_MODULES] = {
43 0x500,
44 0x1000,
45 0X0200
44}; 46};
45 47
46/* 48/* L3 Target standard Error register offsets */
47 * L3 Target standard Error register offsets 49static u32 l3_targ_inst_clk1[] = {
48 */ 50 0x100, /* DMM1 */
49u32 l3_targ_stderrlog_main_clk1[] = { 51 0x200, /* DMM2 */
50 0x148, /* DMM1 */ 52 0x300, /* ABE */
51 0x248, /* DMM2 */ 53 0x400, /* L4CFG */
52 0x348, /* ABE */ 54 0x600 /* CLK2 PWR DISC */
53 0x448, /* L4CFG */
54 0x648 /* CLK2 PWR DISC */
55}; 55};
56 56
57u32 l3_targ_stderrlog_main_clk2[] = { 57static u32 l3_targ_inst_clk2[] = {
58 0x548, /* CORTEX M3 */ 58 0x500, /* CORTEX M3 */
59 0x348, /* DSS */ 59 0x300, /* DSS */
60 0x148, /* GPMC */ 60 0x100, /* GPMC */
61 0x448, /* ISS */ 61 0x400, /* ISS */
62 0x748, /* IVAHD */ 62 0x700, /* IVAHD */
63 0xD48, /* missing in TRM corresponds to AES1*/ 63 0xD00, /* missing in TRM corresponds to AES1*/
64 0x948, /* L4 PER0*/ 64 0x900, /* L4 PER0*/
65 0x248, /* OCMRAM */ 65 0x200, /* OCMRAM */
66 0x148, /* missing in TRM corresponds to GPMC sERROR*/ 66 0x100, /* missing in TRM corresponds to GPMC sERROR*/
67 0x648, /* SGX */ 67 0x600, /* SGX */
68 0x848, /* SL2 */ 68 0x800, /* SL2 */
69 0x1648, /* C2C */ 69 0x1600, /* C2C */
70 0x1148, /* missing in TRM corresponds PWR DISC CLK1*/ 70 0x1100, /* missing in TRM corresponds PWR DISC CLK1*/
71 0xF48, /* missing in TRM corrsponds to SHA1*/ 71 0xF00, /* missing in TRM corrsponds to SHA1*/
72 0xE48, /* missing in TRM corresponds to AES2*/ 72 0xE00, /* missing in TRM corresponds to AES2*/
73 0xC48, /* L4 PER3 */ 73 0xC00, /* L4 PER3 */
74 0xA48, /* L4 PER1*/ 74 0xA00, /* L4 PER1*/
75 0xB48 /* L4 PER2*/ 75 0xB00 /* L4 PER2*/
76}; 76};
77 77
78u32 l3_targ_stderrlog_main_clk3[] = { 78static u32 l3_targ_inst_clk3[] = {
79 0x0148 /* EMUSS */ 79 0x0100 /* EMUSS */
80}; 80};
81 81
82char *l3_targ_stderrlog_main_name[L3_MODULES][18] = { 82static struct l3_masters_data {
83 u32 id;
84 char name[10];
85} l3_masters[] = {
86 { 0x0 , "MPU"},
87 { 0x10, "CS_ADP"},
88 { 0x14, "xxx"},
89 { 0x20, "DSP"},
90 { 0x30, "IVAHD"},
91 { 0x40, "ISS"},
92 { 0x44, "DucatiM3"},
93 { 0x48, "FaceDetect"},
94 { 0x50, "SDMA_Rd"},
95 { 0x54, "SDMA_Wr"},
96 { 0x58, "xxx"},
97 { 0x5C, "xxx"},
98 { 0x60, "SGX"},
99 { 0x70, "DSS"},
100 { 0x80, "C2C"},
101 { 0x88, "xxx"},
102 { 0x8C, "xxx"},
103 { 0x90, "HSI"},
104 { 0xA0, "MMC1"},
105 { 0xA4, "MMC2"},
106 { 0xA8, "MMC6"},
107 { 0xB0, "UNIPRO1"},
108 { 0xC0, "USBHOSTHS"},
109 { 0xC4, "USBOTGHS"},
110 { 0xC8, "USBHOSTFS"}
111};
112
113static char *l3_targ_inst_name[L3_MODULES][18] = {
83 { 114 {
84 "DMM1", 115 "DMM1",
85 "DMM2", 116 "DMM2",
86 "ABE", 117 "ABE",
87 "L4CFG", 118 "L4CFG",
88 "CLK2 PWR DISC", 119 "CLK2 PWR DISC",
89 }, 120 },
90 { 121 {
91 "CORTEX M3" , 122 "CORTEX M3" ,
92 "DSS ", 123 "DSS ",
93 "GPMC ", 124 "GPMC ",
94 "ISS ", 125 "ISS ",
95 "IVAHD ", 126 "IVAHD ",
96 "AES1", 127 "AES1",
97 "L4 PER0", 128 "L4 PER0",
98 "OCMRAM ", 129 "OCMRAM ",
99 "GPMC sERROR", 130 "GPMC sERROR",
100 "SGX ", 131 "SGX ",
101 "SL2 ", 132 "SL2 ",
102 "C2C ", 133 "C2C ",
103 "PWR DISC CLK1", 134 "PWR DISC CLK1",
104 "SHA1", 135 "SHA1",
105 "AES2", 136 "AES2",
106 "L4 PER3", 137 "L4 PER3",
107 "L4 PER1", 138 "L4 PER1",
108 "L4 PER2", 139 "L4 PER2",
109 }, 140 },
110 { 141 {
111 "EMUSS", 142 "EMUSS",
112 }, 143 },
113}; 144};
114 145
115u32 *l3_targ[L3_MODULES] = { 146static u32 *l3_targ[L3_MODULES] = {
116 l3_targ_stderrlog_main_clk1, 147 l3_targ_inst_clk1,
117 l3_targ_stderrlog_main_clk2, 148 l3_targ_inst_clk2,
118 l3_targ_stderrlog_main_clk3, 149 l3_targ_inst_clk3,
119}; 150};
120 151
121struct omap4_l3 { 152struct omap4_l3 {
122 struct device *dev; 153 struct device *dev;
123 struct clk *ick; 154 struct clk *ick;
124 155
125 /* memory base */ 156 /* memory base */
126 void __iomem *l3_base[4]; 157 void __iomem *l3_base[L3_MODULES];
127 158
128 int debug_irq; 159 int debug_irq;
129 int app_irq; 160 int app_irq;
130}; 161};
131
132#endif 162#endif
diff --git a/arch/arm/mach-omap2/omap_l3_smx.c b/arch/arm/mach-omap2/omap_l3_smx.c
index 873c0e33b512..a05a62f9ee5b 100644
--- a/arch/arm/mach-omap2/omap_l3_smx.c
+++ b/arch/arm/mach-omap2/omap_l3_smx.c
@@ -1,26 +1,26 @@
1 /* 1/*
2 * OMAP3XXX L3 Interconnect Driver 2 * OMAP3XXX L3 Interconnect Driver
3 * 3 *
4 * Copyright (C) 2011 Texas Corporation 4 * Copyright (C) 2011 Texas Corporation
5 * Felipe Balbi <balbi@ti.com> 5 * Felipe Balbi <balbi@ti.com>
6 * Santosh Shilimkar <santosh.shilimkar@ti.com> 6 * Santosh Shilimkar <santosh.shilimkar@ti.com>
7 * Sricharan <r.sricharan@ti.com> 7 * Sricharan <r.sricharan@ti.com>
8 * 8 *
9 * This program is free software; you can redistribute it and/or modify 9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by 10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or 11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version. 12 * (at your option) any later version.
13 * 13 *
14 * This program is distributed in the hope that it will be useful, 14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details. 17 * GNU General Public License for more details.
18 * 18 *
19 * You should have received a copy of the GNU General Public License 19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software 20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
22 * USA 22 * USA
23 */ 23 */
24 24
25#include <linux/kernel.h> 25#include <linux/kernel.h>
26#include <linux/slab.h> 26#include <linux/slab.h>
@@ -135,7 +135,7 @@ static char *omap3_l3_initiator_string(u8 initid)
135 } 135 }
136} 136}
137 137
138/** 138/*
139 * omap3_l3_block_irq - handles a register block's irq 139 * omap3_l3_block_irq - handles a register block's irq
140 * @l3: struct omap3_l3 * 140 * @l3: struct omap3_l3 *
141 * @base: register block base address 141 * @base: register block base address
@@ -150,30 +150,29 @@ static char *omap3_l3_initiator_string(u8 initid)
150static irqreturn_t omap3_l3_block_irq(struct omap3_l3 *l3, 150static irqreturn_t omap3_l3_block_irq(struct omap3_l3 *l3,
151 u64 error, int error_addr) 151 u64 error, int error_addr)
152{ 152{
153 u8 code = omap3_l3_decode_error_code(error); 153 u8 code = omap3_l3_decode_error_code(error);
154 u8 initid = omap3_l3_decode_initid(error); 154 u8 initid = omap3_l3_decode_initid(error);
155 u8 multi = error & L3_ERROR_LOG_MULTI; 155 u8 multi = error & L3_ERROR_LOG_MULTI;
156 u32 address = omap3_l3_decode_addr(error_addr); 156 u32 address = omap3_l3_decode_addr(error_addr);
157 157
158 WARN(true, "%s seen by %s %s at address %x\n", 158 WARN(true, "%s seen by %s %s at address %x\n",
159 omap3_l3_code_string(code), 159 omap3_l3_code_string(code),
160 omap3_l3_initiator_string(initid), 160 omap3_l3_initiator_string(initid),
161 multi ? "Multiple Errors" : "", 161 multi ? "Multiple Errors" : "", address);
162 address);
163 162
164 return IRQ_HANDLED; 163 return IRQ_HANDLED;
165} 164}
166 165
167static irqreturn_t omap3_l3_app_irq(int irq, void *_l3) 166static irqreturn_t omap3_l3_app_irq(int irq, void *_l3)
168{ 167{
169 struct omap3_l3 *l3 = _l3; 168 struct omap3_l3 *l3 = _l3;
170 u64 status, clear; 169 u64 status, clear;
171 u64 error; 170 u64 error;
172 u64 error_addr; 171 u64 error_addr;
173 u64 err_source = 0; 172 u64 err_source = 0;
174 void __iomem *base; 173 void __iomem *base;
175 int int_type; 174 int int_type;
176 irqreturn_t ret = IRQ_NONE; 175 irqreturn_t ret = IRQ_NONE;
177 176
178 int_type = irq == l3->app_irq ? L3_APPLICATION_ERROR : L3_DEBUG_ERROR; 177 int_type = irq == l3->app_irq ? L3_APPLICATION_ERROR : L3_DEBUG_ERROR;
179 if (!int_type) { 178 if (!int_type) {
@@ -191,14 +190,12 @@ static irqreturn_t omap3_l3_app_irq(int irq, void *_l3)
191 } 190 }
192 191
193 /* identify the error source */ 192 /* identify the error source */
194 for (err_source = 0; !(status & (1 << err_source)); err_source++) 193 err_source = __ffs(status);
195 ;
196 194
197 base = l3->rt + *(omap3_l3_bases[int_type] + err_source); 195 base = l3->rt + omap3_l3_bases[int_type][err_source];
198 error = omap3_l3_readll(base, L3_ERROR_LOG); 196 error = omap3_l3_readll(base, L3_ERROR_LOG);
199 if (error) { 197 if (error) {
200 error_addr = omap3_l3_readll(base, L3_ERROR_LOG_ADDR); 198 error_addr = omap3_l3_readll(base, L3_ERROR_LOG_ADDR);
201
202 ret |= omap3_l3_block_irq(l3, error, error_addr); 199 ret |= omap3_l3_block_irq(l3, error, error_addr);
203 } 200 }
204 201
@@ -215,9 +212,9 @@ static irqreturn_t omap3_l3_app_irq(int irq, void *_l3)
215 212
216static int __init omap3_l3_probe(struct platform_device *pdev) 213static int __init omap3_l3_probe(struct platform_device *pdev)
217{ 214{
218 struct omap3_l3 *l3; 215 struct omap3_l3 *l3;
219 struct resource *res; 216 struct resource *res;
220 int ret; 217 int ret;
221 218
222 l3 = kzalloc(sizeof(*l3), GFP_KERNEL); 219 l3 = kzalloc(sizeof(*l3), GFP_KERNEL);
223 if (!l3) 220 if (!l3)
diff --git a/arch/arm/mach-omap2/omap_l3_smx.h b/arch/arm/mach-omap2/omap_l3_smx.h
index ba2ed9a850cc..4f3cebca4179 100644
--- a/arch/arm/mach-omap2/omap_l3_smx.h
+++ b/arch/arm/mach-omap2/omap_l3_smx.h
@@ -1,26 +1,26 @@
1 /* 1/*
2 * OMAP3XXX L3 Interconnect Driver header 2 * OMAP3XXX L3 Interconnect Driver header
3 * 3 *
4 * Copyright (C) 2011 Texas Corporation 4 * Copyright (C) 2011 Texas Corporation
5 * Felipe Balbi <balbi@ti.com> 5 * Felipe Balbi <balbi@ti.com>
6 * Santosh Shilimkar <santosh.shilimkar@ti.com> 6 * Santosh Shilimkar <santosh.shilimkar@ti.com>
7 * sricharan <r.sricharan@ti.com> 7 * sricharan <r.sricharan@ti.com>
8 * 8 *
9 * This program is free software; you can redistribute it and/or modify 9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by 10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or 11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version. 12 * (at your option) any later version.
13 * 13 *
14 * This program is distributed in the hope that it will be useful, 14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details. 17 * GNU General Public License for more details.
18 * 18 *
19 * You should have received a copy of the GNU General Public License 19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software 20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
22 * USA 22 * USA
23 */ 23 */
24#ifndef __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H 24#ifndef __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H
25#define __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H 25#define __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H
26 26
@@ -40,7 +40,7 @@
40#define L3_SI_CONTROL 0x020 40#define L3_SI_CONTROL 0x020
41#define L3_SI_FLAG_STATUS_0 0x510 41#define L3_SI_FLAG_STATUS_0 0x510
42 42
43const u64 shift = 1; 43static const u64 shift = 1;
44 44
45#define L3_STATUS_0_MPUIA_BRST (shift << 0) 45#define L3_STATUS_0_MPUIA_BRST (shift << 0)
46#define L3_STATUS_0_MPUIA_RSP (shift << 1) 46#define L3_STATUS_0_MPUIA_RSP (shift << 1)
@@ -78,32 +78,32 @@ const u64 shift = 1;
78#define L3_STATUS_0_L4EMUTA_REQ (shift << 60) 78#define L3_STATUS_0_L4EMUTA_REQ (shift << 60)
79#define L3_STATUS_0_MAD2DTA_REQ (shift << 61) 79#define L3_STATUS_0_MAD2DTA_REQ (shift << 61)
80 80
81#define L3_STATUS_0_TIMEOUT_MASK (L3_STATUS_0_MPUIA_BRST \ 81#define L3_STATUS_0_TIMEOUT_MASK (L3_STATUS_0_MPUIA_BRST \
82 | L3_STATUS_0_MPUIA_RSP \ 82 | L3_STATUS_0_MPUIA_RSP \
83 | L3_STATUS_0_IVAIA_BRST \ 83 | L3_STATUS_0_IVAIA_BRST \
84 | L3_STATUS_0_IVAIA_RSP \ 84 | L3_STATUS_0_IVAIA_RSP \
85 | L3_STATUS_0_SGXIA_BRST \ 85 | L3_STATUS_0_SGXIA_BRST \
86 | L3_STATUS_0_SGXIA_RSP \ 86 | L3_STATUS_0_SGXIA_RSP \
87 | L3_STATUS_0_CAMIA_BRST \ 87 | L3_STATUS_0_CAMIA_BRST \
88 | L3_STATUS_0_CAMIA_RSP \ 88 | L3_STATUS_0_CAMIA_RSP \
89 | L3_STATUS_0_DISPIA_BRST \ 89 | L3_STATUS_0_DISPIA_BRST \
90 | L3_STATUS_0_DISPIA_RSP \ 90 | L3_STATUS_0_DISPIA_RSP \
91 | L3_STATUS_0_DMARDIA_BRST \ 91 | L3_STATUS_0_DMARDIA_BRST \
92 | L3_STATUS_0_DMARDIA_RSP \ 92 | L3_STATUS_0_DMARDIA_RSP \
93 | L3_STATUS_0_DMAWRIA_BRST \ 93 | L3_STATUS_0_DMAWRIA_BRST \
94 | L3_STATUS_0_DMAWRIA_RSP \ 94 | L3_STATUS_0_DMAWRIA_RSP \
95 | L3_STATUS_0_USBOTGIA_BRST \ 95 | L3_STATUS_0_USBOTGIA_BRST \
96 | L3_STATUS_0_USBOTGIA_RSP \ 96 | L3_STATUS_0_USBOTGIA_RSP \
97 | L3_STATUS_0_USBHOSTIA_BRST \ 97 | L3_STATUS_0_USBHOSTIA_BRST \
98 | L3_STATUS_0_SMSTA_REQ \ 98 | L3_STATUS_0_SMSTA_REQ \
99 | L3_STATUS_0_GPMCTA_REQ \ 99 | L3_STATUS_0_GPMCTA_REQ \
100 | L3_STATUS_0_OCMRAMTA_REQ \ 100 | L3_STATUS_0_OCMRAMTA_REQ \
101 | L3_STATUS_0_OCMROMTA_REQ \ 101 | L3_STATUS_0_OCMROMTA_REQ \
102 | L3_STATUS_0_IVATA_REQ \ 102 | L3_STATUS_0_IVATA_REQ \
103 | L3_STATUS_0_SGXTA_REQ \ 103 | L3_STATUS_0_SGXTA_REQ \
104 | L3_STATUS_0_L4CORETA_REQ \ 104 | L3_STATUS_0_L4CORETA_REQ \
105 | L3_STATUS_0_L4PERTA_REQ \ 105 | L3_STATUS_0_L4PERTA_REQ \
106 | L3_STATUS_0_L4EMUTA_REQ \ 106 | L3_STATUS_0_L4EMUTA_REQ \
107 | L3_STATUS_0_MAD2DTA_REQ) 107 | L3_STATUS_0_MAD2DTA_REQ)
108 108
109#define L3_SI_FLAG_STATUS_1 0x530 109#define L3_SI_FLAG_STATUS_1 0x530
@@ -137,19 +137,19 @@ const u64 shift = 1;
137 137
138enum omap3_l3_initiator_id { 138enum omap3_l3_initiator_id {
139 /* LCD has 1 ID */ 139 /* LCD has 1 ID */
140 OMAP_L3_LCD = 29, 140 OMAP_L3_LCD = 29,
141 /* SAD2D has 1 ID */ 141 /* SAD2D has 1 ID */
142 OMAP_L3_SAD2D = 28, 142 OMAP_L3_SAD2D = 28,
143 /* MPU has 5 IDs */ 143 /* MPU has 5 IDs */
144 OMAP_L3_IA_MPU_SS_1 = 27, 144 OMAP_L3_IA_MPU_SS_1 = 27,
145 OMAP_L3_IA_MPU_SS_2 = 26, 145 OMAP_L3_IA_MPU_SS_2 = 26,
146 OMAP_L3_IA_MPU_SS_3 = 25, 146 OMAP_L3_IA_MPU_SS_3 = 25,
147 OMAP_L3_IA_MPU_SS_4 = 24, 147 OMAP_L3_IA_MPU_SS_4 = 24,
148 OMAP_L3_IA_MPU_SS_5 = 23, 148 OMAP_L3_IA_MPU_SS_5 = 23,
149 /* IVA2.2 SS has 3 IDs*/ 149 /* IVA2.2 SS has 3 IDs*/
150 OMAP_L3_IA_IVA_SS_1 = 22, 150 OMAP_L3_IA_IVA_SS_1 = 22,
151 OMAP_L3_IA_IVA_SS_2 = 21, 151 OMAP_L3_IA_IVA_SS_2 = 21,
152 OMAP_L3_IA_IVA_SS_3 = 20, 152 OMAP_L3_IA_IVA_SS_3 = 20,
153 /* IVA 2.2 SS DMA has 6 IDS */ 153 /* IVA 2.2 SS DMA has 6 IDS */
154 OMAP_L3_IA_IVA_SS_DMA_1 = 19, 154 OMAP_L3_IA_IVA_SS_DMA_1 = 19,
155 OMAP_L3_IA_IVA_SS_DMA_2 = 18, 155 OMAP_L3_IA_IVA_SS_DMA_2 = 18,
@@ -158,25 +158,25 @@ enum omap3_l3_initiator_id {
158 OMAP_L3_IA_IVA_SS_DMA_5 = 15, 158 OMAP_L3_IA_IVA_SS_DMA_5 = 15,
159 OMAP_L3_IA_IVA_SS_DMA_6 = 14, 159 OMAP_L3_IA_IVA_SS_DMA_6 = 14,
160 /* SGX has 1 ID */ 160 /* SGX has 1 ID */
161 OMAP_L3_IA_SGX = 13, 161 OMAP_L3_IA_SGX = 13,
162 /* CAM has 3 ID */ 162 /* CAM has 3 ID */
163 OMAP_L3_IA_CAM_1 = 12, 163 OMAP_L3_IA_CAM_1 = 12,
164 OMAP_L3_IA_CAM_2 = 11, 164 OMAP_L3_IA_CAM_2 = 11,
165 OMAP_L3_IA_CAM_3 = 10, 165 OMAP_L3_IA_CAM_3 = 10,
166 /* DAP has 1 ID */ 166 /* DAP has 1 ID */
167 OMAP_L3_IA_DAP = 9, 167 OMAP_L3_IA_DAP = 9,
168 /* SDMA WR has 2 IDs */ 168 /* SDMA WR has 2 IDs */
169 OMAP_L3_SDMA_WR_1 = 8, 169 OMAP_L3_SDMA_WR_1 = 8,
170 OMAP_L3_SDMA_WR_2 = 7, 170 OMAP_L3_SDMA_WR_2 = 7,
171 /* SDMA RD has 4 IDs */ 171 /* SDMA RD has 4 IDs */
172 OMAP_L3_SDMA_RD_1 = 6, 172 OMAP_L3_SDMA_RD_1 = 6,
173 OMAP_L3_SDMA_RD_2 = 5, 173 OMAP_L3_SDMA_RD_2 = 5,
174 OMAP_L3_SDMA_RD_3 = 4, 174 OMAP_L3_SDMA_RD_3 = 4,
175 OMAP_L3_SDMA_RD_4 = 3, 175 OMAP_L3_SDMA_RD_4 = 3,
176 /* HSUSB OTG has 1 ID */ 176 /* HSUSB OTG has 1 ID */
177 OMAP_L3_USBOTG = 2, 177 OMAP_L3_USBOTG = 2,
178 /* HSUSB HOST has 1 ID */ 178 /* HSUSB HOST has 1 ID */
179 OMAP_L3_USBHOST = 1, 179 OMAP_L3_USBHOST = 1,
180}; 180};
181 181
182enum omap3_l3_code { 182enum omap3_l3_code {
@@ -192,21 +192,21 @@ enum omap3_l3_code {
192}; 192};
193 193
194struct omap3_l3 { 194struct omap3_l3 {
195 struct device *dev; 195 struct device *dev;
196 struct clk *ick; 196 struct clk *ick;
197 197
198 /* memory base*/ 198 /* memory base*/
199 void __iomem *rt; 199 void __iomem *rt;
200 200
201 int debug_irq; 201 int debug_irq;
202 int app_irq; 202 int app_irq;
203 203
204 /* true when and inband functional error occurs */ 204 /* true when and inband functional error occurs */
205 unsigned inband:1; 205 unsigned inband:1;
206}; 206};
207 207
208/* offsets for l3 agents in order with the Flag status register */ 208/* offsets for l3 agents in order with the Flag status register */
209unsigned int __iomem omap3_l3_app_bases[] = { 209static unsigned int omap3_l3_app_bases[] = {
210 /* MPU IA */ 210 /* MPU IA */
211 0x1400, 211 0x1400,
212 0x1400, 212 0x1400,
@@ -305,7 +305,7 @@ unsigned int __iomem omap3_l3_app_bases[] = {
305 0, 305 0,
306}; 306};
307 307
308unsigned int __iomem omap3_l3_debug_bases[] = { 308static unsigned int omap3_l3_debug_bases[] = {
309 /* MPU DATA IA */ 309 /* MPU DATA IA */
310 0x1400, 310 0x1400,
311 /* RESERVED */ 311 /* RESERVED */
@@ -321,7 +321,7 @@ unsigned int __iomem omap3_l3_debug_bases[] = {
321 /* REST RESERVED */ 321 /* REST RESERVED */
322}; 322};
323 323
324u32 *omap3_l3_bases[] = { 324static u32 *omap3_l3_bases[] = {
325 omap3_l3_app_bases, 325 omap3_l3_app_bases,
326 omap3_l3_debug_bases, 326 omap3_l3_debug_bases,
327}; 327};
diff --git a/arch/arm/plat-omap/include/plat/io.h b/arch/arm/plat-omap/include/plat/io.h
index d72ec85c97e6..fb5fd246897b 100644
--- a/arch/arm/plat-omap/include/plat/io.h
+++ b/arch/arm/plat-omap/include/plat/io.h
@@ -228,13 +228,13 @@
228 228
229#define OMAP44XX_EMIF2_PHYS OMAP44XX_EMIF2_BASE 229#define OMAP44XX_EMIF2_PHYS OMAP44XX_EMIF2_BASE
230 /* 0x4d000000 --> 0xfd200000 */ 230 /* 0x4d000000 --> 0xfd200000 */
231#define OMAP44XX_EMIF2_VIRT (OMAP44XX_EMIF2_PHYS + OMAP4_L3_PER_IO_OFFSET)
232#define OMAP44XX_EMIF2_SIZE SZ_1M 231#define OMAP44XX_EMIF2_SIZE SZ_1M
232#define OMAP44XX_EMIF2_VIRT (OMAP44XX_EMIF1_VIRT + OMAP44XX_EMIF1_SIZE)
233 233
234#define OMAP44XX_DMM_PHYS OMAP44XX_DMM_BASE 234#define OMAP44XX_DMM_PHYS OMAP44XX_DMM_BASE
235 /* 0x4e000000 --> 0xfd300000 */ 235 /* 0x4e000000 --> 0xfd300000 */
236#define OMAP44XX_DMM_VIRT (OMAP44XX_DMM_PHYS + OMAP4_L3_PER_IO_OFFSET)
237#define OMAP44XX_DMM_SIZE SZ_1M 236#define OMAP44XX_DMM_SIZE SZ_1M
237#define OMAP44XX_DMM_VIRT (OMAP44XX_EMIF2_VIRT + OMAP44XX_EMIF2_SIZE)
238/* 238/*
239 * ---------------------------------------------------------------------------- 239 * ----------------------------------------------------------------------------
240 * Omap specific register access 240 * Omap specific register access
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-10 05:15:04 -0500