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-rw-r--r--arch/arm/boot/dts/exynos4210-origen.dts137
-rw-r--r--arch/arm/boot/dts/exynos4210-smdkv310.dts182
-rw-r--r--arch/arm/boot/dts/exynos4210.dtsi397
-rw-r--r--arch/arm/mach-exynos/Kconfig24
-rw-r--r--arch/arm/mach-exynos/Makefile6
-rw-r--r--arch/arm/mach-exynos/clock.c229
-rw-r--r--arch/arm/mach-exynos/cpu.c17
-rw-r--r--arch/arm/mach-exynos/dma.c229
-rw-r--r--arch/arm/mach-exynos/include/mach/entry-macro.S1
-rw-r--r--arch/arm/mach-exynos/include/mach/irqs.h8
-rw-r--r--arch/arm/mach-exynos/init.c21
-rw-r--r--arch/arm/mach-exynos/mach-exynos4-dt.c85
-rw-r--r--arch/arm/mach-exynos/setup-sdhci.c22
-rw-r--r--arch/arm/mach-s3c2410/mach-bast.c22
-rw-r--r--arch/arm/mach-s3c2410/mach-vr1000.c24
-rw-r--r--arch/arm/mach-s3c2410/s3c2410.c6
-rw-r--r--arch/arm/mach-s3c2412/clock.c7
-rw-r--r--arch/arm/mach-s3c2416/Makefile1
-rw-r--r--arch/arm/mach-s3c2416/clock.c68
-rw-r--r--arch/arm/mach-s3c2416/setup-sdhci.c24
-rw-r--r--arch/arm/mach-s3c2440/clock.c44
-rw-r--r--arch/arm/mach-s3c2440/mach-anubis.c22
-rw-r--r--arch/arm/mach-s3c2440/mach-at2440evb.c22
-rw-r--r--arch/arm/mach-s3c2440/mach-osiris.c24
-rw-r--r--arch/arm/mach-s3c2440/mach-rx1950.c18
-rw-r--r--arch/arm/mach-s3c2440/mach-rx3715.c19
-rw-r--r--arch/arm/mach-s3c64xx/Kconfig8
-rw-r--r--arch/arm/mach-s3c64xx/Makefile3
-rw-r--r--arch/arm/mach-s3c64xx/clock.c243
-rw-r--r--arch/arm/mach-s3c64xx/dev-spi.c180
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/map.h2
-rw-r--r--arch/arm/mach-s3c64xx/setup-sdhci.c24
-rw-r--r--arch/arm/mach-s3c64xx/setup-spi.c45
-rw-r--r--arch/arm/mach-s5p64x0/Kconfig7
-rw-r--r--arch/arm/mach-s5p64x0/Makefile2
-rw-r--r--arch/arm/mach-s5p64x0/clock-s5p6440.c93
-rw-r--r--arch/arm/mach-s5p64x0/clock-s5p6450.c81
-rw-r--r--arch/arm/mach-s5p64x0/dev-spi.c224
-rw-r--r--arch/arm/mach-s5p64x0/dma.c227
-rw-r--r--arch/arm/mach-s5p64x0/include/mach/irqs.h2
-rw-r--r--arch/arm/mach-s5p64x0/include/mach/map.h2
-rw-r--r--arch/arm/mach-s5p64x0/init.c31
-rw-r--r--arch/arm/mach-s5p64x0/setup-spi.c55
-rw-r--r--arch/arm/mach-s5pc100/Kconfig5
-rw-r--r--arch/arm/mach-s5pc100/Makefile3
-rw-r--r--arch/arm/mach-s5pc100/clock.c287
-rw-r--r--arch/arm/mach-s5pc100/dev-spi.c227
-rw-r--r--arch/arm/mach-s5pc100/dma.c247
-rw-r--r--arch/arm/mach-s5pc100/include/mach/irqs.h2
-rw-r--r--arch/arm/mach-s5pc100/include/mach/map.h3
-rw-r--r--arch/arm/mach-s5pc100/setup-sdhci.c23
-rw-r--r--arch/arm/mach-s5pc100/setup-spi.c65
-rw-r--r--arch/arm/mach-s5pv210/Kconfig5
-rw-r--r--arch/arm/mach-s5pv210/Makefile3
-rw-r--r--arch/arm/mach-s5pv210/clock.c324
-rw-r--r--arch/arm/mach-s5pv210/dev-spi.c175
-rw-r--r--arch/arm/mach-s5pv210/dma.c241
-rw-r--r--arch/arm/mach-s5pv210/include/mach/irqs.h2
-rw-r--r--arch/arm/mach-s5pv210/include/mach/map.h2
-rw-r--r--arch/arm/mach-s5pv210/init.c19
-rw-r--r--arch/arm/mach-s5pv210/setup-sdhci.c22
-rw-r--r--arch/arm/mach-s5pv210/setup-spi.c51
-rw-r--r--arch/arm/plat-s3c24xx/s3c2443-clock.c39
-rw-r--r--arch/arm/plat-samsung/Kconfig16
-rw-r--r--arch/arm/plat-samsung/devs.c127
-rw-r--r--arch/arm/plat-samsung/dma-ops.c15
-rw-r--r--arch/arm/plat-samsung/include/plat/devs.h8
-rw-r--r--arch/arm/plat-samsung/include/plat/dma-ops.h1
-rw-r--r--arch/arm/plat-samsung/include/plat/dma-pl330.h3
-rw-r--r--arch/arm/plat-samsung/include/plat/irqs.h3
-rw-r--r--arch/arm/plat-samsung/include/plat/regs-serial.h45
-rw-r--r--arch/arm/plat-samsung/include/plat/s3c64xx-spi.h24
-rw-r--r--arch/arm/plat-samsung/include/plat/sdhci.h31
73 files changed, 2483 insertions, 2423 deletions
diff --git a/arch/arm/boot/dts/exynos4210-origen.dts b/arch/arm/boot/dts/exynos4210-origen.dts
new file mode 100644
index 000000000000..b8c476384eef
--- /dev/null
+++ b/arch/arm/boot/dts/exynos4210-origen.dts
@@ -0,0 +1,137 @@
1/*
2 * Samsung's Exynos4210 based Origen board device tree source
3 *
4 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 * Copyright (c) 2010-2011 Linaro Ltd.
7 * www.linaro.org
8 *
9 * Device tree source file for Insignal's Origen board which is based on
10 * Samsung's Exynos4210 SoC.
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15*/
16
17/dts-v1/;
18/include/ "exynos4210.dtsi"
19
20/ {
21 model = "Insignal Origen evaluation board based on Exynos4210";
22 compatible = "insignal,origen", "samsung,exynos4210";
23
24 memory {
25 reg = <0x40000000 0x40000000>;
26 };
27
28 chosen {
29 bootargs ="root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC2,115200 init=/linuxrc";
30 };
31
32 sdhci@12530000 {
33 samsung,sdhci-bus-width = <4>;
34 linux,mmc_cap_4_bit_data;
35 samsung,sdhci-cd-internal;
36 gpio-cd = <&gpk2 2 2 3 3>;
37 gpios = <&gpk2 0 2 0 3>,
38 <&gpk2 1 2 0 3>,
39 <&gpk2 3 2 3 3>,
40 <&gpk2 4 2 3 3>,
41 <&gpk2 5 2 3 3>,
42 <&gpk2 6 2 3 3>;
43 };
44
45 sdhci@12510000 {
46 samsung,sdhci-bus-width = <4>;
47 linux,mmc_cap_4_bit_data;
48 samsung,sdhci-cd-internal;
49 gpio-cd = <&gpk0 2 2 3 3>;
50 gpios = <&gpk0 0 2 0 3>,
51 <&gpk0 1 2 0 3>,
52 <&gpk0 3 2 3 3>,
53 <&gpk0 4 2 3 3>,
54 <&gpk0 5 2 3 3>,
55 <&gpk0 6 2 3 3>;
56 };
57
58 gpio_keys {
59 compatible = "gpio-keys";
60 #address-cells = <1>;
61 #size-cells = <0>;
62
63 up {
64 label = "Up";
65 gpios = <&gpx2 0 0 0 2>;
66 linux,code = <103>;
67 };
68
69 down {
70 label = "Down";
71 gpios = <&gpx2 1 0 0 2>;
72 linux,code = <108>;
73 };
74
75 back {
76 label = "Back";
77 gpios = <&gpx1 7 0 0 2>;
78 linux,code = <158>;
79 };
80
81 home {
82 label = "Home";
83 gpios = <&gpx1 6 0 0 2>;
84 linux,code = <102>;
85 };
86
87 menu {
88 label = "Menu";
89 gpios = <&gpx1 5 0 0 2>;
90 linux,code = <139>;
91 };
92 };
93
94 keypad@100A0000 {
95 status = "disabled";
96 };
97
98 sdhci@12520000 {
99 status = "disabled";
100 };
101
102 sdhci@12540000 {
103 status = "disabled";
104 };
105
106 i2c@13860000 {
107 status = "disabled";
108 };
109
110 i2c@13870000 {
111 status = "disabled";
112 };
113
114 i2c@13880000 {
115 status = "disabled";
116 };
117
118 i2c@13890000 {
119 status = "disabled";
120 };
121
122 i2c@138A0000 {
123 status = "disabled";
124 };
125
126 i2c@138B0000 {
127 status = "disabled";
128 };
129
130 i2c@138C0000 {
131 status = "disabled";
132 };
133
134 i2c@138D0000 {
135 status = "disabled";
136 };
137};
diff --git a/arch/arm/boot/dts/exynos4210-smdkv310.dts b/arch/arm/boot/dts/exynos4210-smdkv310.dts
new file mode 100644
index 000000000000..27afc8e535ca
--- /dev/null
+++ b/arch/arm/boot/dts/exynos4210-smdkv310.dts
@@ -0,0 +1,182 @@
1/*
2 * Samsung's Exynos4210 based SMDKV310 board device tree source
3 *
4 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 * Copyright (c) 2010-2011 Linaro Ltd.
7 * www.linaro.org
8 *
9 * Device tree source file for Samsung's SMDKV310 board which is based on
10 * Samsung's Exynos4210 SoC.
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15*/
16
17/dts-v1/;
18/include/ "exynos4210.dtsi"
19
20/ {
21 model = "Samsung smdkv310 evaluation board based on Exynos4210";
22 compatible = "samsung,smdkv310", "samsung,exynos4210";
23
24 memory {
25 reg = <0x40000000 0x80000000>;
26 };
27
28 chosen {
29 bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC1,115200 init=/linuxrc";
30 };
31
32 sdhci@12530000 {
33 samsung,sdhci-bus-width = <4>;
34 linux,mmc_cap_4_bit_data;
35 samsung,sdhci-cd-internal;
36 gpio-cd = <&gpk2 2 2 3 3>;
37 gpios = <&gpk2 0 2 0 3>,
38 <&gpk2 1 2 0 3>,
39 <&gpk2 3 2 3 3>,
40 <&gpk2 4 2 3 3>,
41 <&gpk2 5 2 3 3>,
42 <&gpk2 6 2 3 3>;
43 };
44
45 keypad@100A0000 {
46 samsung,keypad-num-rows = <2>;
47 samsung,keypad-num-columns = <8>;
48 linux,keypad-no-autorepeat;
49 linux,keypad-wakeup;
50
51 row-gpios = <&gpx2 0 3 3 0>,
52 <&gpx2 1 3 3 0>;
53
54 col-gpios = <&gpx1 0 3 0 0>,
55 <&gpx1 1 3 0 0>,
56 <&gpx1 2 3 0 0>,
57 <&gpx1 3 3 0 0>,
58 <&gpx1 4 3 0 0>,
59 <&gpx1 5 3 0 0>,
60 <&gpx1 6 3 0 0>,
61 <&gpx1 7 3 0 0>;
62
63 key_1 {
64 keypad,row = <0>;
65 keypad,column = <3>;
66 linux,code = <2>;
67 };
68
69 key_2 {
70 keypad,row = <0>;
71 keypad,column = <4>;
72 linux,code = <3>;
73 };
74
75 key_3 {
76 keypad,row = <0>;
77 keypad,column = <5>;
78 linux,code = <4>;
79 };
80
81 key_4 {
82 keypad,row = <0>;
83 keypad,column = <6>;
84 linux,code = <5>;
85 };
86
87 key_5 {
88 keypad,row = <0>;
89 keypad,column = <7>;
90 linux,code = <6>;
91 };
92
93 key_a {
94 keypad,row = <1>;
95 keypad,column = <3>;
96 linux,code = <30>;
97 };
98
99 key_b {
100 keypad,row = <1>;
101 keypad,column = <4>;
102 linux,code = <48>;
103 };
104
105 key_c {
106 keypad,row = <1>;
107 keypad,column = <5>;
108 linux,code = <46>;
109 };
110
111 key_d {
112 keypad,row = <1>;
113 keypad,column = <6>;
114 linux,code = <32>;
115 };
116
117 key_e {
118 keypad,row = <1>;
119 keypad,column = <7>;
120 linux,code = <18>;
121 };
122 };
123
124 i2c@13860000 {
125 #address-cells = <1>;
126 #size-cells = <0>;
127 samsung,i2c-sda-delay = <100>;
128 samsung,i2c-max-bus-freq = <20000>;
129 gpios = <&gpd1 0 2 3 0>,
130 <&gpd1 1 2 3 0>;
131
132 eeprom@50 {
133 compatible = "samsung,24ad0xd1";
134 reg = <0x50>;
135 };
136
137 eeprom@52 {
138 compatible = "samsung,24ad0xd1";
139 reg = <0x52>;
140 };
141 };
142
143 sdhci@12510000 {
144 status = "disabled";
145 };
146
147 sdhci@12520000 {
148 status = "disabled";
149 };
150
151 sdhci@12540000 {
152 status = "disabled";
153 };
154
155 i2c@13870000 {
156 status = "disabled";
157 };
158
159 i2c@13880000 {
160 status = "disabled";
161 };
162
163 i2c@13890000 {
164 status = "disabled";
165 };
166
167 i2c@138A0000 {
168 status = "disabled";
169 };
170
171 i2c@138B0000 {
172 status = "disabled";
173 };
174
175 i2c@138C0000 {
176 status = "disabled";
177 };
178
179 i2c@138D0000 {
180 status = "disabled";
181 };
182};
diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
new file mode 100644
index 000000000000..63d7578856c1
--- /dev/null
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -0,0 +1,397 @@
1/*
2 * Samsung's Exynos4210 SoC device tree source
3 *
4 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 * Copyright (c) 2010-2011 Linaro Ltd.
7 * www.linaro.org
8 *
9 * Samsung's Exynos4210 SoC device nodes are listed in this file. Exynos4210
10 * based board files can include this file and provide values for board specfic
11 * bindings.
12 *
13 * Note: This file does not include device nodes for all the controllers in
14 * Exynos4210 SoC. As device tree coverage for Exynos4210 increases, additional
15 * nodes can be added to this file.
16 *
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License version 2 as
19 * published by the Free Software Foundation.
20*/
21
22/include/ "skeleton.dtsi"
23
24/ {
25 compatible = "samsung,exynos4210";
26 interrupt-parent = <&gic>;
27
28 gic:interrupt-controller@10490000 {
29 compatible = "arm,cortex-a9-gic";
30 #interrupt-cells = <3>;
31 interrupt-controller;
32 reg = <0x10490000 0x1000>, <0x10480000 0x100>;
33 };
34
35 watchdog@10060000 {
36 compatible = "samsung,s3c2410-wdt";
37 reg = <0x10060000 0x100>;
38 interrupts = <0 43 0>;
39 };
40
41 rtc@10070000 {
42 compatible = "samsung,s3c6410-rtc";
43 reg = <0x10070000 0x100>;
44 interrupts = <0 44 0>, <0 45 0>;
45 };
46
47 keypad@100A0000 {
48 compatible = "samsung,s5pv210-keypad";
49 reg = <0x100A0000 0x100>;
50 interrupts = <0 109 0>;
51 };
52
53 sdhci@12510000 {
54 compatible = "samsung,exynos4210-sdhci";
55 reg = <0x12510000 0x100>;
56 interrupts = <0 73 0>;
57 };
58
59 sdhci@12520000 {
60 compatible = "samsung,exynos4210-sdhci";
61 reg = <0x12520000 0x100>;
62 interrupts = <0 74 0>;
63 };
64
65 sdhci@12530000 {
66 compatible = "samsung,exynos4210-sdhci";
67 reg = <0x12530000 0x100>;
68 interrupts = <0 75 0>;
69 };
70
71 sdhci@12540000 {
72 compatible = "samsung,exynos4210-sdhci";
73 reg = <0x12540000 0x100>;
74 interrupts = <0 76 0>;
75 };
76
77 serial@13800000 {
78 compatible = "samsung,exynos4210-uart";
79 reg = <0x13800000 0x100>;
80 interrupts = <0 52 0>;
81 };
82
83 serial@13810000 {
84 compatible = "samsung,exynos4210-uart";
85 reg = <0x13810000 0x100>;
86 interrupts = <0 53 0>;
87 };
88
89 serial@13820000 {
90 compatible = "samsung,exynos4210-uart";
91 reg = <0x13820000 0x100>;
92 interrupts = <0 54 0>;
93 };
94
95 serial@13830000 {
96 compatible = "samsung,exynos4210-uart";
97 reg = <0x13830000 0x100>;
98 interrupts = <0 55 0>;
99 };
100
101 i2c@13860000 {
102 compatible = "samsung,s3c2440-i2c";
103 reg = <0x13860000 0x100>;
104 interrupts = <0 58 0>;
105 };
106
107 i2c@13870000 {
108 compatible = "samsung,s3c2440-i2c";
109 reg = <0x13870000 0x100>;
110 interrupts = <0 59 0>;
111 };
112
113 i2c@13880000 {
114 compatible = "samsung,s3c2440-i2c";
115 reg = <0x13880000 0x100>;
116 interrupts = <0 60 0>;
117 };
118
119 i2c@13890000 {
120 compatible = "samsung,s3c2440-i2c";
121 reg = <0x13890000 0x100>;
122 interrupts = <0 61 0>;
123 };
124
125 i2c@138A0000 {
126 compatible = "samsung,s3c2440-i2c";
127 reg = <0x138A0000 0x100>;
128 interrupts = <0 62 0>;
129 };
130
131 i2c@138B0000 {
132 compatible = "samsung,s3c2440-i2c";
133 reg = <0x138B0000 0x100>;
134 interrupts = <0 63 0>;
135 };
136
137 i2c@138C0000 {
138 compatible = "samsung,s3c2440-i2c";
139 reg = <0x138C0000 0x100>;
140 interrupts = <0 64 0>;
141 };
142
143 i2c@138D0000 {
144 compatible = "samsung,s3c2440-i2c";
145 reg = <0x138D0000 0x100>;
146 interrupts = <0 65 0>;
147 };
148
149 amba {
150 #address-cells = <1>;
151 #size-cells = <1>;
152 compatible = "arm,amba-bus";
153 interrupt-parent = <&gic>;
154 ranges;
155
156 pdma0: pdma@12680000 {
157 compatible = "arm,pl330", "arm,primecell";
158 reg = <0x12680000 0x1000>;
159 interrupts = <0 35 0>;
160 };
161
162 pdma1: pdma@12690000 {
163 compatible = "arm,pl330", "arm,primecell";
164 reg = <0x12690000 0x1000>;
165 interrupts = <0 36 0>;
166 };
167 };
168
169 gpio-controllers {
170 #address-cells = <1>;
171 #size-cells = <1>;
172 gpio-controller;
173 ranges;
174
175 gpa0: gpio-controller@11400000 {
176 compatible = "samsung,exynos4-gpio";
177 reg = <0x11400000 0x20>;
178 #gpio-cells = <4>;
179 };
180
181 gpa1: gpio-controller@11400020 {
182 compatible = "samsung,exynos4-gpio";
183 reg = <0x11400020 0x20>;
184 #gpio-cells = <4>;
185 };
186
187 gpb: gpio-controller@11400040 {
188 compatible = "samsung,exynos4-gpio";
189 reg = <0x11400040 0x20>;
190 #gpio-cells = <4>;
191 };
192
193 gpc0: gpio-controller@11400060 {
194 compatible = "samsung,exynos4-gpio";
195 reg = <0x11400060 0x20>;
196 #gpio-cells = <4>;
197 };
198
199 gpc1: gpio-controller@11400080 {
200 compatible = "samsung,exynos4-gpio";
201 reg = <0x11400080 0x20>;
202 #gpio-cells = <4>;
203 };
204
205 gpd0: gpio-controller@114000A0 {
206 compatible = "samsung,exynos4-gpio";
207 reg = <0x114000A0 0x20>;
208 #gpio-cells = <4>;
209 };
210
211 gpd1: gpio-controller@114000C0 {
212 compatible = "samsung,exynos4-gpio";
213 reg = <0x114000C0 0x20>;
214 #gpio-cells = <4>;
215 };
216
217 gpe0: gpio-controller@114000E0 {
218 compatible = "samsung,exynos4-gpio";
219 reg = <0x114000E0 0x20>;
220 #gpio-cells = <4>;
221 };
222
223 gpe1: gpio-controller@11400100 {
224 compatible = "samsung,exynos4-gpio";
225 reg = <0x11400100 0x20>;
226 #gpio-cells = <4>;
227 };
228
229 gpe2: gpio-controller@11400120 {
230 compatible = "samsung,exynos4-gpio";
231 reg = <0x11400120 0x20>;
232 #gpio-cells = <4>;
233 };
234
235 gpe3: gpio-controller@11400140 {
236 compatible = "samsung,exynos4-gpio";
237 reg = <0x11400140 0x20>;
238 #gpio-cells = <4>;
239 };
240
241 gpe4: gpio-controller@11400160 {
242 compatible = "samsung,exynos4-gpio";
243 reg = <0x11400160 0x20>;
244 #gpio-cells = <4>;
245 };
246
247 gpf0: gpio-controller@11400180 {
248 compatible = "samsung,exynos4-gpio";
249 reg = <0x11400180 0x20>;
250 #gpio-cells = <4>;
251 };
252
253 gpf1: gpio-controller@114001A0 {
254 compatible = "samsung,exynos4-gpio";
255 reg = <0x114001A0 0x20>;
256 #gpio-cells = <4>;
257 };
258
259 gpf2: gpio-controller@114001C0 {
260 compatible = "samsung,exynos4-gpio";
261 reg = <0x114001C0 0x20>;
262 #gpio-cells = <4>;
263 };
264
265 gpf3: gpio-controller@114001E0 {
266 compatible = "samsung,exynos4-gpio";
267 reg = <0x114001E0 0x20>;
268 #gpio-cells = <4>;
269 };
270
271 gpj0: gpio-controller@11000000 {
272 compatible = "samsung,exynos4-gpio";
273 reg = <0x11000000 0x20>;
274 #gpio-cells = <4>;
275 };
276
277 gpj1: gpio-controller@11000020 {
278 compatible = "samsung,exynos4-gpio";
279 reg = <0x11000020 0x20>;
280 #gpio-cells = <4>;
281 };
282
283 gpk0: gpio-controller@11000040 {
284 compatible = "samsung,exynos4-gpio";
285 reg = <0x11000040 0x20>;
286 #gpio-cells = <4>;
287 };
288
289 gpk1: gpio-controller@11000060 {
290 compatible = "samsung,exynos4-gpio";
291 reg = <0x11000060 0x20>;
292 #gpio-cells = <4>;
293 };
294
295 gpk2: gpio-controller@11000080 {
296 compatible = "samsung,exynos4-gpio";
297 reg = <0x11000080 0x20>;
298 #gpio-cells = <4>;
299 };
300
301 gpk3: gpio-controller@110000A0 {
302 compatible = "samsung,exynos4-gpio";
303 reg = <0x110000A0 0x20>;
304 #gpio-cells = <4>;
305 };
306
307 gpl0: gpio-controller@110000C0 {
308 compatible = "samsung,exynos4-gpio";
309 reg = <0x110000C0 0x20>;
310 #gpio-cells = <4>;
311 };
312
313 gpl1: gpio-controller@110000E0 {
314 compatible = "samsung,exynos4-gpio";
315 reg = <0x110000E0 0x20>;
316 #gpio-cells = <4>;
317 };
318
319 gpl2: gpio-controller@11000100 {
320 compatible = "samsung,exynos4-gpio";
321 reg = <0x11000100 0x20>;
322 #gpio-cells = <4>;
323 };
324
325 gpy0: gpio-controller@11000120 {
326 compatible = "samsung,exynos4-gpio";
327 reg = <0x11000120 0x20>;
328 #gpio-cells = <4>;
329 };
330
331 gpy1: gpio-controller@11000140 {
332 compatible = "samsung,exynos4-gpio";
333 reg = <0x11000140 0x20>;
334 #gpio-cells = <4>;
335 };
336
337 gpy2: gpio-controller@11000160 {
338 compatible = "samsung,exynos4-gpio";
339 reg = <0x11000160 0x20>;
340 #gpio-cells = <4>;
341 };
342
343 gpy3: gpio-controller@11000180 {
344 compatible = "samsung,exynos4-gpio";
345 reg = <0x11000180 0x20>;
346 #gpio-cells = <4>;
347 };
348
349 gpy4: gpio-controller@110001A0 {
350 compatible = "samsung,exynos4-gpio";
351 reg = <0x110001A0 0x20>;
352 #gpio-cells = <4>;
353 };
354
355 gpy5: gpio-controller@110001C0 {
356 compatible = "samsung,exynos4-gpio";
357 reg = <0x110001C0 0x20>;
358 #gpio-cells = <4>;
359 };
360
361 gpy6: gpio-controller@110001E0 {
362 compatible = "samsung,exynos4-gpio";
363 reg = <0x110001E0 0x20>;
364 #gpio-cells = <4>;
365 };
366
367 gpx0: gpio-controller@11000C00 {
368 compatible = "samsung,exynos4-gpio";
369 reg = <0x11000C00 0x20>;
370 #gpio-cells = <4>;
371 };
372
373 gpx1: gpio-controller@11000C20 {
374 compatible = "samsung,exynos4-gpio";
375 reg = <0x11000C20 0x20>;
376 #gpio-cells = <4>;
377 };
378
379 gpx2: gpio-controller@11000C40 {
380 compatible = "samsung,exynos4-gpio";
381 reg = <0x11000C40 0x20>;
382 #gpio-cells = <4>;
383 };
384
385 gpx3: gpio-controller@11000C60 {
386 compatible = "samsung,exynos4-gpio";
387 reg = <0x11000C60 0x20>;
388 #gpio-cells = <4>;
389 };
390
391 gpz: gpio-controller@03860000 {
392 compatible = "samsung,exynos4-gpio";
393 reg = <0x03860000 0x20>;
394 #gpio-cells = <4>;
395 };
396 };
397};
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index 5ca0bddf65fa..0da2ced1ae48 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -57,6 +57,11 @@ config EXYNOS4_MCT
57 help 57 help
58 Use MCT (Multi Core Timer) as kernel timers 58 Use MCT (Multi Core Timer) as kernel timers
59 59
60config EXYNOS4_DEV_DMA
61 bool
62 help
63 Compile in amba device definitions for DMA controller
64
60config EXYNOS4_DEV_AHCI 65config EXYNOS4_DEV_AHCI
61 bool 66 bool
62 help 67 help
@@ -182,6 +187,7 @@ config MACH_SMDKV310
182 select SAMSUNG_DEV_BACKLIGHT 187 select SAMSUNG_DEV_BACKLIGHT
183 select EXYNOS4_DEV_AHCI 188 select EXYNOS4_DEV_AHCI
184 select SAMSUNG_DEV_KEYPAD 189 select SAMSUNG_DEV_KEYPAD
190 select EXYNOS4_DEV_DMA
185 select EXYNOS4_DEV_PD 191 select EXYNOS4_DEV_PD
186 select SAMSUNG_DEV_PWM 192 select SAMSUNG_DEV_PWM
187 select EXYNOS4_DEV_USB_OHCI 193 select EXYNOS4_DEV_USB_OHCI
@@ -203,6 +209,7 @@ config MACH_ARMLEX4210
203 select S3C_DEV_HSMMC2 209 select S3C_DEV_HSMMC2
204 select S3C_DEV_HSMMC3 210 select S3C_DEV_HSMMC3
205 select EXYNOS4_DEV_AHCI 211 select EXYNOS4_DEV_AHCI
212 select EXYNOS4_DEV_DMA
206 select EXYNOS4_DEV_SYSMMU 213 select EXYNOS4_DEV_SYSMMU
207 select EXYNOS4_SETUP_SDHCI 214 select EXYNOS4_SETUP_SDHCI
208 help 215 help
@@ -228,6 +235,7 @@ config MACH_UNIVERSAL_C210
228 select S5P_DEV_MFC 235 select S5P_DEV_MFC
229 select S5P_DEV_ONENAND 236 select S5P_DEV_ONENAND
230 select S5P_DEV_TV 237 select S5P_DEV_TV
238 select EXYNOS4_DEV_DMA
231 select EXYNOS4_DEV_PD 239 select EXYNOS4_DEV_PD
232 select EXYNOS4_SETUP_FIMD0 240 select EXYNOS4_SETUP_FIMD0
233 select EXYNOS4_SETUP_I2C1 241 select EXYNOS4_SETUP_I2C1
@@ -261,6 +269,7 @@ config MACH_NURI
261 select S5P_DEV_MFC 269 select S5P_DEV_MFC
262 select S5P_DEV_USB_EHCI 270 select S5P_DEV_USB_EHCI
263 select S5P_SETUP_MIPIPHY 271 select S5P_SETUP_MIPIPHY
272 select EXYNOS4_DEV_DMA
264 select EXYNOS4_DEV_PD 273 select EXYNOS4_DEV_PD
265 select EXYNOS4_SETUP_FIMC 274 select EXYNOS4_SETUP_FIMC
266 select EXYNOS4_SETUP_FIMD0 275 select EXYNOS4_SETUP_FIMD0
@@ -293,6 +302,7 @@ config MACH_ORIGEN
293 select S5P_DEV_USB_EHCI 302 select S5P_DEV_USB_EHCI
294 select SAMSUNG_DEV_BACKLIGHT 303 select SAMSUNG_DEV_BACKLIGHT
295 select SAMSUNG_DEV_PWM 304 select SAMSUNG_DEV_PWM
305 select EXYNOS4_DEV_DMA
296 select EXYNOS4_DEV_PD 306 select EXYNOS4_DEV_PD
297 select EXYNOS4_DEV_USB_OHCI 307 select EXYNOS4_DEV_USB_OHCI
298 select EXYNOS4_SETUP_FIMD0 308 select EXYNOS4_SETUP_FIMD0
@@ -334,6 +344,20 @@ config MACH_SMDK4412
334 Machine support for Samsung SMDK4412 344 Machine support for Samsung SMDK4412
335endif 345endif
336 346
347comment "Flattened Device Tree based board for Exynos4 based SoC"
348
349config MACH_EXYNOS4_DT
350 bool "Samsung Exynos4 Machine using device tree"
351 select CPU_EXYNOS4210
352 select USE_OF
353 select ARM_AMBA
354 select HAVE_SAMSUNG_KEYPAD if INPUT_KEYBOARD
355 help
356 Machine support for Samsung Exynos4 machine with device tree enabled.
357 Select this if a fdt blob is available for the Exynos4 SoC based board.
358 Note: This is under development and not all peripherals can be supported
359 with this machine file.
360
337if ARCH_EXYNOS4 361if ARCH_EXYNOS4
338 362
339comment "Configuration for HSMMC 8-bit bus width" 363comment "Configuration for HSMMC 8-bit bus width"
diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
index f5f3b7994923..a0959ad04077 100644
--- a/arch/arm/mach-exynos/Makefile
+++ b/arch/arm/mach-exynos/Makefile
@@ -13,7 +13,7 @@ obj- :=
13# Core support for EXYNOS4 system 13# Core support for EXYNOS4 system
14 14
15obj-$(CONFIG_ARCH_EXYNOS4) += cpu.o init.o clock.o irq-combiner.o setup-i2c0.o 15obj-$(CONFIG_ARCH_EXYNOS4) += cpu.o init.o clock.o irq-combiner.o setup-i2c0.o
16obj-$(CONFIG_ARCH_EXYNOS4) += irq-eint.o dma.o pmu.o 16obj-$(CONFIG_ARCH_EXYNOS4) += irq-eint.o pmu.o
17obj-$(CONFIG_CPU_EXYNOS4210) += clock-exynos4210.o 17obj-$(CONFIG_CPU_EXYNOS4210) += clock-exynos4210.o
18obj-$(CONFIG_SOC_EXYNOS4212) += clock-exynos4212.o 18obj-$(CONFIG_SOC_EXYNOS4212) += clock-exynos4212.o
19obj-$(CONFIG_PM) += pm.o 19obj-$(CONFIG_PM) += pm.o
@@ -37,6 +37,8 @@ obj-$(CONFIG_MACH_ORIGEN) += mach-origen.o
37obj-$(CONFIG_MACH_SMDK4212) += mach-smdk4x12.o 37obj-$(CONFIG_MACH_SMDK4212) += mach-smdk4x12.o
38obj-$(CONFIG_MACH_SMDK4412) += mach-smdk4x12.o 38obj-$(CONFIG_MACH_SMDK4412) += mach-smdk4x12.o
39 39
40obj-$(CONFIG_MACH_EXYNOS4_DT) += mach-exynos4-dt.o
41
40# device support 42# device support
41 43
42obj-$(CONFIG_ARCH_EXYNOS4) += dev-audio.o 44obj-$(CONFIG_ARCH_EXYNOS4) += dev-audio.o
@@ -44,6 +46,7 @@ obj-$(CONFIG_EXYNOS4_DEV_AHCI) += dev-ahci.o
44obj-$(CONFIG_EXYNOS4_DEV_PD) += dev-pd.o 46obj-$(CONFIG_EXYNOS4_DEV_PD) += dev-pd.o
45obj-$(CONFIG_EXYNOS4_DEV_SYSMMU) += dev-sysmmu.o 47obj-$(CONFIG_EXYNOS4_DEV_SYSMMU) += dev-sysmmu.o
46obj-$(CONFIG_EXYNOS4_DEV_DWMCI) += dev-dwmci.o 48obj-$(CONFIG_EXYNOS4_DEV_DWMCI) += dev-dwmci.o
49obj-$(CONFIG_EXYNOS4_DEV_DMA) += dma.o
47obj-$(CONFIG_EXYNOS4_DEV_USB_OHCI) += dev-ohci.o 50obj-$(CONFIG_EXYNOS4_DEV_USB_OHCI) += dev-ohci.o
48 51
49obj-$(CONFIG_EXYNOS4_SETUP_FIMC) += setup-fimc.o 52obj-$(CONFIG_EXYNOS4_SETUP_FIMC) += setup-fimc.o
@@ -56,6 +59,5 @@ obj-$(CONFIG_EXYNOS4_SETUP_I2C5) += setup-i2c5.o
56obj-$(CONFIG_EXYNOS4_SETUP_I2C6) += setup-i2c6.o 59obj-$(CONFIG_EXYNOS4_SETUP_I2C6) += setup-i2c6.o
57obj-$(CONFIG_EXYNOS4_SETUP_I2C7) += setup-i2c7.o 60obj-$(CONFIG_EXYNOS4_SETUP_I2C7) += setup-i2c7.o
58obj-$(CONFIG_EXYNOS4_SETUP_KEYPAD) += setup-keypad.o 61obj-$(CONFIG_EXYNOS4_SETUP_KEYPAD) += setup-keypad.o
59obj-$(CONFIG_EXYNOS4_SETUP_SDHCI) += setup-sdhci.o
60obj-$(CONFIG_EXYNOS4_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o 62obj-$(CONFIG_EXYNOS4_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o
61obj-$(CONFIG_EXYNOS4_SETUP_USB_PHY) += setup-usb-phy.o 63obj-$(CONFIG_EXYNOS4_SETUP_USB_PHY) += setup-usb-phy.o
diff --git a/arch/arm/mach-exynos/clock.c b/arch/arm/mach-exynos/clock.c
index 2894f0adef5c..5d8d4831e244 100644
--- a/arch/arm/mach-exynos/clock.c
+++ b/arch/arm/mach-exynos/clock.c
@@ -553,16 +553,6 @@ static struct clk init_clocks_off[] = {
553 .enable = exynos4_clk_dac_ctrl, 553 .enable = exynos4_clk_dac_ctrl,
554 .ctrlbit = (1 << 0), 554 .ctrlbit = (1 << 0),
555 }, { 555 }, {
556 .name = "dma",
557 .devname = "dma-pl330.0",
558 .enable = exynos4_clk_ip_fsys_ctrl,
559 .ctrlbit = (1 << 0),
560 }, {
561 .name = "dma",
562 .devname = "dma-pl330.1",
563 .enable = exynos4_clk_ip_fsys_ctrl,
564 .ctrlbit = (1 << 1),
565 }, {
566 .name = "adc", 556 .name = "adc",
567 .enable = exynos4_clk_ip_peril_ctrl, 557 .enable = exynos4_clk_ip_peril_ctrl,
568 .ctrlbit = (1 << 15), 558 .ctrlbit = (1 << 15),
@@ -778,6 +768,20 @@ static struct clk init_clocks[] = {
778 } 768 }
779}; 769};
780 770
771static struct clk clk_pdma0 = {
772 .name = "dma",
773 .devname = "dma-pl330.0",
774 .enable = exynos4_clk_ip_fsys_ctrl,
775 .ctrlbit = (1 << 0),
776};
777
778static struct clk clk_pdma1 = {
779 .name = "dma",
780 .devname = "dma-pl330.1",
781 .enable = exynos4_clk_ip_fsys_ctrl,
782 .ctrlbit = (1 << 1),
783};
784
781struct clk *clkset_group_list[] = { 785struct clk *clkset_group_list[] = {
782 [0] = &clk_ext_xtal_mux, 786 [0] = &clk_ext_xtal_mux,
783 [1] = &clk_xusbxti, 787 [1] = &clk_xusbxti,
@@ -1009,46 +1013,6 @@ static struct clksrc_clk clk_dout_mmc4 = {
1009 1013
1010static struct clksrc_clk clksrcs[] = { 1014static struct clksrc_clk clksrcs[] = {
1011 { 1015 {
1012 .clk = {
1013 .name = "uclk1",
1014 .devname = "s5pv210-uart.0",
1015 .enable = exynos4_clksrc_mask_peril0_ctrl,
1016 .ctrlbit = (1 << 0),
1017 },
1018 .sources = &clkset_group,
1019 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 0, .size = 4 },
1020 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 0, .size = 4 },
1021 }, {
1022 .clk = {
1023 .name = "uclk1",
1024 .devname = "s5pv210-uart.1",
1025 .enable = exynos4_clksrc_mask_peril0_ctrl,
1026 .ctrlbit = (1 << 4),
1027 },
1028 .sources = &clkset_group,
1029 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 4, .size = 4 },
1030 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 4, .size = 4 },
1031 }, {
1032 .clk = {
1033 .name = "uclk1",
1034 .devname = "s5pv210-uart.2",
1035 .enable = exynos4_clksrc_mask_peril0_ctrl,
1036 .ctrlbit = (1 << 8),
1037 },
1038 .sources = &clkset_group,
1039 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 8, .size = 4 },
1040 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 8, .size = 4 },
1041 }, {
1042 .clk = {
1043 .name = "uclk1",
1044 .devname = "s5pv210-uart.3",
1045 .enable = exynos4_clksrc_mask_peril0_ctrl,
1046 .ctrlbit = (1 << 12),
1047 },
1048 .sources = &clkset_group,
1049 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 12, .size = 4 },
1050 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 12, .size = 4 },
1051 }, {
1052 .clk = { 1016 .clk = {
1053 .name = "sclk_pwm", 1017 .name = "sclk_pwm",
1054 .enable = exynos4_clksrc_mask_peril0_ctrl, 1018 .enable = exynos4_clksrc_mask_peril0_ctrl,
@@ -1192,42 +1156,6 @@ static struct clksrc_clk clksrcs[] = {
1192 .reg_div = { .reg = S5P_CLKDIV_MFC, .shift = 0, .size = 4 }, 1156 .reg_div = { .reg = S5P_CLKDIV_MFC, .shift = 0, .size = 4 },
1193 }, { 1157 }, {
1194 .clk = { 1158 .clk = {
1195 .name = "sclk_mmc",
1196 .devname = "s3c-sdhci.0",
1197 .parent = &clk_dout_mmc0.clk,
1198 .enable = exynos4_clksrc_mask_fsys_ctrl,
1199 .ctrlbit = (1 << 0),
1200 },
1201 .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 8, .size = 8 },
1202 }, {
1203 .clk = {
1204 .name = "sclk_mmc",
1205 .devname = "s3c-sdhci.1",
1206 .parent = &clk_dout_mmc1.clk,
1207 .enable = exynos4_clksrc_mask_fsys_ctrl,
1208 .ctrlbit = (1 << 4),
1209 },
1210 .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 24, .size = 8 },
1211 }, {
1212 .clk = {
1213 .name = "sclk_mmc",
1214 .devname = "s3c-sdhci.2",
1215 .parent = &clk_dout_mmc2.clk,
1216 .enable = exynos4_clksrc_mask_fsys_ctrl,
1217 .ctrlbit = (1 << 8),
1218 },
1219 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 8, .size = 8 },
1220 }, {
1221 .clk = {
1222 .name = "sclk_mmc",
1223 .devname = "s3c-sdhci.3",
1224 .parent = &clk_dout_mmc3.clk,
1225 .enable = exynos4_clksrc_mask_fsys_ctrl,
1226 .ctrlbit = (1 << 12),
1227 },
1228 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 },
1229 }, {
1230 .clk = {
1231 .name = "sclk_dwmmc", 1159 .name = "sclk_dwmmc",
1232 .parent = &clk_dout_mmc4.clk, 1160 .parent = &clk_dout_mmc4.clk,
1233 .enable = exynos4_clksrc_mask_fsys_ctrl, 1161 .enable = exynos4_clksrc_mask_fsys_ctrl,
@@ -1237,6 +1165,98 @@ static struct clksrc_clk clksrcs[] = {
1237 } 1165 }
1238}; 1166};
1239 1167
1168static struct clksrc_clk clk_sclk_uart0 = {
1169 .clk = {
1170 .name = "uclk1",
1171 .devname = "exynos4210-uart.0",
1172 .enable = exynos4_clksrc_mask_peril0_ctrl,
1173 .ctrlbit = (1 << 0),
1174 },
1175 .sources = &clkset_group,
1176 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 0, .size = 4 },
1177 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 0, .size = 4 },
1178};
1179
1180static struct clksrc_clk clk_sclk_uart1 = {
1181 .clk = {
1182 .name = "uclk1",
1183 .devname = "exynos4210-uart.1",
1184 .enable = exynos4_clksrc_mask_peril0_ctrl,
1185 .ctrlbit = (1 << 4),
1186 },
1187 .sources = &clkset_group,
1188 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 4, .size = 4 },
1189 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 4, .size = 4 },
1190};
1191
1192static struct clksrc_clk clk_sclk_uart2 = {
1193 .clk = {
1194 .name = "uclk1",
1195 .devname = "exynos4210-uart.2",
1196 .enable = exynos4_clksrc_mask_peril0_ctrl,
1197 .ctrlbit = (1 << 8),
1198 },
1199 .sources = &clkset_group,
1200 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 8, .size = 4 },
1201 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 8, .size = 4 },
1202};
1203
1204static struct clksrc_clk clk_sclk_uart3 = {
1205 .clk = {
1206 .name = "uclk1",
1207 .devname = "exynos4210-uart.3",
1208 .enable = exynos4_clksrc_mask_peril0_ctrl,
1209 .ctrlbit = (1 << 12),
1210 },
1211 .sources = &clkset_group,
1212 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 12, .size = 4 },
1213 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 12, .size = 4 },
1214};
1215
1216static struct clksrc_clk clk_sclk_mmc0 = {
1217 .clk = {
1218 .name = "sclk_mmc",
1219 .devname = "s3c-sdhci.0",
1220 .parent = &clk_dout_mmc0.clk,
1221 .enable = exynos4_clksrc_mask_fsys_ctrl,
1222 .ctrlbit = (1 << 0),
1223 },
1224 .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 8, .size = 8 },
1225};
1226
1227static struct clksrc_clk clk_sclk_mmc1 = {
1228 .clk = {
1229 .name = "sclk_mmc",
1230 .devname = "s3c-sdhci.1",
1231 .parent = &clk_dout_mmc1.clk,
1232 .enable = exynos4_clksrc_mask_fsys_ctrl,
1233 .ctrlbit = (1 << 4),
1234 },
1235 .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 24, .size = 8 },
1236};
1237
1238static struct clksrc_clk clk_sclk_mmc2 = {
1239 .clk = {
1240 .name = "sclk_mmc",
1241 .devname = "s3c-sdhci.2",
1242 .parent = &clk_dout_mmc2.clk,
1243 .enable = exynos4_clksrc_mask_fsys_ctrl,
1244 .ctrlbit = (1 << 8),
1245 },
1246 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 8, .size = 8 },
1247};
1248
1249static struct clksrc_clk clk_sclk_mmc3 = {
1250 .clk = {
1251 .name = "sclk_mmc",
1252 .devname = "s3c-sdhci.3",
1253 .parent = &clk_dout_mmc3.clk,
1254 .enable = exynos4_clksrc_mask_fsys_ctrl,
1255 .ctrlbit = (1 << 12),
1256 },
1257 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 },
1258};
1259
1240/* Clock initialization code */ 1260/* Clock initialization code */
1241static struct clksrc_clk *sysclks[] = { 1261static struct clksrc_clk *sysclks[] = {
1242 &clk_mout_apll, 1262 &clk_mout_apll,
@@ -1271,6 +1291,35 @@ static struct clksrc_clk *sysclks[] = {
1271 &clk_mout_mfc1, 1291 &clk_mout_mfc1,
1272}; 1292};
1273 1293
1294static struct clk *clk_cdev[] = {
1295 &clk_pdma0,
1296 &clk_pdma1,
1297};
1298
1299static struct clksrc_clk *clksrc_cdev[] = {
1300 &clk_sclk_uart0,
1301 &clk_sclk_uart1,
1302 &clk_sclk_uart2,
1303 &clk_sclk_uart3,
1304 &clk_sclk_mmc0,
1305 &clk_sclk_mmc1,
1306 &clk_sclk_mmc2,
1307 &clk_sclk_mmc3,
1308};
1309
1310static struct clk_lookup exynos4_clk_lookup[] = {
1311 CLKDEV_INIT("exynos4210-uart.0", "clk_uart_baud0", &clk_sclk_uart0.clk),
1312 CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &clk_sclk_uart1.clk),
1313 CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &clk_sclk_uart2.clk),
1314 CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &clk_sclk_uart3.clk),
1315 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
1316 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
1317 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
1318 CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &clk_sclk_mmc3.clk),
1319 CLKDEV_INIT("dma-pl330.0", "apb_pclk", &clk_pdma0),
1320 CLKDEV_INIT("dma-pl330.1", "apb_pclk", &clk_pdma1),
1321};
1322
1274static int xtal_rate; 1323static int xtal_rate;
1275 1324
1276static unsigned long exynos4_fout_apll_get_rate(struct clk *clk) 1325static unsigned long exynos4_fout_apll_get_rate(struct clk *clk)
@@ -1478,11 +1527,19 @@ void __init exynos4_register_clocks(void)
1478 for (ptr = 0; ptr < ARRAY_SIZE(sclk_tv); ptr++) 1527 for (ptr = 0; ptr < ARRAY_SIZE(sclk_tv); ptr++)
1479 s3c_register_clksrc(sclk_tv[ptr], 1); 1528 s3c_register_clksrc(sclk_tv[ptr], 1);
1480 1529
1530 for (ptr = 0; ptr < ARRAY_SIZE(clksrc_cdev); ptr++)
1531 s3c_register_clksrc(clksrc_cdev[ptr], 1);
1532
1481 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs)); 1533 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
1482 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks)); 1534 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
1483 1535
1536 s3c24xx_register_clocks(clk_cdev, ARRAY_SIZE(clk_cdev));
1537 for (ptr = 0; ptr < ARRAY_SIZE(clk_cdev); ptr++)
1538 s3c_disable_clocks(clk_cdev[ptr], 1);
1539
1484 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); 1540 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
1485 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); 1541 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
1542 clkdev_add_table(exynos4_clk_lookup, ARRAY_SIZE(exynos4_clk_lookup));
1486 1543
1487 register_syscore_ops(&exynos4_clock_syscore_ops); 1544 register_syscore_ops(&exynos4_clock_syscore_ops);
1488 s3c24xx_register_clock(&dummy_apb_pclk); 1545 s3c24xx_register_clock(&dummy_apb_pclk);
diff --git a/arch/arm/mach-exynos/cpu.c b/arch/arm/mach-exynos/cpu.c
index 90ec247f3b37..0eb7b6a6903d 100644
--- a/arch/arm/mach-exynos/cpu.c
+++ b/arch/arm/mach-exynos/cpu.c
@@ -10,6 +10,8 @@
10 10
11#include <linux/sched.h> 11#include <linux/sched.h>
12#include <linux/sysdev.h> 12#include <linux/sysdev.h>
13#include <linux/of.h>
14#include <linux/of_irq.h>
13 15
14#include <asm/mach/map.h> 16#include <asm/mach/map.h>
15#include <asm/mach/irq.h> 17#include <asm/mach/irq.h>
@@ -218,13 +220,26 @@ static void exynos4_gic_irq_fix_base(struct irq_data *d)
218 (gic_bank_offset * smp_processor_id()); 220 (gic_bank_offset * smp_processor_id());
219} 221}
220 222
223#ifdef CONFIG_OF
224static const struct of_device_id exynos4_dt_irq_match[] = {
225 { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
226 {},
227};
228#endif
229
221void __init exynos4_init_irq(void) 230void __init exynos4_init_irq(void)
222{ 231{
223 int irq; 232 int irq;
224 233
225 gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000; 234 gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000;
226 235
227 gic_init(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU); 236 if (!of_have_populated_dt())
237 gic_init(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU);
238#ifdef CONFIG_OF
239 else
240 of_irq_init(exynos4_dt_irq_match);
241#endif
242
228 gic_arch_extn.irq_eoi = exynos4_gic_irq_fix_base; 243 gic_arch_extn.irq_eoi = exynos4_gic_irq_fix_base;
229 gic_arch_extn.irq_unmask = exynos4_gic_irq_fix_base; 244 gic_arch_extn.irq_unmask = exynos4_gic_irq_fix_base;
230 gic_arch_extn.irq_mask = exynos4_gic_irq_fix_base; 245 gic_arch_extn.irq_mask = exynos4_gic_irq_fix_base;
diff --git a/arch/arm/mach-exynos/dma.c b/arch/arm/mach-exynos/dma.c
index 9667c61e64fb..b10fcd270f07 100644
--- a/arch/arm/mach-exynos/dma.c
+++ b/arch/arm/mach-exynos/dma.c
@@ -24,6 +24,7 @@
24#include <linux/dma-mapping.h> 24#include <linux/dma-mapping.h>
25#include <linux/amba/bus.h> 25#include <linux/amba/bus.h>
26#include <linux/amba/pl330.h> 26#include <linux/amba/pl330.h>
27#include <linux/of.h>
27 28
28#include <asm/irq.h> 29#include <asm/irq.h>
29#include <plat/devs.h> 30#include <plat/devs.h>
@@ -35,95 +36,42 @@
35 36
36static u64 dma_dmamask = DMA_BIT_MASK(32); 37static u64 dma_dmamask = DMA_BIT_MASK(32);
37 38
38struct dma_pl330_peri pdma0_peri[28] = { 39u8 pdma0_peri[] = {
39 { 40 DMACH_PCM0_RX,
40 .peri_id = (u8)DMACH_PCM0_RX, 41 DMACH_PCM0_TX,
41 .rqtype = DEVTOMEM, 42 DMACH_PCM2_RX,
42 }, { 43 DMACH_PCM2_TX,
43 .peri_id = (u8)DMACH_PCM0_TX, 44 DMACH_MSM_REQ0,
44 .rqtype = MEMTODEV, 45 DMACH_MSM_REQ2,
45 }, { 46 DMACH_SPI0_RX,
46 .peri_id = (u8)DMACH_PCM2_RX, 47 DMACH_SPI0_TX,
47 .rqtype = DEVTOMEM, 48 DMACH_SPI2_RX,
48 }, { 49 DMACH_SPI2_TX,
49 .peri_id = (u8)DMACH_PCM2_TX, 50 DMACH_I2S0S_TX,
50 .rqtype = MEMTODEV, 51 DMACH_I2S0_RX,
51 }, { 52 DMACH_I2S0_TX,
52 .peri_id = (u8)DMACH_MSM_REQ0, 53 DMACH_I2S2_RX,
53 }, { 54 DMACH_I2S2_TX,
54 .peri_id = (u8)DMACH_MSM_REQ2, 55 DMACH_UART0_RX,
55 }, { 56 DMACH_UART0_TX,
56 .peri_id = (u8)DMACH_SPI0_RX, 57 DMACH_UART2_RX,
57 .rqtype = DEVTOMEM, 58 DMACH_UART2_TX,
58 }, { 59 DMACH_UART4_RX,
59 .peri_id = (u8)DMACH_SPI0_TX, 60 DMACH_UART4_TX,
60 .rqtype = MEMTODEV, 61 DMACH_SLIMBUS0_RX,
61 }, { 62 DMACH_SLIMBUS0_TX,
62 .peri_id = (u8)DMACH_SPI2_RX, 63 DMACH_SLIMBUS2_RX,
63 .rqtype = DEVTOMEM, 64 DMACH_SLIMBUS2_TX,
64 }, { 65 DMACH_SLIMBUS4_RX,
65 .peri_id = (u8)DMACH_SPI2_TX, 66 DMACH_SLIMBUS4_TX,
66 .rqtype = MEMTODEV, 67 DMACH_AC97_MICIN,
67 }, { 68 DMACH_AC97_PCMIN,
68 .peri_id = (u8)DMACH_I2S0S_TX, 69 DMACH_AC97_PCMOUT,
69 .rqtype = MEMTODEV,
70 }, {
71 .peri_id = (u8)DMACH_I2S0_RX,
72 .rqtype = DEVTOMEM,
73 }, {
74 .peri_id = (u8)DMACH_I2S0_TX,
75 .rqtype = MEMTODEV,
76 }, {
77 .peri_id = (u8)DMACH_UART0_RX,
78 .rqtype = DEVTOMEM,
79 }, {
80 .peri_id = (u8)DMACH_UART0_TX,
81 .rqtype = MEMTODEV,
82 }, {
83 .peri_id = (u8)DMACH_UART2_RX,
84 .rqtype = DEVTOMEM,
85 }, {
86 .peri_id = (u8)DMACH_UART2_TX,
87 .rqtype = MEMTODEV,
88 }, {
89 .peri_id = (u8)DMACH_UART4_RX,
90 .rqtype = DEVTOMEM,
91 }, {
92 .peri_id = (u8)DMACH_UART4_TX,
93 .rqtype = MEMTODEV,
94 }, {
95 .peri_id = (u8)DMACH_SLIMBUS0_RX,
96 .rqtype = DEVTOMEM,
97 }, {
98 .peri_id = (u8)DMACH_SLIMBUS0_TX,
99 .rqtype = MEMTODEV,
100 }, {
101 .peri_id = (u8)DMACH_SLIMBUS2_RX,
102 .rqtype = DEVTOMEM,
103 }, {
104 .peri_id = (u8)DMACH_SLIMBUS2_TX,
105 .rqtype = MEMTODEV,
106 }, {
107 .peri_id = (u8)DMACH_SLIMBUS4_RX,
108 .rqtype = DEVTOMEM,
109 }, {
110 .peri_id = (u8)DMACH_SLIMBUS4_TX,
111 .rqtype = MEMTODEV,
112 }, {
113 .peri_id = (u8)DMACH_AC97_MICIN,
114 .rqtype = DEVTOMEM,
115 }, {
116 .peri_id = (u8)DMACH_AC97_PCMIN,
117 .rqtype = DEVTOMEM,
118 }, {
119 .peri_id = (u8)DMACH_AC97_PCMOUT,
120 .rqtype = MEMTODEV,
121 },
122}; 70};
123 71
124struct dma_pl330_platdata exynos4_pdma0_pdata = { 72struct dma_pl330_platdata exynos4_pdma0_pdata = {
125 .nr_valid_peri = ARRAY_SIZE(pdma0_peri), 73 .nr_valid_peri = ARRAY_SIZE(pdma0_peri),
126 .peri = pdma0_peri, 74 .peri_id = pdma0_peri,
127}; 75};
128 76
129struct amba_device exynos4_device_pdma0 = { 77struct amba_device exynos4_device_pdma0 = {
@@ -142,86 +90,37 @@ struct amba_device exynos4_device_pdma0 = {
142 .periphid = 0x00041330, 90 .periphid = 0x00041330,
143}; 91};
144 92
145struct dma_pl330_peri pdma1_peri[25] = { 93u8 pdma1_peri[] = {
146 { 94 DMACH_PCM0_RX,
147 .peri_id = (u8)DMACH_PCM0_RX, 95 DMACH_PCM0_TX,
148 .rqtype = DEVTOMEM, 96 DMACH_PCM1_RX,
149 }, { 97 DMACH_PCM1_TX,
150 .peri_id = (u8)DMACH_PCM0_TX, 98 DMACH_MSM_REQ1,
151 .rqtype = MEMTODEV, 99 DMACH_MSM_REQ3,
152 }, { 100 DMACH_SPI1_RX,
153 .peri_id = (u8)DMACH_PCM1_RX, 101 DMACH_SPI1_TX,
154 .rqtype = DEVTOMEM, 102 DMACH_I2S0S_TX,
155 }, { 103 DMACH_I2S0_RX,
156 .peri_id = (u8)DMACH_PCM1_TX, 104 DMACH_I2S0_TX,
157 .rqtype = MEMTODEV, 105 DMACH_I2S1_RX,
158 }, { 106 DMACH_I2S1_TX,
159 .peri_id = (u8)DMACH_MSM_REQ1, 107 DMACH_UART0_RX,
160 }, { 108 DMACH_UART0_TX,
161 .peri_id = (u8)DMACH_MSM_REQ3, 109 DMACH_UART1_RX,
162 }, { 110 DMACH_UART1_TX,
163 .peri_id = (u8)DMACH_SPI1_RX, 111 DMACH_UART3_RX,
164 .rqtype = DEVTOMEM, 112 DMACH_UART3_TX,
165 }, { 113 DMACH_SLIMBUS1_RX,
166 .peri_id = (u8)DMACH_SPI1_TX, 114 DMACH_SLIMBUS1_TX,
167 .rqtype = MEMTODEV, 115 DMACH_SLIMBUS3_RX,
168 }, { 116 DMACH_SLIMBUS3_TX,
169 .peri_id = (u8)DMACH_I2S0S_TX, 117 DMACH_SLIMBUS5_RX,
170 .rqtype = MEMTODEV, 118 DMACH_SLIMBUS5_TX,
171 }, {
172 .peri_id = (u8)DMACH_I2S0_RX,
173 .rqtype = DEVTOMEM,
174 }, {
175 .peri_id = (u8)DMACH_I2S0_TX,
176 .rqtype = MEMTODEV,
177 }, {
178 .peri_id = (u8)DMACH_I2S1_RX,
179 .rqtype = DEVTOMEM,
180 }, {
181 .peri_id = (u8)DMACH_I2S1_TX,
182 .rqtype = MEMTODEV,
183 }, {
184 .peri_id = (u8)DMACH_UART0_RX,
185 .rqtype = DEVTOMEM,
186 }, {
187 .peri_id = (u8)DMACH_UART0_TX,
188 .rqtype = MEMTODEV,
189 }, {
190 .peri_id = (u8)DMACH_UART1_RX,
191 .rqtype = DEVTOMEM,
192 }, {
193 .peri_id = (u8)DMACH_UART1_TX,
194 .rqtype = MEMTODEV,
195 }, {
196 .peri_id = (u8)DMACH_UART3_RX,
197 .rqtype = DEVTOMEM,
198 }, {
199 .peri_id = (u8)DMACH_UART3_TX,
200 .rqtype = MEMTODEV,
201 }, {
202 .peri_id = (u8)DMACH_SLIMBUS1_RX,
203 .rqtype = DEVTOMEM,
204 }, {
205 .peri_id = (u8)DMACH_SLIMBUS1_TX,
206 .rqtype = MEMTODEV,
207 }, {
208 .peri_id = (u8)DMACH_SLIMBUS3_RX,
209 .rqtype = DEVTOMEM,
210 }, {
211 .peri_id = (u8)DMACH_SLIMBUS3_TX,
212 .rqtype = MEMTODEV,
213 }, {
214 .peri_id = (u8)DMACH_SLIMBUS5_RX,
215 .rqtype = DEVTOMEM,
216 }, {
217 .peri_id = (u8)DMACH_SLIMBUS5_TX,
218 .rqtype = MEMTODEV,
219 },
220}; 119};
221 120
222struct dma_pl330_platdata exynos4_pdma1_pdata = { 121struct dma_pl330_platdata exynos4_pdma1_pdata = {
223 .nr_valid_peri = ARRAY_SIZE(pdma1_peri), 122 .nr_valid_peri = ARRAY_SIZE(pdma1_peri),
224 .peri = pdma1_peri, 123 .peri_id = pdma1_peri,
225}; 124};
226 125
227struct amba_device exynos4_device_pdma1 = { 126struct amba_device exynos4_device_pdma1 = {
@@ -242,7 +141,15 @@ struct amba_device exynos4_device_pdma1 = {
242 141
243static int __init exynos4_dma_init(void) 142static int __init exynos4_dma_init(void)
244{ 143{
144 if (of_have_populated_dt())
145 return 0;
146
147 dma_cap_set(DMA_SLAVE, exynos4_pdma0_pdata.cap_mask);
148 dma_cap_set(DMA_CYCLIC, exynos4_pdma0_pdata.cap_mask);
245 amba_device_register(&exynos4_device_pdma0, &iomem_resource); 149 amba_device_register(&exynos4_device_pdma0, &iomem_resource);
150
151 dma_cap_set(DMA_SLAVE, exynos4_pdma1_pdata.cap_mask);
152 dma_cap_set(DMA_CYCLIC, exynos4_pdma1_pdata.cap_mask);
246 amba_device_register(&exynos4_device_pdma1, &iomem_resource); 153 amba_device_register(&exynos4_device_pdma1, &iomem_resource);
247 154
248 return 0; 155 return 0;
diff --git a/arch/arm/mach-exynos/include/mach/entry-macro.S b/arch/arm/mach-exynos/include/mach/entry-macro.S
index f5e9fd8e37b4..d7dfcd7eb921 100644
--- a/arch/arm/mach-exynos/include/mach/entry-macro.S
+++ b/arch/arm/mach-exynos/include/mach/entry-macro.S
@@ -72,7 +72,6 @@
72 cmpcc \irqnr, \irqnr 72 cmpcc \irqnr, \irqnr
73 cmpne \irqnr, \tmp 73 cmpne \irqnr, \tmp
74 cmpcs \irqnr, \irqnr 74 cmpcs \irqnr, \irqnr
75 addne \irqnr, \irqnr, #32
76 75
77 .endm 76 .endm
78 77
diff --git a/arch/arm/mach-exynos/include/mach/irqs.h b/arch/arm/mach-exynos/include/mach/irqs.h
index dfd4b7eecb90..713dd5251c64 100644
--- a/arch/arm/mach-exynos/include/mach/irqs.h
+++ b/arch/arm/mach-exynos/include/mach/irqs.h
@@ -17,13 +17,13 @@
17 17
18/* PPI: Private Peripheral Interrupt */ 18/* PPI: Private Peripheral Interrupt */
19 19
20#define IRQ_PPI(x) S5P_IRQ(x+16) 20#define IRQ_PPI(x) (x+16)
21 21
22#define IRQ_MCT_LOCALTIMER IRQ_PPI(12) 22#define IRQ_MCT_LOCALTIMER IRQ_PPI(12)
23 23
24/* SPI: Shared Peripheral Interrupt */ 24/* SPI: Shared Peripheral Interrupt */
25 25
26#define IRQ_SPI(x) S5P_IRQ(x+32) 26#define IRQ_SPI(x) (x+32)
27 27
28#define IRQ_EINT0 IRQ_SPI(16) 28#define IRQ_EINT0 IRQ_SPI(16)
29#define IRQ_EINT1 IRQ_SPI(17) 29#define IRQ_EINT1 IRQ_SPI(17)
@@ -163,7 +163,9 @@
163#define IRQ_GPIO2_NR_GROUPS 9 163#define IRQ_GPIO2_NR_GROUPS 9
164#define IRQ_GPIO_END (S5P_GPIOINT_BASE + S5P_GPIOINT_COUNT) 164#define IRQ_GPIO_END (S5P_GPIOINT_BASE + S5P_GPIOINT_COUNT)
165 165
166#define IRQ_TIMER_BASE (IRQ_GPIO_END + 64)
167
166/* Set the default NR_IRQS */ 168/* Set the default NR_IRQS */
167#define NR_IRQS (IRQ_GPIO_END + 64) 169#define NR_IRQS (IRQ_TIMER_BASE + IRQ_TIMER_COUNT)
168 170
169#endif /* __ASM_ARCH_IRQS_H */ 171#endif /* __ASM_ARCH_IRQS_H */
diff --git a/arch/arm/mach-exynos/init.c b/arch/arm/mach-exynos/init.c
index a8a83e3881a4..5b35978029be 100644
--- a/arch/arm/mach-exynos/init.c
+++ b/arch/arm/mach-exynos/init.c
@@ -14,29 +14,14 @@
14#include <plat/devs.h> 14#include <plat/devs.h>
15#include <plat/regs-serial.h> 15#include <plat/regs-serial.h>
16 16
17static struct s3c24xx_uart_clksrc exynos4_serial_clocks[] = {
18 [0] = {
19 .name = "uclk1",
20 .divisor = 1,
21 .min_baud = 0,
22 .max_baud = 0,
23 },
24};
25
26/* uart registration process */ 17/* uart registration process */
27void __init exynos4_common_init_uarts(struct s3c2410_uartcfg *cfg, int no) 18void __init exynos4_common_init_uarts(struct s3c2410_uartcfg *cfg, int no)
28{ 19{
29 struct s3c2410_uartcfg *tcfg = cfg; 20 struct s3c2410_uartcfg *tcfg = cfg;
30 u32 ucnt; 21 u32 ucnt;
31 22
32 for (ucnt = 0; ucnt < no; ucnt++, tcfg++) { 23 for (ucnt = 0; ucnt < no; ucnt++, tcfg++)
33 if (!tcfg->clocks) { 24 tcfg->has_fracval = 1;
34 tcfg->has_fracval = 1;
35 tcfg->clocks = exynos4_serial_clocks;
36 tcfg->clocks_size = ARRAY_SIZE(exynos4_serial_clocks);
37 }
38 tcfg->flags |= NO_NEED_CHECK_CLKSRC;
39 }
40 25
41 s3c24xx_init_uartdevs("s5pv210-uart", s5p_uart_resources, cfg, no); 26 s3c24xx_init_uartdevs("exynos4210-uart", s5p_uart_resources, cfg, no);
42} 27}
diff --git a/arch/arm/mach-exynos/mach-exynos4-dt.c b/arch/arm/mach-exynos/mach-exynos4-dt.c
new file mode 100644
index 000000000000..85fa02767d67
--- /dev/null
+++ b/arch/arm/mach-exynos/mach-exynos4-dt.c
@@ -0,0 +1,85 @@
1/*
2 * Samsung's Exynos4210 flattened device tree enabled machine
3 *
4 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 * Copyright (c) 2010-2011 Linaro Ltd.
7 * www.linaro.org
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14#include <linux/of_platform.h>
15#include <linux/serial_core.h>
16
17#include <asm/mach/arch.h>
18#include <mach/map.h>
19
20#include <plat/cpu.h>
21#include <plat/regs-serial.h>
22#include <plat/exynos4.h>
23
24/*
25 * The following lookup table is used to override device names when devices
26 * are registered from device tree. This is temporarily added to enable
27 * device tree support addition for the Exynos4 architecture.
28 *
29 * For drivers that require platform data to be provided from the machine
30 * file, a platform data pointer can also be supplied along with the
31 * devices names. Usually, the platform data elements that cannot be parsed
32 * from the device tree by the drivers (example: function pointers) are
33 * supplied. But it should be noted that this is a temporary mechanism and
34 * at some point, the drivers should be capable of parsing all the platform
35 * data from the device tree.
36 */
37static const struct of_dev_auxdata exynos4210_auxdata_lookup[] __initconst = {
38 OF_DEV_AUXDATA("samsung,exynos4210-uart", S5P_PA_UART0,
39 "exynos4210-uart.0", NULL),
40 OF_DEV_AUXDATA("samsung,exynos4210-uart", S5P_PA_UART1,
41 "exynos4210-uart.1", NULL),
42 OF_DEV_AUXDATA("samsung,exynos4210-uart", S5P_PA_UART2,
43 "exynos4210-uart.2", NULL),
44 OF_DEV_AUXDATA("samsung,exynos4210-uart", S5P_PA_UART3,
45 "exynos4210-uart.3", NULL),
46 OF_DEV_AUXDATA("samsung,exynos4210-sdhci", EXYNOS4_PA_HSMMC(0),
47 "exynos4-sdhci.0", NULL),
48 OF_DEV_AUXDATA("samsung,exynos4210-sdhci", EXYNOS4_PA_HSMMC(1),
49 "exynos4-sdhci.1", NULL),
50 OF_DEV_AUXDATA("samsung,exynos4210-sdhci", EXYNOS4_PA_HSMMC(2),
51 "exynos4-sdhci.2", NULL),
52 OF_DEV_AUXDATA("samsung,exynos4210-sdhci", EXYNOS4_PA_HSMMC(3),
53 "exynos4-sdhci.3", NULL),
54 OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(0),
55 "s3c2440-i2c.0", NULL),
56 OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_PDMA0, "dma-pl330.0", NULL),
57 OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_PDMA1, "dma-pl330.1", NULL),
58 {},
59};
60
61static void __init exynos4210_dt_map_io(void)
62{
63 s5p_init_io(NULL, 0, S5P_VA_CHIPID);
64 s3c24xx_init_clocks(24000000);
65}
66
67static void __init exynos4210_dt_machine_init(void)
68{
69 of_platform_populate(NULL, of_default_bus_match_table,
70 exynos4210_auxdata_lookup, NULL);
71}
72
73static char const *exynos4210_dt_compat[] __initdata = {
74 "samsung,exynos4210",
75 NULL
76};
77
78DT_MACHINE_START(EXYNOS4210_DT, "Samsung Exynos4 (Flattened Device Tree)")
79 /* Maintainer: Thomas Abraham <thomas.abraham@linaro.org> */
80 .init_irq = exynos4_init_irq,
81 .map_io = exynos4210_dt_map_io,
82 .init_machine = exynos4210_dt_machine_init,
83 .timer = &exynos4_timer,
84 .dt_compat = exynos4210_dt_compat,
85MACHINE_END
diff --git a/arch/arm/mach-exynos/setup-sdhci.c b/arch/arm/mach-exynos/setup-sdhci.c
deleted file mode 100644
index 92937b410906..000000000000
--- a/arch/arm/mach-exynos/setup-sdhci.c
+++ /dev/null
@@ -1,22 +0,0 @@
1/* linux/arch/arm/mach-exynos4/setup-sdhci.c
2 *
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * EXYNOS4 - Helper functions for settign up SDHCI device(s) (HSMMC)
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/types.h>
14
15/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */
16
17char *exynos4_hsmmc_clksrcs[4] = {
18 [0] = NULL,
19 [1] = NULL,
20 [2] = "sclk_mmc", /* mmc_bus */
21 [3] = NULL,
22};
diff --git a/arch/arm/mach-s3c2410/mach-bast.c b/arch/arm/mach-s3c2410/mach-bast.c
index a20ae1ad4062..71b955877793 100644
--- a/arch/arm/mach-s3c2410/mach-bast.c
+++ b/arch/arm/mach-s3c2410/mach-bast.c
@@ -164,22 +164,6 @@ static struct map_desc bast_iodesc[] __initdata = {
164#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB 164#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
165#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE 165#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
166 166
167static struct s3c24xx_uart_clksrc bast_serial_clocks[] = {
168 [0] = {
169 .name = "uclk",
170 .divisor = 1,
171 .min_baud = 0,
172 .max_baud = 0,
173 },
174 [1] = {
175 .name = "pclk",
176 .divisor = 1,
177 .min_baud = 0,
178 .max_baud = 0,
179 }
180};
181
182
183static struct s3c2410_uartcfg bast_uartcfgs[] __initdata = { 167static struct s3c2410_uartcfg bast_uartcfgs[] __initdata = {
184 [0] = { 168 [0] = {
185 .hwport = 0, 169 .hwport = 0,
@@ -187,8 +171,6 @@ static struct s3c2410_uartcfg bast_uartcfgs[] __initdata = {
187 .ucon = UCON, 171 .ucon = UCON,
188 .ulcon = ULCON, 172 .ulcon = ULCON,
189 .ufcon = UFCON, 173 .ufcon = UFCON,
190 .clocks = bast_serial_clocks,
191 .clocks_size = ARRAY_SIZE(bast_serial_clocks),
192 }, 174 },
193 [1] = { 175 [1] = {
194 .hwport = 1, 176 .hwport = 1,
@@ -196,8 +178,6 @@ static struct s3c2410_uartcfg bast_uartcfgs[] __initdata = {
196 .ucon = UCON, 178 .ucon = UCON,
197 .ulcon = ULCON, 179 .ulcon = ULCON,
198 .ufcon = UFCON, 180 .ufcon = UFCON,
199 .clocks = bast_serial_clocks,
200 .clocks_size = ARRAY_SIZE(bast_serial_clocks),
201 }, 181 },
202 /* port 2 is not actually used */ 182 /* port 2 is not actually used */
203 [2] = { 183 [2] = {
@@ -206,8 +186,6 @@ static struct s3c2410_uartcfg bast_uartcfgs[] __initdata = {
206 .ucon = UCON, 186 .ucon = UCON,
207 .ulcon = ULCON, 187 .ulcon = ULCON,
208 .ufcon = UFCON, 188 .ufcon = UFCON,
209 .clocks = bast_serial_clocks,
210 .clocks_size = ARRAY_SIZE(bast_serial_clocks),
211 } 189 }
212}; 190};
213 191
diff --git a/arch/arm/mach-s3c2410/mach-vr1000.c b/arch/arm/mach-s3c2410/mach-vr1000.c
index df47e8e90065..0f0a9a1795e9 100644
--- a/arch/arm/mach-s3c2410/mach-vr1000.c
+++ b/arch/arm/mach-s3c2410/mach-vr1000.c
@@ -109,23 +109,6 @@ static struct map_desc vr1000_iodesc[] __initdata = {
109#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB 109#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
110#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE 110#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
111 111
112/* uart clock source(s) */
113
114static struct s3c24xx_uart_clksrc vr1000_serial_clocks[] = {
115 [0] = {
116 .name = "uclk",
117 .divisor = 1,
118 .min_baud = 0,
119 .max_baud = 0,
120 },
121 [1] = {
122 .name = "pclk",
123 .divisor = 1,
124 .min_baud = 0,
125 .max_baud = 0.
126 }
127};
128
129static struct s3c2410_uartcfg vr1000_uartcfgs[] __initdata = { 112static struct s3c2410_uartcfg vr1000_uartcfgs[] __initdata = {
130 [0] = { 113 [0] = {
131 .hwport = 0, 114 .hwport = 0,
@@ -133,8 +116,6 @@ static struct s3c2410_uartcfg vr1000_uartcfgs[] __initdata = {
133 .ucon = UCON, 116 .ucon = UCON,
134 .ulcon = ULCON, 117 .ulcon = ULCON,
135 .ufcon = UFCON, 118 .ufcon = UFCON,
136 .clocks = vr1000_serial_clocks,
137 .clocks_size = ARRAY_SIZE(vr1000_serial_clocks),
138 }, 119 },
139 [1] = { 120 [1] = {
140 .hwport = 1, 121 .hwport = 1,
@@ -142,8 +123,6 @@ static struct s3c2410_uartcfg vr1000_uartcfgs[] __initdata = {
142 .ucon = UCON, 123 .ucon = UCON,
143 .ulcon = ULCON, 124 .ulcon = ULCON,
144 .ufcon = UFCON, 125 .ufcon = UFCON,
145 .clocks = vr1000_serial_clocks,
146 .clocks_size = ARRAY_SIZE(vr1000_serial_clocks),
147 }, 126 },
148 /* port 2 is not actually used */ 127 /* port 2 is not actually used */
149 [2] = { 128 [2] = {
@@ -152,9 +131,6 @@ static struct s3c2410_uartcfg vr1000_uartcfgs[] __initdata = {
152 .ucon = UCON, 131 .ucon = UCON,
153 .ulcon = ULCON, 132 .ulcon = ULCON,
154 .ufcon = UFCON, 133 .ufcon = UFCON,
155 .clocks = vr1000_serial_clocks,
156 .clocks_size = ARRAY_SIZE(vr1000_serial_clocks),
157
158 } 134 }
159}; 135};
160 136
diff --git a/arch/arm/mach-s3c2410/s3c2410.c b/arch/arm/mach-s3c2410/s3c2410.c
index 3d7ebc557a72..af74927bca14 100644
--- a/arch/arm/mach-s3c2410/s3c2410.c
+++ b/arch/arm/mach-s3c2410/s3c2410.c
@@ -123,12 +123,18 @@ static struct clk s3c2410_armclk = {
123 .id = -1, 123 .id = -1,
124}; 124};
125 125
126static struct clk_lookup s3c2410_clk_lookup[] = {
127 CLKDEV_INIT(NULL, "clk_uart_baud0", &clk_p),
128 CLKDEV_INIT(NULL, "clk_uart_baud1", &s3c24xx_uclk),
129};
130
126void __init s3c2410_init_clocks(int xtal) 131void __init s3c2410_init_clocks(int xtal)
127{ 132{
128 s3c24xx_register_baseclocks(xtal); 133 s3c24xx_register_baseclocks(xtal);
129 s3c2410_setup_clocks(); 134 s3c2410_setup_clocks();
130 s3c2410_baseclk_add(); 135 s3c2410_baseclk_add();
131 s3c24xx_register_clock(&s3c2410_armclk); 136 s3c24xx_register_clock(&s3c2410_armclk);
137 clkdev_add_table(s3c2410_clk_lookup, ARRAY_SIZE(s3c2410_clk_lookup));
132} 138}
133 139
134struct sysdev_class s3c2410_sysclass = { 140struct sysdev_class s3c2410_sysclass = {
diff --git a/arch/arm/mach-s3c2412/clock.c b/arch/arm/mach-s3c2412/clock.c
index 140711db6c89..cd50291931f7 100644
--- a/arch/arm/mach-s3c2412/clock.c
+++ b/arch/arm/mach-s3c2412/clock.c
@@ -659,6 +659,12 @@ static struct clk *clks[] __initdata = {
659 &clk_armclk, 659 &clk_armclk,
660}; 660};
661 661
662static struct clk_lookup s3c2412_clk_lookup[] = {
663 CLKDEV_INIT(NULL, "clk_uart_baud1", &s3c24xx_uclk),
664 CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p),
665 CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_usysclk),
666};
667
662int __init s3c2412_baseclk_add(void) 668int __init s3c2412_baseclk_add(void)
663{ 669{
664 unsigned long clkcon = __raw_readl(S3C2410_CLKCON); 670 unsigned long clkcon = __raw_readl(S3C2410_CLKCON);
@@ -751,6 +757,7 @@ int __init s3c2412_baseclk_add(void)
751 s3c2412_clkcon_enable(clkp, 0); 757 s3c2412_clkcon_enable(clkp, 0);
752 } 758 }
753 759
760 clkdev_add_table(s3c2412_clk_lookup, ARRAY_SIZE(s3c2412_clk_lookup));
754 s3c_pwmclk_init(); 761 s3c_pwmclk_init();
755 return 0; 762 return 0;
756} 763}
diff --git a/arch/arm/mach-s3c2416/Makefile b/arch/arm/mach-s3c2416/Makefile
index 7b805b279caf..ca0cd227f873 100644
--- a/arch/arm/mach-s3c2416/Makefile
+++ b/arch/arm/mach-s3c2416/Makefile
@@ -15,7 +15,6 @@ obj-$(CONFIG_S3C2416_PM) += pm.o
15#obj-$(CONFIG_S3C2416_DMA) += dma.o 15#obj-$(CONFIG_S3C2416_DMA) += dma.o
16 16
17# Device setup 17# Device setup
18obj-$(CONFIG_S3C2416_SETUP_SDHCI) += setup-sdhci.o
19obj-$(CONFIG_S3C2416_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o 18obj-$(CONFIG_S3C2416_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o
20 19
21# Machine support 20# Machine support
diff --git a/arch/arm/mach-s3c2416/clock.c b/arch/arm/mach-s3c2416/clock.c
index afbbe8bc21d1..59f54d1d7f8b 100644
--- a/arch/arm/mach-s3c2416/clock.c
+++ b/arch/arm/mach-s3c2416/clock.c
@@ -90,39 +90,38 @@ static struct clksrc_clk hsmmc_div[] = {
90 }, 90 },
91}; 91};
92 92
93static struct clksrc_clk hsmmc_mux[] = { 93static struct clksrc_clk hsmmc_mux0 = {
94 [0] = { 94 .clk = {
95 .clk = { 95 .name = "hsmmc-if",
96 .name = "hsmmc-if", 96 .devname = "s3c-sdhci.0",
97 .devname = "s3c-sdhci.0", 97 .ctrlbit = (1 << 6),
98 .ctrlbit = (1 << 6), 98 .enable = s3c2443_clkcon_enable_s,
99 .enable = s3c2443_clkcon_enable_s,
100 },
101 .sources = &(struct clksrc_sources) {
102 .nr_sources = 2,
103 .sources = (struct clk *[]) {
104 [0] = &hsmmc_div[0].clk,
105 [1] = NULL, /* to fix */
106 },
107 },
108 .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 16 },
109 }, 99 },
110 [1] = { 100 .sources = &(struct clksrc_sources) {
111 .clk = { 101 .nr_sources = 2,
112 .name = "hsmmc-if", 102 .sources = (struct clk * []) {
113 .devname = "s3c-sdhci.1", 103 [0] = &hsmmc_div[0].clk,
114 .ctrlbit = (1 << 12), 104 [1] = NULL, /* to fix */
115 .enable = s3c2443_clkcon_enable_s,
116 }, 105 },
117 .sources = &(struct clksrc_sources) { 106 },
118 .nr_sources = 2, 107 .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 16 },
119 .sources = (struct clk *[]) { 108};
120 [0] = &hsmmc_div[1].clk, 109
121 [1] = NULL, /* to fix */ 110static struct clksrc_clk hsmmc_mux1 = {
122 }, 111 .clk = {
112 .name = "hsmmc-if",
113 .devname = "s3c-sdhci.1",
114 .ctrlbit = (1 << 12),
115 .enable = s3c2443_clkcon_enable_s,
116 },
117 .sources = &(struct clksrc_sources) {
118 .nr_sources = 2,
119 .sources = (struct clk * []) {
120 [0] = &hsmmc_div[1].clk,
121 [1] = NULL, /* to fix */
123 }, 122 },
124 .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 17 },
125 }, 123 },
124 .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 17 },
126}; 125};
127 126
128static struct clk hsmmc0_clk = { 127static struct clk hsmmc0_clk = {
@@ -144,8 +143,14 @@ static struct clksrc_clk *clksrcs[] __initdata = {
144 &hsspi_mux, 143 &hsspi_mux,
145 &hsmmc_div[0], 144 &hsmmc_div[0],
146 &hsmmc_div[1], 145 &hsmmc_div[1],
147 &hsmmc_mux[0], 146 &hsmmc_mux0,
148 &hsmmc_mux[1], 147 &hsmmc_mux1,
148};
149
150static struct clk_lookup s3c2416_clk_lookup[] = {
151 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &hsmmc0_clk),
152 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &hsmmc_mux0.clk),
153 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &hsmmc_mux1.clk),
149}; 154};
150 155
151void __init s3c2416_init_clocks(int xtal) 156void __init s3c2416_init_clocks(int xtal)
@@ -167,6 +172,7 @@ void __init s3c2416_init_clocks(int xtal)
167 s3c_register_clksrc(clksrcs[ptr], 1); 172 s3c_register_clksrc(clksrcs[ptr], 1);
168 173
169 s3c24xx_register_clock(&hsmmc0_clk); 174 s3c24xx_register_clock(&hsmmc0_clk);
175 clkdev_add_table(s3c2416_clk_lookup, ARRAY_SIZE(s3c2416_clk_lookup));
170 176
171 s3c_pwmclk_init(); 177 s3c_pwmclk_init();
172 178
diff --git a/arch/arm/mach-s3c2416/setup-sdhci.c b/arch/arm/mach-s3c2416/setup-sdhci.c
deleted file mode 100644
index cee53955eb02..000000000000
--- a/arch/arm/mach-s3c2416/setup-sdhci.c
+++ /dev/null
@@ -1,24 +0,0 @@
1/* linux/arch/arm/mach-s3c2416/setup-sdhci.c
2 *
3 * Copyright 2010 Promwad Innovation Company
4 * Yauhen Kharuzhy <yauhen.kharuzhy@promwad.com>
5 *
6 * S3C2416 - Helper functions for settign up SDHCI device(s) (HSMMC)
7 *
8 * Based on mach-s3c64xx/setup-sdhci.c
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#include <linux/types.h>
16
17/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */
18
19char *s3c2416_hsmmc_clksrcs[4] = {
20 [0] = "hsmmc",
21 [1] = "hsmmc",
22 [2] = "hsmmc-if",
23 /* [3] = "48m", - note not successfully used yet */
24};
diff --git a/arch/arm/mach-s3c2440/clock.c b/arch/arm/mach-s3c2440/clock.c
index f9e6bdaf41d2..c9879af42b08 100644
--- a/arch/arm/mach-s3c2440/clock.c
+++ b/arch/arm/mach-s3c2440/clock.c
@@ -34,6 +34,7 @@
34#include <linux/mutex.h> 34#include <linux/mutex.h>
35#include <linux/clk.h> 35#include <linux/clk.h>
36#include <linux/io.h> 36#include <linux/io.h>
37#include <linux/serial_core.h>
37 38
38#include <mach/hardware.h> 39#include <mach/hardware.h>
39#include <linux/atomic.h> 40#include <linux/atomic.h>
@@ -43,6 +44,7 @@
43 44
44#include <plat/clock.h> 45#include <plat/clock.h>
45#include <plat/cpu.h> 46#include <plat/cpu.h>
47#include <plat/regs-serial.h>
46 48
47/* S3C2440 extended clock support */ 49/* S3C2440 extended clock support */
48 50
@@ -108,6 +110,46 @@ static struct clk s3c2440_clk_ac97 = {
108 .ctrlbit = S3C2440_CLKCON_CAMERA, 110 .ctrlbit = S3C2440_CLKCON_CAMERA,
109}; 111};
110 112
113static unsigned long s3c2440_fclk_n_getrate(struct clk *clk)
114{
115 unsigned long ucon0, ucon1, ucon2, divisor;
116
117 /* the fun of calculating the uart divisors on the s3c2440 */
118 ucon0 = __raw_readl(S3C24XX_VA_UART0 + S3C2410_UCON);
119 ucon1 = __raw_readl(S3C24XX_VA_UART1 + S3C2410_UCON);
120 ucon2 = __raw_readl(S3C24XX_VA_UART2 + S3C2410_UCON);
121
122 ucon0 &= S3C2440_UCON0_DIVMASK;
123 ucon1 &= S3C2440_UCON1_DIVMASK;
124 ucon2 &= S3C2440_UCON2_DIVMASK;
125
126 if (ucon0 != 0)
127 divisor = (ucon0 >> S3C2440_UCON_DIVSHIFT) + 6;
128 else if (ucon1 != 0)
129 divisor = (ucon1 >> S3C2440_UCON_DIVSHIFT) + 21;
130 else if (ucon2 != 0)
131 divisor = (ucon2 >> S3C2440_UCON_DIVSHIFT) + 36;
132 else
133 /* manual calims 44, seems to be 9 */
134 divisor = 9;
135
136 return clk_get_rate(clk->parent) / divisor;
137}
138
139static struct clk s3c2440_clk_fclk_n = {
140 .name = "fclk_n",
141 .parent = &clk_f,
142 .ops = &(struct clk_ops) {
143 .get_rate = s3c2440_fclk_n_getrate,
144 },
145};
146
147static struct clk_lookup s3c2440_clk_lookup[] = {
148 CLKDEV_INIT(NULL, "clk_uart_baud1", &s3c24xx_uclk),
149 CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p),
150 CLKDEV_INIT(NULL, "clk_uart_baud3", &s3c2440_clk_fclk_n),
151};
152
111static int s3c2440_clk_add(struct sys_device *sysdev) 153static int s3c2440_clk_add(struct sys_device *sysdev)
112{ 154{
113 struct clk *clock_upll; 155 struct clk *clock_upll;
@@ -126,10 +168,12 @@ static int s3c2440_clk_add(struct sys_device *sysdev)
126 s3c2440_clk_cam.parent = clock_h; 168 s3c2440_clk_cam.parent = clock_h;
127 s3c2440_clk_ac97.parent = clock_p; 169 s3c2440_clk_ac97.parent = clock_p;
128 s3c2440_clk_cam_upll.parent = clock_upll; 170 s3c2440_clk_cam_upll.parent = clock_upll;
171 s3c24xx_register_clock(&s3c2440_clk_fclk_n);
129 172
130 s3c24xx_register_clock(&s3c2440_clk_ac97); 173 s3c24xx_register_clock(&s3c2440_clk_ac97);
131 s3c24xx_register_clock(&s3c2440_clk_cam); 174 s3c24xx_register_clock(&s3c2440_clk_cam);
132 s3c24xx_register_clock(&s3c2440_clk_cam_upll); 175 s3c24xx_register_clock(&s3c2440_clk_cam_upll);
176 clkdev_add_table(s3c2440_clk_lookup, ARRAY_SIZE(s3c2440_clk_lookup));
133 177
134 clk_disable(&s3c2440_clk_ac97); 178 clk_disable(&s3c2440_clk_ac97);
135 clk_disable(&s3c2440_clk_cam); 179 clk_disable(&s3c2440_clk_cam);
diff --git a/arch/arm/mach-s3c2440/mach-anubis.c b/arch/arm/mach-s3c2440/mach-anubis.c
index 74f92fc3fd04..d8f36c0a16ad 100644
--- a/arch/arm/mach-s3c2440/mach-anubis.c
+++ b/arch/arm/mach-s3c2440/mach-anubis.c
@@ -96,22 +96,6 @@ static struct map_desc anubis_iodesc[] __initdata = {
96#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB 96#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
97#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE 97#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
98 98
99static struct s3c24xx_uart_clksrc anubis_serial_clocks[] = {
100 [0] = {
101 .name = "uclk",
102 .divisor = 1,
103 .min_baud = 0,
104 .max_baud = 0,
105 },
106 [1] = {
107 .name = "pclk",
108 .divisor = 1,
109 .min_baud = 0,
110 .max_baud = 0,
111 }
112};
113
114
115static struct s3c2410_uartcfg anubis_uartcfgs[] __initdata = { 99static struct s3c2410_uartcfg anubis_uartcfgs[] __initdata = {
116 [0] = { 100 [0] = {
117 .hwport = 0, 101 .hwport = 0,
@@ -119,8 +103,7 @@ static struct s3c2410_uartcfg anubis_uartcfgs[] __initdata = {
119 .ucon = UCON, 103 .ucon = UCON,
120 .ulcon = ULCON, 104 .ulcon = ULCON,
121 .ufcon = UFCON, 105 .ufcon = UFCON,
122 .clocks = anubis_serial_clocks, 106 .clk_sel = S3C2410_UCON_CLKSEL1 | S3C2410_UCON_CLKSEL2,
123 .clocks_size = ARRAY_SIZE(anubis_serial_clocks),
124 }, 107 },
125 [1] = { 108 [1] = {
126 .hwport = 2, 109 .hwport = 2,
@@ -128,8 +111,7 @@ static struct s3c2410_uartcfg anubis_uartcfgs[] __initdata = {
128 .ucon = UCON, 111 .ucon = UCON,
129 .ulcon = ULCON, 112 .ulcon = ULCON,
130 .ufcon = UFCON, 113 .ufcon = UFCON,
131 .clocks = anubis_serial_clocks, 114 .clk_sel = S3C2410_UCON_CLKSEL1 | S3C2410_UCON_CLKSEL2,
132 .clocks_size = ARRAY_SIZE(anubis_serial_clocks),
133 }, 115 },
134}; 116};
135 117
diff --git a/arch/arm/mach-s3c2440/mach-at2440evb.c b/arch/arm/mach-s3c2440/mach-at2440evb.c
index 38887ee0c784..aa86ca8fa1e9 100644
--- a/arch/arm/mach-s3c2440/mach-at2440evb.c
+++ b/arch/arm/mach-s3c2440/mach-at2440evb.c
@@ -57,22 +57,6 @@ static struct map_desc at2440evb_iodesc[] __initdata = {
57#define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE) 57#define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE)
58#define UFCON (S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE) 58#define UFCON (S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE)
59 59
60static struct s3c24xx_uart_clksrc at2440evb_serial_clocks[] = {
61 [0] = {
62 .name = "uclk",
63 .divisor = 1,
64 .min_baud = 0,
65 .max_baud = 0,
66 },
67 [1] = {
68 .name = "pclk",
69 .divisor = 1,
70 .min_baud = 0,
71 .max_baud = 0,
72 }
73};
74
75
76static struct s3c2410_uartcfg at2440evb_uartcfgs[] __initdata = { 60static struct s3c2410_uartcfg at2440evb_uartcfgs[] __initdata = {
77 [0] = { 61 [0] = {
78 .hwport = 0, 62 .hwport = 0,
@@ -80,8 +64,7 @@ static struct s3c2410_uartcfg at2440evb_uartcfgs[] __initdata = {
80 .ucon = UCON, 64 .ucon = UCON,
81 .ulcon = ULCON, 65 .ulcon = ULCON,
82 .ufcon = UFCON, 66 .ufcon = UFCON,
83 .clocks = at2440evb_serial_clocks, 67 .clk_sel = S3C2410_UCON_CLKSEL1 | S3C2410_UCON_CLKSEL2,
84 .clocks_size = ARRAY_SIZE(at2440evb_serial_clocks),
85 }, 68 },
86 [1] = { 69 [1] = {
87 .hwport = 1, 70 .hwport = 1,
@@ -89,8 +72,7 @@ static struct s3c2410_uartcfg at2440evb_uartcfgs[] __initdata = {
89 .ucon = UCON, 72 .ucon = UCON,
90 .ulcon = ULCON, 73 .ulcon = ULCON,
91 .ufcon = UFCON, 74 .ufcon = UFCON,
92 .clocks = at2440evb_serial_clocks, 75 .clk_sel = S3C2410_UCON_CLKSEL1 | S3C2410_UCON_CLKSEL2,
93 .clocks_size = ARRAY_SIZE(at2440evb_serial_clocks),
94 }, 76 },
95}; 77};
96 78
diff --git a/arch/arm/mach-s3c2440/mach-osiris.c b/arch/arm/mach-s3c2440/mach-osiris.c
index dc142ebf8cba..d7e47b2b6ec9 100644
--- a/arch/arm/mach-s3c2440/mach-osiris.c
+++ b/arch/arm/mach-s3c2440/mach-osiris.c
@@ -100,21 +100,6 @@ static struct map_desc osiris_iodesc[] __initdata = {
100#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB 100#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
101#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE 101#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
102 102
103static struct s3c24xx_uart_clksrc osiris_serial_clocks[] = {
104 [0] = {
105 .name = "uclk",
106 .divisor = 1,
107 .min_baud = 0,
108 .max_baud = 0,
109 },
110 [1] = {
111 .name = "pclk",
112 .divisor = 1,
113 .min_baud = 0,
114 .max_baud = 0,
115 }
116};
117
118static struct s3c2410_uartcfg osiris_uartcfgs[] __initdata = { 103static struct s3c2410_uartcfg osiris_uartcfgs[] __initdata = {
119 [0] = { 104 [0] = {
120 .hwport = 0, 105 .hwport = 0,
@@ -122,8 +107,7 @@ static struct s3c2410_uartcfg osiris_uartcfgs[] __initdata = {
122 .ucon = UCON, 107 .ucon = UCON,
123 .ulcon = ULCON, 108 .ulcon = ULCON,
124 .ufcon = UFCON, 109 .ufcon = UFCON,
125 .clocks = osiris_serial_clocks, 110 .clk_sel = S3C2410_UCON_CLKSEL1 | S3C2410_UCON_CLKSEL2,
126 .clocks_size = ARRAY_SIZE(osiris_serial_clocks),
127 }, 111 },
128 [1] = { 112 [1] = {
129 .hwport = 1, 113 .hwport = 1,
@@ -131,8 +115,7 @@ static struct s3c2410_uartcfg osiris_uartcfgs[] __initdata = {
131 .ucon = UCON, 115 .ucon = UCON,
132 .ulcon = ULCON, 116 .ulcon = ULCON,
133 .ufcon = UFCON, 117 .ufcon = UFCON,
134 .clocks = osiris_serial_clocks, 118 .clk_sel = S3C2410_UCON_CLKSEL1 | S3C2410_UCON_CLKSEL2,
135 .clocks_size = ARRAY_SIZE(osiris_serial_clocks),
136 }, 119 },
137 [2] = { 120 [2] = {
138 .hwport = 2, 121 .hwport = 2,
@@ -140,8 +123,7 @@ static struct s3c2410_uartcfg osiris_uartcfgs[] __initdata = {
140 .ucon = UCON, 123 .ucon = UCON,
141 .ulcon = ULCON, 124 .ulcon = ULCON,
142 .ufcon = UFCON, 125 .ufcon = UFCON,
143 .clocks = osiris_serial_clocks, 126 .clk_sel = S3C2410_UCON_CLKSEL1 | S3C2410_UCON_CLKSEL2,
144 .clocks_size = ARRAY_SIZE(osiris_serial_clocks),
145 } 127 }
146}; 128};
147 129
diff --git a/arch/arm/mach-s3c2440/mach-rx1950.c b/arch/arm/mach-s3c2440/mach-rx1950.c
index 0d3453bf567c..4267cd56bfe7 100644
--- a/arch/arm/mach-s3c2440/mach-rx1950.c
+++ b/arch/arm/mach-s3c2440/mach-rx1950.c
@@ -68,15 +68,6 @@
68static struct map_desc rx1950_iodesc[] __initdata = { 68static struct map_desc rx1950_iodesc[] __initdata = {
69}; 69};
70 70
71static struct s3c24xx_uart_clksrc rx1950_serial_clocks[] = {
72 [0] = {
73 .name = "fclk",
74 .divisor = 0x0a,
75 .min_baud = 0,
76 .max_baud = 0,
77 },
78};
79
80static struct s3c2410_uartcfg rx1950_uartcfgs[] __initdata = { 71static struct s3c2410_uartcfg rx1950_uartcfgs[] __initdata = {
81 [0] = { 72 [0] = {
82 .hwport = 0, 73 .hwport = 0,
@@ -84,8 +75,7 @@ static struct s3c2410_uartcfg rx1950_uartcfgs[] __initdata = {
84 .ucon = 0x3c5, 75 .ucon = 0x3c5,
85 .ulcon = 0x03, 76 .ulcon = 0x03,
86 .ufcon = 0x51, 77 .ufcon = 0x51,
87 .clocks = rx1950_serial_clocks, 78 .clk_sel = S3C2410_UCON_CLKSEL3,
88 .clocks_size = ARRAY_SIZE(rx1950_serial_clocks),
89 }, 79 },
90 [1] = { 80 [1] = {
91 .hwport = 1, 81 .hwport = 1,
@@ -93,8 +83,7 @@ static struct s3c2410_uartcfg rx1950_uartcfgs[] __initdata = {
93 .ucon = 0x3c5, 83 .ucon = 0x3c5,
94 .ulcon = 0x03, 84 .ulcon = 0x03,
95 .ufcon = 0x51, 85 .ufcon = 0x51,
96 .clocks = rx1950_serial_clocks, 86 .clk_sel = S3C2410_UCON_CLKSEL3,
97 .clocks_size = ARRAY_SIZE(rx1950_serial_clocks),
98 }, 87 },
99 /* IR port */ 88 /* IR port */
100 [2] = { 89 [2] = {
@@ -103,8 +92,7 @@ static struct s3c2410_uartcfg rx1950_uartcfgs[] __initdata = {
103 .ucon = 0x3c5, 92 .ucon = 0x3c5,
104 .ulcon = 0x43, 93 .ulcon = 0x43,
105 .ufcon = 0xf1, 94 .ufcon = 0xf1,
106 .clocks = rx1950_serial_clocks, 95 .clk_sel = S3C2410_UCON_CLKSEL3,
107 .clocks_size = ARRAY_SIZE(rx1950_serial_clocks),
108 }, 96 },
109}; 97};
110 98
diff --git a/arch/arm/mach-s3c2440/mach-rx3715.c b/arch/arm/mach-s3c2440/mach-rx3715.c
index e19499c2f909..3d5e2e67971e 100644
--- a/arch/arm/mach-s3c2440/mach-rx3715.c
+++ b/arch/arm/mach-s3c2440/mach-rx3715.c
@@ -67,16 +67,6 @@ static struct map_desc rx3715_iodesc[] __initdata = {
67 }, 67 },
68}; 68};
69 69
70
71static struct s3c24xx_uart_clksrc rx3715_serial_clocks[] = {
72 [0] = {
73 .name = "fclk",
74 .divisor = 0,
75 .min_baud = 0,
76 .max_baud = 0,
77 }
78};
79
80static struct s3c2410_uartcfg rx3715_uartcfgs[] = { 70static struct s3c2410_uartcfg rx3715_uartcfgs[] = {
81 [0] = { 71 [0] = {
82 .hwport = 0, 72 .hwport = 0,
@@ -84,8 +74,7 @@ static struct s3c2410_uartcfg rx3715_uartcfgs[] = {
84 .ucon = 0x3c5, 74 .ucon = 0x3c5,
85 .ulcon = 0x03, 75 .ulcon = 0x03,
86 .ufcon = 0x51, 76 .ufcon = 0x51,
87 .clocks = rx3715_serial_clocks, 77 .clk_sel = S3C2410_UCON_CLKSEL3,
88 .clocks_size = ARRAY_SIZE(rx3715_serial_clocks),
89 }, 78 },
90 [1] = { 79 [1] = {
91 .hwport = 1, 80 .hwport = 1,
@@ -93,8 +82,7 @@ static struct s3c2410_uartcfg rx3715_uartcfgs[] = {
93 .ucon = 0x3c5, 82 .ucon = 0x3c5,
94 .ulcon = 0x03, 83 .ulcon = 0x03,
95 .ufcon = 0x00, 84 .ufcon = 0x00,
96 .clocks = rx3715_serial_clocks, 85 .clk_sel = S3C2410_UCON_CLKSEL3,
97 .clocks_size = ARRAY_SIZE(rx3715_serial_clocks),
98 }, 86 },
99 /* IR port */ 87 /* IR port */
100 [2] = { 88 [2] = {
@@ -103,8 +91,7 @@ static struct s3c2410_uartcfg rx3715_uartcfgs[] = {
103 .ucon = 0x3c5, 91 .ucon = 0x3c5,
104 .ulcon = 0x43, 92 .ulcon = 0x43,
105 .ufcon = 0x51, 93 .ufcon = 0x51,
106 .clocks = rx3715_serial_clocks, 94 .clk_sel = S3C2410_UCON_CLKSEL3,
107 .clocks_size = ARRAY_SIZE(rx3715_serial_clocks),
108 } 95 }
109}; 96};
110 97
diff --git a/arch/arm/mach-s3c64xx/Kconfig b/arch/arm/mach-s3c64xx/Kconfig
index 5552e048c2be..90b34ab75b53 100644
--- a/arch/arm/mach-s3c64xx/Kconfig
+++ b/arch/arm/mach-s3c64xx/Kconfig
@@ -77,6 +77,11 @@ config S3C64XX_SETUP_SDHCI_GPIO
77 help 77 help
78 Common setup code for S3C64XX SDHCI GPIO configurations 78 Common setup code for S3C64XX SDHCI GPIO configurations
79 79
80config S3C64XX_SETUP_SPI
81 bool
82 help
83 Common setup code for SPI GPIO configurations
84
80# S36400 Macchine support 85# S36400 Macchine support
81 86
82config MACH_SMDK6400 87config MACH_SMDK6400
@@ -276,6 +281,7 @@ config MACH_WLF_CRAGG_6410
276 select S3C64XX_SETUP_IDE 281 select S3C64XX_SETUP_IDE
277 select S3C64XX_SETUP_FB_24BPP 282 select S3C64XX_SETUP_FB_24BPP
278 select S3C64XX_SETUP_KEYPAD 283 select S3C64XX_SETUP_KEYPAD
284 select S3C64XX_SETUP_SPI
279 select SAMSUNG_DEV_ADC 285 select SAMSUNG_DEV_ADC
280 select SAMSUNG_DEV_KEYPAD 286 select SAMSUNG_DEV_KEYPAD
281 select S3C_DEV_USB_HOST 287 select S3C_DEV_USB_HOST
@@ -286,7 +292,7 @@ config MACH_WLF_CRAGG_6410
286 select S3C_DEV_I2C1 292 select S3C_DEV_I2C1
287 select S3C_DEV_WDT 293 select S3C_DEV_WDT
288 select S3C_DEV_RTC 294 select S3C_DEV_RTC
289 select S3C64XX_DEV_SPI 295 select S3C64XX_DEV_SPI0
290 select S3C24XX_GPIO_EXTRA128 296 select S3C24XX_GPIO_EXTRA128
291 select I2C 297 select I2C
292 help 298 help
diff --git a/arch/arm/mach-s3c64xx/Makefile b/arch/arm/mach-s3c64xx/Makefile
index cfc0b9941808..d7d9bb5dfb72 100644
--- a/arch/arm/mach-s3c64xx/Makefile
+++ b/arch/arm/mach-s3c64xx/Makefile
@@ -32,9 +32,9 @@ obj-$(CONFIG_S3C64XX_SETUP_I2C0) += setup-i2c0.o
32obj-$(CONFIG_S3C64XX_SETUP_I2C1) += setup-i2c1.o 32obj-$(CONFIG_S3C64XX_SETUP_I2C1) += setup-i2c1.o
33obj-$(CONFIG_S3C64XX_SETUP_IDE) += setup-ide.o 33obj-$(CONFIG_S3C64XX_SETUP_IDE) += setup-ide.o
34obj-$(CONFIG_S3C64XX_SETUP_KEYPAD) += setup-keypad.o 34obj-$(CONFIG_S3C64XX_SETUP_KEYPAD) += setup-keypad.o
35obj-$(CONFIG_S3C64XX_SETUP_SDHCI) += setup-sdhci.o
36obj-$(CONFIG_S3C64XX_SETUP_FB_24BPP) += setup-fb-24bpp.o 35obj-$(CONFIG_S3C64XX_SETUP_FB_24BPP) += setup-fb-24bpp.o
37obj-$(CONFIG_S3C64XX_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o 36obj-$(CONFIG_S3C64XX_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o
37obj-$(CONFIG_S3C64XX_SETUP_SPI) += setup-spi.o
38 38
39# PM 39# PM
40 40
@@ -60,4 +60,3 @@ obj-$(CONFIG_MACH_WLF_CRAGG_6410) += mach-crag6410.o mach-crag6410-module.o
60 60
61obj-y += dev-uart.o 61obj-y += dev-uart.o
62obj-y += dev-audio.o 62obj-y += dev-audio.o
63obj-$(CONFIG_S3C64XX_DEV_SPI) += dev-spi.o
diff --git a/arch/arm/mach-s3c64xx/clock.c b/arch/arm/mach-s3c64xx/clock.c
index 39c238d7a3dc..0187cde3a5dc 100644
--- a/arch/arm/mach-s3c64xx/clock.c
+++ b/arch/arm/mach-s3c64xx/clock.c
@@ -184,18 +184,6 @@ static struct clk init_clocks_off[] = {
184 .enable = s3c64xx_pclk_ctrl, 184 .enable = s3c64xx_pclk_ctrl,
185 .ctrlbit = S3C_CLKCON_PCLK_SPI1, 185 .ctrlbit = S3C_CLKCON_PCLK_SPI1,
186 }, { 186 }, {
187 .name = "spi_48m",
188 .devname = "s3c64xx-spi.0",
189 .parent = &clk_48m,
190 .enable = s3c64xx_sclk_ctrl,
191 .ctrlbit = S3C_CLKCON_SCLK_SPI0_48,
192 }, {
193 .name = "spi_48m",
194 .devname = "s3c64xx-spi.1",
195 .parent = &clk_48m,
196 .enable = s3c64xx_sclk_ctrl,
197 .ctrlbit = S3C_CLKCON_SCLK_SPI1_48,
198 }, {
199 .name = "48m", 187 .name = "48m",
200 .devname = "s3c-sdhci.0", 188 .devname = "s3c-sdhci.0",
201 .parent = &clk_48m, 189 .parent = &clk_48m,
@@ -226,6 +214,22 @@ static struct clk init_clocks_off[] = {
226 }, 214 },
227}; 215};
228 216
217static struct clk clk_48m_spi0 = {
218 .name = "spi_48m",
219 .devname = "s3c64xx-spi.0",
220 .parent = &clk_48m,
221 .enable = s3c64xx_sclk_ctrl,
222 .ctrlbit = S3C_CLKCON_SCLK_SPI0_48,
223};
224
225static struct clk clk_48m_spi1 = {
226 .name = "spi_48m",
227 .devname = "s3c64xx-spi.1",
228 .parent = &clk_48m,
229 .enable = s3c64xx_sclk_ctrl,
230 .ctrlbit = S3C_CLKCON_SCLK_SPI1_48,
231};
232
229static struct clk init_clocks[] = { 233static struct clk init_clocks[] = {
230 { 234 {
231 .name = "lcd", 235 .name = "lcd",
@@ -243,24 +247,6 @@ static struct clk init_clocks[] = {
243 .enable = s3c64xx_hclk_ctrl, 247 .enable = s3c64xx_hclk_ctrl,
244 .ctrlbit = S3C_CLKCON_HCLK_UHOST, 248 .ctrlbit = S3C_CLKCON_HCLK_UHOST,
245 }, { 249 }, {
246 .name = "hsmmc",
247 .devname = "s3c-sdhci.0",
248 .parent = &clk_h,
249 .enable = s3c64xx_hclk_ctrl,
250 .ctrlbit = S3C_CLKCON_HCLK_HSMMC0,
251 }, {
252 .name = "hsmmc",
253 .devname = "s3c-sdhci.1",
254 .parent = &clk_h,
255 .enable = s3c64xx_hclk_ctrl,
256 .ctrlbit = S3C_CLKCON_HCLK_HSMMC1,
257 }, {
258 .name = "hsmmc",
259 .devname = "s3c-sdhci.2",
260 .parent = &clk_h,
261 .enable = s3c64xx_hclk_ctrl,
262 .ctrlbit = S3C_CLKCON_HCLK_HSMMC2,
263 }, {
264 .name = "otg", 250 .name = "otg",
265 .parent = &clk_h, 251 .parent = &clk_h,
266 .enable = s3c64xx_hclk_ctrl, 252 .enable = s3c64xx_hclk_ctrl,
@@ -310,6 +296,29 @@ static struct clk init_clocks[] = {
310 } 296 }
311}; 297};
312 298
299static struct clk clk_hsmmc0 = {
300 .name = "hsmmc",
301 .devname = "s3c-sdhci.0",
302 .parent = &clk_h,
303 .enable = s3c64xx_hclk_ctrl,
304 .ctrlbit = S3C_CLKCON_HCLK_HSMMC0,
305};
306
307static struct clk clk_hsmmc1 = {
308 .name = "hsmmc",
309 .devname = "s3c-sdhci.1",
310 .parent = &clk_h,
311 .enable = s3c64xx_hclk_ctrl,
312 .ctrlbit = S3C_CLKCON_HCLK_HSMMC1,
313};
314
315static struct clk clk_hsmmc2 = {
316 .name = "hsmmc",
317 .devname = "s3c-sdhci.2",
318 .parent = &clk_h,
319 .enable = s3c64xx_hclk_ctrl,
320 .ctrlbit = S3C_CLKCON_HCLK_HSMMC2,
321};
313 322
314static struct clk clk_fout_apll = { 323static struct clk clk_fout_apll = {
315 .name = "fout_apll", 324 .name = "fout_apll",
@@ -578,36 +587,6 @@ static struct clksrc_sources clkset_camif = {
578static struct clksrc_clk clksrcs[] = { 587static struct clksrc_clk clksrcs[] = {
579 { 588 {
580 .clk = { 589 .clk = {
581 .name = "mmc_bus",
582 .devname = "s3c-sdhci.0",
583 .ctrlbit = S3C_CLKCON_SCLK_MMC0,
584 .enable = s3c64xx_sclk_ctrl,
585 },
586 .reg_src = { .reg = S3C_CLK_SRC, .shift = 18, .size = 2 },
587 .reg_div = { .reg = S3C_CLK_DIV1, .shift = 0, .size = 4 },
588 .sources = &clkset_spi_mmc,
589 }, {
590 .clk = {
591 .name = "mmc_bus",
592 .devname = "s3c-sdhci.1",
593 .ctrlbit = S3C_CLKCON_SCLK_MMC1,
594 .enable = s3c64xx_sclk_ctrl,
595 },
596 .reg_src = { .reg = S3C_CLK_SRC, .shift = 20, .size = 2 },
597 .reg_div = { .reg = S3C_CLK_DIV1, .shift = 4, .size = 4 },
598 .sources = &clkset_spi_mmc,
599 }, {
600 .clk = {
601 .name = "mmc_bus",
602 .devname = "s3c-sdhci.2",
603 .ctrlbit = S3C_CLKCON_SCLK_MMC2,
604 .enable = s3c64xx_sclk_ctrl,
605 },
606 .reg_src = { .reg = S3C_CLK_SRC, .shift = 22, .size = 2 },
607 .reg_div = { .reg = S3C_CLK_DIV1, .shift = 8, .size = 4 },
608 .sources = &clkset_spi_mmc,
609 }, {
610 .clk = {
611 .name = "usb-bus-host", 590 .name = "usb-bus-host",
612 .ctrlbit = S3C_CLKCON_SCLK_UHOST, 591 .ctrlbit = S3C_CLKCON_SCLK_UHOST,
613 .enable = s3c64xx_sclk_ctrl, 592 .enable = s3c64xx_sclk_ctrl,
@@ -617,35 +596,6 @@ static struct clksrc_clk clksrcs[] = {
617 .sources = &clkset_uhost, 596 .sources = &clkset_uhost,
618 }, { 597 }, {
619 .clk = { 598 .clk = {
620 .name = "uclk1",
621 .ctrlbit = S3C_CLKCON_SCLK_UART,
622 .enable = s3c64xx_sclk_ctrl,
623 },
624 .reg_src = { .reg = S3C_CLK_SRC, .shift = 13, .size = 1 },
625 .reg_div = { .reg = S3C_CLK_DIV2, .shift = 16, .size = 4 },
626 .sources = &clkset_uart,
627 }, {
628/* Where does UCLK0 come from? */
629 .clk = {
630 .name = "spi-bus",
631 .devname = "s3c64xx-spi.0",
632 .ctrlbit = S3C_CLKCON_SCLK_SPI0,
633 .enable = s3c64xx_sclk_ctrl,
634 },
635 .reg_src = { .reg = S3C_CLK_SRC, .shift = 14, .size = 2 },
636 .reg_div = { .reg = S3C_CLK_DIV2, .shift = 0, .size = 4 },
637 .sources = &clkset_spi_mmc,
638 }, {
639 .clk = {
640 .name = "spi-bus",
641 .devname = "s3c64xx-spi.1",
642 .enable = s3c64xx_sclk_ctrl,
643 },
644 .reg_src = { .reg = S3C_CLK_SRC, .shift = 16, .size = 2 },
645 .reg_div = { .reg = S3C_CLK_DIV2, .shift = 4, .size = 4 },
646 .sources = &clkset_spi_mmc,
647 }, {
648 .clk = {
649 .name = "audio-bus", 599 .name = "audio-bus",
650 .devname = "samsung-i2s.0", 600 .devname = "samsung-i2s.0",
651 .ctrlbit = S3C_CLKCON_SCLK_AUDIO0, 601 .ctrlbit = S3C_CLKCON_SCLK_AUDIO0,
@@ -695,6 +645,78 @@ static struct clksrc_clk clksrcs[] = {
695 }, 645 },
696}; 646};
697 647
648/* Where does UCLK0 come from? */
649static struct clksrc_clk clk_sclk_uclk = {
650 .clk = {
651 .name = "uclk1",
652 .ctrlbit = S3C_CLKCON_SCLK_UART,
653 .enable = s3c64xx_sclk_ctrl,
654 },
655 .reg_src = { .reg = S3C_CLK_SRC, .shift = 13, .size = 1 },
656 .reg_div = { .reg = S3C_CLK_DIV2, .shift = 16, .size = 4 },
657 .sources = &clkset_uart,
658};
659
660static struct clksrc_clk clk_sclk_mmc0 = {
661 .clk = {
662 .name = "mmc_bus",
663 .devname = "s3c-sdhci.0",
664 .ctrlbit = S3C_CLKCON_SCLK_MMC0,
665 .enable = s3c64xx_sclk_ctrl,
666 },
667 .reg_src = { .reg = S3C_CLK_SRC, .shift = 18, .size = 2 },
668 .reg_div = { .reg = S3C_CLK_DIV1, .shift = 0, .size = 4 },
669 .sources = &clkset_spi_mmc,
670};
671
672static struct clksrc_clk clk_sclk_mmc1 = {
673 .clk = {
674 .name = "mmc_bus",
675 .devname = "s3c-sdhci.1",
676 .ctrlbit = S3C_CLKCON_SCLK_MMC1,
677 .enable = s3c64xx_sclk_ctrl,
678 },
679 .reg_src = { .reg = S3C_CLK_SRC, .shift = 20, .size = 2 },
680 .reg_div = { .reg = S3C_CLK_DIV1, .shift = 4, .size = 4 },
681 .sources = &clkset_spi_mmc,
682};
683
684static struct clksrc_clk clk_sclk_mmc2 = {
685 .clk = {
686 .name = "mmc_bus",
687 .devname = "s3c-sdhci.2",
688 .ctrlbit = S3C_CLKCON_SCLK_MMC2,
689 .enable = s3c64xx_sclk_ctrl,
690 },
691 .reg_src = { .reg = S3C_CLK_SRC, .shift = 22, .size = 2 },
692 .reg_div = { .reg = S3C_CLK_DIV1, .shift = 8, .size = 4 },
693 .sources = &clkset_spi_mmc,
694};
695
696static struct clksrc_clk clk_sclk_spi0 = {
697 .clk = {
698 .name = "spi-bus",
699 .devname = "s3c64xx-spi.0",
700 .ctrlbit = S3C_CLKCON_SCLK_SPI0,
701 .enable = s3c64xx_sclk_ctrl,
702 },
703 .reg_src = { .reg = S3C_CLK_SRC, .shift = 14, .size = 2 },
704 .reg_div = { .reg = S3C_CLK_DIV2, .shift = 0, .size = 4 },
705 .sources = &clkset_spi_mmc,
706};
707
708static struct clksrc_clk clk_sclk_spi1 = {
709 .clk = {
710 .name = "spi-bus",
711 .devname = "s3c64xx-spi.1",
712 .ctrlbit = S3C_CLKCON_SCLK_SPI1,
713 .enable = s3c64xx_sclk_ctrl,
714 },
715 .reg_src = { .reg = S3C_CLK_SRC, .shift = 16, .size = 2 },
716 .reg_div = { .reg = S3C_CLK_DIV2, .shift = 4, .size = 4 },
717 .sources = &clkset_spi_mmc,
718};
719
698/* Clock initialisation code */ 720/* Clock initialisation code */
699 721
700static struct clksrc_clk *init_parents[] = { 722static struct clksrc_clk *init_parents[] = {
@@ -703,6 +725,39 @@ static struct clksrc_clk *init_parents[] = {
703 &clk_mout_mpll, 725 &clk_mout_mpll,
704}; 726};
705 727
728static struct clksrc_clk *clksrc_cdev[] = {
729 &clk_sclk_uclk,
730 &clk_sclk_mmc0,
731 &clk_sclk_mmc1,
732 &clk_sclk_mmc2,
733 &clk_sclk_spi0,
734 &clk_sclk_spi1,
735};
736
737static struct clk *clk_cdev[] = {
738 &clk_hsmmc0,
739 &clk_hsmmc1,
740 &clk_hsmmc2,
741 &clk_48m_spi0,
742 &clk_48m_spi1,
743};
744
745static struct clk_lookup s3c64xx_clk_lookup[] = {
746 CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p),
747 CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uclk.clk),
748 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &clk_hsmmc0),
749 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &clk_hsmmc1),
750 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.0", &clk_hsmmc2),
751 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
752 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
753 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
754 CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
755 CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
756 CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk2", &clk_48m_spi0),
757 CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
758 CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk2", &clk_48m_spi1),
759};
760
706#define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1) 761#define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1)
707 762
708void __init_or_cpufreq s3c6400_setup_clocks(void) 763void __init_or_cpufreq s3c6400_setup_clocks(void)
@@ -811,6 +866,8 @@ static struct clk *clks[] __initdata = {
811void __init s3c64xx_register_clocks(unsigned long xtal, 866void __init s3c64xx_register_clocks(unsigned long xtal,
812 unsigned armclk_divlimit) 867 unsigned armclk_divlimit)
813{ 868{
869 unsigned int cnt;
870
814 armclk_mask = armclk_divlimit; 871 armclk_mask = armclk_divlimit;
815 872
816 s3c24xx_register_baseclocks(xtal); 873 s3c24xx_register_baseclocks(xtal);
@@ -821,7 +878,15 @@ void __init s3c64xx_register_clocks(unsigned long xtal,
821 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); 878 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
822 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); 879 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
823 880
881 s3c24xx_register_clocks(clk_cdev, ARRAY_SIZE(clk_cdev));
882 for (cnt = 0; cnt < ARRAY_SIZE(clk_cdev); cnt++)
883 s3c_disable_clocks(clk_cdev[cnt], 1);
884
824 s3c24xx_register_clocks(clks1, ARRAY_SIZE(clks1)); 885 s3c24xx_register_clocks(clks1, ARRAY_SIZE(clks1));
825 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs)); 886 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
887 for (cnt = 0; cnt < ARRAY_SIZE(clksrc_cdev); cnt++)
888 s3c_register_clksrc(clksrc_cdev[cnt], 1);
889 clkdev_add_table(s3c64xx_clk_lookup, ARRAY_SIZE(s3c64xx_clk_lookup));
890
826 s3c_pwmclk_init(); 891 s3c_pwmclk_init();
827} 892}
diff --git a/arch/arm/mach-s3c64xx/dev-spi.c b/arch/arm/mach-s3c64xx/dev-spi.c
deleted file mode 100644
index 3341fd118723..000000000000
--- a/arch/arm/mach-s3c64xx/dev-spi.c
+++ /dev/null
@@ -1,180 +0,0 @@
1/* linux/arch/arm/plat-s3c64xx/dev-spi.c
2 *
3 * Copyright (C) 2009 Samsung Electronics Ltd.
4 * Jaswinder Singh <jassi.brar@samsung.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/kernel.h>
12#include <linux/string.h>
13#include <linux/export.h>
14#include <linux/platform_device.h>
15#include <linux/dma-mapping.h>
16#include <linux/gpio.h>
17
18#include <mach/dma.h>
19#include <mach/map.h>
20#include <mach/spi-clocks.h>
21#include <mach/irqs.h>
22
23#include <plat/s3c64xx-spi.h>
24#include <plat/gpio-cfg.h>
25#include <plat/devs.h>
26
27static char *spi_src_clks[] = {
28 [S3C64XX_SPI_SRCCLK_PCLK] = "pclk",
29 [S3C64XX_SPI_SRCCLK_SPIBUS] = "spi-bus",
30 [S3C64XX_SPI_SRCCLK_48M] = "spi_48m",
31};
32
33/* SPI Controller platform_devices */
34
35/* Since we emulate multi-cs capability, we do not touch the GPC-3,7.
36 * The emulated CS is toggled by board specific mechanism, as it can
37 * be either some immediate GPIO or some signal out of some other
38 * chip in between ... or some yet another way.
39 * We simply do not assume anything about CS.
40 */
41static int s3c64xx_spi_cfg_gpio(struct platform_device *pdev)
42{
43 unsigned int base;
44
45 switch (pdev->id) {
46 case 0:
47 base = S3C64XX_GPC(0);
48 break;
49
50 case 1:
51 base = S3C64XX_GPC(4);
52 break;
53
54 default:
55 dev_err(&pdev->dev, "Invalid SPI Controller number!");
56 return -EINVAL;
57 }
58
59 s3c_gpio_cfgall_range(base, 3,
60 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
61
62 return 0;
63}
64
65static struct resource s3c64xx_spi0_resource[] = {
66 [0] = {
67 .start = S3C64XX_PA_SPI0,
68 .end = S3C64XX_PA_SPI0 + 0x100 - 1,
69 .flags = IORESOURCE_MEM,
70 },
71 [1] = {
72 .start = DMACH_SPI0_TX,
73 .end = DMACH_SPI0_TX,
74 .flags = IORESOURCE_DMA,
75 },
76 [2] = {
77 .start = DMACH_SPI0_RX,
78 .end = DMACH_SPI0_RX,
79 .flags = IORESOURCE_DMA,
80 },
81 [3] = {
82 .start = IRQ_SPI0,
83 .end = IRQ_SPI0,
84 .flags = IORESOURCE_IRQ,
85 },
86};
87
88static struct s3c64xx_spi_info s3c64xx_spi0_pdata = {
89 .cfg_gpio = s3c64xx_spi_cfg_gpio,
90 .fifo_lvl_mask = 0x7f,
91 .rx_lvl_offset = 13,
92 .tx_st_done = 21,
93};
94
95static u64 spi_dmamask = DMA_BIT_MASK(32);
96
97struct platform_device s3c64xx_device_spi0 = {
98 .name = "s3c64xx-spi",
99 .id = 0,
100 .num_resources = ARRAY_SIZE(s3c64xx_spi0_resource),
101 .resource = s3c64xx_spi0_resource,
102 .dev = {
103 .dma_mask = &spi_dmamask,
104 .coherent_dma_mask = DMA_BIT_MASK(32),
105 .platform_data = &s3c64xx_spi0_pdata,
106 },
107};
108EXPORT_SYMBOL(s3c64xx_device_spi0);
109
110static struct resource s3c64xx_spi1_resource[] = {
111 [0] = {
112 .start = S3C64XX_PA_SPI1,
113 .end = S3C64XX_PA_SPI1 + 0x100 - 1,
114 .flags = IORESOURCE_MEM,
115 },
116 [1] = {
117 .start = DMACH_SPI1_TX,
118 .end = DMACH_SPI1_TX,
119 .flags = IORESOURCE_DMA,
120 },
121 [2] = {
122 .start = DMACH_SPI1_RX,
123 .end = DMACH_SPI1_RX,
124 .flags = IORESOURCE_DMA,
125 },
126 [3] = {
127 .start = IRQ_SPI1,
128 .end = IRQ_SPI1,
129 .flags = IORESOURCE_IRQ,
130 },
131};
132
133static struct s3c64xx_spi_info s3c64xx_spi1_pdata = {
134 .cfg_gpio = s3c64xx_spi_cfg_gpio,
135 .fifo_lvl_mask = 0x7f,
136 .rx_lvl_offset = 13,
137 .tx_st_done = 21,
138};
139
140struct platform_device s3c64xx_device_spi1 = {
141 .name = "s3c64xx-spi",
142 .id = 1,
143 .num_resources = ARRAY_SIZE(s3c64xx_spi1_resource),
144 .resource = s3c64xx_spi1_resource,
145 .dev = {
146 .dma_mask = &spi_dmamask,
147 .coherent_dma_mask = DMA_BIT_MASK(32),
148 .platform_data = &s3c64xx_spi1_pdata,
149 },
150};
151EXPORT_SYMBOL(s3c64xx_device_spi1);
152
153void __init s3c64xx_spi_set_info(int cntrlr, int src_clk_nr, int num_cs)
154{
155 struct s3c64xx_spi_info *pd;
156
157 /* Reject invalid configuration */
158 if (!num_cs || src_clk_nr < 0
159 || src_clk_nr > S3C64XX_SPI_SRCCLK_48M) {
160 printk(KERN_ERR "%s: Invalid SPI configuration\n", __func__);
161 return;
162 }
163
164 switch (cntrlr) {
165 case 0:
166 pd = &s3c64xx_spi0_pdata;
167 break;
168 case 1:
169 pd = &s3c64xx_spi1_pdata;
170 break;
171 default:
172 printk(KERN_ERR "%s: Invalid SPI controller(%d)\n",
173 __func__, cntrlr);
174 return;
175 }
176
177 pd->num_cs = num_cs;
178 pd->src_clk_nr = src_clk_nr;
179 pd->src_clk_name = spi_src_clks[src_clk_nr];
180}
diff --git a/arch/arm/mach-s3c64xx/include/mach/map.h b/arch/arm/mach-s3c64xx/include/mach/map.h
index 23a1d71e4d53..8e2097bb208a 100644
--- a/arch/arm/mach-s3c64xx/include/mach/map.h
+++ b/arch/arm/mach-s3c64xx/include/mach/map.h
@@ -115,6 +115,8 @@
115#define S3C_PA_USB_HSOTG S3C64XX_PA_USB_HSOTG 115#define S3C_PA_USB_HSOTG S3C64XX_PA_USB_HSOTG
116#define S3C_PA_RTC S3C64XX_PA_RTC 116#define S3C_PA_RTC S3C64XX_PA_RTC
117#define S3C_PA_WDT S3C64XX_PA_WATCHDOG 117#define S3C_PA_WDT S3C64XX_PA_WATCHDOG
118#define S3C_PA_SPI0 S3C64XX_PA_SPI0
119#define S3C_PA_SPI1 S3C64XX_PA_SPI1
118 120
119#define SAMSUNG_PA_ADC S3C64XX_PA_ADC 121#define SAMSUNG_PA_ADC S3C64XX_PA_ADC
120#define SAMSUNG_PA_CFCON S3C64XX_PA_CFCON 122#define SAMSUNG_PA_CFCON S3C64XX_PA_CFCON
diff --git a/arch/arm/mach-s3c64xx/setup-sdhci.c b/arch/arm/mach-s3c64xx/setup-sdhci.c
deleted file mode 100644
index c75a71b21165..000000000000
--- a/arch/arm/mach-s3c64xx/setup-sdhci.c
+++ /dev/null
@@ -1,24 +0,0 @@
1/* linux/arch/arm/mach-s3c64xx/setup-sdhci.c
2 *
3 * Copyright 2008 Simtec Electronics
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * S3C6400/S3C6410 - Helper functions for settign up SDHCI device(s) (HSMMC)
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#include <linux/types.h>
16
17/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */
18
19char *s3c64xx_hsmmc_clksrcs[4] = {
20 [0] = "hsmmc",
21 [1] = "hsmmc",
22 [2] = "mmc_bus",
23 /* [3] = "48m", - note not successfully used yet */
24};
diff --git a/arch/arm/mach-s3c64xx/setup-spi.c b/arch/arm/mach-s3c64xx/setup-spi.c
new file mode 100644
index 000000000000..d9592ad7a825
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/setup-spi.c
@@ -0,0 +1,45 @@
1/* linux/arch/arm/mach-s3c64xx/setup-spi.c
2 *
3 * Copyright (C) 2011 Samsung Electronics Ltd.
4 * http://www.samsung.com/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/gpio.h>
12#include <linux/platform_device.h>
13
14#include <plat/gpio-cfg.h>
15#include <plat/s3c64xx-spi.h>
16
17#ifdef CONFIG_S3C64XX_DEV_SPI0
18struct s3c64xx_spi_info s3c64xx_spi0_pdata __initdata = {
19 .fifo_lvl_mask = 0x7f,
20 .rx_lvl_offset = 13,
21 .tx_st_done = 21,
22};
23
24int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
25{
26 s3c_gpio_cfgall_range(S3C64XX_GPC(0), 3,
27 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
28 return 0;
29}
30#endif
31
32#ifdef CONFIG_S3C64XX_DEV_SPI1
33struct s3c64xx_spi_info s3c64xx_spi1_pdata __initdata = {
34 .fifo_lvl_mask = 0x7f,
35 .rx_lvl_offset = 13,
36 .tx_st_done = 21,
37};
38
39int s3c64xx_spi1_cfg_gpio(struct platform_device *dev)
40{
41 s3c_gpio_cfgall_range(S3C64XX_GPC(4), 3,
42 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
43 return 0;
44}
45#endif
diff --git a/arch/arm/mach-s5p64x0/Kconfig b/arch/arm/mach-s5p64x0/Kconfig
index 18690c5f99e6..dd8c85ef6dab 100644
--- a/arch/arm/mach-s5p64x0/Kconfig
+++ b/arch/arm/mach-s5p64x0/Kconfig
@@ -36,6 +36,11 @@ config S5P64X0_SETUP_I2C1
36 help 36 help
37 Common setup code for i2c bus 1. 37 Common setup code for i2c bus 1.
38 38
39config S5P64X0_SETUP_SPI
40 bool
41 help
42 Common setup code for SPI GPIO configurations
43
39# machine support 44# machine support
40 45
41config MACH_SMDK6440 46config MACH_SMDK6440
@@ -45,7 +50,6 @@ config MACH_SMDK6440
45 select S3C_DEV_I2C1 50 select S3C_DEV_I2C1
46 select S3C_DEV_RTC 51 select S3C_DEV_RTC
47 select S3C_DEV_WDT 52 select S3C_DEV_WDT
48 select S3C64XX_DEV_SPI
49 select SAMSUNG_DEV_ADC 53 select SAMSUNG_DEV_ADC
50 select SAMSUNG_DEV_BACKLIGHT 54 select SAMSUNG_DEV_BACKLIGHT
51 select SAMSUNG_DEV_PWM 55 select SAMSUNG_DEV_PWM
@@ -62,7 +66,6 @@ config MACH_SMDK6450
62 select S3C_DEV_I2C1 66 select S3C_DEV_I2C1
63 select S3C_DEV_RTC 67 select S3C_DEV_RTC
64 select S3C_DEV_WDT 68 select S3C_DEV_WDT
65 select S3C64XX_DEV_SPI
66 select SAMSUNG_DEV_ADC 69 select SAMSUNG_DEV_ADC
67 select SAMSUNG_DEV_BACKLIGHT 70 select SAMSUNG_DEV_BACKLIGHT
68 select SAMSUNG_DEV_PWM 71 select SAMSUNG_DEV_PWM
diff --git a/arch/arm/mach-s5p64x0/Makefile b/arch/arm/mach-s5p64x0/Makefile
index a1324d8dc4e0..a7d7a499d99e 100644
--- a/arch/arm/mach-s5p64x0/Makefile
+++ b/arch/arm/mach-s5p64x0/Makefile
@@ -26,7 +26,7 @@ obj-$(CONFIG_MACH_SMDK6450) += mach-smdk6450.o
26# device support 26# device support
27 27
28obj-y += dev-audio.o 28obj-y += dev-audio.o
29obj-$(CONFIG_S3C64XX_DEV_SPI) += dev-spi.o
30 29
31obj-$(CONFIG_S5P64X0_SETUP_I2C1) += setup-i2c1.o 30obj-$(CONFIG_S5P64X0_SETUP_I2C1) += setup-i2c1.o
32obj-$(CONFIG_S5P64X0_SETUP_FB_24BPP) += setup-fb-24bpp.o 31obj-$(CONFIG_S5P64X0_SETUP_FB_24BPP) += setup-fb-24bpp.o
32obj-$(CONFIG_S5P64X0_SETUP_SPI) += setup-spi.o
diff --git a/arch/arm/mach-s5p64x0/clock-s5p6440.c b/arch/arm/mach-s5p64x0/clock-s5p6440.c
index c54c65d511f0..73c7cc9ef0dd 100644
--- a/arch/arm/mach-s5p64x0/clock-s5p6440.c
+++ b/arch/arm/mach-s5p64x0/clock-s5p6440.c
@@ -268,18 +268,6 @@ static struct clk init_clocks_off[] = {
268 .enable = s5p64x0_pclk_ctrl, 268 .enable = s5p64x0_pclk_ctrl,
269 .ctrlbit = (1 << 31), 269 .ctrlbit = (1 << 31),
270 }, { 270 }, {
271 .name = "sclk_spi_48",
272 .devname = "s3c64xx-spi.0",
273 .parent = &clk_48m,
274 .enable = s5p64x0_sclk_ctrl,
275 .ctrlbit = (1 << 22),
276 }, {
277 .name = "sclk_spi_48",
278 .devname = "s3c64xx-spi.1",
279 .parent = &clk_48m,
280 .enable = s5p64x0_sclk_ctrl,
281 .ctrlbit = (1 << 23),
282 }, {
283 .name = "mmc_48m", 271 .name = "mmc_48m",
284 .devname = "s3c-sdhci.0", 272 .devname = "s3c-sdhci.0",
285 .parent = &clk_48m, 273 .parent = &clk_48m,
@@ -421,35 +409,6 @@ static struct clksrc_clk clksrcs[] = {
421 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 }, 409 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 },
422 }, { 410 }, {
423 .clk = { 411 .clk = {
424 .name = "uclk1",
425 .ctrlbit = (1 << 5),
426 .enable = s5p64x0_sclk_ctrl,
427 },
428 .sources = &clkset_uart,
429 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 13, .size = 1 },
430 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 16, .size = 4 },
431 }, {
432 .clk = {
433 .name = "sclk_spi",
434 .devname = "s3c64xx-spi.0",
435 .ctrlbit = (1 << 20),
436 .enable = s5p64x0_sclk_ctrl,
437 },
438 .sources = &clkset_group1,
439 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 14, .size = 2 },
440 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 0, .size = 4 },
441 }, {
442 .clk = {
443 .name = "sclk_spi",
444 .devname = "s3c64xx-spi.1",
445 .ctrlbit = (1 << 21),
446 .enable = s5p64x0_sclk_ctrl,
447 },
448 .sources = &clkset_group1,
449 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 16, .size = 2 },
450 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 4, .size = 4 },
451 }, {
452 .clk = {
453 .name = "sclk_post", 412 .name = "sclk_post",
454 .ctrlbit = (1 << 10), 413 .ctrlbit = (1 << 10),
455 .enable = s5p64x0_sclk_ctrl, 414 .enable = s5p64x0_sclk_ctrl,
@@ -487,6 +446,41 @@ static struct clksrc_clk clksrcs[] = {
487 }, 446 },
488}; 447};
489 448
449static struct clksrc_clk clk_sclk_uclk = {
450 .clk = {
451 .name = "uclk1",
452 .ctrlbit = (1 << 5),
453 .enable = s5p64x0_sclk_ctrl,
454 },
455 .sources = &clkset_uart,
456 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 13, .size = 1 },
457 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 16, .size = 4 },
458};
459
460static struct clksrc_clk clk_sclk_spi0 = {
461 .clk = {
462 .name = "sclk_spi",
463 .devname = "s3c64xx-spi.0",
464 .ctrlbit = (1 << 20),
465 .enable = s5p64x0_sclk_ctrl,
466 },
467 .sources = &clkset_group1,
468 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 14, .size = 2 },
469 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 0, .size = 4 },
470};
471
472static struct clksrc_clk clk_sclk_spi1 = {
473 .clk = {
474 .name = "sclk_spi",
475 .devname = "s3c64xx-spi.1",
476 .ctrlbit = (1 << 21),
477 .enable = s5p64x0_sclk_ctrl,
478 },
479 .sources = &clkset_group1,
480 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 16, .size = 2 },
481 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 4, .size = 4 },
482};
483
490/* Clock initialization code */ 484/* Clock initialization code */
491static struct clksrc_clk *sysclks[] = { 485static struct clksrc_clk *sysclks[] = {
492 &clk_mout_apll, 486 &clk_mout_apll,
@@ -505,6 +499,20 @@ static struct clk dummy_apb_pclk = {
505 .id = -1, 499 .id = -1,
506}; 500};
507 501
502static struct clksrc_clk *clksrc_cdev[] = {
503 &clk_sclk_uclk,
504 &clk_sclk_spi0,
505 &clk_sclk_spi1,
506};
507
508static struct clk_lookup s5p6440_clk_lookup[] = {
509 CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_pclk_low.clk),
510 CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uclk.clk),
511 CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
512 CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
513 CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
514};
515
508void __init_or_cpufreq s5p6440_setup_clocks(void) 516void __init_or_cpufreq s5p6440_setup_clocks(void)
509{ 517{
510 struct clk *xtal_clk; 518 struct clk *xtal_clk;
@@ -583,9 +591,12 @@ void __init s5p6440_register_clocks(void)
583 591
584 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs)); 592 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
585 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks)); 593 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
594 for (ptr = 0; ptr < ARRAY_SIZE(clksrc_cdev); ptr++)
595 s3c_register_clksrc(clksrc_cdev[ptr], 1);
586 596
587 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); 597 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
588 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); 598 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
599 clkdev_add_table(s5p6440_clk_lookup, ARRAY_SIZE(s5p6440_clk_lookup));
589 600
590 s3c24xx_register_clock(&dummy_apb_pclk); 601 s3c24xx_register_clock(&dummy_apb_pclk);
591 602
diff --git a/arch/arm/mach-s5p64x0/clock-s5p6450.c b/arch/arm/mach-s5p64x0/clock-s5p6450.c
index 2d04abfba12e..50f90cbf7798 100644
--- a/arch/arm/mach-s5p64x0/clock-s5p6450.c
+++ b/arch/arm/mach-s5p64x0/clock-s5p6450.c
@@ -443,35 +443,6 @@ static struct clksrc_clk clksrcs[] = {
443 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 }, 443 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 },
444 }, { 444 }, {
445 .clk = { 445 .clk = {
446 .name = "uclk1",
447 .ctrlbit = (1 << 5),
448 .enable = s5p64x0_sclk_ctrl,
449 },
450 .sources = &clkset_uart,
451 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 13, .size = 1 },
452 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 16, .size = 4 },
453 }, {
454 .clk = {
455 .name = "sclk_spi",
456 .devname = "s3c64xx-spi.0",
457 .ctrlbit = (1 << 20),
458 .enable = s5p64x0_sclk_ctrl,
459 },
460 .sources = &clkset_group2,
461 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 14, .size = 2 },
462 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 0, .size = 4 },
463 }, {
464 .clk = {
465 .name = "sclk_spi",
466 .devname = "s3c64xx-spi.1",
467 .ctrlbit = (1 << 21),
468 .enable = s5p64x0_sclk_ctrl,
469 },
470 .sources = &clkset_group2,
471 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 16, .size = 2 },
472 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 4, .size = 4 },
473 }, {
474 .clk = {
475 .name = "sclk_fimc", 446 .name = "sclk_fimc",
476 .ctrlbit = (1 << 10), 447 .ctrlbit = (1 << 10),
477 .enable = s5p64x0_sclk_ctrl, 448 .enable = s5p64x0_sclk_ctrl,
@@ -536,6 +507,55 @@ static struct clksrc_clk clksrcs[] = {
536 }, 507 },
537}; 508};
538 509
510static struct clksrc_clk clk_sclk_uclk = {
511 .clk = {
512 .name = "uclk1",
513 .ctrlbit = (1 << 5),
514 .enable = s5p64x0_sclk_ctrl,
515 },
516 .sources = &clkset_uart,
517 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 13, .size = 1 },
518 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 16, .size = 4 },
519};
520
521static struct clksrc_clk clk_sclk_spi0 = {
522 .clk = {
523 .name = "sclk_spi",
524 .devname = "s3c64xx-spi.0",
525 .ctrlbit = (1 << 20),
526 .enable = s5p64x0_sclk_ctrl,
527 },
528 .sources = &clkset_group2,
529 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 14, .size = 2 },
530 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 0, .size = 4 },
531};
532
533static struct clksrc_clk clk_sclk_spi1 = {
534 .clk = {
535 .name = "sclk_spi",
536 .devname = "s3c64xx-spi.1",
537 .ctrlbit = (1 << 21),
538 .enable = s5p64x0_sclk_ctrl,
539 },
540 .sources = &clkset_group2,
541 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 16, .size = 2 },
542 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 4, .size = 4 },
543};
544
545static struct clksrc_clk *clksrc_cdev[] = {
546 &clk_sclk_uclk,
547 &clk_sclk_spi0,
548 &clk_sclk_spi1,
549};
550
551static struct clk_lookup s5p6450_clk_lookup[] = {
552 CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_pclk_low.clk),
553 CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uclk.clk),
554 CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
555 CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
556 CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
557};
558
539/* Clock initialization code */ 559/* Clock initialization code */
540static struct clksrc_clk *sysclks[] = { 560static struct clksrc_clk *sysclks[] = {
541 &clk_mout_apll, 561 &clk_mout_apll,
@@ -634,9 +654,12 @@ void __init s5p6450_register_clocks(void)
634 654
635 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs)); 655 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
636 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks)); 656 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
657 for (ptr = 0; ptr < ARRAY_SIZE(clksrc_cdev); ptr++)
658 s3c_register_clksrc(clksrc_cdev[ptr], 1);
637 659
638 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); 660 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
639 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); 661 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
662 clkdev_add_table(s5p6450_clk_lookup, ARRAY_SIZE(s5p6450_clk_lookup));
640 663
641 s3c24xx_register_clock(&dummy_apb_pclk); 664 s3c24xx_register_clock(&dummy_apb_pclk);
642 665
diff --git a/arch/arm/mach-s5p64x0/dev-spi.c b/arch/arm/mach-s5p64x0/dev-spi.c
deleted file mode 100644
index 1fd9c79c7dbc..000000000000
--- a/arch/arm/mach-s5p64x0/dev-spi.c
+++ /dev/null
@@ -1,224 +0,0 @@
1/* linux/arch/arm/mach-s5p64x0/dev-spi.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * Copyright (C) 2010 Samsung Electronics Co. Ltd.
7 * Jaswinder Singh <jassi.brar@samsung.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14#include <linux/platform_device.h>
15#include <linux/dma-mapping.h>
16#include <linux/gpio.h>
17
18#include <mach/dma.h>
19#include <mach/map.h>
20#include <mach/irqs.h>
21#include <mach/regs-clock.h>
22#include <mach/spi-clocks.h>
23
24#include <plat/cpu.h>
25#include <plat/s3c64xx-spi.h>
26#include <plat/gpio-cfg.h>
27
28static char *s5p64x0_spi_src_clks[] = {
29 [S5P64X0_SPI_SRCCLK_PCLK] = "pclk",
30 [S5P64X0_SPI_SRCCLK_SCLK] = "sclk_spi",
31};
32
33/* SPI Controller platform_devices */
34
35/* Since we emulate multi-cs capability, we do not touch the CS.
36 * The emulated CS is toggled by board specific mechanism, as it can
37 * be either some immediate GPIO or some signal out of some other
38 * chip in between ... or some yet another way.
39 * We simply do not assume anything about CS.
40 */
41static int s5p6440_spi_cfg_gpio(struct platform_device *pdev)
42{
43 unsigned int base;
44
45 switch (pdev->id) {
46 case 0:
47 base = S5P6440_GPC(0);
48 break;
49
50 case 1:
51 base = S5P6440_GPC(4);
52 break;
53
54 default:
55 dev_err(&pdev->dev, "Invalid SPI Controller number!");
56 return -EINVAL;
57 }
58
59 s3c_gpio_cfgall_range(base, 3,
60 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
61
62 return 0;
63}
64
65static int s5p6450_spi_cfg_gpio(struct platform_device *pdev)
66{
67 unsigned int base;
68
69 switch (pdev->id) {
70 case 0:
71 base = S5P6450_GPC(0);
72 break;
73
74 case 1:
75 base = S5P6450_GPC(4);
76 break;
77
78 default:
79 dev_err(&pdev->dev, "Invalid SPI Controller number!");
80 return -EINVAL;
81 }
82
83 s3c_gpio_cfgall_range(base, 3,
84 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
85
86 return 0;
87}
88
89static struct resource s5p64x0_spi0_resource[] = {
90 [0] = {
91 .start = S5P64X0_PA_SPI0,
92 .end = S5P64X0_PA_SPI0 + 0x100 - 1,
93 .flags = IORESOURCE_MEM,
94 },
95 [1] = {
96 .start = DMACH_SPI0_TX,
97 .end = DMACH_SPI0_TX,
98 .flags = IORESOURCE_DMA,
99 },
100 [2] = {
101 .start = DMACH_SPI0_RX,
102 .end = DMACH_SPI0_RX,
103 .flags = IORESOURCE_DMA,
104 },
105 [3] = {
106 .start = IRQ_SPI0,
107 .end = IRQ_SPI0,
108 .flags = IORESOURCE_IRQ,
109 },
110};
111
112static struct s3c64xx_spi_info s5p6440_spi0_pdata = {
113 .cfg_gpio = s5p6440_spi_cfg_gpio,
114 .fifo_lvl_mask = 0x1ff,
115 .rx_lvl_offset = 15,
116 .tx_st_done = 25,
117};
118
119static struct s3c64xx_spi_info s5p6450_spi0_pdata = {
120 .cfg_gpio = s5p6450_spi_cfg_gpio,
121 .fifo_lvl_mask = 0x1ff,
122 .rx_lvl_offset = 15,
123 .tx_st_done = 25,
124};
125
126static u64 spi_dmamask = DMA_BIT_MASK(32);
127
128struct platform_device s5p64x0_device_spi0 = {
129 .name = "s3c64xx-spi",
130 .id = 0,
131 .num_resources = ARRAY_SIZE(s5p64x0_spi0_resource),
132 .resource = s5p64x0_spi0_resource,
133 .dev = {
134 .dma_mask = &spi_dmamask,
135 .coherent_dma_mask = DMA_BIT_MASK(32),
136 },
137};
138
139static struct resource s5p64x0_spi1_resource[] = {
140 [0] = {
141 .start = S5P64X0_PA_SPI1,
142 .end = S5P64X0_PA_SPI1 + 0x100 - 1,
143 .flags = IORESOURCE_MEM,
144 },
145 [1] = {
146 .start = DMACH_SPI1_TX,
147 .end = DMACH_SPI1_TX,
148 .flags = IORESOURCE_DMA,
149 },
150 [2] = {
151 .start = DMACH_SPI1_RX,
152 .end = DMACH_SPI1_RX,
153 .flags = IORESOURCE_DMA,
154 },
155 [3] = {
156 .start = IRQ_SPI1,
157 .end = IRQ_SPI1,
158 .flags = IORESOURCE_IRQ,
159 },
160};
161
162static struct s3c64xx_spi_info s5p6440_spi1_pdata = {
163 .cfg_gpio = s5p6440_spi_cfg_gpio,
164 .fifo_lvl_mask = 0x7f,
165 .rx_lvl_offset = 15,
166 .tx_st_done = 25,
167};
168
169static struct s3c64xx_spi_info s5p6450_spi1_pdata = {
170 .cfg_gpio = s5p6450_spi_cfg_gpio,
171 .fifo_lvl_mask = 0x7f,
172 .rx_lvl_offset = 15,
173 .tx_st_done = 25,
174};
175
176struct platform_device s5p64x0_device_spi1 = {
177 .name = "s3c64xx-spi",
178 .id = 1,
179 .num_resources = ARRAY_SIZE(s5p64x0_spi1_resource),
180 .resource = s5p64x0_spi1_resource,
181 .dev = {
182 .dma_mask = &spi_dmamask,
183 .coherent_dma_mask = DMA_BIT_MASK(32),
184 },
185};
186
187void __init s5p64x0_spi_set_info(int cntrlr, int src_clk_nr, int num_cs)
188{
189 struct s3c64xx_spi_info *pd;
190
191 /* Reject invalid configuration */
192 if (!num_cs || src_clk_nr < 0
193 || src_clk_nr > S5P64X0_SPI_SRCCLK_SCLK) {
194 printk(KERN_ERR "%s: Invalid SPI configuration\n", __func__);
195 return;
196 }
197
198 switch (cntrlr) {
199 case 0:
200 if (soc_is_s5p6450())
201 pd = &s5p6450_spi0_pdata;
202 else
203 pd = &s5p6440_spi0_pdata;
204
205 s5p64x0_device_spi0.dev.platform_data = pd;
206 break;
207 case 1:
208 if (soc_is_s5p6450())
209 pd = &s5p6450_spi1_pdata;
210 else
211 pd = &s5p6440_spi1_pdata;
212
213 s5p64x0_device_spi1.dev.platform_data = pd;
214 break;
215 default:
216 printk(KERN_ERR "%s: Invalid SPI controller(%d)\n",
217 __func__, cntrlr);
218 return;
219 }
220
221 pd->num_cs = num_cs;
222 pd->src_clk_nr = src_clk_nr;
223 pd->src_clk_name = s5p64x0_spi_src_clks[src_clk_nr];
224}
diff --git a/arch/arm/mach-s5p64x0/dma.c b/arch/arm/mach-s5p64x0/dma.c
index 442dd4ad12da..f820c0744405 100644
--- a/arch/arm/mach-s5p64x0/dma.c
+++ b/arch/arm/mach-s5p64x0/dma.c
@@ -38,176 +38,74 @@
38 38
39static u64 dma_dmamask = DMA_BIT_MASK(32); 39static u64 dma_dmamask = DMA_BIT_MASK(32);
40 40
41struct dma_pl330_peri s5p6440_pdma_peri[22] = { 41u8 s5p6440_pdma_peri[] = {
42 { 42 DMACH_UART0_RX,
43 .peri_id = (u8)DMACH_UART0_RX, 43 DMACH_UART0_TX,
44 .rqtype = DEVTOMEM, 44 DMACH_UART1_RX,
45 }, { 45 DMACH_UART1_TX,
46 .peri_id = (u8)DMACH_UART0_TX, 46 DMACH_UART2_RX,
47 .rqtype = MEMTODEV, 47 DMACH_UART2_TX,
48 }, { 48 DMACH_UART3_RX,
49 .peri_id = (u8)DMACH_UART1_RX, 49 DMACH_UART3_TX,
50 .rqtype = DEVTOMEM, 50 DMACH_MAX,
51 }, { 51 DMACH_MAX,
52 .peri_id = (u8)DMACH_UART1_TX, 52 DMACH_PCM0_TX,
53 .rqtype = MEMTODEV, 53 DMACH_PCM0_RX,
54 }, { 54 DMACH_I2S0_TX,
55 .peri_id = (u8)DMACH_UART2_RX, 55 DMACH_I2S0_RX,
56 .rqtype = DEVTOMEM, 56 DMACH_SPI0_TX,
57 }, { 57 DMACH_SPI0_RX,
58 .peri_id = (u8)DMACH_UART2_TX, 58 DMACH_MAX,
59 .rqtype = MEMTODEV, 59 DMACH_MAX,
60 }, { 60 DMACH_MAX,
61 .peri_id = (u8)DMACH_UART3_RX, 61 DMACH_MAX,
62 .rqtype = DEVTOMEM, 62 DMACH_SPI1_TX,
63 }, { 63 DMACH_SPI1_RX,
64 .peri_id = (u8)DMACH_UART3_TX,
65 .rqtype = MEMTODEV,
66 }, {
67 .peri_id = DMACH_MAX,
68 }, {
69 .peri_id = DMACH_MAX,
70 }, {
71 .peri_id = (u8)DMACH_PCM0_TX,
72 .rqtype = MEMTODEV,
73 }, {
74 .peri_id = (u8)DMACH_PCM0_RX,
75 .rqtype = DEVTOMEM,
76 }, {
77 .peri_id = (u8)DMACH_I2S0_TX,
78 .rqtype = MEMTODEV,
79 }, {
80 .peri_id = (u8)DMACH_I2S0_RX,
81 .rqtype = DEVTOMEM,
82 }, {
83 .peri_id = (u8)DMACH_SPI0_TX,
84 .rqtype = MEMTODEV,
85 }, {
86 .peri_id = (u8)DMACH_SPI0_RX,
87 .rqtype = DEVTOMEM,
88 }, {
89 .peri_id = (u8)DMACH_MAX,
90 }, {
91 .peri_id = (u8)DMACH_MAX,
92 }, {
93 .peri_id = (u8)DMACH_MAX,
94 }, {
95 .peri_id = (u8)DMACH_MAX,
96 }, {
97 .peri_id = (u8)DMACH_SPI1_TX,
98 .rqtype = MEMTODEV,
99 }, {
100 .peri_id = (u8)DMACH_SPI1_RX,
101 .rqtype = DEVTOMEM,
102 },
103}; 64};
104 65
105struct dma_pl330_platdata s5p6440_pdma_pdata = { 66struct dma_pl330_platdata s5p6440_pdma_pdata = {
106 .nr_valid_peri = ARRAY_SIZE(s5p6440_pdma_peri), 67 .nr_valid_peri = ARRAY_SIZE(s5p6440_pdma_peri),
107 .peri = s5p6440_pdma_peri, 68 .peri_id = s5p6440_pdma_peri,
108}; 69};
109 70
110struct dma_pl330_peri s5p6450_pdma_peri[32] = { 71u8 s5p6450_pdma_peri[] = {
111 { 72 DMACH_UART0_RX,
112 .peri_id = (u8)DMACH_UART0_RX, 73 DMACH_UART0_TX,
113 .rqtype = DEVTOMEM, 74 DMACH_UART1_RX,
114 }, { 75 DMACH_UART1_TX,
115 .peri_id = (u8)DMACH_UART0_TX, 76 DMACH_UART2_RX,
116 .rqtype = MEMTODEV, 77 DMACH_UART2_TX,
117 }, { 78 DMACH_UART3_RX,
118 .peri_id = (u8)DMACH_UART1_RX, 79 DMACH_UART3_TX,
119 .rqtype = DEVTOMEM, 80 DMACH_UART4_RX,
120 }, { 81 DMACH_UART4_TX,
121 .peri_id = (u8)DMACH_UART1_TX, 82 DMACH_PCM0_TX,
122 .rqtype = MEMTODEV, 83 DMACH_PCM0_RX,
123 }, { 84 DMACH_I2S0_TX,
124 .peri_id = (u8)DMACH_UART2_RX, 85 DMACH_I2S0_RX,
125 .rqtype = DEVTOMEM, 86 DMACH_SPI0_TX,
126 }, { 87 DMACH_SPI0_RX,
127 .peri_id = (u8)DMACH_UART2_TX, 88 DMACH_PCM1_TX,
128 .rqtype = MEMTODEV, 89 DMACH_PCM1_RX,
129 }, { 90 DMACH_PCM2_TX,
130 .peri_id = (u8)DMACH_UART3_RX, 91 DMACH_PCM2_RX,
131 .rqtype = DEVTOMEM, 92 DMACH_SPI1_TX,
132 }, { 93 DMACH_SPI1_RX,
133 .peri_id = (u8)DMACH_UART3_TX, 94 DMACH_USI_TX,
134 .rqtype = MEMTODEV, 95 DMACH_USI_RX,
135 }, { 96 DMACH_MAX,
136 .peri_id = (u8)DMACH_UART4_RX, 97 DMACH_I2S1_TX,
137 .rqtype = DEVTOMEM, 98 DMACH_I2S1_RX,
138 }, { 99 DMACH_I2S2_TX,
139 .peri_id = (u8)DMACH_UART4_TX, 100 DMACH_I2S2_RX,
140 .rqtype = MEMTODEV, 101 DMACH_PWM,
141 }, { 102 DMACH_UART5_RX,
142 .peri_id = (u8)DMACH_PCM0_TX, 103 DMACH_UART5_TX,
143 .rqtype = MEMTODEV,
144 }, {
145 .peri_id = (u8)DMACH_PCM0_RX,
146 .rqtype = DEVTOMEM,
147 }, {
148 .peri_id = (u8)DMACH_I2S0_TX,
149 .rqtype = MEMTODEV,
150 }, {
151 .peri_id = (u8)DMACH_I2S0_RX,
152 .rqtype = DEVTOMEM,
153 }, {
154 .peri_id = (u8)DMACH_SPI0_TX,
155 .rqtype = MEMTODEV,
156 }, {
157 .peri_id = (u8)DMACH_SPI0_RX,
158 .rqtype = DEVTOMEM,
159 }, {
160 .peri_id = (u8)DMACH_PCM1_TX,
161 .rqtype = MEMTODEV,
162 }, {
163 .peri_id = (u8)DMACH_PCM1_RX,
164 .rqtype = DEVTOMEM,
165 }, {
166 .peri_id = (u8)DMACH_PCM2_TX,
167 .rqtype = MEMTODEV,
168 }, {
169 .peri_id = (u8)DMACH_PCM2_RX,
170 .rqtype = DEVTOMEM,
171 }, {
172 .peri_id = (u8)DMACH_SPI1_TX,
173 .rqtype = MEMTODEV,
174 }, {
175 .peri_id = (u8)DMACH_SPI1_RX,
176 .rqtype = DEVTOMEM,
177 }, {
178 .peri_id = (u8)DMACH_USI_TX,
179 .rqtype = MEMTODEV,
180 }, {
181 .peri_id = (u8)DMACH_USI_RX,
182 .rqtype = DEVTOMEM,
183 }, {
184 .peri_id = (u8)DMACH_MAX,
185 }, {
186 .peri_id = (u8)DMACH_I2S1_TX,
187 .rqtype = MEMTODEV,
188 }, {
189 .peri_id = (u8)DMACH_I2S1_RX,
190 .rqtype = DEVTOMEM,
191 }, {
192 .peri_id = (u8)DMACH_I2S2_TX,
193 .rqtype = MEMTODEV,
194 }, {
195 .peri_id = (u8)DMACH_I2S2_RX,
196 .rqtype = DEVTOMEM,
197 }, {
198 .peri_id = (u8)DMACH_PWM,
199 }, {
200 .peri_id = (u8)DMACH_UART5_RX,
201 .rqtype = DEVTOMEM,
202 }, {
203 .peri_id = (u8)DMACH_UART5_TX,
204 .rqtype = MEMTODEV,
205 },
206}; 104};
207 105
208struct dma_pl330_platdata s5p6450_pdma_pdata = { 106struct dma_pl330_platdata s5p6450_pdma_pdata = {
209 .nr_valid_peri = ARRAY_SIZE(s5p6450_pdma_peri), 107 .nr_valid_peri = ARRAY_SIZE(s5p6450_pdma_peri),
210 .peri = s5p6450_pdma_peri, 108 .peri_id = s5p6450_pdma_peri,
211}; 109};
212 110
213struct amba_device s5p64x0_device_pdma = { 111struct amba_device s5p64x0_device_pdma = {
@@ -227,10 +125,15 @@ struct amba_device s5p64x0_device_pdma = {
227 125
228static int __init s5p64x0_dma_init(void) 126static int __init s5p64x0_dma_init(void)
229{ 127{
230 if (soc_is_s5p6450()) 128 if (soc_is_s5p6450()) {
129 dma_cap_set(DMA_SLAVE, s5p6450_pdma_pdata.cap_mask);
130 dma_cap_set(DMA_CYCLIC, s5p6450_pdma_pdata.cap_mask);
231 s5p64x0_device_pdma.dev.platform_data = &s5p6450_pdma_pdata; 131 s5p64x0_device_pdma.dev.platform_data = &s5p6450_pdma_pdata;
232 else 132 } else {
133 dma_cap_set(DMA_SLAVE, s5p6440_pdma_pdata.cap_mask);
134 dma_cap_set(DMA_CYCLIC, s5p6440_pdma_pdata.cap_mask);
233 s5p64x0_device_pdma.dev.platform_data = &s5p6440_pdma_pdata; 135 s5p64x0_device_pdma.dev.platform_data = &s5p6440_pdma_pdata;
136 }
234 137
235 amba_device_register(&s5p64x0_device_pdma, &iomem_resource); 138 amba_device_register(&s5p64x0_device_pdma, &iomem_resource);
236 139
diff --git a/arch/arm/mach-s5p64x0/include/mach/irqs.h b/arch/arm/mach-s5p64x0/include/mach/irqs.h
index 53982db9d259..5b845e849b30 100644
--- a/arch/arm/mach-s5p64x0/include/mach/irqs.h
+++ b/arch/arm/mach-s5p64x0/include/mach/irqs.h
@@ -141,6 +141,8 @@
141 141
142#define IRQ_EINT_GROUP(grp, x) (IRQ_EINT_GROUP##grp##_BASE + (x)) 142#define IRQ_EINT_GROUP(grp, x) (IRQ_EINT_GROUP##grp##_BASE + (x))
143 143
144#define IRQ_TIMER_BASE (11)
145
144/* Set the default NR_IRQS */ 146/* Set the default NR_IRQS */
145 147
146#define NR_IRQS (IRQ_EINT_GROUP8_BASE + IRQ_EINT_GROUP8_NR + 1) 148#define NR_IRQS (IRQ_EINT_GROUP8_BASE + IRQ_EINT_GROUP8_NR + 1)
diff --git a/arch/arm/mach-s5p64x0/include/mach/map.h b/arch/arm/mach-s5p64x0/include/mach/map.h
index 4d3ac8a3709d..0c0175dbfa34 100644
--- a/arch/arm/mach-s5p64x0/include/mach/map.h
+++ b/arch/arm/mach-s5p64x0/include/mach/map.h
@@ -67,6 +67,8 @@
67#define S3C_PA_RTC S5P64X0_PA_RTC 67#define S3C_PA_RTC S5P64X0_PA_RTC
68#define S3C_PA_WDT S5P64X0_PA_WDT 68#define S3C_PA_WDT S5P64X0_PA_WDT
69#define S3C_PA_FB S5P64X0_PA_FB 69#define S3C_PA_FB S5P64X0_PA_FB
70#define S3C_PA_SPI0 S5P64X0_PA_SPI0
71#define S3C_PA_SPI1 S5P64X0_PA_SPI1
70 72
71#define S5P_PA_CHIPID S5P64X0_PA_CHIPID 73#define S5P_PA_CHIPID S5P64X0_PA_CHIPID
72#define S5P_PA_SROMC S5P64X0_PA_SROMC 74#define S5P_PA_SROMC S5P64X0_PA_SROMC
diff --git a/arch/arm/mach-s5p64x0/init.c b/arch/arm/mach-s5p64x0/init.c
index 79833caf8165..659a66c131a1 100644
--- a/arch/arm/mach-s5p64x0/init.c
+++ b/arch/arm/mach-s5p64x0/init.c
@@ -23,36 +23,7 @@
23#include <plat/s5p6450.h> 23#include <plat/s5p6450.h>
24#include <plat/regs-serial.h> 24#include <plat/regs-serial.h>
25 25
26static struct s3c24xx_uart_clksrc s5p64x0_serial_clocks[] = {
27 [0] = {
28 .name = "pclk_low",
29 .divisor = 1,
30 .min_baud = 0,
31 .max_baud = 0,
32 },
33 [1] = {
34 .name = "uclk1",
35 .divisor = 1,
36 .min_baud = 0,
37 .max_baud = 0,
38 },
39};
40
41/* uart registration process */ 26/* uart registration process */
42
43void __init s5p64x0_common_init_uarts(struct s3c2410_uartcfg *cfg, int no)
44{
45 struct s3c2410_uartcfg *tcfg = cfg;
46 u32 ucnt;
47
48 for (ucnt = 0; ucnt < no; ucnt++, tcfg++) {
49 if (!tcfg->clocks) {
50 tcfg->clocks = s5p64x0_serial_clocks;
51 tcfg->clocks_size = ARRAY_SIZE(s5p64x0_serial_clocks);
52 }
53 }
54}
55
56void __init s5p6440_init_uarts(struct s3c2410_uartcfg *cfg, int no) 27void __init s5p6440_init_uarts(struct s3c2410_uartcfg *cfg, int no)
57{ 28{
58 int uart; 29 int uart;
@@ -62,12 +33,10 @@ void __init s5p6440_init_uarts(struct s3c2410_uartcfg *cfg, int no)
62 s5p_uart_resources[uart].resources->end = S5P6440_PA_UART(uart) + S5P_SZ_UART; 33 s5p_uart_resources[uart].resources->end = S5P6440_PA_UART(uart) + S5P_SZ_UART;
63 } 34 }
64 35
65 s5p64x0_common_init_uarts(cfg, no);
66 s3c24xx_init_uartdevs("s3c6400-uart", s5p_uart_resources, cfg, no); 36 s3c24xx_init_uartdevs("s3c6400-uart", s5p_uart_resources, cfg, no);
67} 37}
68 38
69void __init s5p6450_init_uarts(struct s3c2410_uartcfg *cfg, int no) 39void __init s5p6450_init_uarts(struct s3c2410_uartcfg *cfg, int no)
70{ 40{
71 s5p64x0_common_init_uarts(cfg, no);
72 s3c24xx_init_uartdevs("s3c6400-uart", s5p_uart_resources, cfg, no); 41 s3c24xx_init_uartdevs("s3c6400-uart", s5p_uart_resources, cfg, no);
73} 42}
diff --git a/arch/arm/mach-s5p64x0/setup-spi.c b/arch/arm/mach-s5p64x0/setup-spi.c
new file mode 100644
index 000000000000..e9b841240352
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/setup-spi.c
@@ -0,0 +1,55 @@
1/* linux/arch/arm/mach-s5p64x0/setup-spi.c
2 *
3 * Copyright (C) 2011 Samsung Electronics Ltd.
4 * http://www.samsung.com/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/gpio.h>
12#include <linux/platform_device.h>
13#include <linux/io.h>
14
15#include <plat/gpio-cfg.h>
16#include <plat/cpu.h>
17#include <plat/s3c64xx-spi.h>
18
19#ifdef CONFIG_S3C64XX_DEV_SPI0
20struct s3c64xx_spi_info s3c64xx_spi0_pdata __initdata = {
21 .fifo_lvl_mask = 0x1ff,
22 .rx_lvl_offset = 15,
23 .tx_st_done = 25,
24};
25
26int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
27{
28 if (soc_is_s5p6450())
29 s3c_gpio_cfgall_range(S5P6450_GPC(0), 3,
30 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
31 else
32 s3c_gpio_cfgall_range(S5P6440_GPC(0), 3,
33 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
34 return 0;
35}
36#endif
37
38#ifdef CONFIG_S3C64XX_DEV_SPI1
39struct s3c64xx_spi_info s3c64xx_spi1_pdata __initdata = {
40 .fifo_lvl_mask = 0x7f,
41 .rx_lvl_offset = 15,
42 .tx_st_done = 25,
43};
44
45int s3c64xx_spi1_cfg_gpio(struct platform_device *dev)
46{
47 if (soc_is_s5p6450())
48 s3c_gpio_cfgall_range(S5P6450_GPC(4), 3,
49 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
50 else
51 s3c_gpio_cfgall_range(S5P6440_GPC(4), 3,
52 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
53 return 0;
54}
55#endif
diff --git a/arch/arm/mach-s5pc100/Kconfig b/arch/arm/mach-s5pc100/Kconfig
index e538a4c67e9c..75a26eaf2633 100644
--- a/arch/arm/mach-s5pc100/Kconfig
+++ b/arch/arm/mach-s5pc100/Kconfig
@@ -45,6 +45,11 @@ config S5PC100_SETUP_SDHCI_GPIO
45 help 45 help
46 Common setup code for SDHCI gpio. 46 Common setup code for SDHCI gpio.
47 47
48config S5PC100_SETUP_SPI
49 bool
50 help
51 Common setup code for SPI GPIO configurations.
52
48config MACH_SMDKC100 53config MACH_SMDKC100
49 bool "SMDKC100" 54 bool "SMDKC100"
50 select CPU_S5PC100 55 select CPU_S5PC100
diff --git a/arch/arm/mach-s5pc100/Makefile b/arch/arm/mach-s5pc100/Makefile
index a5e6e608b498..291e246c0ec0 100644
--- a/arch/arm/mach-s5pc100/Makefile
+++ b/arch/arm/mach-s5pc100/Makefile
@@ -21,12 +21,11 @@ obj-$(CONFIG_S5PC100_SETUP_FB_24BPP) += setup-fb-24bpp.o
21obj-$(CONFIG_S5PC100_SETUP_I2C1) += setup-i2c1.o 21obj-$(CONFIG_S5PC100_SETUP_I2C1) += setup-i2c1.o
22obj-$(CONFIG_S5PC100_SETUP_IDE) += setup-ide.o 22obj-$(CONFIG_S5PC100_SETUP_IDE) += setup-ide.o
23obj-$(CONFIG_S5PC100_SETUP_KEYPAD) += setup-keypad.o 23obj-$(CONFIG_S5PC100_SETUP_KEYPAD) += setup-keypad.o
24obj-$(CONFIG_S5PC100_SETUP_SDHCI) += setup-sdhci.o
25obj-$(CONFIG_S5PC100_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o 24obj-$(CONFIG_S5PC100_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o
25obj-$(CONFIG_S5PC100_SETUP_SPI) += setup-spi.o
26 26
27# device support 27# device support
28obj-y += dev-audio.o 28obj-y += dev-audio.o
29obj-$(CONFIG_S3C64XX_DEV_SPI) += dev-spi.o
30 29
31# machine support 30# machine support
32 31
diff --git a/arch/arm/mach-s5pc100/clock.c b/arch/arm/mach-s5pc100/clock.c
index 8d47709da713..eba721b551fc 100644
--- a/arch/arm/mach-s5pc100/clock.c
+++ b/arch/arm/mach-s5pc100/clock.c
@@ -426,24 +426,6 @@ static struct clk init_clocks_off[] = {
426 .enable = s5pc100_d0_2_ctrl, 426 .enable = s5pc100_d0_2_ctrl,
427 .ctrlbit = (1 << 1), 427 .ctrlbit = (1 << 1),
428 }, { 428 }, {
429 .name = "hsmmc",
430 .devname = "s3c-sdhci.2",
431 .parent = &clk_div_d1_bus.clk,
432 .enable = s5pc100_d1_0_ctrl,
433 .ctrlbit = (1 << 7),
434 }, {
435 .name = "hsmmc",
436 .devname = "s3c-sdhci.1",
437 .parent = &clk_div_d1_bus.clk,
438 .enable = s5pc100_d1_0_ctrl,
439 .ctrlbit = (1 << 6),
440 }, {
441 .name = "hsmmc",
442 .devname = "s3c-sdhci.0",
443 .parent = &clk_div_d1_bus.clk,
444 .enable = s5pc100_d1_0_ctrl,
445 .ctrlbit = (1 << 5),
446 }, {
447 .name = "modemif", 429 .name = "modemif",
448 .parent = &clk_div_d1_bus.clk, 430 .parent = &clk_div_d1_bus.clk,
449 .enable = s5pc100_d1_0_ctrl, 431 .enable = s5pc100_d1_0_ctrl,
@@ -673,24 +655,6 @@ static struct clk init_clocks_off[] = {
673 .enable = s5pc100_d1_5_ctrl, 655 .enable = s5pc100_d1_5_ctrl,
674 .ctrlbit = (1 << 8), 656 .ctrlbit = (1 << 8),
675 }, { 657 }, {
676 .name = "spi_48m",
677 .devname = "s3c64xx-spi.0",
678 .parent = &clk_mout_48m.clk,
679 .enable = s5pc100_sclk0_ctrl,
680 .ctrlbit = (1 << 7),
681 }, {
682 .name = "spi_48m",
683 .devname = "s3c64xx-spi.1",
684 .parent = &clk_mout_48m.clk,
685 .enable = s5pc100_sclk0_ctrl,
686 .ctrlbit = (1 << 8),
687 }, {
688 .name = "spi_48m",
689 .devname = "s3c64xx-spi.2",
690 .parent = &clk_mout_48m.clk,
691 .enable = s5pc100_sclk0_ctrl,
692 .ctrlbit = (1 << 9),
693 }, {
694 .name = "mmc_48m", 658 .name = "mmc_48m",
695 .devname = "s3c-sdhci.0", 659 .devname = "s3c-sdhci.0",
696 .parent = &clk_mout_48m.clk, 660 .parent = &clk_mout_48m.clk,
@@ -711,6 +675,54 @@ static struct clk init_clocks_off[] = {
711 }, 675 },
712}; 676};
713 677
678static struct clk clk_hsmmc2 = {
679 .name = "hsmmc",
680 .devname = "s3c-sdhci.2",
681 .parent = &clk_div_d1_bus.clk,
682 .enable = s5pc100_d1_0_ctrl,
683 .ctrlbit = (1 << 7),
684};
685
686static struct clk clk_hsmmc1 = {
687 .name = "hsmmc",
688 .devname = "s3c-sdhci.1",
689 .parent = &clk_div_d1_bus.clk,
690 .enable = s5pc100_d1_0_ctrl,
691 .ctrlbit = (1 << 6),
692};
693
694static struct clk clk_hsmmc0 = {
695 .name = "hsmmc",
696 .devname = "s3c-sdhci.0",
697 .parent = &clk_div_d1_bus.clk,
698 .enable = s5pc100_d1_0_ctrl,
699 .ctrlbit = (1 << 5),
700};
701
702static struct clk clk_48m_spi0 = {
703 .name = "spi_48m",
704 .devname = "s3c64xx-spi.0",
705 .parent = &clk_mout_48m.clk,
706 .enable = s5pc100_sclk0_ctrl,
707 .ctrlbit = (1 << 7),
708};
709
710static struct clk clk_48m_spi1 = {
711 .name = "spi_48m",
712 .devname = "s3c64xx-spi.1",
713 .parent = &clk_mout_48m.clk,
714 .enable = s5pc100_sclk0_ctrl,
715 .ctrlbit = (1 << 8),
716};
717
718static struct clk clk_48m_spi2 = {
719 .name = "spi_48m",
720 .devname = "s3c64xx-spi.2",
721 .parent = &clk_mout_48m.clk,
722 .enable = s5pc100_sclk0_ctrl,
723 .ctrlbit = (1 << 9),
724};
725
714static struct clk clk_vclk54m = { 726static struct clk clk_vclk54m = {
715 .name = "vclk_54m", 727 .name = "vclk_54m",
716 .rate = 54000000, 728 .rate = 54000000,
@@ -929,49 +941,6 @@ static struct clksrc_clk clk_sclk_spdif = {
929static struct clksrc_clk clksrcs[] = { 941static struct clksrc_clk clksrcs[] = {
930 { 942 {
931 .clk = { 943 .clk = {
932 .name = "sclk_spi",
933 .devname = "s3c64xx-spi.0",
934 .ctrlbit = (1 << 4),
935 .enable = s5pc100_sclk0_ctrl,
936
937 },
938 .sources = &clk_src_group1,
939 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 2 },
940 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 4, .size = 4 },
941 }, {
942 .clk = {
943 .name = "sclk_spi",
944 .devname = "s3c64xx-spi.1",
945 .ctrlbit = (1 << 5),
946 .enable = s5pc100_sclk0_ctrl,
947
948 },
949 .sources = &clk_src_group1,
950 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 8, .size = 2 },
951 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 8, .size = 4 },
952 }, {
953 .clk = {
954 .name = "sclk_spi",
955 .devname = "s3c64xx-spi.2",
956 .ctrlbit = (1 << 6),
957 .enable = s5pc100_sclk0_ctrl,
958
959 },
960 .sources = &clk_src_group1,
961 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 12, .size = 2 },
962 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 12, .size = 4 },
963 }, {
964 .clk = {
965 .name = "uclk1",
966 .ctrlbit = (1 << 3),
967 .enable = s5pc100_sclk0_ctrl,
968
969 },
970 .sources = &clk_src_group2,
971 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 0, .size = 1 },
972 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 0, .size = 4 },
973 }, {
974 .clk = {
975 .name = "sclk_mixer", 944 .name = "sclk_mixer",
976 .ctrlbit = (1 << 6), 945 .ctrlbit = (1 << 6),
977 .enable = s5pc100_sclk0_ctrl, 946 .enable = s5pc100_sclk0_ctrl,
@@ -1024,39 +993,6 @@ static struct clksrc_clk clksrcs[] = {
1024 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 24, .size = 4 }, 993 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 24, .size = 4 },
1025 }, { 994 }, {
1026 .clk = { 995 .clk = {
1027 .name = "sclk_mmc",
1028 .devname = "s3c-sdhci.0",
1029 .ctrlbit = (1 << 12),
1030 .enable = s5pc100_sclk1_ctrl,
1031
1032 },
1033 .sources = &clk_src_mmc0,
1034 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 0, .size = 2 },
1035 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 0, .size = 4 },
1036 }, {
1037 .clk = {
1038 .name = "sclk_mmc",
1039 .devname = "s3c-sdhci.1",
1040 .ctrlbit = (1 << 13),
1041 .enable = s5pc100_sclk1_ctrl,
1042
1043 },
1044 .sources = &clk_src_mmc12,
1045 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 4, .size = 2 },
1046 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 4, .size = 4 },
1047 }, {
1048 .clk = {
1049 .name = "sclk_mmc",
1050 .devname = "s3c-sdhci.2",
1051 .ctrlbit = (1 << 14),
1052 .enable = s5pc100_sclk1_ctrl,
1053
1054 },
1055 .sources = &clk_src_mmc12,
1056 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 8, .size = 2 },
1057 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 8, .size = 4 },
1058 }, {
1059 .clk = {
1060 .name = "sclk_irda", 996 .name = "sclk_irda",
1061 .ctrlbit = (1 << 10), 997 .ctrlbit = (1 << 10),
1062 .enable = s5pc100_sclk0_ctrl, 998 .enable = s5pc100_sclk0_ctrl,
@@ -1098,6 +1034,89 @@ static struct clksrc_clk clksrcs[] = {
1098 }, 1034 },
1099}; 1035};
1100 1036
1037static struct clksrc_clk clk_sclk_uart = {
1038 .clk = {
1039 .name = "uclk1",
1040 .ctrlbit = (1 << 3),
1041 .enable = s5pc100_sclk0_ctrl,
1042 },
1043 .sources = &clk_src_group2,
1044 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 0, .size = 1 },
1045 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 0, .size = 4 },
1046};
1047
1048static struct clksrc_clk clk_sclk_mmc0 = {
1049 .clk = {
1050 .name = "sclk_mmc",
1051 .devname = "s3c-sdhci.0",
1052 .ctrlbit = (1 << 12),
1053 .enable = s5pc100_sclk1_ctrl,
1054 },
1055 .sources = &clk_src_mmc0,
1056 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 0, .size = 2 },
1057 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 0, .size = 4 },
1058};
1059
1060static struct clksrc_clk clk_sclk_mmc1 = {
1061 .clk = {
1062 .name = "sclk_mmc",
1063 .devname = "s3c-sdhci.1",
1064 .ctrlbit = (1 << 13),
1065 .enable = s5pc100_sclk1_ctrl,
1066 },
1067 .sources = &clk_src_mmc12,
1068 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 4, .size = 2 },
1069 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 4, .size = 4 },
1070};
1071
1072static struct clksrc_clk clk_sclk_mmc2 = {
1073 .clk = {
1074 .name = "sclk_mmc",
1075 .devname = "s3c-sdhci.2",
1076 .ctrlbit = (1 << 14),
1077 .enable = s5pc100_sclk1_ctrl,
1078 },
1079 .sources = &clk_src_mmc12,
1080 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 8, .size = 2 },
1081 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 8, .size = 4 },
1082};
1083
1084static struct clksrc_clk clk_sclk_spi0 = {
1085 .clk = {
1086 .name = "sclk_spi",
1087 .devname = "s3c64xx-spi.0",
1088 .ctrlbit = (1 << 4),
1089 .enable = s5pc100_sclk0_ctrl,
1090 },
1091 .sources = &clk_src_group1,
1092 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 2 },
1093 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 4, .size = 4 },
1094};
1095
1096static struct clksrc_clk clk_sclk_spi1 = {
1097 .clk = {
1098 .name = "sclk_spi",
1099 .devname = "s3c64xx-spi.1",
1100 .ctrlbit = (1 << 5),
1101 .enable = s5pc100_sclk0_ctrl,
1102 },
1103 .sources = &clk_src_group1,
1104 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 8, .size = 2 },
1105 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 8, .size = 4 },
1106};
1107
1108static struct clksrc_clk clk_sclk_spi2 = {
1109 .clk = {
1110 .name = "sclk_spi",
1111 .devname = "s3c64xx-spi.2",
1112 .ctrlbit = (1 << 6),
1113 .enable = s5pc100_sclk0_ctrl,
1114 },
1115 .sources = &clk_src_group1,
1116 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 12, .size = 2 },
1117 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 12, .size = 4 },
1118};
1119
1101/* Clock initialisation code */ 1120/* Clock initialisation code */
1102static struct clksrc_clk *sysclks[] = { 1121static struct clksrc_clk *sysclks[] = {
1103 &clk_mout_apll, 1122 &clk_mout_apll,
@@ -1127,6 +1146,25 @@ static struct clksrc_clk *sysclks[] = {
1127 &clk_sclk_spdif, 1146 &clk_sclk_spdif,
1128}; 1147};
1129 1148
1149static struct clk *clk_cdev[] = {
1150 &clk_hsmmc0,
1151 &clk_hsmmc1,
1152 &clk_hsmmc2,
1153 &clk_48m_spi0,
1154 &clk_48m_spi1,
1155 &clk_48m_spi2,
1156};
1157
1158static struct clksrc_clk *clksrc_cdev[] = {
1159 &clk_sclk_uart,
1160 &clk_sclk_mmc0,
1161 &clk_sclk_mmc1,
1162 &clk_sclk_mmc2,
1163 &clk_sclk_spi0,
1164 &clk_sclk_spi1,
1165 &clk_sclk_spi2,
1166};
1167
1130void __init_or_cpufreq s5pc100_setup_clocks(void) 1168void __init_or_cpufreq s5pc100_setup_clocks(void)
1131{ 1169{
1132 unsigned long xtal; 1170 unsigned long xtal;
@@ -1266,6 +1304,24 @@ static struct clk *clks[] __initdata = {
1266 &clk_pcmcdclk1, 1304 &clk_pcmcdclk1,
1267}; 1305};
1268 1306
1307static struct clk_lookup s5pc100_clk_lookup[] = {
1308 CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p),
1309 CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uart.clk),
1310 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &clk_hsmmc0),
1311 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &clk_hsmmc1),
1312 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.0", &clk_hsmmc2),
1313 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
1314 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
1315 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
1316 CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
1317 CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_48m_spi0),
1318 CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk2", &clk_sclk_spi0.clk),
1319 CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_48m_spi1),
1320 CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk2", &clk_sclk_spi1.clk),
1321 CLKDEV_INIT("s3c64xx-spi.2", "spi_busclk1", &clk_48m_spi2),
1322 CLKDEV_INIT("s3c64xx-spi.2", "spi_busclk2", &clk_sclk_spi2.clk),
1323};
1324
1269void __init s5pc100_register_clocks(void) 1325void __init s5pc100_register_clocks(void)
1270{ 1326{
1271 int ptr; 1327 int ptr;
@@ -1277,9 +1333,16 @@ void __init s5pc100_register_clocks(void)
1277 1333
1278 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs)); 1334 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
1279 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks)); 1335 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
1336 for (ptr = 0; ptr < ARRAY_SIZE(clksrc_cdev); ptr++)
1337 s3c_register_clksrc(clksrc_cdev[ptr], 1);
1280 1338
1281 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); 1339 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
1282 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); 1340 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
1341 clkdev_add_table(s5pc100_clk_lookup, ARRAY_SIZE(s5pc100_clk_lookup));
1342
1343 s3c24xx_register_clocks(clk_cdev, ARRAY_SIZE(clk_cdev));
1344 for (ptr = 0; ptr < ARRAY_SIZE(clk_cdev); ptr++)
1345 s3c_disable_clocks(clk_cdev[ptr], 1);
1283 1346
1284 s3c24xx_register_clock(&dummy_apb_pclk); 1347 s3c24xx_register_clock(&dummy_apb_pclk);
1285 1348
diff --git a/arch/arm/mach-s5pc100/dev-spi.c b/arch/arm/mach-s5pc100/dev-spi.c
deleted file mode 100644
index e5d6c4dceb56..000000000000
--- a/arch/arm/mach-s5pc100/dev-spi.c
+++ /dev/null
@@ -1,227 +0,0 @@
1/* linux/arch/arm/mach-s5pc100/dev-spi.c
2 *
3 * Copyright (C) 2010 Samsung Electronics Co. Ltd.
4 * Jaswinder Singh <jassi.brar@samsung.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/platform_device.h>
12#include <linux/dma-mapping.h>
13#include <linux/gpio.h>
14
15#include <mach/dma.h>
16#include <mach/map.h>
17#include <mach/spi-clocks.h>
18#include <mach/irqs.h>
19
20#include <plat/s3c64xx-spi.h>
21#include <plat/gpio-cfg.h>
22#include <plat/irqs.h>
23
24static char *spi_src_clks[] = {
25 [S5PC100_SPI_SRCCLK_PCLK] = "pclk",
26 [S5PC100_SPI_SRCCLK_48M] = "spi_48m",
27 [S5PC100_SPI_SRCCLK_SPIBUS] = "spi_bus",
28};
29
30/* SPI Controller platform_devices */
31
32/* Since we emulate multi-cs capability, we do not touch the CS.
33 * The emulated CS is toggled by board specific mechanism, as it can
34 * be either some immediate GPIO or some signal out of some other
35 * chip in between ... or some yet another way.
36 * We simply do not assume anything about CS.
37 */
38static int s5pc100_spi_cfg_gpio(struct platform_device *pdev)
39{
40 switch (pdev->id) {
41 case 0:
42 s3c_gpio_cfgall_range(S5PC100_GPB(0), 3,
43 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
44 break;
45
46 case 1:
47 s3c_gpio_cfgall_range(S5PC100_GPB(4), 3,
48 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
49 break;
50
51 case 2:
52 s3c_gpio_cfgpin(S5PC100_GPG3(0), S3C_GPIO_SFN(3));
53 s3c_gpio_setpull(S5PC100_GPG3(0), S3C_GPIO_PULL_UP);
54 s3c_gpio_cfgall_range(S5PC100_GPB(2), 2,
55 S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
56 break;
57
58 default:
59 dev_err(&pdev->dev, "Invalid SPI Controller number!");
60 return -EINVAL;
61 }
62
63 return 0;
64}
65
66static struct resource s5pc100_spi0_resource[] = {
67 [0] = {
68 .start = S5PC100_PA_SPI0,
69 .end = S5PC100_PA_SPI0 + 0x100 - 1,
70 .flags = IORESOURCE_MEM,
71 },
72 [1] = {
73 .start = DMACH_SPI0_TX,
74 .end = DMACH_SPI0_TX,
75 .flags = IORESOURCE_DMA,
76 },
77 [2] = {
78 .start = DMACH_SPI0_RX,
79 .end = DMACH_SPI0_RX,
80 .flags = IORESOURCE_DMA,
81 },
82 [3] = {
83 .start = IRQ_SPI0,
84 .end = IRQ_SPI0,
85 .flags = IORESOURCE_IRQ,
86 },
87};
88
89static struct s3c64xx_spi_info s5pc100_spi0_pdata = {
90 .cfg_gpio = s5pc100_spi_cfg_gpio,
91 .fifo_lvl_mask = 0x7f,
92 .rx_lvl_offset = 13,
93 .high_speed = 1,
94 .tx_st_done = 21,
95};
96
97static u64 spi_dmamask = DMA_BIT_MASK(32);
98
99struct platform_device s5pc100_device_spi0 = {
100 .name = "s3c64xx-spi",
101 .id = 0,
102 .num_resources = ARRAY_SIZE(s5pc100_spi0_resource),
103 .resource = s5pc100_spi0_resource,
104 .dev = {
105 .dma_mask = &spi_dmamask,
106 .coherent_dma_mask = DMA_BIT_MASK(32),
107 .platform_data = &s5pc100_spi0_pdata,
108 },
109};
110
111static struct resource s5pc100_spi1_resource[] = {
112 [0] = {
113 .start = S5PC100_PA_SPI1,
114 .end = S5PC100_PA_SPI1 + 0x100 - 1,
115 .flags = IORESOURCE_MEM,
116 },
117 [1] = {
118 .start = DMACH_SPI1_TX,
119 .end = DMACH_SPI1_TX,
120 .flags = IORESOURCE_DMA,
121 },
122 [2] = {
123 .start = DMACH_SPI1_RX,
124 .end = DMACH_SPI1_RX,
125 .flags = IORESOURCE_DMA,
126 },
127 [3] = {
128 .start = IRQ_SPI1,
129 .end = IRQ_SPI1,
130 .flags = IORESOURCE_IRQ,
131 },
132};
133
134static struct s3c64xx_spi_info s5pc100_spi1_pdata = {
135 .cfg_gpio = s5pc100_spi_cfg_gpio,
136 .fifo_lvl_mask = 0x7f,
137 .rx_lvl_offset = 13,
138 .high_speed = 1,
139 .tx_st_done = 21,
140};
141
142struct platform_device s5pc100_device_spi1 = {
143 .name = "s3c64xx-spi",
144 .id = 1,
145 .num_resources = ARRAY_SIZE(s5pc100_spi1_resource),
146 .resource = s5pc100_spi1_resource,
147 .dev = {
148 .dma_mask = &spi_dmamask,
149 .coherent_dma_mask = DMA_BIT_MASK(32),
150 .platform_data = &s5pc100_spi1_pdata,
151 },
152};
153
154static struct resource s5pc100_spi2_resource[] = {
155 [0] = {
156 .start = S5PC100_PA_SPI2,
157 .end = S5PC100_PA_SPI2 + 0x100 - 1,
158 .flags = IORESOURCE_MEM,
159 },
160 [1] = {
161 .start = DMACH_SPI2_TX,
162 .end = DMACH_SPI2_TX,
163 .flags = IORESOURCE_DMA,
164 },
165 [2] = {
166 .start = DMACH_SPI2_RX,
167 .end = DMACH_SPI2_RX,
168 .flags = IORESOURCE_DMA,
169 },
170 [3] = {
171 .start = IRQ_SPI2,
172 .end = IRQ_SPI2,
173 .flags = IORESOURCE_IRQ,
174 },
175};
176
177static struct s3c64xx_spi_info s5pc100_spi2_pdata = {
178 .cfg_gpio = s5pc100_spi_cfg_gpio,
179 .fifo_lvl_mask = 0x7f,
180 .rx_lvl_offset = 13,
181 .high_speed = 1,
182 .tx_st_done = 21,
183};
184
185struct platform_device s5pc100_device_spi2 = {
186 .name = "s3c64xx-spi",
187 .id = 2,
188 .num_resources = ARRAY_SIZE(s5pc100_spi2_resource),
189 .resource = s5pc100_spi2_resource,
190 .dev = {
191 .dma_mask = &spi_dmamask,
192 .coherent_dma_mask = DMA_BIT_MASK(32),
193 .platform_data = &s5pc100_spi2_pdata,
194 },
195};
196
197void __init s5pc100_spi_set_info(int cntrlr, int src_clk_nr, int num_cs)
198{
199 struct s3c64xx_spi_info *pd;
200
201 /* Reject invalid configuration */
202 if (!num_cs || src_clk_nr < 0
203 || src_clk_nr > S5PC100_SPI_SRCCLK_SPIBUS) {
204 printk(KERN_ERR "%s: Invalid SPI configuration\n", __func__);
205 return;
206 }
207
208 switch (cntrlr) {
209 case 0:
210 pd = &s5pc100_spi0_pdata;
211 break;
212 case 1:
213 pd = &s5pc100_spi1_pdata;
214 break;
215 case 2:
216 pd = &s5pc100_spi2_pdata;
217 break;
218 default:
219 printk(KERN_ERR "%s: Invalid SPI controller(%d)\n",
220 __func__, cntrlr);
221 return;
222 }
223
224 pd->num_cs = num_cs;
225 pd->src_clk_nr = src_clk_nr;
226 pd->src_clk_name = spi_src_clks[src_clk_nr];
227}
diff --git a/arch/arm/mach-s5pc100/dma.c b/arch/arm/mach-s5pc100/dma.c
index 065a087f5a8b..c841f4d313f2 100644
--- a/arch/arm/mach-s5pc100/dma.c
+++ b/arch/arm/mach-s5pc100/dma.c
@@ -35,100 +35,42 @@
35 35
36static u64 dma_dmamask = DMA_BIT_MASK(32); 36static u64 dma_dmamask = DMA_BIT_MASK(32);
37 37
38struct dma_pl330_peri pdma0_peri[30] = { 38u8 pdma0_peri[] = {
39 { 39 DMACH_UART0_RX,
40 .peri_id = (u8)DMACH_UART0_RX, 40 DMACH_UART0_TX,
41 .rqtype = DEVTOMEM, 41 DMACH_UART1_RX,
42 }, { 42 DMACH_UART1_TX,
43 .peri_id = (u8)DMACH_UART0_TX, 43 DMACH_UART2_RX,
44 .rqtype = MEMTODEV, 44 DMACH_UART2_TX,
45 }, { 45 DMACH_UART3_RX,
46 .peri_id = (u8)DMACH_UART1_RX, 46 DMACH_UART3_TX,
47 .rqtype = DEVTOMEM, 47 DMACH_IRDA,
48 }, { 48 DMACH_I2S0_RX,
49 .peri_id = (u8)DMACH_UART1_TX, 49 DMACH_I2S0_TX,
50 .rqtype = MEMTODEV, 50 DMACH_I2S0S_TX,
51 }, { 51 DMACH_I2S1_RX,
52 .peri_id = (u8)DMACH_UART2_RX, 52 DMACH_I2S1_TX,
53 .rqtype = DEVTOMEM, 53 DMACH_I2S2_RX,
54 }, { 54 DMACH_I2S2_TX,
55 .peri_id = (u8)DMACH_UART2_TX, 55 DMACH_SPI0_RX,
56 .rqtype = MEMTODEV, 56 DMACH_SPI0_TX,
57 }, { 57 DMACH_SPI1_RX,
58 .peri_id = (u8)DMACH_UART3_RX, 58 DMACH_SPI1_TX,
59 .rqtype = DEVTOMEM, 59 DMACH_SPI2_RX,
60 }, { 60 DMACH_SPI2_TX,
61 .peri_id = (u8)DMACH_UART3_TX, 61 DMACH_AC97_MICIN,
62 .rqtype = MEMTODEV, 62 DMACH_AC97_PCMIN,
63 }, { 63 DMACH_AC97_PCMOUT,
64 .peri_id = DMACH_IRDA, 64 DMACH_EXTERNAL,
65 }, { 65 DMACH_PWM,
66 .peri_id = (u8)DMACH_I2S0_RX, 66 DMACH_SPDIF,
67 .rqtype = DEVTOMEM, 67 DMACH_HSI_RX,
68 }, { 68 DMACH_HSI_TX,
69 .peri_id = (u8)DMACH_I2S0_TX,
70 .rqtype = MEMTODEV,
71 }, {
72 .peri_id = (u8)DMACH_I2S0S_TX,
73 .rqtype = MEMTODEV,
74 }, {
75 .peri_id = (u8)DMACH_I2S1_RX,
76 .rqtype = DEVTOMEM,
77 }, {
78 .peri_id = (u8)DMACH_I2S1_TX,
79 .rqtype = MEMTODEV,
80 }, {
81 .peri_id = (u8)DMACH_I2S2_RX,
82 .rqtype = DEVTOMEM,
83 }, {
84 .peri_id = (u8)DMACH_I2S2_TX,
85 .rqtype = MEMTODEV,
86 }, {
87 .peri_id = (u8)DMACH_SPI0_RX,
88 .rqtype = DEVTOMEM,
89 }, {
90 .peri_id = (u8)DMACH_SPI0_TX,
91 .rqtype = MEMTODEV,
92 }, {
93 .peri_id = (u8)DMACH_SPI1_RX,
94 .rqtype = DEVTOMEM,
95 }, {
96 .peri_id = (u8)DMACH_SPI1_TX,
97 .rqtype = MEMTODEV,
98 }, {
99 .peri_id = (u8)DMACH_SPI2_RX,
100 .rqtype = DEVTOMEM,
101 }, {
102 .peri_id = (u8)DMACH_SPI2_TX,
103 .rqtype = MEMTODEV,
104 }, {
105 .peri_id = (u8)DMACH_AC97_MICIN,
106 .rqtype = DEVTOMEM,
107 }, {
108 .peri_id = (u8)DMACH_AC97_PCMIN,
109 .rqtype = DEVTOMEM,
110 }, {
111 .peri_id = (u8)DMACH_AC97_PCMOUT,
112 .rqtype = MEMTODEV,
113 }, {
114 .peri_id = (u8)DMACH_EXTERNAL,
115 }, {
116 .peri_id = (u8)DMACH_PWM,
117 }, {
118 .peri_id = (u8)DMACH_SPDIF,
119 .rqtype = MEMTODEV,
120 }, {
121 .peri_id = (u8)DMACH_HSI_RX,
122 .rqtype = DEVTOMEM,
123 }, {
124 .peri_id = (u8)DMACH_HSI_TX,
125 .rqtype = MEMTODEV,
126 },
127}; 69};
128 70
129struct dma_pl330_platdata s5pc100_pdma0_pdata = { 71struct dma_pl330_platdata s5pc100_pdma0_pdata = {
130 .nr_valid_peri = ARRAY_SIZE(pdma0_peri), 72 .nr_valid_peri = ARRAY_SIZE(pdma0_peri),
131 .peri = pdma0_peri, 73 .peri_id = pdma0_peri,
132}; 74};
133 75
134struct amba_device s5pc100_device_pdma0 = { 76struct amba_device s5pc100_device_pdma0 = {
@@ -147,98 +89,42 @@ struct amba_device s5pc100_device_pdma0 = {
147 .periphid = 0x00041330, 89 .periphid = 0x00041330,
148}; 90};
149 91
150struct dma_pl330_peri pdma1_peri[30] = { 92u8 pdma1_peri[] = {
151 { 93 DMACH_UART0_RX,
152 .peri_id = (u8)DMACH_UART0_RX, 94 DMACH_UART0_TX,
153 .rqtype = DEVTOMEM, 95 DMACH_UART1_RX,
154 }, { 96 DMACH_UART1_TX,
155 .peri_id = (u8)DMACH_UART0_TX, 97 DMACH_UART2_RX,
156 .rqtype = MEMTODEV, 98 DMACH_UART2_TX,
157 }, { 99 DMACH_UART3_RX,
158 .peri_id = (u8)DMACH_UART1_RX, 100 DMACH_UART3_TX,
159 .rqtype = DEVTOMEM, 101 DMACH_IRDA,
160 }, { 102 DMACH_I2S0_RX,
161 .peri_id = (u8)DMACH_UART1_TX, 103 DMACH_I2S0_TX,
162 .rqtype = MEMTODEV, 104 DMACH_I2S0S_TX,
163 }, { 105 DMACH_I2S1_RX,
164 .peri_id = (u8)DMACH_UART2_RX, 106 DMACH_I2S1_TX,
165 .rqtype = DEVTOMEM, 107 DMACH_I2S2_RX,
166 }, { 108 DMACH_I2S2_TX,
167 .peri_id = (u8)DMACH_UART2_TX, 109 DMACH_SPI0_RX,
168 .rqtype = MEMTODEV, 110 DMACH_SPI0_TX,
169 }, { 111 DMACH_SPI1_RX,
170 .peri_id = (u8)DMACH_UART3_RX, 112 DMACH_SPI1_TX,
171 .rqtype = DEVTOMEM, 113 DMACH_SPI2_RX,
172 }, { 114 DMACH_SPI2_TX,
173 .peri_id = (u8)DMACH_UART3_TX, 115 DMACH_PCM0_RX,
174 .rqtype = MEMTODEV, 116 DMACH_PCM0_TX,
175 }, { 117 DMACH_PCM1_RX,
176 .peri_id = DMACH_IRDA, 118 DMACH_PCM1_TX,
177 }, { 119 DMACH_MSM_REQ0,
178 .peri_id = (u8)DMACH_I2S0_RX, 120 DMACH_MSM_REQ1,
179 .rqtype = DEVTOMEM, 121 DMACH_MSM_REQ2,
180 }, { 122 DMACH_MSM_REQ3,
181 .peri_id = (u8)DMACH_I2S0_TX,
182 .rqtype = MEMTODEV,
183 }, {
184 .peri_id = (u8)DMACH_I2S0S_TX,
185 .rqtype = MEMTODEV,
186 }, {
187 .peri_id = (u8)DMACH_I2S1_RX,
188 .rqtype = DEVTOMEM,
189 }, {
190 .peri_id = (u8)DMACH_I2S1_TX,
191 .rqtype = MEMTODEV,
192 }, {
193 .peri_id = (u8)DMACH_I2S2_RX,
194 .rqtype = DEVTOMEM,
195 }, {
196 .peri_id = (u8)DMACH_I2S2_TX,
197 .rqtype = MEMTODEV,
198 }, {
199 .peri_id = (u8)DMACH_SPI0_RX,
200 .rqtype = DEVTOMEM,
201 }, {
202 .peri_id = (u8)DMACH_SPI0_TX,
203 .rqtype = MEMTODEV,
204 }, {
205 .peri_id = (u8)DMACH_SPI1_RX,
206 .rqtype = DEVTOMEM,
207 }, {
208 .peri_id = (u8)DMACH_SPI1_TX,
209 .rqtype = MEMTODEV,
210 }, {
211 .peri_id = (u8)DMACH_SPI2_RX,
212 .rqtype = DEVTOMEM,
213 }, {
214 .peri_id = (u8)DMACH_SPI2_TX,
215 .rqtype = MEMTODEV,
216 }, {
217 .peri_id = (u8)DMACH_PCM0_RX,
218 .rqtype = DEVTOMEM,
219 }, {
220 .peri_id = (u8)DMACH_PCM1_TX,
221 .rqtype = MEMTODEV,
222 }, {
223 .peri_id = (u8)DMACH_PCM1_RX,
224 .rqtype = DEVTOMEM,
225 }, {
226 .peri_id = (u8)DMACH_PCM1_TX,
227 .rqtype = MEMTODEV,
228 }, {
229 .peri_id = (u8)DMACH_MSM_REQ0,
230 }, {
231 .peri_id = (u8)DMACH_MSM_REQ1,
232 }, {
233 .peri_id = (u8)DMACH_MSM_REQ2,
234 }, {
235 .peri_id = (u8)DMACH_MSM_REQ3,
236 },
237}; 123};
238 124
239struct dma_pl330_platdata s5pc100_pdma1_pdata = { 125struct dma_pl330_platdata s5pc100_pdma1_pdata = {
240 .nr_valid_peri = ARRAY_SIZE(pdma1_peri), 126 .nr_valid_peri = ARRAY_SIZE(pdma1_peri),
241 .peri = pdma1_peri, 127 .peri_id = pdma1_peri,
242}; 128};
243 129
244struct amba_device s5pc100_device_pdma1 = { 130struct amba_device s5pc100_device_pdma1 = {
@@ -259,7 +145,12 @@ struct amba_device s5pc100_device_pdma1 = {
259 145
260static int __init s5pc100_dma_init(void) 146static int __init s5pc100_dma_init(void)
261{ 147{
148 dma_cap_set(DMA_SLAVE, s5pc100_pdma0_pdata.cap_mask);
149 dma_cap_set(DMA_CYCLIC, s5pc100_pdma0_pdata.cap_mask);
262 amba_device_register(&s5pc100_device_pdma0, &iomem_resource); 150 amba_device_register(&s5pc100_device_pdma0, &iomem_resource);
151
152 dma_cap_set(DMA_SLAVE, s5pc100_pdma1_pdata.cap_mask);
153 dma_cap_set(DMA_CYCLIC, s5pc100_pdma1_pdata.cap_mask);
263 amba_device_register(&s5pc100_device_pdma1, &iomem_resource); 154 amba_device_register(&s5pc100_device_pdma1, &iomem_resource);
264 155
265 return 0; 156 return 0;
diff --git a/arch/arm/mach-s5pc100/include/mach/irqs.h b/arch/arm/mach-s5pc100/include/mach/irqs.h
index d2eb4757381f..2870f12c7926 100644
--- a/arch/arm/mach-s5pc100/include/mach/irqs.h
+++ b/arch/arm/mach-s5pc100/include/mach/irqs.h
@@ -97,6 +97,8 @@
97#define IRQ_SDMFIQ S5P_IRQ_VIC2(31) 97#define IRQ_SDMFIQ S5P_IRQ_VIC2(31)
98#define IRQ_VIC_END S5P_IRQ_VIC2(31) 98#define IRQ_VIC_END S5P_IRQ_VIC2(31)
99 99
100#define IRQ_TIMER_BASE (11)
101
100#define S5P_EINT_BASE1 (S5P_IRQ_VIC0(0)) 102#define S5P_EINT_BASE1 (S5P_IRQ_VIC0(0))
101#define S5P_EINT_BASE2 (IRQ_VIC_END + 1) 103#define S5P_EINT_BASE2 (IRQ_VIC_END + 1)
102 104
diff --git a/arch/arm/mach-s5pc100/include/mach/map.h b/arch/arm/mach-s5pc100/include/mach/map.h
index ccbe6b767f7d..54bc4f82e17a 100644
--- a/arch/arm/mach-s5pc100/include/mach/map.h
+++ b/arch/arm/mach-s5pc100/include/mach/map.h
@@ -100,6 +100,9 @@
100#define S3C_PA_USB_HSOTG S5PC100_PA_USB_HSOTG 100#define S3C_PA_USB_HSOTG S5PC100_PA_USB_HSOTG
101#define S3C_PA_USB_HSPHY S5PC100_PA_USB_HSPHY 101#define S3C_PA_USB_HSPHY S5PC100_PA_USB_HSPHY
102#define S3C_PA_WDT S5PC100_PA_WATCHDOG 102#define S3C_PA_WDT S5PC100_PA_WATCHDOG
103#define S3C_PA_SPI0 S5PC100_PA_SPI0
104#define S3C_PA_SPI1 S5PC100_PA_SPI1
105#define S3C_PA_SPI2 S5PC100_PA_SPI2
103 106
104#define S5P_PA_CHIPID S5PC100_PA_CHIPID 107#define S5P_PA_CHIPID S5PC100_PA_CHIPID
105#define S5P_PA_FIMC0 S5PC100_PA_FIMC0 108#define S5P_PA_FIMC0 S5PC100_PA_FIMC0
diff --git a/arch/arm/mach-s5pc100/setup-sdhci.c b/arch/arm/mach-s5pc100/setup-sdhci.c
deleted file mode 100644
index 6418c6e8a7b7..000000000000
--- a/arch/arm/mach-s5pc100/setup-sdhci.c
+++ /dev/null
@@ -1,23 +0,0 @@
1/* linux/arch/arm/mach-s5pc100/setup-sdhci.c
2 *
3 * Copyright 2008 Samsung Electronics
4 *
5 * S5PC100 - Helper functions for settign up SDHCI device(s) (HSMMC)
6 *
7 * Based on mach-s3c6410/setup-sdhci.c
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14#include <linux/types.h>
15
16/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */
17
18char *s5pc100_hsmmc_clksrcs[4] = {
19 [0] = "hsmmc", /* HCLK */
20 /* [1] = "hsmmc", - duplicate HCLK entry */
21 [2] = "sclk_mmc", /* mmc_bus */
22 /* [3] = "48m", - note not successfully used yet */
23};
diff --git a/arch/arm/mach-s5pc100/setup-spi.c b/arch/arm/mach-s5pc100/setup-spi.c
new file mode 100644
index 000000000000..431a6f747caa
--- /dev/null
+++ b/arch/arm/mach-s5pc100/setup-spi.c
@@ -0,0 +1,65 @@
1/* linux/arch/arm/mach-s5pc100/setup-spi.c
2 *
3 * Copyright (C) 2011 Samsung Electronics Ltd.
4 * http://www.samsung.com/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/gpio.h>
12#include <linux/platform_device.h>
13
14#include <plat/gpio-cfg.h>
15#include <plat/s3c64xx-spi.h>
16
17#ifdef CONFIG_S3C64XX_DEV_SPI0
18struct s3c64xx_spi_info s3c64xx_spi0_pdata __initdata = {
19 .fifo_lvl_mask = 0x7f,
20 .rx_lvl_offset = 13,
21 .high_speed = 1,
22 .tx_st_done = 21,
23};
24
25int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
26{
27 s3c_gpio_cfgall_range(S5PC100_GPB(0), 3,
28 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
29 return 0;
30}
31#endif
32
33#ifdef CONFIG_S3C64XX_DEV_SPI1
34struct s3c64xx_spi_info s3c64xx_spi1_pdata __initdata = {
35 .fifo_lvl_mask = 0x7f,
36 .rx_lvl_offset = 13,
37 .high_speed = 1,
38 .tx_st_done = 21,
39};
40
41int s3c64xx_spi1_cfg_gpio(struct platform_device *dev)
42{
43 s3c_gpio_cfgall_range(S5PC100_GPB(4), 3,
44 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
45 return 0;
46}
47#endif
48
49#ifdef CONFIG_S3C64XX_DEV_SPI2
50struct s3c64xx_spi_info s3c64xx_spi2_pdata __initdata = {
51 .fifo_lvl_mask = 0x7f,
52 .rx_lvl_offset = 13,
53 .high_speed = 1,
54 .tx_st_done = 21,
55};
56
57int s3c64xx_spi2_cfg_gpio(struct platform_device *dev)
58{
59 s3c_gpio_cfgpin(S5PC100_GPG3(0), S3C_GPIO_SFN(3));
60 s3c_gpio_setpull(S5PC100_GPG3(0), S3C_GPIO_PULL_UP);
61 s3c_gpio_cfgall_range(S5PC100_GPB(2), 2,
62 S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
63 return 0;
64}
65#endif
diff --git a/arch/arm/mach-s5pv210/Kconfig b/arch/arm/mach-s5pv210/Kconfig
index 646057ab2e4c..2cdc42e838b8 100644
--- a/arch/arm/mach-s5pv210/Kconfig
+++ b/arch/arm/mach-s5pv210/Kconfig
@@ -60,6 +60,11 @@ config S5PV210_SETUP_FIMC
60 help 60 help
61 Common setup code for the camera interfaces. 61 Common setup code for the camera interfaces.
62 62
63config S5PV210_SETUP_SPI
64 bool
65 help
66 Common setup code for SPI GPIO configurations.
67
63menu "S5PC110 Machines" 68menu "S5PC110 Machines"
64 69
65config MACH_AQUILA 70config MACH_AQUILA
diff --git a/arch/arm/mach-s5pv210/Makefile b/arch/arm/mach-s5pv210/Makefile
index 009fbe53df96..471df5d2d25c 100644
--- a/arch/arm/mach-s5pv210/Makefile
+++ b/arch/arm/mach-s5pv210/Makefile
@@ -27,7 +27,6 @@ obj-$(CONFIG_MACH_TORBRECK) += mach-torbreck.o
27# device support 27# device support
28 28
29obj-y += dev-audio.o 29obj-y += dev-audio.o
30obj-$(CONFIG_S3C64XX_DEV_SPI) += dev-spi.o
31 30
32obj-$(CONFIG_S5PV210_SETUP_FB_24BPP) += setup-fb-24bpp.o 31obj-$(CONFIG_S5PV210_SETUP_FB_24BPP) += setup-fb-24bpp.o
33obj-$(CONFIG_S5PV210_SETUP_FIMC) += setup-fimc.o 32obj-$(CONFIG_S5PV210_SETUP_FIMC) += setup-fimc.o
@@ -35,5 +34,5 @@ obj-$(CONFIG_S5PV210_SETUP_I2C1) += setup-i2c1.o
35obj-$(CONFIG_S5PV210_SETUP_I2C2) += setup-i2c2.o 34obj-$(CONFIG_S5PV210_SETUP_I2C2) += setup-i2c2.o
36obj-$(CONFIG_S5PV210_SETUP_IDE) += setup-ide.o 35obj-$(CONFIG_S5PV210_SETUP_IDE) += setup-ide.o
37obj-$(CONFIG_S5PV210_SETUP_KEYPAD) += setup-keypad.o 36obj-$(CONFIG_S5PV210_SETUP_KEYPAD) += setup-keypad.o
38obj-$(CONFIG_S5PV210_SETUP_SDHCI) += setup-sdhci.o
39obj-$(CONFIG_S5PV210_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o 37obj-$(CONFIG_S5PV210_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o
38obj-$(CONFIG_S5PV210_SETUP_SPI) += setup-spi.o
diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c
index 4c5ac7a69e9e..cead51321b29 100644
--- a/arch/arm/mach-s5pv210/clock.c
+++ b/arch/arm/mach-s5pv210/clock.c
@@ -399,30 +399,6 @@ static struct clk init_clocks_off[] = {
399 .enable = s5pv210_clk_ip1_ctrl, 399 .enable = s5pv210_clk_ip1_ctrl,
400 .ctrlbit = (1<<25), 400 .ctrlbit = (1<<25),
401 }, { 401 }, {
402 .name = "hsmmc",
403 .devname = "s3c-sdhci.0",
404 .parent = &clk_hclk_psys.clk,
405 .enable = s5pv210_clk_ip2_ctrl,
406 .ctrlbit = (1<<16),
407 }, {
408 .name = "hsmmc",
409 .devname = "s3c-sdhci.1",
410 .parent = &clk_hclk_psys.clk,
411 .enable = s5pv210_clk_ip2_ctrl,
412 .ctrlbit = (1<<17),
413 }, {
414 .name = "hsmmc",
415 .devname = "s3c-sdhci.2",
416 .parent = &clk_hclk_psys.clk,
417 .enable = s5pv210_clk_ip2_ctrl,
418 .ctrlbit = (1<<18),
419 }, {
420 .name = "hsmmc",
421 .devname = "s3c-sdhci.3",
422 .parent = &clk_hclk_psys.clk,
423 .enable = s5pv210_clk_ip2_ctrl,
424 .ctrlbit = (1<<19),
425 }, {
426 .name = "systimer", 402 .name = "systimer",
427 .parent = &clk_pclk_psys.clk, 403 .parent = &clk_pclk_psys.clk,
428 .enable = s5pv210_clk_ip3_ctrl, 404 .enable = s5pv210_clk_ip3_ctrl,
@@ -559,6 +535,38 @@ static struct clk init_clocks[] = {
559 }, 535 },
560}; 536};
561 537
538static struct clk clk_hsmmc0 = {
539 .name = "hsmmc",
540 .devname = "s3c-sdhci.0",
541 .parent = &clk_hclk_psys.clk,
542 .enable = s5pv210_clk_ip2_ctrl,
543 .ctrlbit = (1<<16),
544};
545
546static struct clk clk_hsmmc1 = {
547 .name = "hsmmc",
548 .devname = "s3c-sdhci.1",
549 .parent = &clk_hclk_psys.clk,
550 .enable = s5pv210_clk_ip2_ctrl,
551 .ctrlbit = (1<<17),
552};
553
554static struct clk clk_hsmmc2 = {
555 .name = "hsmmc",
556 .devname = "s3c-sdhci.2",
557 .parent = &clk_hclk_psys.clk,
558 .enable = s5pv210_clk_ip2_ctrl,
559 .ctrlbit = (1<<18),
560};
561
562static struct clk clk_hsmmc3 = {
563 .name = "hsmmc",
564 .devname = "s3c-sdhci.3",
565 .parent = &clk_hclk_psys.clk,
566 .enable = s5pv210_clk_ip2_ctrl,
567 .ctrlbit = (1<<19),
568};
569
562static struct clk *clkset_uart_list[] = { 570static struct clk *clkset_uart_list[] = {
563 [6] = &clk_mout_mpll.clk, 571 [6] = &clk_mout_mpll.clk,
564 [7] = &clk_mout_epll.clk, 572 [7] = &clk_mout_epll.clk,
@@ -809,46 +817,6 @@ static struct clksrc_clk clksrcs[] = {
809 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 12, .size = 3 }, 817 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 12, .size = 3 },
810 }, { 818 }, {
811 .clk = { 819 .clk = {
812 .name = "uclk1",
813 .devname = "s5pv210-uart.0",
814 .enable = s5pv210_clk_mask0_ctrl,
815 .ctrlbit = (1 << 12),
816 },
817 .sources = &clkset_uart,
818 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 16, .size = 4 },
819 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 16, .size = 4 },
820 }, {
821 .clk = {
822 .name = "uclk1",
823 .devname = "s5pv210-uart.1",
824 .enable = s5pv210_clk_mask0_ctrl,
825 .ctrlbit = (1 << 13),
826 },
827 .sources = &clkset_uart,
828 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 20, .size = 4 },
829 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 20, .size = 4 },
830 }, {
831 .clk = {
832 .name = "uclk1",
833 .devname = "s5pv210-uart.2",
834 .enable = s5pv210_clk_mask0_ctrl,
835 .ctrlbit = (1 << 14),
836 },
837 .sources = &clkset_uart,
838 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 24, .size = 4 },
839 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 24, .size = 4 },
840 }, {
841 .clk = {
842 .name = "uclk1",
843 .devname = "s5pv210-uart.3",
844 .enable = s5pv210_clk_mask0_ctrl,
845 .ctrlbit = (1 << 15),
846 },
847 .sources = &clkset_uart,
848 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 28, .size = 4 },
849 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 28, .size = 4 },
850 }, {
851 .clk = {
852 .name = "sclk_fimc", 820 .name = "sclk_fimc",
853 .devname = "s5pv210-fimc.0", 821 .devname = "s5pv210-fimc.0",
854 .enable = s5pv210_clk_mask1_ctrl, 822 .enable = s5pv210_clk_mask1_ctrl,
@@ -906,46 +874,6 @@ static struct clksrc_clk clksrcs[] = {
906 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 20, .size = 4 }, 874 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 20, .size = 4 },
907 }, { 875 }, {
908 .clk = { 876 .clk = {
909 .name = "sclk_mmc",
910 .devname = "s3c-sdhci.0",
911 .enable = s5pv210_clk_mask0_ctrl,
912 .ctrlbit = (1 << 8),
913 },
914 .sources = &clkset_group2,
915 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 0, .size = 4 },
916 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 0, .size = 4 },
917 }, {
918 .clk = {
919 .name = "sclk_mmc",
920 .devname = "s3c-sdhci.1",
921 .enable = s5pv210_clk_mask0_ctrl,
922 .ctrlbit = (1 << 9),
923 },
924 .sources = &clkset_group2,
925 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 4, .size = 4 },
926 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 4, .size = 4 },
927 }, {
928 .clk = {
929 .name = "sclk_mmc",
930 .devname = "s3c-sdhci.2",
931 .enable = s5pv210_clk_mask0_ctrl,
932 .ctrlbit = (1 << 10),
933 },
934 .sources = &clkset_group2,
935 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 8, .size = 4 },
936 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 8, .size = 4 },
937 }, {
938 .clk = {
939 .name = "sclk_mmc",
940 .devname = "s3c-sdhci.3",
941 .enable = s5pv210_clk_mask0_ctrl,
942 .ctrlbit = (1 << 11),
943 },
944 .sources = &clkset_group2,
945 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 12, .size = 4 },
946 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 12, .size = 4 },
947 }, {
948 .clk = {
949 .name = "sclk_mfc", 877 .name = "sclk_mfc",
950 .devname = "s5p-mfc", 878 .devname = "s5p-mfc",
951 .enable = s5pv210_clk_ip0_ctrl, 879 .enable = s5pv210_clk_ip0_ctrl,
@@ -983,26 +911,6 @@ static struct clksrc_clk clksrcs[] = {
983 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 28, .size = 4 }, 911 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 28, .size = 4 },
984 }, { 912 }, {
985 .clk = { 913 .clk = {
986 .name = "sclk_spi",
987 .devname = "s3c64xx-spi.0",
988 .enable = s5pv210_clk_mask0_ctrl,
989 .ctrlbit = (1 << 16),
990 },
991 .sources = &clkset_group2,
992 .reg_src = { .reg = S5P_CLK_SRC5, .shift = 0, .size = 4 },
993 .reg_div = { .reg = S5P_CLK_DIV5, .shift = 0, .size = 4 },
994 }, {
995 .clk = {
996 .name = "sclk_spi",
997 .devname = "s3c64xx-spi.1",
998 .enable = s5pv210_clk_mask0_ctrl,
999 .ctrlbit = (1 << 17),
1000 },
1001 .sources = &clkset_group2,
1002 .reg_src = { .reg = S5P_CLK_SRC5, .shift = 4, .size = 4 },
1003 .reg_div = { .reg = S5P_CLK_DIV5, .shift = 4, .size = 4 },
1004 }, {
1005 .clk = {
1006 .name = "sclk_pwi", 914 .name = "sclk_pwi",
1007 .enable = s5pv210_clk_mask0_ctrl, 915 .enable = s5pv210_clk_mask0_ctrl,
1008 .ctrlbit = (1 << 29), 916 .ctrlbit = (1 << 29),
@@ -1022,6 +930,147 @@ static struct clksrc_clk clksrcs[] = {
1022 }, 930 },
1023}; 931};
1024 932
933static struct clksrc_clk clk_sclk_uart0 = {
934 .clk = {
935 .name = "uclk1",
936 .devname = "s5pv210-uart.0",
937 .enable = s5pv210_clk_mask0_ctrl,
938 .ctrlbit = (1 << 12),
939 },
940 .sources = &clkset_uart,
941 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 16, .size = 4 },
942 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 16, .size = 4 },
943};
944
945static struct clksrc_clk clk_sclk_uart1 = {
946 .clk = {
947 .name = "uclk1",
948 .devname = "s5pv210-uart.1",
949 .enable = s5pv210_clk_mask0_ctrl,
950 .ctrlbit = (1 << 13),
951 },
952 .sources = &clkset_uart,
953 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 20, .size = 4 },
954 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 20, .size = 4 },
955};
956
957static struct clksrc_clk clk_sclk_uart2 = {
958 .clk = {
959 .name = "uclk1",
960 .devname = "s5pv210-uart.2",
961 .enable = s5pv210_clk_mask0_ctrl,
962 .ctrlbit = (1 << 14),
963 },
964 .sources = &clkset_uart,
965 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 24, .size = 4 },
966 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 24, .size = 4 },
967};
968
969static struct clksrc_clk clk_sclk_uart3 = {
970 .clk = {
971 .name = "uclk1",
972 .devname = "s5pv210-uart.3",
973 .enable = s5pv210_clk_mask0_ctrl,
974 .ctrlbit = (1 << 15),
975 },
976 .sources = &clkset_uart,
977 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 28, .size = 4 },
978 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 28, .size = 4 },
979};
980
981static struct clksrc_clk clk_sclk_mmc0 = {
982 .clk = {
983 .name = "sclk_mmc",
984 .devname = "s3c-sdhci.0",
985 .enable = s5pv210_clk_mask0_ctrl,
986 .ctrlbit = (1 << 8),
987 },
988 .sources = &clkset_group2,
989 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 0, .size = 4 },
990 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 0, .size = 4 },
991};
992
993static struct clksrc_clk clk_sclk_mmc1 = {
994 .clk = {
995 .name = "sclk_mmc",
996 .devname = "s3c-sdhci.1",
997 .enable = s5pv210_clk_mask0_ctrl,
998 .ctrlbit = (1 << 9),
999 },
1000 .sources = &clkset_group2,
1001 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 4, .size = 4 },
1002 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 4, .size = 4 },
1003};
1004
1005static struct clksrc_clk clk_sclk_mmc2 = {
1006 .clk = {
1007 .name = "sclk_mmc",
1008 .devname = "s3c-sdhci.2",
1009 .enable = s5pv210_clk_mask0_ctrl,
1010 .ctrlbit = (1 << 10),
1011 },
1012 .sources = &clkset_group2,
1013 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 8, .size = 4 },
1014 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 8, .size = 4 },
1015};
1016
1017static struct clksrc_clk clk_sclk_mmc3 = {
1018 .clk = {
1019 .name = "sclk_mmc",
1020 .devname = "s3c-sdhci.3",
1021 .enable = s5pv210_clk_mask0_ctrl,
1022 .ctrlbit = (1 << 11),
1023 },
1024 .sources = &clkset_group2,
1025 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 12, .size = 4 },
1026 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 12, .size = 4 },
1027};
1028
1029static struct clksrc_clk clk_sclk_spi0 = {
1030 .clk = {
1031 .name = "sclk_spi",
1032 .devname = "s3c64xx-spi.0",
1033 .enable = s5pv210_clk_mask0_ctrl,
1034 .ctrlbit = (1 << 16),
1035 },
1036 .sources = &clkset_group2,
1037 .reg_src = { .reg = S5P_CLK_SRC5, .shift = 0, .size = 4 },
1038 .reg_div = { .reg = S5P_CLK_DIV5, .shift = 0, .size = 4 },
1039 };
1040
1041static struct clksrc_clk clk_sclk_spi1 = {
1042 .clk = {
1043 .name = "sclk_spi",
1044 .devname = "s3c64xx-spi.1",
1045 .enable = s5pv210_clk_mask0_ctrl,
1046 .ctrlbit = (1 << 17),
1047 },
1048 .sources = &clkset_group2,
1049 .reg_src = { .reg = S5P_CLK_SRC5, .shift = 4, .size = 4 },
1050 .reg_div = { .reg = S5P_CLK_DIV5, .shift = 4, .size = 4 },
1051 };
1052
1053
1054static struct clksrc_clk *clksrc_cdev[] = {
1055 &clk_sclk_uart0,
1056 &clk_sclk_uart1,
1057 &clk_sclk_uart2,
1058 &clk_sclk_uart3,
1059 &clk_sclk_mmc0,
1060 &clk_sclk_mmc1,
1061 &clk_sclk_mmc2,
1062 &clk_sclk_mmc3,
1063 &clk_sclk_spi0,
1064 &clk_sclk_spi1,
1065};
1066
1067static struct clk *clk_cdev[] = {
1068 &clk_hsmmc0,
1069 &clk_hsmmc1,
1070 &clk_hsmmc2,
1071 &clk_hsmmc3,
1072};
1073
1025/* Clock initialisation code */ 1074/* Clock initialisation code */
1026static struct clksrc_clk *sysclks[] = { 1075static struct clksrc_clk *sysclks[] = {
1027 &clk_mout_apll, 1076 &clk_mout_apll,
@@ -1261,6 +1310,25 @@ static struct clk *clks[] __initdata = {
1261 &clk_pcmcdclk2, 1310 &clk_pcmcdclk2,
1262}; 1311};
1263 1312
1313static struct clk_lookup s5pv210_clk_lookup[] = {
1314 CLKDEV_INIT(NULL, "clk_uart_baud0", &clk_p),
1315 CLKDEV_INIT("s5pv210-uart.0", "clk_uart_baud1", &clk_sclk_uart0.clk),
1316 CLKDEV_INIT("s5pv210-uart.1", "clk_uart_baud1", &clk_sclk_uart1.clk),
1317 CLKDEV_INIT("s5pv210-uart.2", "clk_uart_baud1", &clk_sclk_uart2.clk),
1318 CLKDEV_INIT("s5pv210-uart.3", "clk_uart_baud1", &clk_sclk_uart3.clk),
1319 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &clk_hsmmc0),
1320 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &clk_hsmmc1),
1321 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.0", &clk_hsmmc2),
1322 CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.0", &clk_hsmmc3),
1323 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
1324 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
1325 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
1326 CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &clk_sclk_mmc3.clk),
1327 CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
1328 CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
1329 CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
1330};
1331
1264void __init s5pv210_register_clocks(void) 1332void __init s5pv210_register_clocks(void)
1265{ 1333{
1266 int ptr; 1334 int ptr;
@@ -1273,11 +1341,19 @@ void __init s5pv210_register_clocks(void)
1273 for (ptr = 0; ptr < ARRAY_SIZE(sclk_tv); ptr++) 1341 for (ptr = 0; ptr < ARRAY_SIZE(sclk_tv); ptr++)
1274 s3c_register_clksrc(sclk_tv[ptr], 1); 1342 s3c_register_clksrc(sclk_tv[ptr], 1);
1275 1343
1344 for (ptr = 0; ptr < ARRAY_SIZE(clksrc_cdev); ptr++)
1345 s3c_register_clksrc(clksrc_cdev[ptr], 1);
1346
1276 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs)); 1347 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
1277 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks)); 1348 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
1278 1349
1279 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); 1350 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
1280 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); 1351 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
1352 clkdev_add_table(s5pv210_clk_lookup, ARRAY_SIZE(s5pv210_clk_lookup));
1353
1354 s3c24xx_register_clocks(clk_cdev, ARRAY_SIZE(clk_cdev));
1355 for (ptr = 0; ptr < ARRAY_SIZE(clk_cdev); ptr++)
1356 s3c_disable_clocks(clk_cdev[ptr], 1);
1281 1357
1282 s3c24xx_register_clock(&dummy_apb_pclk); 1358 s3c24xx_register_clock(&dummy_apb_pclk);
1283 s3c_pwmclk_init(); 1359 s3c_pwmclk_init();
diff --git a/arch/arm/mach-s5pv210/dev-spi.c b/arch/arm/mach-s5pv210/dev-spi.c
deleted file mode 100644
index eaf9a7bff7a0..000000000000
--- a/arch/arm/mach-s5pv210/dev-spi.c
+++ /dev/null
@@ -1,175 +0,0 @@
1/* linux/arch/arm/mach-s5pv210/dev-spi.c
2 *
3 * Copyright (C) 2010 Samsung Electronics Co. Ltd.
4 * Jaswinder Singh <jassi.brar@samsung.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/platform_device.h>
12#include <linux/dma-mapping.h>
13#include <linux/gpio.h>
14
15#include <mach/dma.h>
16#include <mach/map.h>
17#include <mach/irqs.h>
18#include <mach/spi-clocks.h>
19
20#include <plat/s3c64xx-spi.h>
21#include <plat/gpio-cfg.h>
22
23static char *spi_src_clks[] = {
24 [S5PV210_SPI_SRCCLK_PCLK] = "pclk",
25 [S5PV210_SPI_SRCCLK_SCLK] = "sclk_spi",
26};
27
28/* SPI Controller platform_devices */
29
30/* Since we emulate multi-cs capability, we do not touch the CS.
31 * The emulated CS is toggled by board specific mechanism, as it can
32 * be either some immediate GPIO or some signal out of some other
33 * chip in between ... or some yet another way.
34 * We simply do not assume anything about CS.
35 */
36static int s5pv210_spi_cfg_gpio(struct platform_device *pdev)
37{
38 unsigned int base;
39
40 switch (pdev->id) {
41 case 0:
42 base = S5PV210_GPB(0);
43 break;
44
45 case 1:
46 base = S5PV210_GPB(4);
47 break;
48
49 default:
50 dev_err(&pdev->dev, "Invalid SPI Controller number!");
51 return -EINVAL;
52 }
53
54 s3c_gpio_cfgall_range(base, 3,
55 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
56
57 return 0;
58}
59
60static struct resource s5pv210_spi0_resource[] = {
61 [0] = {
62 .start = S5PV210_PA_SPI0,
63 .end = S5PV210_PA_SPI0 + 0x100 - 1,
64 .flags = IORESOURCE_MEM,
65 },
66 [1] = {
67 .start = DMACH_SPI0_TX,
68 .end = DMACH_SPI0_TX,
69 .flags = IORESOURCE_DMA,
70 },
71 [2] = {
72 .start = DMACH_SPI0_RX,
73 .end = DMACH_SPI0_RX,
74 .flags = IORESOURCE_DMA,
75 },
76 [3] = {
77 .start = IRQ_SPI0,
78 .end = IRQ_SPI0,
79 .flags = IORESOURCE_IRQ,
80 },
81};
82
83static struct s3c64xx_spi_info s5pv210_spi0_pdata = {
84 .cfg_gpio = s5pv210_spi_cfg_gpio,
85 .fifo_lvl_mask = 0x1ff,
86 .rx_lvl_offset = 15,
87 .high_speed = 1,
88 .tx_st_done = 25,
89};
90
91static u64 spi_dmamask = DMA_BIT_MASK(32);
92
93struct platform_device s5pv210_device_spi0 = {
94 .name = "s3c64xx-spi",
95 .id = 0,
96 .num_resources = ARRAY_SIZE(s5pv210_spi0_resource),
97 .resource = s5pv210_spi0_resource,
98 .dev = {
99 .dma_mask = &spi_dmamask,
100 .coherent_dma_mask = DMA_BIT_MASK(32),
101 .platform_data = &s5pv210_spi0_pdata,
102 },
103};
104
105static struct resource s5pv210_spi1_resource[] = {
106 [0] = {
107 .start = S5PV210_PA_SPI1,
108 .end = S5PV210_PA_SPI1 + 0x100 - 1,
109 .flags = IORESOURCE_MEM,
110 },
111 [1] = {
112 .start = DMACH_SPI1_TX,
113 .end = DMACH_SPI1_TX,
114 .flags = IORESOURCE_DMA,
115 },
116 [2] = {
117 .start = DMACH_SPI1_RX,
118 .end = DMACH_SPI1_RX,
119 .flags = IORESOURCE_DMA,
120 },
121 [3] = {
122 .start = IRQ_SPI1,
123 .end = IRQ_SPI1,
124 .flags = IORESOURCE_IRQ,
125 },
126};
127
128static struct s3c64xx_spi_info s5pv210_spi1_pdata = {
129 .cfg_gpio = s5pv210_spi_cfg_gpio,
130 .fifo_lvl_mask = 0x7f,
131 .rx_lvl_offset = 15,
132 .high_speed = 1,
133 .tx_st_done = 25,
134};
135
136struct platform_device s5pv210_device_spi1 = {
137 .name = "s3c64xx-spi",
138 .id = 1,
139 .num_resources = ARRAY_SIZE(s5pv210_spi1_resource),
140 .resource = s5pv210_spi1_resource,
141 .dev = {
142 .dma_mask = &spi_dmamask,
143 .coherent_dma_mask = DMA_BIT_MASK(32),
144 .platform_data = &s5pv210_spi1_pdata,
145 },
146};
147
148void __init s5pv210_spi_set_info(int cntrlr, int src_clk_nr, int num_cs)
149{
150 struct s3c64xx_spi_info *pd;
151
152 /* Reject invalid configuration */
153 if (!num_cs || src_clk_nr < 0
154 || src_clk_nr > S5PV210_SPI_SRCCLK_SCLK) {
155 printk(KERN_ERR "%s: Invalid SPI configuration\n", __func__);
156 return;
157 }
158
159 switch (cntrlr) {
160 case 0:
161 pd = &s5pv210_spi0_pdata;
162 break;
163 case 1:
164 pd = &s5pv210_spi1_pdata;
165 break;
166 default:
167 printk(KERN_ERR "%s: Invalid SPI controller(%d)\n",
168 __func__, cntrlr);
169 return;
170 }
171
172 pd->num_cs = num_cs;
173 pd->src_clk_nr = src_clk_nr;
174 pd->src_clk_name = spi_src_clks[src_clk_nr];
175}
diff --git a/arch/arm/mach-s5pv210/dma.c b/arch/arm/mach-s5pv210/dma.c
index 86b749c18b77..a6113e0267f2 100644
--- a/arch/arm/mach-s5pv210/dma.c
+++ b/arch/arm/mach-s5pv210/dma.c
@@ -35,90 +35,40 @@
35 35
36static u64 dma_dmamask = DMA_BIT_MASK(32); 36static u64 dma_dmamask = DMA_BIT_MASK(32);
37 37
38struct dma_pl330_peri pdma0_peri[28] = { 38u8 pdma0_peri[] = {
39 { 39 DMACH_UART0_RX,
40 .peri_id = (u8)DMACH_UART0_RX, 40 DMACH_UART0_TX,
41 .rqtype = DEVTOMEM, 41 DMACH_UART1_RX,
42 }, { 42 DMACH_UART1_TX,
43 .peri_id = (u8)DMACH_UART0_TX, 43 DMACH_UART2_RX,
44 .rqtype = MEMTODEV, 44 DMACH_UART2_TX,
45 }, { 45 DMACH_UART3_RX,
46 .peri_id = (u8)DMACH_UART1_RX, 46 DMACH_UART3_TX,
47 .rqtype = DEVTOMEM, 47 DMACH_MAX,
48 }, { 48 DMACH_I2S0_RX,
49 .peri_id = (u8)DMACH_UART1_TX, 49 DMACH_I2S0_TX,
50 .rqtype = MEMTODEV, 50 DMACH_I2S0S_TX,
51 }, { 51 DMACH_I2S1_RX,
52 .peri_id = (u8)DMACH_UART2_RX, 52 DMACH_I2S1_TX,
53 .rqtype = DEVTOMEM, 53 DMACH_MAX,
54 }, { 54 DMACH_MAX,
55 .peri_id = (u8)DMACH_UART2_TX, 55 DMACH_SPI0_RX,
56 .rqtype = MEMTODEV, 56 DMACH_SPI0_TX,
57 }, { 57 DMACH_SPI1_RX,
58 .peri_id = (u8)DMACH_UART3_RX, 58 DMACH_SPI1_TX,
59 .rqtype = DEVTOMEM, 59 DMACH_MAX,
60 }, { 60 DMACH_MAX,
61 .peri_id = (u8)DMACH_UART3_TX, 61 DMACH_AC97_MICIN,
62 .rqtype = MEMTODEV, 62 DMACH_AC97_PCMIN,
63 }, { 63 DMACH_AC97_PCMOUT,
64 .peri_id = DMACH_MAX, 64 DMACH_MAX,
65 }, { 65 DMACH_PWM,
66 .peri_id = (u8)DMACH_I2S0_RX, 66 DMACH_SPDIF,
67 .rqtype = DEVTOMEM,
68 }, {
69 .peri_id = (u8)DMACH_I2S0_TX,
70 .rqtype = MEMTODEV,
71 }, {
72 .peri_id = (u8)DMACH_I2S0S_TX,
73 .rqtype = MEMTODEV,
74 }, {
75 .peri_id = (u8)DMACH_I2S1_RX,
76 .rqtype = DEVTOMEM,
77 }, {
78 .peri_id = (u8)DMACH_I2S1_TX,
79 .rqtype = MEMTODEV,
80 }, {
81 .peri_id = (u8)DMACH_MAX,
82 }, {
83 .peri_id = (u8)DMACH_MAX,
84 }, {
85 .peri_id = (u8)DMACH_SPI0_RX,
86 .rqtype = DEVTOMEM,
87 }, {
88 .peri_id = (u8)DMACH_SPI0_TX,
89 .rqtype = MEMTODEV,
90 }, {
91 .peri_id = (u8)DMACH_SPI1_RX,
92 .rqtype = DEVTOMEM,
93 }, {
94 .peri_id = (u8)DMACH_SPI1_TX,
95 .rqtype = MEMTODEV,
96 }, {
97 .peri_id = (u8)DMACH_MAX,
98 }, {
99 .peri_id = (u8)DMACH_MAX,
100 }, {
101 .peri_id = (u8)DMACH_AC97_MICIN,
102 .rqtype = DEVTOMEM,
103 }, {
104 .peri_id = (u8)DMACH_AC97_PCMIN,
105 .rqtype = DEVTOMEM,
106 }, {
107 .peri_id = (u8)DMACH_AC97_PCMOUT,
108 .rqtype = MEMTODEV,
109 }, {
110 .peri_id = (u8)DMACH_MAX,
111 }, {
112 .peri_id = (u8)DMACH_PWM,
113 }, {
114 .peri_id = (u8)DMACH_SPDIF,
115 .rqtype = MEMTODEV,
116 },
117}; 67};
118 68
119struct dma_pl330_platdata s5pv210_pdma0_pdata = { 69struct dma_pl330_platdata s5pv210_pdma0_pdata = {
120 .nr_valid_peri = ARRAY_SIZE(pdma0_peri), 70 .nr_valid_peri = ARRAY_SIZE(pdma0_peri),
121 .peri = pdma0_peri, 71 .peri_id = pdma0_peri,
122}; 72};
123 73
124struct amba_device s5pv210_device_pdma0 = { 74struct amba_device s5pv210_device_pdma0 = {
@@ -137,102 +87,44 @@ struct amba_device s5pv210_device_pdma0 = {
137 .periphid = 0x00041330, 87 .periphid = 0x00041330,
138}; 88};
139 89
140struct dma_pl330_peri pdma1_peri[32] = { 90u8 pdma1_peri[] = {
141 { 91 DMACH_UART0_RX,
142 .peri_id = (u8)DMACH_UART0_RX, 92 DMACH_UART0_TX,
143 .rqtype = DEVTOMEM, 93 DMACH_UART1_RX,
144 }, { 94 DMACH_UART1_TX,
145 .peri_id = (u8)DMACH_UART0_TX, 95 DMACH_UART2_RX,
146 .rqtype = MEMTODEV, 96 DMACH_UART2_TX,
147 }, { 97 DMACH_UART3_RX,
148 .peri_id = (u8)DMACH_UART1_RX, 98 DMACH_UART3_TX,
149 .rqtype = DEVTOMEM, 99 DMACH_MAX,
150 }, { 100 DMACH_I2S0_RX,
151 .peri_id = (u8)DMACH_UART1_TX, 101 DMACH_I2S0_TX,
152 .rqtype = MEMTODEV, 102 DMACH_I2S0S_TX,
153 }, { 103 DMACH_I2S1_RX,
154 .peri_id = (u8)DMACH_UART2_RX, 104 DMACH_I2S1_TX,
155 .rqtype = DEVTOMEM, 105 DMACH_I2S2_RX,
156 }, { 106 DMACH_I2S2_TX,
157 .peri_id = (u8)DMACH_UART2_TX, 107 DMACH_SPI0_RX,
158 .rqtype = MEMTODEV, 108 DMACH_SPI0_TX,
159 }, { 109 DMACH_SPI1_RX,
160 .peri_id = (u8)DMACH_UART3_RX, 110 DMACH_SPI1_TX,
161 .rqtype = DEVTOMEM, 111 DMACH_MAX,
162 }, { 112 DMACH_MAX,
163 .peri_id = (u8)DMACH_UART3_TX, 113 DMACH_PCM0_RX,
164 .rqtype = MEMTODEV, 114 DMACH_PCM0_TX,
165 }, { 115 DMACH_PCM1_RX,
166 .peri_id = DMACH_MAX, 116 DMACH_PCM1_TX,
167 }, { 117 DMACH_MSM_REQ0,
168 .peri_id = (u8)DMACH_I2S0_RX, 118 DMACH_MSM_REQ1,
169 .rqtype = DEVTOMEM, 119 DMACH_MSM_REQ2,
170 }, { 120 DMACH_MSM_REQ3,
171 .peri_id = (u8)DMACH_I2S0_TX, 121 DMACH_PCM2_RX,
172 .rqtype = MEMTODEV, 122 DMACH_PCM2_TX,
173 }, {
174 .peri_id = (u8)DMACH_I2S0S_TX,
175 .rqtype = MEMTODEV,
176 }, {
177 .peri_id = (u8)DMACH_I2S1_RX,
178 .rqtype = DEVTOMEM,
179 }, {
180 .peri_id = (u8)DMACH_I2S1_TX,
181 .rqtype = MEMTODEV,
182 }, {
183 .peri_id = (u8)DMACH_I2S2_RX,
184 .rqtype = DEVTOMEM,
185 }, {
186 .peri_id = (u8)DMACH_I2S2_TX,
187 .rqtype = MEMTODEV,
188 }, {
189 .peri_id = (u8)DMACH_SPI0_RX,
190 .rqtype = DEVTOMEM,
191 }, {
192 .peri_id = (u8)DMACH_SPI0_TX,
193 .rqtype = MEMTODEV,
194 }, {
195 .peri_id = (u8)DMACH_SPI1_RX,
196 .rqtype = DEVTOMEM,
197 }, {
198 .peri_id = (u8)DMACH_SPI1_TX,
199 .rqtype = MEMTODEV,
200 }, {
201 .peri_id = (u8)DMACH_MAX,
202 }, {
203 .peri_id = (u8)DMACH_MAX,
204 }, {
205 .peri_id = (u8)DMACH_PCM0_RX,
206 .rqtype = DEVTOMEM,
207 }, {
208 .peri_id = (u8)DMACH_PCM0_TX,
209 .rqtype = MEMTODEV,
210 }, {
211 .peri_id = (u8)DMACH_PCM1_RX,
212 .rqtype = DEVTOMEM,
213 }, {
214 .peri_id = (u8)DMACH_PCM1_TX,
215 .rqtype = MEMTODEV,
216 }, {
217 .peri_id = (u8)DMACH_MSM_REQ0,
218 }, {
219 .peri_id = (u8)DMACH_MSM_REQ1,
220 }, {
221 .peri_id = (u8)DMACH_MSM_REQ2,
222 }, {
223 .peri_id = (u8)DMACH_MSM_REQ3,
224 }, {
225 .peri_id = (u8)DMACH_PCM2_RX,
226 .rqtype = DEVTOMEM,
227 }, {
228 .peri_id = (u8)DMACH_PCM2_TX,
229 .rqtype = MEMTODEV,
230 },
231}; 123};
232 124
233struct dma_pl330_platdata s5pv210_pdma1_pdata = { 125struct dma_pl330_platdata s5pv210_pdma1_pdata = {
234 .nr_valid_peri = ARRAY_SIZE(pdma1_peri), 126 .nr_valid_peri = ARRAY_SIZE(pdma1_peri),
235 .peri = pdma1_peri, 127 .peri_id = pdma1_peri,
236}; 128};
237 129
238struct amba_device s5pv210_device_pdma1 = { 130struct amba_device s5pv210_device_pdma1 = {
@@ -253,7 +145,12 @@ struct amba_device s5pv210_device_pdma1 = {
253 145
254static int __init s5pv210_dma_init(void) 146static int __init s5pv210_dma_init(void)
255{ 147{
148 dma_cap_set(DMA_SLAVE, s5pv210_pdma0_pdata.cap_mask);
149 dma_cap_set(DMA_CYCLIC, s5pv210_pdma0_pdata.cap_mask);
256 amba_device_register(&s5pv210_device_pdma0, &iomem_resource); 150 amba_device_register(&s5pv210_device_pdma0, &iomem_resource);
151
152 dma_cap_set(DMA_SLAVE, s5pv210_pdma1_pdata.cap_mask);
153 dma_cap_set(DMA_CYCLIC, s5pv210_pdma1_pdata.cap_mask);
257 amba_device_register(&s5pv210_device_pdma1, &iomem_resource); 154 amba_device_register(&s5pv210_device_pdma1, &iomem_resource);
258 155
259 return 0; 156 return 0;
diff --git a/arch/arm/mach-s5pv210/include/mach/irqs.h b/arch/arm/mach-s5pv210/include/mach/irqs.h
index 5e0de3a31f3d..e777e010ed2e 100644
--- a/arch/arm/mach-s5pv210/include/mach/irqs.h
+++ b/arch/arm/mach-s5pv210/include/mach/irqs.h
@@ -118,6 +118,8 @@
118#define IRQ_MDNIE3 S5P_IRQ_VIC3(8) 118#define IRQ_MDNIE3 S5P_IRQ_VIC3(8)
119#define IRQ_VIC_END S5P_IRQ_VIC3(31) 119#define IRQ_VIC_END S5P_IRQ_VIC3(31)
120 120
121#define IRQ_TIMER_BASE (11)
122
121#define S5P_EINT_BASE1 (S5P_IRQ_VIC0(0)) 123#define S5P_EINT_BASE1 (S5P_IRQ_VIC0(0))
122#define S5P_EINT_BASE2 (IRQ_VIC_END + 1) 124#define S5P_EINT_BASE2 (IRQ_VIC_END + 1)
123 125
diff --git a/arch/arm/mach-s5pv210/include/mach/map.h b/arch/arm/mach-s5pv210/include/mach/map.h
index 7ff609f1568b..89c34b8f73bf 100644
--- a/arch/arm/mach-s5pv210/include/mach/map.h
+++ b/arch/arm/mach-s5pv210/include/mach/map.h
@@ -109,6 +109,8 @@
109#define S3C_PA_RTC S5PV210_PA_RTC 109#define S3C_PA_RTC S5PV210_PA_RTC
110#define S3C_PA_USB_HSOTG S5PV210_PA_HSOTG 110#define S3C_PA_USB_HSOTG S5PV210_PA_HSOTG
111#define S3C_PA_WDT S5PV210_PA_WATCHDOG 111#define S3C_PA_WDT S5PV210_PA_WATCHDOG
112#define S3C_PA_SPI0 S5PV210_PA_SPI0
113#define S3C_PA_SPI1 S5PV210_PA_SPI1
112 114
113#define S5P_PA_CHIPID S5PV210_PA_CHIPID 115#define S5P_PA_CHIPID S5PV210_PA_CHIPID
114#define S5P_PA_FIMC0 S5PV210_PA_FIMC0 116#define S5P_PA_FIMC0 S5PV210_PA_FIMC0
diff --git a/arch/arm/mach-s5pv210/init.c b/arch/arm/mach-s5pv210/init.c
index 4865ae2c475a..468a5f886193 100644
--- a/arch/arm/mach-s5pv210/init.c
+++ b/arch/arm/mach-s5pv210/init.c
@@ -18,27 +18,8 @@
18#include <plat/s5pv210.h> 18#include <plat/s5pv210.h>
19#include <plat/regs-serial.h> 19#include <plat/regs-serial.h>
20 20
21static struct s3c24xx_uart_clksrc s5pv210_serial_clocks[] = {
22 [0] = {
23 .name = "pclk",
24 .divisor = 1,
25 .min_baud = 0,
26 .max_baud = 0,
27 },
28};
29
30/* uart registration process */ 21/* uart registration process */
31void __init s5pv210_common_init_uarts(struct s3c2410_uartcfg *cfg, int no) 22void __init s5pv210_common_init_uarts(struct s3c2410_uartcfg *cfg, int no)
32{ 23{
33 struct s3c2410_uartcfg *tcfg = cfg;
34 u32 ucnt;
35
36 for (ucnt = 0; ucnt < no; ucnt++, tcfg++) {
37 if (!tcfg->clocks) {
38 tcfg->clocks = s5pv210_serial_clocks;
39 tcfg->clocks_size = ARRAY_SIZE(s5pv210_serial_clocks);
40 }
41 }
42
43 s3c24xx_init_uartdevs("s5pv210-uart", s5p_uart_resources, cfg, no); 24 s3c24xx_init_uartdevs("s5pv210-uart", s5p_uart_resources, cfg, no);
44} 25}
diff --git a/arch/arm/mach-s5pv210/setup-sdhci.c b/arch/arm/mach-s5pv210/setup-sdhci.c
deleted file mode 100644
index 6b8ccc4d35fd..000000000000
--- a/arch/arm/mach-s5pv210/setup-sdhci.c
+++ /dev/null
@@ -1,22 +0,0 @@
1/* linux/arch/arm/mach-s5pv210/setup-sdhci.c
2 *
3 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5PV210 - Helper functions for settign up SDHCI device(s) (HSMMC)
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/types.h>
14
15/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */
16
17char *s5pv210_hsmmc_clksrcs[4] = {
18 [0] = "hsmmc", /* HCLK */
19 /* [1] = "hsmmc", - duplicate HCLK entry */
20 [2] = "sclk_mmc", /* mmc_bus */
21 /* [3] = NULL, - reserved */
22};
diff --git a/arch/arm/mach-s5pv210/setup-spi.c b/arch/arm/mach-s5pv210/setup-spi.c
new file mode 100644
index 000000000000..f43c5048a37d
--- /dev/null
+++ b/arch/arm/mach-s5pv210/setup-spi.c
@@ -0,0 +1,51 @@
1/* linux/arch/arm/mach-s5pv210/setup-spi.c
2 *
3 * Copyright (C) 2011 Samsung Electronics Ltd.
4 * http://www.samsung.com/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/gpio.h>
12#include <linux/platform_device.h>
13
14#include <plat/gpio-cfg.h>
15#include <plat/s3c64xx-spi.h>
16
17#ifdef CONFIG_S3C64XX_DEV_SPI0
18struct s3c64xx_spi_info s3c64xx_spi0_pdata = {
19 .fifo_lvl_mask = 0x1ff,
20 .rx_lvl_offset = 15,
21 .high_speed = 1,
22 .tx_st_done = 25,
23};
24
25int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
26{
27 s3c_gpio_cfgpin(S5PV210_GPB(0), S3C_GPIO_SFN(2));
28 s3c_gpio_setpull(S5PV210_GPB(0), S3C_GPIO_PULL_UP);
29 s3c_gpio_cfgall_range(S5PV210_GPB(2), 2,
30 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
31 return 0;
32}
33#endif
34
35#ifdef CONFIG_S3C64XX_DEV_SPI1
36struct s3c64xx_spi_info s3c64xx_spi1_pdata = {
37 .fifo_lvl_mask = 0x7f,
38 .rx_lvl_offset = 15,
39 .high_speed = 1,
40 .tx_st_done = 25,
41};
42
43int s3c64xx_spi1_cfg_gpio(struct platform_device *dev)
44{
45 s3c_gpio_cfgpin(S5PV210_GPB(4), S3C_GPIO_SFN(2));
46 s3c_gpio_setpull(S5PV210_GPB(4), S3C_GPIO_PULL_UP);
47 s3c_gpio_cfgall_range(S5PV210_GPB(6), 2,
48 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
49 return 0;
50}
51#endif
diff --git a/arch/arm/plat-s3c24xx/s3c2443-clock.c b/arch/arm/plat-s3c24xx/s3c2443-clock.c
index 5a21b15b2a97..95e68190d593 100644
--- a/arch/arm/plat-s3c24xx/s3c2443-clock.c
+++ b/arch/arm/plat-s3c24xx/s3c2443-clock.c
@@ -297,13 +297,6 @@ static struct clksrc_clk clk_usb_bus_host = {
297 297
298static struct clksrc_clk clksrc_clks[] = { 298static struct clksrc_clk clksrc_clks[] = {
299 { 299 {
300 /* ART baud-rate clock sourced from esysclk via a divisor */
301 .clk = {
302 .name = "uartclk",
303 .parent = &clk_esysclk.clk,
304 },
305 .reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 8 },
306 }, {
307 /* camera interface bus-clock, divided down from esysclk */ 300 /* camera interface bus-clock, divided down from esysclk */
308 .clk = { 301 .clk = {
309 .name = "camif-upll", /* same as 2440 name */ 302 .name = "camif-upll", /* same as 2440 name */
@@ -323,6 +316,15 @@ static struct clksrc_clk clksrc_clks[] = {
323 }, 316 },
324}; 317};
325 318
319static struct clksrc_clk clk_esys_uart = {
320 /* ART baud-rate clock sourced from esysclk via a divisor */
321 .clk = {
322 .name = "uartclk",
323 .parent = &clk_esysclk.clk,
324 },
325 .reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 8 },
326};
327
326static struct clk clk_i2s_ext = { 328static struct clk clk_i2s_ext = {
327 .name = "i2s-ext", 329 .name = "i2s-ext",
328}; 330};
@@ -425,12 +427,6 @@ static struct clk init_clocks[] = {
425 .enable = s3c2443_clkcon_enable_h, 427 .enable = s3c2443_clkcon_enable_h,
426 .ctrlbit = S3C2443_HCLKCON_DMA5, 428 .ctrlbit = S3C2443_HCLKCON_DMA5,
427 }, { 429 }, {
428 .name = "hsmmc",
429 .devname = "s3c-sdhci.1",
430 .parent = &clk_h,
431 .enable = s3c2443_clkcon_enable_h,
432 .ctrlbit = S3C2443_HCLKCON_HSMMC,
433 }, {
434 .name = "gpio", 430 .name = "gpio",
435 .parent = &clk_p, 431 .parent = &clk_p,
436 .enable = s3c2443_clkcon_enable_p, 432 .enable = s3c2443_clkcon_enable_p,
@@ -512,6 +508,14 @@ static struct clk init_clocks[] = {
512 } 508 }
513}; 509};
514 510
511static struct clk hsmmc1_clk = {
512 .name = "hsmmc",
513 .devname = "s3c-sdhci.1",
514 .parent = &clk_h,
515 .enable = s3c2443_clkcon_enable_h,
516 .ctrlbit = S3C2443_HCLKCON_HSMMC,
517};
518
515static inline unsigned long s3c2443_get_hdiv(unsigned long clkcon0) 519static inline unsigned long s3c2443_get_hdiv(unsigned long clkcon0)
516{ 520{
517 clkcon0 &= S3C2443_CLKDIV0_HCLKDIV_MASK; 521 clkcon0 &= S3C2443_CLKDIV0_HCLKDIV_MASK;
@@ -577,6 +581,7 @@ static struct clk *clks[] __initdata = {
577 &clk_epll, 581 &clk_epll,
578 &clk_usb_bus, 582 &clk_usb_bus,
579 &clk_armdiv, 583 &clk_armdiv,
584 &hsmmc1_clk,
580}; 585};
581 586
582static struct clksrc_clk *clksrcs[] __initdata = { 587static struct clksrc_clk *clksrcs[] __initdata = {
@@ -589,6 +594,13 @@ static struct clksrc_clk *clksrcs[] __initdata = {
589 &clk_arm, 594 &clk_arm,
590}; 595};
591 596
597static struct clk_lookup s3c2443_clk_lookup[] = {
598 CLKDEV_INIT(NULL, "clk_uart_baud1", &s3c24xx_uclk),
599 CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p),
600 CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_esys_uart.clk),
601 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &hsmmc1_clk),
602};
603
592void __init s3c2443_common_init_clocks(int xtal, pll_fn get_mpll, 604void __init s3c2443_common_init_clocks(int xtal, pll_fn get_mpll,
593 unsigned int *divs, int nr_divs, 605 unsigned int *divs, int nr_divs,
594 int divmask) 606 int divmask)
@@ -618,6 +630,7 @@ void __init s3c2443_common_init_clocks(int xtal, pll_fn get_mpll,
618 /* See s3c2443/etc notes on disabling clocks at init time */ 630 /* See s3c2443/etc notes on disabling clocks at init time */
619 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); 631 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
620 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); 632 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
633 clkdev_add_table(s3c2443_clk_lookup, ARRAY_SIZE(s3c2443_clk_lookup));
621 634
622 s3c2443_common_setup_clocks(get_mpll); 635 s3c2443_common_setup_clocks(get_mpll);
623} 636}
diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig
index 313eb26cfa62..160eea15a6ef 100644
--- a/arch/arm/plat-samsung/Kconfig
+++ b/arch/arm/plat-samsung/Kconfig
@@ -226,11 +226,23 @@ config SAMSUNG_DEV_IDE
226 help 226 help
227 Compile in platform device definitions for IDE 227 Compile in platform device definitions for IDE
228 228
229config S3C64XX_DEV_SPI 229config S3C64XX_DEV_SPI0
230 bool 230 bool
231 help 231 help
232 Compile in platform device definitions for S3C64XX's type 232 Compile in platform device definitions for S3C64XX's type
233 SPI controllers. 233 SPI controller 0
234
235config S3C64XX_DEV_SPI1
236 bool
237 help
238 Compile in platform device definitions for S3C64XX's type
239 SPI controller 1
240
241config S3C64XX_DEV_SPI2
242 bool
243 help
244 Compile in platform device definitions for S3C64XX's type
245 SPI controller 2
234 246
235config SAMSUNG_DEV_TS 247config SAMSUNG_DEV_TS
236 bool 248 bool
diff --git a/arch/arm/plat-samsung/devs.c b/arch/arm/plat-samsung/devs.c
index 4ca8b571f971..de0d88d6a0f1 100644
--- a/arch/arm/plat-samsung/devs.c
+++ b/arch/arm/plat-samsung/devs.c
@@ -61,6 +61,7 @@
61#include <plat/regs-iic.h> 61#include <plat/regs-iic.h>
62#include <plat/regs-serial.h> 62#include <plat/regs-serial.h>
63#include <plat/regs-spi.h> 63#include <plat/regs-spi.h>
64#include <plat/s3c64xx-spi.h>
64 65
65static u64 samsung_device_dma_mask = DMA_BIT_MASK(32); 66static u64 samsung_device_dma_mask = DMA_BIT_MASK(32);
66 67
@@ -1461,3 +1462,129 @@ struct platform_device s3c_device_wdt = {
1461 .resource = s3c_wdt_resource, 1462 .resource = s3c_wdt_resource,
1462}; 1463};
1463#endif /* CONFIG_S3C_DEV_WDT */ 1464#endif /* CONFIG_S3C_DEV_WDT */
1465
1466#ifdef CONFIG_S3C64XX_DEV_SPI0
1467static struct resource s3c64xx_spi0_resource[] = {
1468 [0] = DEFINE_RES_MEM(S3C_PA_SPI0, SZ_256),
1469 [1] = DEFINE_RES_DMA(DMACH_SPI0_TX),
1470 [2] = DEFINE_RES_DMA(DMACH_SPI0_RX),
1471 [3] = DEFINE_RES_IRQ(IRQ_SPI0),
1472};
1473
1474struct platform_device s3c64xx_device_spi0 = {
1475 .name = "s3c64xx-spi",
1476 .id = 0,
1477 .num_resources = ARRAY_SIZE(s3c64xx_spi0_resource),
1478 .resource = s3c64xx_spi0_resource,
1479 .dev = {
1480 .dma_mask = &samsung_device_dma_mask,
1481 .coherent_dma_mask = DMA_BIT_MASK(32),
1482 },
1483};
1484
1485void __init s3c64xx_spi0_set_platdata(struct s3c64xx_spi_info *pd,
1486 int src_clk_nr, int num_cs)
1487{
1488 if (!pd) {
1489 pr_err("%s:Need to pass platform data\n", __func__);
1490 return;
1491 }
1492
1493 /* Reject invalid configuration */
1494 if (!num_cs || src_clk_nr < 0) {
1495 pr_err("%s: Invalid SPI configuration\n", __func__);
1496 return;
1497 }
1498
1499 pd->num_cs = num_cs;
1500 pd->src_clk_nr = src_clk_nr;
1501 if (!pd->cfg_gpio)
1502 pd->cfg_gpio = s3c64xx_spi0_cfg_gpio;
1503
1504 s3c_set_platdata(pd, sizeof(*pd), &s3c64xx_device_spi0);
1505}
1506#endif /* CONFIG_S3C64XX_DEV_SPI0 */
1507
1508#ifdef CONFIG_S3C64XX_DEV_SPI1
1509static struct resource s3c64xx_spi1_resource[] = {
1510 [0] = DEFINE_RES_MEM(S3C_PA_SPI1, SZ_256),
1511 [1] = DEFINE_RES_DMA(DMACH_SPI1_TX),
1512 [2] = DEFINE_RES_DMA(DMACH_SPI1_RX),
1513 [3] = DEFINE_RES_IRQ(IRQ_SPI1),
1514};
1515
1516struct platform_device s3c64xx_device_spi1 = {
1517 .name = "s3c64xx-spi",
1518 .id = 1,
1519 .num_resources = ARRAY_SIZE(s3c64xx_spi1_resource),
1520 .resource = s3c64xx_spi1_resource,
1521 .dev = {
1522 .dma_mask = &samsung_device_dma_mask,
1523 .coherent_dma_mask = DMA_BIT_MASK(32),
1524 },
1525};
1526
1527void __init s3c64xx_spi1_set_platdata(struct s3c64xx_spi_info *pd,
1528 int src_clk_nr, int num_cs)
1529{
1530 if (!pd) {
1531 pr_err("%s:Need to pass platform data\n", __func__);
1532 return;
1533 }
1534
1535 /* Reject invalid configuration */
1536 if (!num_cs || src_clk_nr < 0) {
1537 pr_err("%s: Invalid SPI configuration\n", __func__);
1538 return;
1539 }
1540
1541 pd->num_cs = num_cs;
1542 pd->src_clk_nr = src_clk_nr;
1543 if (!pd->cfg_gpio)
1544 pd->cfg_gpio = s3c64xx_spi1_cfg_gpio;
1545
1546 s3c_set_platdata(pd, sizeof(*pd), &s3c64xx_device_spi1);
1547}
1548#endif /* CONFIG_S3C64XX_DEV_SPI1 */
1549
1550#ifdef CONFIG_S3C64XX_DEV_SPI2
1551static struct resource s3c64xx_spi2_resource[] = {
1552 [0] = DEFINE_RES_MEM(S3C_PA_SPI2, SZ_256),
1553 [1] = DEFINE_RES_DMA(DMACH_SPI2_TX),
1554 [2] = DEFINE_RES_DMA(DMACH_SPI2_RX),
1555 [3] = DEFINE_RES_IRQ(IRQ_SPI2),
1556};
1557
1558struct platform_device s3c64xx_device_spi2 = {
1559 .name = "s3c64xx-spi",
1560 .id = 2,
1561 .num_resources = ARRAY_SIZE(s3c64xx_spi2_resource),
1562 .resource = s3c64xx_spi2_resource,
1563 .dev = {
1564 .dma_mask = &samsung_device_dma_mask,
1565 .coherent_dma_mask = DMA_BIT_MASK(32),
1566 },
1567};
1568
1569void __init s3c64xx_spi2_set_platdata(struct s3c64xx_spi_info *pd,
1570 int src_clk_nr, int num_cs)
1571{
1572 if (!pd) {
1573 pr_err("%s:Need to pass platform data\n", __func__);
1574 return;
1575 }
1576
1577 /* Reject invalid configuration */
1578 if (!num_cs || src_clk_nr < 0) {
1579 pr_err("%s: Invalid SPI configuration\n", __func__);
1580 return;
1581 }
1582
1583 pd->num_cs = num_cs;
1584 pd->src_clk_nr = src_clk_nr;
1585 if (!pd->cfg_gpio)
1586 pd->cfg_gpio = s3c64xx_spi2_cfg_gpio;
1587
1588 s3c_set_platdata(pd, sizeof(*pd), &s3c64xx_device_spi2);
1589}
1590#endif /* CONFIG_S3C64XX_DEV_SPI2 */
diff --git a/arch/arm/plat-samsung/dma-ops.c b/arch/arm/plat-samsung/dma-ops.c
index 93a994a5dd8f..2cded872f22b 100644
--- a/arch/arm/plat-samsung/dma-ops.c
+++ b/arch/arm/plat-samsung/dma-ops.c
@@ -18,23 +18,24 @@
18 18
19#include <mach/dma.h> 19#include <mach/dma.h>
20 20
21static inline bool pl330_filter(struct dma_chan *chan, void *param)
22{
23 struct dma_pl330_peri *peri = chan->private;
24 return peri->peri_id == (unsigned)param;
25}
26
27static unsigned samsung_dmadev_request(enum dma_ch dma_ch, 21static unsigned samsung_dmadev_request(enum dma_ch dma_ch,
28 struct samsung_dma_info *info) 22 struct samsung_dma_info *info)
29{ 23{
30 struct dma_chan *chan; 24 struct dma_chan *chan;
31 dma_cap_mask_t mask; 25 dma_cap_mask_t mask;
32 struct dma_slave_config slave_config; 26 struct dma_slave_config slave_config;
27 void *filter_param;
33 28
34 dma_cap_zero(mask); 29 dma_cap_zero(mask);
35 dma_cap_set(info->cap, mask); 30 dma_cap_set(info->cap, mask);
36 31
37 chan = dma_request_channel(mask, pl330_filter, (void *)dma_ch); 32 /*
33 * If a dma channel property of a device node from device tree is
34 * specified, use that as the fliter parameter.
35 */
36 filter_param = (dma_ch == DMACH_DT_PROP) ? (void *)info->dt_dmach_prop :
37 (void *)dma_ch;
38 chan = dma_request_channel(mask, pl330_filter, filter_param);
38 39
39 if (info->direction == DMA_FROM_DEVICE) { 40 if (info->direction == DMA_FROM_DEVICE) {
40 memset(&slave_config, 0, sizeof(struct dma_slave_config)); 41 memset(&slave_config, 0, sizeof(struct dma_slave_config));
diff --git a/arch/arm/plat-samsung/include/plat/devs.h b/arch/arm/plat-samsung/include/plat/devs.h
index a2ff27e3ec30..4214ea0ff8fe 100644
--- a/arch/arm/plat-samsung/include/plat/devs.h
+++ b/arch/arm/plat-samsung/include/plat/devs.h
@@ -39,6 +39,7 @@ extern struct platform_device s3c64xx_device_pcm0;
39extern struct platform_device s3c64xx_device_pcm1; 39extern struct platform_device s3c64xx_device_pcm1;
40extern struct platform_device s3c64xx_device_spi0; 40extern struct platform_device s3c64xx_device_spi0;
41extern struct platform_device s3c64xx_device_spi1; 41extern struct platform_device s3c64xx_device_spi1;
42extern struct platform_device s3c64xx_device_spi2;
42 43
43extern struct platform_device s3c_device_adc; 44extern struct platform_device s3c_device_adc;
44extern struct platform_device s3c_device_cfcon; 45extern struct platform_device s3c_device_cfcon;
@@ -98,8 +99,6 @@ extern struct platform_device s5p6450_device_iis1;
98extern struct platform_device s5p6450_device_iis2; 99extern struct platform_device s5p6450_device_iis2;
99extern struct platform_device s5p6450_device_pcm0; 100extern struct platform_device s5p6450_device_pcm0;
100 101
101extern struct platform_device s5p64x0_device_spi0;
102extern struct platform_device s5p64x0_device_spi1;
103 102
104extern struct platform_device s5pc100_device_ac97; 103extern struct platform_device s5pc100_device_ac97;
105extern struct platform_device s5pc100_device_iis0; 104extern struct platform_device s5pc100_device_iis0;
@@ -108,9 +107,6 @@ extern struct platform_device s5pc100_device_iis2;
108extern struct platform_device s5pc100_device_pcm0; 107extern struct platform_device s5pc100_device_pcm0;
109extern struct platform_device s5pc100_device_pcm1; 108extern struct platform_device s5pc100_device_pcm1;
110extern struct platform_device s5pc100_device_spdif; 109extern struct platform_device s5pc100_device_spdif;
111extern struct platform_device s5pc100_device_spi0;
112extern struct platform_device s5pc100_device_spi1;
113extern struct platform_device s5pc100_device_spi2;
114 110
115extern struct platform_device s5pv210_device_ac97; 111extern struct platform_device s5pv210_device_ac97;
116extern struct platform_device s5pv210_device_iis0; 112extern struct platform_device s5pv210_device_iis0;
@@ -120,8 +116,6 @@ extern struct platform_device s5pv210_device_pcm0;
120extern struct platform_device s5pv210_device_pcm1; 116extern struct platform_device s5pv210_device_pcm1;
121extern struct platform_device s5pv210_device_pcm2; 117extern struct platform_device s5pv210_device_pcm2;
122extern struct platform_device s5pv210_device_spdif; 118extern struct platform_device s5pv210_device_spdif;
123extern struct platform_device s5pv210_device_spi0;
124extern struct platform_device s5pv210_device_spi1;
125 119
126extern struct platform_device exynos4_device_ac97; 120extern struct platform_device exynos4_device_ac97;
127extern struct platform_device exynos4_device_ahci; 121extern struct platform_device exynos4_device_ahci;
diff --git a/arch/arm/plat-samsung/include/plat/dma-ops.h b/arch/arm/plat-samsung/include/plat/dma-ops.h
index 4c1a363526cf..22eafc310bd7 100644
--- a/arch/arm/plat-samsung/include/plat/dma-ops.h
+++ b/arch/arm/plat-samsung/include/plat/dma-ops.h
@@ -31,6 +31,7 @@ struct samsung_dma_info {
31 enum dma_slave_buswidth width; 31 enum dma_slave_buswidth width;
32 dma_addr_t fifo; 32 dma_addr_t fifo;
33 struct s3c2410_dma_client *client; 33 struct s3c2410_dma_client *client;
34 struct property *dt_dmach_prop;
34}; 35};
35 36
36struct samsung_dma_ops { 37struct samsung_dma_ops {
diff --git a/arch/arm/plat-samsung/include/plat/dma-pl330.h b/arch/arm/plat-samsung/include/plat/dma-pl330.h
index 2e55e5958674..c5eaad529de5 100644
--- a/arch/arm/plat-samsung/include/plat/dma-pl330.h
+++ b/arch/arm/plat-samsung/include/plat/dma-pl330.h
@@ -21,7 +21,8 @@
21 * use these just as IDs. 21 * use these just as IDs.
22 */ 22 */
23enum dma_ch { 23enum dma_ch {
24 DMACH_UART0_RX, 24 DMACH_DT_PROP = -1,
25 DMACH_UART0_RX = 0,
25 DMACH_UART0_TX, 26 DMACH_UART0_TX,
26 DMACH_UART1_RX, 27 DMACH_UART1_RX,
27 DMACH_UART1_TX, 28 DMACH_UART1_TX,
diff --git a/arch/arm/plat-samsung/include/plat/irqs.h b/arch/arm/plat-samsung/include/plat/irqs.h
index 08d1a7ef97b7..df46b776976a 100644
--- a/arch/arm/plat-samsung/include/plat/irqs.h
+++ b/arch/arm/plat-samsung/include/plat/irqs.h
@@ -44,13 +44,14 @@
44#define S5P_IRQ_VIC2(x) (S5P_VIC2_BASE + (x)) 44#define S5P_IRQ_VIC2(x) (S5P_VIC2_BASE + (x))
45#define S5P_IRQ_VIC3(x) (S5P_VIC3_BASE + (x)) 45#define S5P_IRQ_VIC3(x) (S5P_VIC3_BASE + (x))
46 46
47#define S5P_TIMER_IRQ(x) (11 + (x)) 47#define S5P_TIMER_IRQ(x) (IRQ_TIMER_BASE + (x))
48 48
49#define IRQ_TIMER0 S5P_TIMER_IRQ(0) 49#define IRQ_TIMER0 S5P_TIMER_IRQ(0)
50#define IRQ_TIMER1 S5P_TIMER_IRQ(1) 50#define IRQ_TIMER1 S5P_TIMER_IRQ(1)
51#define IRQ_TIMER2 S5P_TIMER_IRQ(2) 51#define IRQ_TIMER2 S5P_TIMER_IRQ(2)
52#define IRQ_TIMER3 S5P_TIMER_IRQ(3) 52#define IRQ_TIMER3 S5P_TIMER_IRQ(3)
53#define IRQ_TIMER4 S5P_TIMER_IRQ(4) 53#define IRQ_TIMER4 S5P_TIMER_IRQ(4)
54#define IRQ_TIMER_COUNT (5)
54 55
55#define IRQ_EINT(x) ((x) < 16 ? ((x) + S5P_EINT_BASE1) \ 56#define IRQ_EINT(x) ((x) < 16 ? ((x) + S5P_EINT_BASE1) \
56 : ((x) - 16 + S5P_EINT_BASE2)) 57 : ((x) - 16 + S5P_EINT_BASE2))
diff --git a/arch/arm/plat-samsung/include/plat/regs-serial.h b/arch/arm/plat-samsung/include/plat/regs-serial.h
index 720734847027..29c26a818842 100644
--- a/arch/arm/plat-samsung/include/plat/regs-serial.h
+++ b/arch/arm/plat-samsung/include/plat/regs-serial.h
@@ -71,6 +71,7 @@
71#define S3C2410_LCON_IRM (1<<6) 71#define S3C2410_LCON_IRM (1<<6)
72 72
73#define S3C2440_UCON_CLKMASK (3<<10) 73#define S3C2440_UCON_CLKMASK (3<<10)
74#define S3C2440_UCON_CLKSHIFT (10)
74#define S3C2440_UCON_PCLK (0<<10) 75#define S3C2440_UCON_PCLK (0<<10)
75#define S3C2440_UCON_UCLK (1<<10) 76#define S3C2440_UCON_UCLK (1<<10)
76#define S3C2440_UCON_PCLK2 (2<<10) 77#define S3C2440_UCON_PCLK2 (2<<10)
@@ -78,6 +79,7 @@
78#define S3C2443_UCON_EPLL (3<<10) 79#define S3C2443_UCON_EPLL (3<<10)
79 80
80#define S3C6400_UCON_CLKMASK (3<<10) 81#define S3C6400_UCON_CLKMASK (3<<10)
82#define S3C6400_UCON_CLKSHIFT (10)
81#define S3C6400_UCON_PCLK (0<<10) 83#define S3C6400_UCON_PCLK (0<<10)
82#define S3C6400_UCON_PCLK2 (2<<10) 84#define S3C6400_UCON_PCLK2 (2<<10)
83#define S3C6400_UCON_UCLK0 (1<<10) 85#define S3C6400_UCON_UCLK0 (1<<10)
@@ -90,11 +92,14 @@
90#define S3C2440_UCON_DIVSHIFT (12) 92#define S3C2440_UCON_DIVSHIFT (12)
91 93
92#define S3C2412_UCON_CLKMASK (3<<10) 94#define S3C2412_UCON_CLKMASK (3<<10)
95#define S3C2412_UCON_CLKSHIFT (10)
93#define S3C2412_UCON_UCLK (1<<10) 96#define S3C2412_UCON_UCLK (1<<10)
94#define S3C2412_UCON_USYSCLK (3<<10) 97#define S3C2412_UCON_USYSCLK (3<<10)
95#define S3C2412_UCON_PCLK (0<<10) 98#define S3C2412_UCON_PCLK (0<<10)
96#define S3C2412_UCON_PCLK2 (2<<10) 99#define S3C2412_UCON_PCLK2 (2<<10)
97 100
101#define S3C2410_UCON_CLKMASK (1 << 10)
102#define S3C2410_UCON_CLKSHIFT (10)
98#define S3C2410_UCON_UCLK (1<<10) 103#define S3C2410_UCON_UCLK (1<<10)
99#define S3C2410_UCON_SBREAK (1<<4) 104#define S3C2410_UCON_SBREAK (1<<4)
100 105
@@ -193,6 +198,7 @@
193 198
194/* Following are specific to S5PV210 */ 199/* Following are specific to S5PV210 */
195#define S5PV210_UCON_CLKMASK (1<<10) 200#define S5PV210_UCON_CLKMASK (1<<10)
201#define S5PV210_UCON_CLKSHIFT (10)
196#define S5PV210_UCON_PCLK (0<<10) 202#define S5PV210_UCON_PCLK (0<<10)
197#define S5PV210_UCON_UCLK (1<<10) 203#define S5PV210_UCON_UCLK (1<<10)
198 204
@@ -221,29 +227,24 @@
221#define S5PV210_UFSTAT_RXMASK (255<<0) 227#define S5PV210_UFSTAT_RXMASK (255<<0)
222#define S5PV210_UFSTAT_RXSHIFT (0) 228#define S5PV210_UFSTAT_RXSHIFT (0)
223 229
224#define NO_NEED_CHECK_CLKSRC 1 230#define S3C2410_UCON_CLKSEL0 (1 << 0)
231#define S3C2410_UCON_CLKSEL1 (1 << 1)
232#define S3C2410_UCON_CLKSEL2 (1 << 2)
233#define S3C2410_UCON_CLKSEL3 (1 << 3)
225 234
226#ifndef __ASSEMBLY__ 235/* Default values for s5pv210 UCON and UFCON uart registers */
236#define S5PV210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
237 S3C2410_UCON_RXILEVEL | \
238 S3C2410_UCON_TXIRQMODE | \
239 S3C2410_UCON_RXIRQMODE | \
240 S3C2410_UCON_RXFIFO_TOI | \
241 S3C2443_UCON_RXERR_IRQEN)
227 242
228/* struct s3c24xx_uart_clksrc 243#define S5PV210_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
229 * 244 S5PV210_UFCON_TXTRIG4 | \
230 * this structure defines a named clock source that can be used for the 245 S5PV210_UFCON_RXTRIG4)
231 * uart, so that the best clock can be selected for the requested baud
232 * rate.
233 *
234 * min_baud and max_baud define the range of baud-rates this clock is
235 * acceptable for, if they are both zero, it is assumed any baud rate that
236 * can be generated from this clock will be used.
237 *
238 * divisor gives the divisor from the clock to the one seen by the uart
239*/
240 246
241struct s3c24xx_uart_clksrc { 247#ifndef __ASSEMBLY__
242 const char *name;
243 unsigned int divisor;
244 unsigned int min_baud;
245 unsigned int max_baud;
246};
247 248
248/* configuration structure for per-machine configurations for the 249/* configuration structure for per-machine configurations for the
249 * serial port 250 * serial port
@@ -257,15 +258,13 @@ struct s3c2410_uartcfg {
257 unsigned char unused; 258 unsigned char unused;
258 unsigned short flags; 259 unsigned short flags;
259 upf_t uart_flags; /* default uart flags */ 260 upf_t uart_flags; /* default uart flags */
261 unsigned int clk_sel;
260 262
261 unsigned int has_fracval; 263 unsigned int has_fracval;
262 264
263 unsigned long ucon; /* value of ucon for port */ 265 unsigned long ucon; /* value of ucon for port */
264 unsigned long ulcon; /* value of ulcon for port */ 266 unsigned long ulcon; /* value of ulcon for port */
265 unsigned long ufcon; /* value of ufcon for port */ 267 unsigned long ufcon; /* value of ufcon for port */
266
267 struct s3c24xx_uart_clksrc *clocks;
268 unsigned int clocks_size;
269}; 268};
270 269
271/* s3c24xx_uart_devs 270/* s3c24xx_uart_devs
diff --git a/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h b/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
index 4c16fa3621bb..aea68b60ef98 100644
--- a/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
+++ b/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
@@ -31,7 +31,6 @@ struct s3c64xx_spi_csinfo {
31/** 31/**
32 * struct s3c64xx_spi_info - SPI Controller defining structure 32 * struct s3c64xx_spi_info - SPI Controller defining structure
33 * @src_clk_nr: Clock source index for the CLK_CFG[SPI_CLKSEL] field. 33 * @src_clk_nr: Clock source index for the CLK_CFG[SPI_CLKSEL] field.
34 * @src_clk_name: Platform name of the corresponding clock.
35 * @clk_from_cmu: If the SPI clock/prescalar control block is present 34 * @clk_from_cmu: If the SPI clock/prescalar control block is present
36 * by the platform's clock-management-unit and not in SPI controller. 35 * by the platform's clock-management-unit and not in SPI controller.
37 * @num_cs: Number of CS this controller emulates. 36 * @num_cs: Number of CS this controller emulates.
@@ -43,7 +42,6 @@ struct s3c64xx_spi_csinfo {
43 */ 42 */
44struct s3c64xx_spi_info { 43struct s3c64xx_spi_info {
45 int src_clk_nr; 44 int src_clk_nr;
46 char *src_clk_name;
47 bool clk_from_cmu; 45 bool clk_from_cmu;
48 46
49 int num_cs; 47 int num_cs;
@@ -58,18 +56,28 @@ struct s3c64xx_spi_info {
58}; 56};
59 57
60/** 58/**
61 * s3c64xx_spi_set_info - SPI Controller configure callback by the board 59 * s3c64xx_spi_set_platdata - SPI Controller configure callback by the board
62 * initialization code. 60 * initialization code.
63 * @cntrlr: SPI controller number the configuration is for. 61 * @pd: SPI platform data to set.
64 * @src_clk_nr: Clock the SPI controller is to use to generate SPI clocks. 62 * @src_clk_nr: Clock the SPI controller is to use to generate SPI clocks.
65 * @num_cs: Number of elements in the 'cs' array. 63 * @num_cs: Number of elements in the 'cs' array.
66 * 64 *
67 * Call this from machine init code for each SPI Controller that 65 * Call this from machine init code for each SPI Controller that
68 * has some chips attached to it. 66 * has some chips attached to it.
69 */ 67 */
70extern void s3c64xx_spi_set_info(int cntrlr, int src_clk_nr, int num_cs); 68extern void s3c64xx_spi0_set_platdata(struct s3c64xx_spi_info *pd,
71extern void s5pc100_spi_set_info(int cntrlr, int src_clk_nr, int num_cs); 69 int src_clk_nr, int num_cs);
72extern void s5pv210_spi_set_info(int cntrlr, int src_clk_nr, int num_cs); 70extern void s3c64xx_spi1_set_platdata(struct s3c64xx_spi_info *pd,
73extern void s5p64x0_spi_set_info(int cntrlr, int src_clk_nr, int num_cs); 71 int src_clk_nr, int num_cs);
72extern void s3c64xx_spi2_set_platdata(struct s3c64xx_spi_info *pd,
73 int src_clk_nr, int num_cs);
74 74
75/* defined by architecture to configure gpio */
76extern int s3c64xx_spi0_cfg_gpio(struct platform_device *dev);
77extern int s3c64xx_spi1_cfg_gpio(struct platform_device *dev);
78extern int s3c64xx_spi2_cfg_gpio(struct platform_device *dev);
79
80extern struct s3c64xx_spi_info s3c64xx_spi0_pdata;
81extern struct s3c64xx_spi_info s3c64xx_spi1_pdata;
82extern struct s3c64xx_spi_info s3c64xx_spi2_pdata;
75#endif /* __S3C64XX_PLAT_SPI_H */ 83#endif /* __S3C64XX_PLAT_SPI_H */
diff --git a/arch/arm/plat-samsung/include/plat/sdhci.h b/arch/arm/plat-samsung/include/plat/sdhci.h
index e7b3c752e919..dcff7dd1ae8a 100644
--- a/arch/arm/plat-samsung/include/plat/sdhci.h
+++ b/arch/arm/plat-samsung/include/plat/sdhci.h
@@ -66,8 +66,6 @@ struct s3c_sdhci_platdata {
66 enum cd_types cd_type; 66 enum cd_types cd_type;
67 enum clk_types clk_type; 67 enum clk_types clk_type;
68 68
69 char **clocks; /* set of clock sources */
70
71 int ext_cd_gpio; 69 int ext_cd_gpio;
72 bool ext_cd_gpio_invert; 70 bool ext_cd_gpio_invert;
73 int (*ext_cd_init)(void (*notify_func)(struct platform_device *, 71 int (*ext_cd_init)(void (*notify_func)(struct platform_device *,
@@ -129,12 +127,9 @@ extern void exynos4_setup_sdhci3_cfg_gpio(struct platform_device *, int w);
129/* S3C2416 SDHCI setup */ 127/* S3C2416 SDHCI setup */
130 128
131#ifdef CONFIG_S3C2416_SETUP_SDHCI 129#ifdef CONFIG_S3C2416_SETUP_SDHCI
132extern char *s3c2416_hsmmc_clksrcs[4];
133
134static inline void s3c2416_default_sdhci0(void) 130static inline void s3c2416_default_sdhci0(void)
135{ 131{
136#ifdef CONFIG_S3C_DEV_HSMMC 132#ifdef CONFIG_S3C_DEV_HSMMC
137 s3c_hsmmc0_def_platdata.clocks = s3c2416_hsmmc_clksrcs;
138 s3c_hsmmc0_def_platdata.cfg_gpio = s3c2416_setup_sdhci0_cfg_gpio; 133 s3c_hsmmc0_def_platdata.cfg_gpio = s3c2416_setup_sdhci0_cfg_gpio;
139#endif /* CONFIG_S3C_DEV_HSMMC */ 134#endif /* CONFIG_S3C_DEV_HSMMC */
140} 135}
@@ -142,7 +137,6 @@ static inline void s3c2416_default_sdhci0(void)
142static inline void s3c2416_default_sdhci1(void) 137static inline void s3c2416_default_sdhci1(void)
143{ 138{
144#ifdef CONFIG_S3C_DEV_HSMMC1 139#ifdef CONFIG_S3C_DEV_HSMMC1
145 s3c_hsmmc1_def_platdata.clocks = s3c2416_hsmmc_clksrcs;
146 s3c_hsmmc1_def_platdata.cfg_gpio = s3c2416_setup_sdhci1_cfg_gpio; 140 s3c_hsmmc1_def_platdata.cfg_gpio = s3c2416_setup_sdhci1_cfg_gpio;
147#endif /* CONFIG_S3C_DEV_HSMMC1 */ 141#endif /* CONFIG_S3C_DEV_HSMMC1 */
148} 142}
@@ -155,12 +149,9 @@ static inline void s3c2416_default_sdhci1(void) { }
155/* S3C64XX SDHCI setup */ 149/* S3C64XX SDHCI setup */
156 150
157#ifdef CONFIG_S3C64XX_SETUP_SDHCI 151#ifdef CONFIG_S3C64XX_SETUP_SDHCI
158extern char *s3c64xx_hsmmc_clksrcs[4];
159
160static inline void s3c6400_default_sdhci0(void) 152static inline void s3c6400_default_sdhci0(void)
161{ 153{
162#ifdef CONFIG_S3C_DEV_HSMMC 154#ifdef CONFIG_S3C_DEV_HSMMC
163 s3c_hsmmc0_def_platdata.clocks = s3c64xx_hsmmc_clksrcs;
164 s3c_hsmmc0_def_platdata.cfg_gpio = s3c64xx_setup_sdhci0_cfg_gpio; 155 s3c_hsmmc0_def_platdata.cfg_gpio = s3c64xx_setup_sdhci0_cfg_gpio;
165#endif 156#endif
166} 157}
@@ -168,7 +159,6 @@ static inline void s3c6400_default_sdhci0(void)
168static inline void s3c6400_default_sdhci1(void) 159static inline void s3c6400_default_sdhci1(void)
169{ 160{
170#ifdef CONFIG_S3C_DEV_HSMMC1 161#ifdef CONFIG_S3C_DEV_HSMMC1
171 s3c_hsmmc1_def_platdata.clocks = s3c64xx_hsmmc_clksrcs;
172 s3c_hsmmc1_def_platdata.cfg_gpio = s3c64xx_setup_sdhci1_cfg_gpio; 162 s3c_hsmmc1_def_platdata.cfg_gpio = s3c64xx_setup_sdhci1_cfg_gpio;
173#endif 163#endif
174} 164}
@@ -176,7 +166,6 @@ static inline void s3c6400_default_sdhci1(void)
176static inline void s3c6400_default_sdhci2(void) 166static inline void s3c6400_default_sdhci2(void)
177{ 167{
178#ifdef CONFIG_S3C_DEV_HSMMC2 168#ifdef CONFIG_S3C_DEV_HSMMC2
179 s3c_hsmmc2_def_platdata.clocks = s3c64xx_hsmmc_clksrcs;
180 s3c_hsmmc2_def_platdata.cfg_gpio = s3c64xx_setup_sdhci2_cfg_gpio; 169 s3c_hsmmc2_def_platdata.cfg_gpio = s3c64xx_setup_sdhci2_cfg_gpio;
181#endif 170#endif
182} 171}
@@ -184,7 +173,6 @@ static inline void s3c6400_default_sdhci2(void)
184static inline void s3c6410_default_sdhci0(void) 173static inline void s3c6410_default_sdhci0(void)
185{ 174{
186#ifdef CONFIG_S3C_DEV_HSMMC 175#ifdef CONFIG_S3C_DEV_HSMMC
187 s3c_hsmmc0_def_platdata.clocks = s3c64xx_hsmmc_clksrcs;
188 s3c_hsmmc0_def_platdata.cfg_gpio = s3c64xx_setup_sdhci0_cfg_gpio; 176 s3c_hsmmc0_def_platdata.cfg_gpio = s3c64xx_setup_sdhci0_cfg_gpio;
189#endif 177#endif
190} 178}
@@ -192,7 +180,6 @@ static inline void s3c6410_default_sdhci0(void)
192static inline void s3c6410_default_sdhci1(void) 180static inline void s3c6410_default_sdhci1(void)
193{ 181{
194#ifdef CONFIG_S3C_DEV_HSMMC1 182#ifdef CONFIG_S3C_DEV_HSMMC1
195 s3c_hsmmc1_def_platdata.clocks = s3c64xx_hsmmc_clksrcs;
196 s3c_hsmmc1_def_platdata.cfg_gpio = s3c64xx_setup_sdhci1_cfg_gpio; 183 s3c_hsmmc1_def_platdata.cfg_gpio = s3c64xx_setup_sdhci1_cfg_gpio;
197#endif 184#endif
198} 185}
@@ -200,7 +187,6 @@ static inline void s3c6410_default_sdhci1(void)
200static inline void s3c6410_default_sdhci2(void) 187static inline void s3c6410_default_sdhci2(void)
201{ 188{
202#ifdef CONFIG_S3C_DEV_HSMMC2 189#ifdef CONFIG_S3C_DEV_HSMMC2
203 s3c_hsmmc2_def_platdata.clocks = s3c64xx_hsmmc_clksrcs;
204 s3c_hsmmc2_def_platdata.cfg_gpio = s3c64xx_setup_sdhci2_cfg_gpio; 190 s3c_hsmmc2_def_platdata.cfg_gpio = s3c64xx_setup_sdhci2_cfg_gpio;
205#endif 191#endif
206} 192}
@@ -218,12 +204,9 @@ static inline void s3c6400_default_sdhci2(void) { }
218/* S5PC100 SDHCI setup */ 204/* S5PC100 SDHCI setup */
219 205
220#ifdef CONFIG_S5PC100_SETUP_SDHCI 206#ifdef CONFIG_S5PC100_SETUP_SDHCI
221extern char *s5pc100_hsmmc_clksrcs[4];
222
223static inline void s5pc100_default_sdhci0(void) 207static inline void s5pc100_default_sdhci0(void)
224{ 208{
225#ifdef CONFIG_S3C_DEV_HSMMC 209#ifdef CONFIG_S3C_DEV_HSMMC
226 s3c_hsmmc0_def_platdata.clocks = s5pc100_hsmmc_clksrcs;
227 s3c_hsmmc0_def_platdata.cfg_gpio = s5pc100_setup_sdhci0_cfg_gpio; 210 s3c_hsmmc0_def_platdata.cfg_gpio = s5pc100_setup_sdhci0_cfg_gpio;
228#endif 211#endif
229} 212}
@@ -231,7 +214,6 @@ static inline void s5pc100_default_sdhci0(void)
231static inline void s5pc100_default_sdhci1(void) 214static inline void s5pc100_default_sdhci1(void)
232{ 215{
233#ifdef CONFIG_S3C_DEV_HSMMC1 216#ifdef CONFIG_S3C_DEV_HSMMC1
234 s3c_hsmmc1_def_platdata.clocks = s5pc100_hsmmc_clksrcs;
235 s3c_hsmmc1_def_platdata.cfg_gpio = s5pc100_setup_sdhci1_cfg_gpio; 217 s3c_hsmmc1_def_platdata.cfg_gpio = s5pc100_setup_sdhci1_cfg_gpio;
236#endif 218#endif
237} 219}
@@ -239,7 +221,6 @@ static inline void s5pc100_default_sdhci1(void)
239static inline void s5pc100_default_sdhci2(void) 221static inline void s5pc100_default_sdhci2(void)
240{ 222{
241#ifdef CONFIG_S3C_DEV_HSMMC2 223#ifdef CONFIG_S3C_DEV_HSMMC2
242 s3c_hsmmc2_def_platdata.clocks = s5pc100_hsmmc_clksrcs;
243 s3c_hsmmc2_def_platdata.cfg_gpio = s5pc100_setup_sdhci2_cfg_gpio; 224 s3c_hsmmc2_def_platdata.cfg_gpio = s5pc100_setup_sdhci2_cfg_gpio;
244#endif 225#endif
245} 226}
@@ -254,12 +235,9 @@ static inline void s5pc100_default_sdhci2(void) { }
254/* S5PV210 SDHCI setup */ 235/* S5PV210 SDHCI setup */
255 236
256#ifdef CONFIG_S5PV210_SETUP_SDHCI 237#ifdef CONFIG_S5PV210_SETUP_SDHCI
257extern char *s5pv210_hsmmc_clksrcs[4];
258
259static inline void s5pv210_default_sdhci0(void) 238static inline void s5pv210_default_sdhci0(void)
260{ 239{
261#ifdef CONFIG_S3C_DEV_HSMMC 240#ifdef CONFIG_S3C_DEV_HSMMC
262 s3c_hsmmc0_def_platdata.clocks = s5pv210_hsmmc_clksrcs;
263 s3c_hsmmc0_def_platdata.cfg_gpio = s5pv210_setup_sdhci0_cfg_gpio; 241 s3c_hsmmc0_def_platdata.cfg_gpio = s5pv210_setup_sdhci0_cfg_gpio;
264#endif 242#endif
265} 243}
@@ -267,7 +245,6 @@ static inline void s5pv210_default_sdhci0(void)
267static inline void s5pv210_default_sdhci1(void) 245static inline void s5pv210_default_sdhci1(void)
268{ 246{
269#ifdef CONFIG_S3C_DEV_HSMMC1 247#ifdef CONFIG_S3C_DEV_HSMMC1
270 s3c_hsmmc1_def_platdata.clocks = s5pv210_hsmmc_clksrcs;
271 s3c_hsmmc1_def_platdata.cfg_gpio = s5pv210_setup_sdhci1_cfg_gpio; 248 s3c_hsmmc1_def_platdata.cfg_gpio = s5pv210_setup_sdhci1_cfg_gpio;
272#endif 249#endif
273} 250}
@@ -275,7 +252,6 @@ static inline void s5pv210_default_sdhci1(void)
275static inline void s5pv210_default_sdhci2(void) 252static inline void s5pv210_default_sdhci2(void)
276{ 253{
277#ifdef CONFIG_S3C_DEV_HSMMC2 254#ifdef CONFIG_S3C_DEV_HSMMC2
278 s3c_hsmmc2_def_platdata.clocks = s5pv210_hsmmc_clksrcs;
279 s3c_hsmmc2_def_platdata.cfg_gpio = s5pv210_setup_sdhci2_cfg_gpio; 255 s3c_hsmmc2_def_platdata.cfg_gpio = s5pv210_setup_sdhci2_cfg_gpio;
280#endif 256#endif
281} 257}
@@ -283,7 +259,6 @@ static inline void s5pv210_default_sdhci2(void)
283static inline void s5pv210_default_sdhci3(void) 259static inline void s5pv210_default_sdhci3(void)
284{ 260{
285#ifdef CONFIG_S3C_DEV_HSMMC3 261#ifdef CONFIG_S3C_DEV_HSMMC3
286 s3c_hsmmc3_def_platdata.clocks = s5pv210_hsmmc_clksrcs;
287 s3c_hsmmc3_def_platdata.cfg_gpio = s5pv210_setup_sdhci3_cfg_gpio; 262 s3c_hsmmc3_def_platdata.cfg_gpio = s5pv210_setup_sdhci3_cfg_gpio;
288#endif 263#endif
289} 264}
@@ -298,12 +273,9 @@ static inline void s5pv210_default_sdhci3(void) { }
298 273
299/* EXYNOS4 SDHCI setup */ 274/* EXYNOS4 SDHCI setup */
300#ifdef CONFIG_EXYNOS4_SETUP_SDHCI 275#ifdef CONFIG_EXYNOS4_SETUP_SDHCI
301extern char *exynos4_hsmmc_clksrcs[4];
302
303static inline void exynos4_default_sdhci0(void) 276static inline void exynos4_default_sdhci0(void)
304{ 277{
305#ifdef CONFIG_S3C_DEV_HSMMC 278#ifdef CONFIG_S3C_DEV_HSMMC
306 s3c_hsmmc0_def_platdata.clocks = exynos4_hsmmc_clksrcs;
307 s3c_hsmmc0_def_platdata.cfg_gpio = exynos4_setup_sdhci0_cfg_gpio; 279 s3c_hsmmc0_def_platdata.cfg_gpio = exynos4_setup_sdhci0_cfg_gpio;
308#endif 280#endif
309} 281}
@@ -311,7 +283,6 @@ static inline void exynos4_default_sdhci0(void)
311static inline void exynos4_default_sdhci1(void) 283static inline void exynos4_default_sdhci1(void)
312{ 284{
313#ifdef CONFIG_S3C_DEV_HSMMC1 285#ifdef CONFIG_S3C_DEV_HSMMC1
314 s3c_hsmmc1_def_platdata.clocks = exynos4_hsmmc_clksrcs;
315 s3c_hsmmc1_def_platdata.cfg_gpio = exynos4_setup_sdhci1_cfg_gpio; 286 s3c_hsmmc1_def_platdata.cfg_gpio = exynos4_setup_sdhci1_cfg_gpio;
316#endif 287#endif
317} 288}
@@ -319,7 +290,6 @@ static inline void exynos4_default_sdhci1(void)
319static inline void exynos4_default_sdhci2(void) 290static inline void exynos4_default_sdhci2(void)
320{ 291{
321#ifdef CONFIG_S3C_DEV_HSMMC2 292#ifdef CONFIG_S3C_DEV_HSMMC2
322 s3c_hsmmc2_def_platdata.clocks = exynos4_hsmmc_clksrcs;
323 s3c_hsmmc2_def_platdata.cfg_gpio = exynos4_setup_sdhci2_cfg_gpio; 293 s3c_hsmmc2_def_platdata.cfg_gpio = exynos4_setup_sdhci2_cfg_gpio;
324#endif 294#endif
325} 295}
@@ -327,7 +297,6 @@ static inline void exynos4_default_sdhci2(void)
327static inline void exynos4_default_sdhci3(void) 297static inline void exynos4_default_sdhci3(void)
328{ 298{
329#ifdef CONFIG_S3C_DEV_HSMMC3 299#ifdef CONFIG_S3C_DEV_HSMMC3
330 s3c_hsmmc3_def_platdata.clocks = exynos4_hsmmc_clksrcs;
331 s3c_hsmmc3_def_platdata.cfg_gpio = exynos4_setup_sdhci3_cfg_gpio; 300 s3c_hsmmc3_def_platdata.cfg_gpio = exynos4_setup_sdhci3_cfg_gpio;
332#endif 301#endif
333} 302}
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-01 23:03:41 -0500