3 files changed, 16 insertions, 0 deletions

diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi
index bfa65abe8ef2..39eb88e9971c 100644
--- a/arch/arm/boot/dts/imx51.dtsi
+++ b/arch/arm/boot/dts/imx51.dtsi
@@ -259,6 +259,13 @@
                                 status = "disabled";
                         };
 
+                        nand@83fdb000 {
+                                compatible = "fsl,imx51-nand";
+                                reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>;
+                                interrupts = <8>;
+                                status = "disabled";
+                        };
+
                         ssi3: ssi@83fe8000 {
                                 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
                                 reg = <0x83fe8000 0x4000>;
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
index e3e869470cd3..2b5caf9fe660 100644
--- a/arch/arm/boot/dts/imx53.dtsi
+++ b/arch/arm/boot/dts/imx53.dtsi
@@ -314,6 +314,13 @@
                                 status = "disabled";
                         };
 
+                        nand@63fdb000 {
+                                compatible = "fsl,imx53-nand";
+                                reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>;
+                                interrupts = <8>;
+                                status = "disabled";
+                        };
+
                         ssi3: ssi@63fe8000 {
                                 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
                                 reg = <0x63fe8000 0x4000>;
diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c
index fcd94f3b0f0e..7b525c1230d9 100644
--- a/arch/arm/mach-imx/clk-imx51-imx53.c
+++ b/arch/arm/mach-imx/clk-imx51-imx53.c
@@ -357,6 +357,7 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
         clk_register_clkdev(clk[ssi1_ipg_gate], NULL, "83fcc000.ssi");
         clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "70014000.ssi");
         clk_register_clkdev(clk[ssi3_ipg_gate], NULL, "83fe8000.ssi");
+        clk_register_clkdev(clk[nfc_gate], NULL, "83fdb000.nand");
 
         /* set the usboh3 parent to pll2_sw */
         clk_set_parent(clk[usboh3_sel], clk[pll2_sw]);
@@ -446,6 +447,7 @@ int __init mx53_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
         clk_register_clkdev(clk[ssi1_ipg_gate], NULL, "63fcc000.ssi");
         clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "50014000.ssi");
         clk_register_clkdev(clk[ssi3_ipg_gate], NULL, "63fd0000.ssi");
+        clk_register_clkdev(clk[nfc_gate], NULL, "63fdb000.nand");
 
         /* set SDHC root clock to 200MHZ*/
         clk_set_rate(clk[esdhc_a_podf], 200000000);