257 files changed, 3564 insertions, 4933 deletions

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 5fa0cc590887..38b5d5dad8e4 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -673,6 +673,7 @@ config ARCH_TEGRA
         select HAVE_CLK
         select HAVE_SMP
         select MIGHT_HAVE_CACHE_L2X0
+        select SOC_BUS
         select SPARSE_IRQ
         select USE_OF
         help
@@ -769,12 +770,15 @@ config ARCH_SA1100
 config ARCH_S3C24XX
         bool "Samsung S3C24XX SoCs"
         select ARCH_HAS_CPUFREQ
-        select ARCH_USES_GETTIMEOFFSET
         select CLKDEV_LOOKUP
+        select CLKSRC_MMIO
+        select GENERIC_CLOCKEVENTS
+        select GENERIC_GPIO
         select HAVE_CLK
         select HAVE_S3C2410_I2C if I2C
         select HAVE_S3C2410_WATCHDOG if WATCHDOG
         select HAVE_S3C_RTC if RTC_CLASS
+        select MULTI_IRQ_HANDLER
         select NEED_MACH_GPIO_H
         select NEED_MACH_IO_H
         help
@@ -787,10 +791,11 @@ config ARCH_S3C64XX
         bool "Samsung S3C64XX"
         select ARCH_HAS_CPUFREQ
         select ARCH_REQUIRE_GPIOLIB
-        select ARCH_USES_GETTIMEOFFSET
         select ARM_VIC
         select CLKDEV_LOOKUP
+        select CLKSRC_MMIO
         select CPU_V6
+        select GENERIC_CLOCKEVENTS
         select HAVE_CLK
         select HAVE_S3C2410_I2C if I2C
         select HAVE_S3C2410_WATCHDOG if WATCHDOG
@@ -824,9 +829,11 @@ config ARCH_S5P64X0
 
 config ARCH_S5PC100
         bool "Samsung S5PC100"
-        select ARCH_USES_GETTIMEOFFSET
         select CLKDEV_LOOKUP
+        select CLKSRC_MMIO
         select CPU_V7
+        select GENERIC_CLOCKEVENTS
+        select GENERIC_GPIO
         select HAVE_CLK
         select HAVE_S3C2410_I2C if I2C
         select HAVE_S3C2410_WATCHDOG if WATCHDOG
@@ -1165,6 +1172,7 @@ config PLAT_VERSATILE
 config ARM_TIMER_SP804
         bool
         select CLKSRC_MMIO
+        select CLKSRC_OF if OF
         select HAVE_SCHED_CLOCK
 
 source arch/arm/mm/Kconfig
@@ -1595,6 +1603,7 @@ config HAVE_ARM_ARCH_TIMER
 config HAVE_ARM_TWD
         bool
         depends on SMP
+        select CLKSRC_OF if OF
         help
           This options enables support for the ARM timer and watchdog unit
 
@@ -1648,7 +1657,7 @@ config LOCAL_TIMERS
         bool "Use local timer interrupts"
         depends on SMP
         default y
-        select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
+        select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !CLKSRC_EXYNOS_MCT)
         help
           Enable support for local timers on SMP platforms, rather then the
           legacy IPI broadcast method.  Local timers allows the system
@@ -1663,7 +1672,8 @@ config ARCH_NR_GPIO
         default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
         default 512 if SOC_OMAP5
         default 355 if ARCH_U8500
-        default 288 if ARCH_VT8500 || ARCH_SUNXI
+        default 352 if ARCH_VT8500
+        default 288 if ARCH_SUNXI
         default 264 if MACH_H4700
         default 0
         help
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 234e78f7014e..e35b0a7ac77b 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -170,6 +170,8 @@ dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \
         tegra30-cardhu-a04.dtb \
         tegra114-dalmore.dtb \
         tegra114-pluto.dtb
+dtb-$(CONFIG_ARCH_VERSATILE) += versatile-ab.dtb \
+        versatile-pb.dtb
 dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2p-ca5s.dtb \
         vexpress-v2p-ca9.dtb \
         vexpress-v2p-ca15-tc1.dtb \
diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
index 2feffc70814c..49a2786e00b9 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -47,6 +47,28 @@
                              <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>;
         };
 
+        mct@10050000 {
+                compatible = "samsung,exynos4210-mct";
+                reg = <0x10050000 0x800>;
+                interrupt-controller;
+                #interrups-cells = <2>;
+                interrupt-parent = <&mct_map>;
+                interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
+                             <4 0>, <5 0>;
+
+                mct_map: mct-map {
+                        #interrupt-cells = <2>;
+                        #address-cells = <0>;
+                        #size-cells = <0>;
+                        interrupt-map = <0x0 0 &gic 0 57 0>,
+                                        <0x1 0 &gic 0 69 0>,
+                                        <0x2 0 &combiner 12 6>,
+                                        <0x3 0 &combiner 12 7>,
+                                        <0x4 0 &gic 0 42 0>,
+                                        <0x5 0 &gic 0 48 0>;
+                };
+        };
+
         pinctrl_0: pinctrl@11400000 {
                 compatible = "samsung,exynos4210-pinctrl";
                 reg = <0x11400000 0x1000>;
diff --git a/arch/arm/boot/dts/exynos4212.dtsi b/arch/arm/boot/dts/exynos4212.dtsi
index c6ae2005961f..36d4299789ef 100644
--- a/arch/arm/boot/dts/exynos4212.dtsi
+++ b/arch/arm/boot/dts/exynos4212.dtsi
@@ -25,4 +25,26 @@
         gic:interrupt-controller@10490000 {
                 cpu-offset = <0x8000>;
         };
+
+        mct@10050000 {
+                compatible = "samsung,exynos4412-mct";
+                reg = <0x10050000 0x800>;
+                interrupt-controller;
+                #interrups-cells = <2>;
+                interrupt-parent = <&mct_map>;
+                interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
+                             <4 0>, <5 0>;
+
+                mct_map: mct-map {
+                        #interrupt-cells = <2>;
+                        #address-cells = <0>;
+                        #size-cells = <0>;
+                        interrupt-map = <0x0 0 &gic 0 57 0>,
+                                        <0x1 0 &combiner 12 5>,
+                                        <0x2 0 &combiner 12 6>,
+                                        <0x3 0 &combiner 12 7>,
+                                        <0x4 0 &gic 1 12 0>,
+                                        <0x5 0 &gic 1 12 0>;
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi
index d7dfe312772a..821c9fdd1e3b 100644
--- a/arch/arm/boot/dts/exynos4412.dtsi
+++ b/arch/arm/boot/dts/exynos4412.dtsi
@@ -25,4 +25,28 @@
         gic:interrupt-controller@10490000 {
                 cpu-offset = <0x4000>;
         };
+
+        mct@10050000 {
+                compatible = "samsung,exynos4412-mct";
+                reg = <0x10050000 0x800>;
+                interrupt-controller;
+                #interrups-cells = <2>;
+                interrupt-parent = <&mct_map>;
+                interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
+                             <4 0>, <5 0>, <6 0>, <7 0>;
+
+                mct_map: mct-map {
+                        #interrupt-cells = <2>;
+                        #address-cells = <0>;
+                        #size-cells = <0>;
+                        interrupt-map = <0x0 0 &gic 0 57 0>,
+                                        <0x1 0 &combiner 12 5>,
+                                        <0x2 0 &combiner 12 6>,
+                                        <0x3 0 &combiner 12 7>,
+                                        <0x4 0 &gic 1 12 0>,
+                                        <0x5 0 &gic 1 12 0>,
+                                        <0x6 0 &gic 1 12 0>,
+                                        <0x7 0 &gic 1 12 0>;
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index b1ac73e21c80..c60108e0d27e 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -69,6 +69,28 @@
                              <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>;
         };
 
+        mct@101C0000 {
+                compatible = "samsung,exynos4210-mct";
+                reg = <0x101C0000 0x800>;
+                interrupt-controller;
+                #interrups-cells = <2>;
+                interrupt-parent = <&mct_map>;
+                interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
+                             <4 0>, <5 0>;
+
+                mct_map: mct-map {
+                        #interrupt-cells = <2>;
+                        #address-cells = <0>;
+                        #size-cells = <0>;
+                        interrupt-map = <0x0 0 &combiner 23 3>,
+                                        <0x1 0 &combiner 23 4>,
+                                        <0x2 0 &combiner 25 2>,
+                                        <0x3 0 &combiner 25 3>,
+                                        <0x4 0 &gic 0 120 0>,
+                                        <0x5 0 &gic 0 121 0>;
+                };
+        };
+
         watchdog {
                 compatible = "samsung,s3c2410-wdt";
                 reg = <0x101D0000 0x100>;
diff --git a/arch/arm/boot/dts/integratorcp.dts b/arch/arm/boot/dts/integratorcp.dts
index 8b119399025a..ff1aea0ee043 100644
--- a/arch/arm/boot/dts/integratorcp.dts
+++ b/arch/arm/boot/dts/integratorcp.dts
@@ -24,15 +24,15 @@
         };
 
         timer0: timer@13000000 {
-                compatible = "arm,sp804", "arm,primecell";
+                compatible = "arm,integrator-cp-timer";
         };
 
         timer1: timer@13000100 {
-                compatible = "arm,sp804", "arm,primecell";
+                compatible = "arm,integrator-cp-timer";
         };
 
         timer2: timer@13000200 {
-                compatible = "arm,sp804", "arm,primecell";
+                compatible = "arm,integrator-cp-timer";
         };
 
         pic: pic@14000000 {
diff --git a/arch/arm/boot/dts/omap3-beagle.dts b/arch/arm/boot/dts/omap3-beagle.dts
index f624dc85d441..02d23f15fd86 100644
--- a/arch/arm/boot/dts/omap3-beagle.dts
+++ b/arch/arm/boot/dts/omap3-beagle.dts
@@ -38,6 +38,57 @@
                 };
         };
 
+        /* HS USB Port 2 RESET */
+        hsusb2_reset: hsusb2_reset_reg {
+                compatible = "regulator-fixed";
+                regulator-name = "hsusb2_reset";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                gpio = <&gpio5 19 0>;   /* gpio_147 */
+                startup-delay-us = <70000>;
+                enable-active-high;
+        };
+
+        /* HS USB Port 2 Power */
+        hsusb2_power: hsusb2_power_reg {
+                compatible = "regulator-fixed";
+                regulator-name = "hsusb2_vbus";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                gpio = <&twl_gpio 18 0>;        /* GPIO LEDA */
+                startup-delay-us = <70000>;
+        };
+
+        /* HS USB Host PHY on PORT 2 */
+        hsusb2_phy: hsusb2_phy {
+                compatible = "usb-nop-xceiv";
+                reset-supply = <&hsusb2_reset>;
+                vcc-supply = <&hsusb2_power>;
+        };
+};
+
+&omap3_pmx_core {
+        pinctrl-names = "default";
+        pinctrl-0 = <
+                        &hsusbb2_pins
+        >;
+
+        hsusbb2_pins: pinmux_hsusbb2_pins {
+                pinctrl-single,pins = <
+                        0x5c0 0x3  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_clk OUTPUT */
+                        0x5c2 0x3  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_stp OUTPUT */
+                        0x5c4 0x10b  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dir INPUT | PULLDOWN */
+                        0x5c6 0x10b  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_nxt INPUT | PULLDOWN */
+                        0x5c8 0x10b  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat0 INPUT | PULLDOWN */
+                        0x5cA 0x10b  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat1 INPUT | PULLDOWN */
+                        0x1a4 0x10b  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat2 INPUT | PULLDOWN */
+                        0x1a6 0x10b  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat3 INPUT | PULLDOWN */
+                        0x1a8 0x10b  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat4 INPUT | PULLDOWN */
+                        0x1aa 0x10b  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat5 INPUT | PULLDOWN */
+                        0x1ac 0x10b  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat6 INPUT | PULLDOWN */
+                        0x1ae 0x10b  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat7 INPUT | PULLDOWN */
+                >;
+        };
 };
 
 &i2c1 {
@@ -65,3 +116,23 @@
 &mmc3 {
         status = "disabled";
 };
+
+&usbhshost {
+        port2-mode = "ehci-phy";
+};
+
+&usbhsehci {
+        phys = <0 &hsusb2_phy>;
+};
+
+&twl_gpio {
+        ti,use-leds;
+        /* pullups: BIT(1) */
+        ti,pullups = <0x000002>;
+        /*
+         * pulldowns:
+         * BIT(2), BIT(6), BIT(7), BIT(8), BIT(13)
+         * BIT(15), BIT(16), BIT(17)
+         */
+        ti,pulldowns = <0x03a1c4>;
+};
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index 1acc26148ffc..a14f74bbce7c 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -397,5 +397,36 @@
                         ti,timer-alwon;
                         ti,timer-secure;
                 };
+
+                usbhstll: usbhstll@48062000 {
+                        compatible = "ti,usbhs-tll";
+                        reg = <0x48062000 0x1000>;
+                        interrupts = <78>;
+                        ti,hwmods = "usb_tll_hs";
+                };
+
+                usbhshost: usbhshost@48064000 {
+                        compatible = "ti,usbhs-host";
+                        reg = <0x48064000 0x400>;
+                        ti,hwmods = "usb_host_hs";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges;
+
+                        usbhsohci: ohci@48064400 {
+                                compatible = "ti,ohci-omap3", "usb-ohci";
+                                reg = <0x48064400 0x400>;
+                                interrupt-parent = <&intc>;
+                                interrupts = <76>;
+                        };
+
+                        usbhsehci: ehci@48064800 {
+                                compatible = "ti,ehci-omap", "usb-ehci";
+                                reg = <0x48064800 0x400>;
+                                interrupt-parent = <&intc>;
+                                interrupts = <77>;
+                        };
+                };
+
         };
 };
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 739bb79e410e..b7db1a2b6ca7 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -529,5 +529,35 @@
                         ti,hwmods = "timer11";
                         ti,timer-pwm;
                 };
+
+                usbhstll: usbhstll@4a062000 {
+                        compatible = "ti,usbhs-tll";
+                        reg = <0x4a062000 0x1000>;
+                        interrupts = <0 78 0x4>;
+                        ti,hwmods = "usb_tll_hs";
+                };
+
+                usbhshost: usbhshost@4a064000 {
+                        compatible = "ti,usbhs-host";
+                        reg = <0x4a064000 0x800>;
+                        ti,hwmods = "usb_host_hs";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges;
+
+                        usbhsohci: ohci@4a064800 {
+                                compatible = "ti,ohci-omap3", "usb-ohci";
+                                reg = <0x4a064800 0x400>;
+                                interrupt-parent = <&gic>;
+                                interrupts = <0 76 0x4>;
+                        };
+
+                        usbhsehci: ehci@4a064c00 {
+                                compatible = "ti,ehci-omap", "usb-ehci";
+                                reg = <0x4a064c00 0x400>;
+                                interrupt-parent = <&gic>;
+                                interrupts = <0 77 0x4>;
+                        };
+                };
         };
 };
diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi
new file mode 100644
index 000000000000..fe5c6f213271
--- /dev/null
+++ b/arch/arm/boot/dts/r8a7779.dtsi
@@ -0,0 +1,98 @@
+/*
+ * Device Tree Source for Renesas r8a7779
+ *
+ * Copyright (C) 2013 Renesas Solutions Corp.
+ * Copyright (C) 2013 Simon Horman
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+        compatible = "renesas,r8a7779";
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                cpu@0 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a9";
+                        reg = <0>;
+                };
+                cpu@1 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a9";
+                        reg = <1>;
+                };
+                cpu@2 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a9";
+                        reg = <2>;
+                };
+                cpu@3 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a9";
+                        reg = <3>;
+                };
+        };
+
+        gic: interrupt-controller@f0001000 {
+                compatible = "arm,cortex-a9-gic";
+                #interrupt-cells = <3>;
+                interrupt-controller;
+                reg = <0xf0001000 0x1000>,
+                      <0xf0000100 0x100>;
+        };
+
+        i2c0: i2c@0xffc70000 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "renesas,rmobile-iic";
+                reg = <0xffc70000 0x1000>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 79 0x4>;
+        };
+
+        i2c1: i2c@0xffc71000 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "renesas,rmobile-iic";
+                reg = <0xffc71000 0x1000>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 82 0x4>;
+        };
+
+        i2c2: i2c@0xffc72000 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "renesas,rmobile-iic";
+                reg = <0xffc72000 0x1000>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 80 0x4>;
+        };
+
+        i2c3: i2c@0xffc73000 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "renesas,rmobile-iic";
+                reg = <0xffc73000 0x1000>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 81 0x4>;
+        };
+
+        thermal@ffc48000 {
+                compatible = "renesas,rcar-thermal";
+                reg = <0xffc48000 0x38>;
+        };
+
+        sata: sata@fc600000 {
+                compatible = "renesas,rcar-sata";
+                reg = <0xfc600000 0x2000>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 100 0x4>;
+        };
+};
diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts b/arch/arm/boot/dts/tegra114-dalmore.dts
index a30aca62658a..616990dc92db 100644
--- a/arch/arm/boot/dts/tegra114-dalmore.dts
+++ b/arch/arm/boot/dts/tegra114-dalmore.dts
@@ -12,10 +12,22 @@
 
         serial@70006300 {
                 status = "okay";
-                clock-frequency = <408000000>;
         };
 
         pmc {
                 nvidia,invert-interrupt;
         };
+
+        clocks {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                clk32k_in: clock {
+                        compatible = "fixed-clock";
+                        reg=<0>;
+                        #clock-cells = <0>;
+                        clock-frequency = <32768>;
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/tegra114-pluto.dts b/arch/arm/boot/dts/tegra114-pluto.dts
index 9bea8f57aa47..6bbc8efae9c0 100644
--- a/arch/arm/boot/dts/tegra114-pluto.dts
+++ b/arch/arm/boot/dts/tegra114-pluto.dts
@@ -12,10 +12,22 @@
 
         serial@70006300 {
                 status = "okay";
-                clock-frequency = <408000000>;
         };
 
         pmc {
                 nvidia,invert-interrupt;
         };
+
+        clocks {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                clk32k_in: clock {
+                        compatible = "fixed-clock";
+                        reg=<0>;
+                        #clock-cells = <0>;
+                        clock-frequency = <32768>;
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi
index 1dfaf2874c57..c1110a9b2a91 100644
--- a/arch/arm/boot/dts/tegra114.dtsi
+++ b/arch/arm/boot/dts/tegra114.dtsi
@@ -24,10 +24,11 @@
                               0 42 0x04
                               0 121 0x04
                               0 122 0x04>;
+                clocks = <&tegra_car 5>;
         };
 
         tegra_car: clock {
-                compatible = "nvidia,tegra114-car, nvidia,tegra30-car";
+                compatible = "nvidia,tegra114-car";
                 reg = <0x60006000 0x1000>;
                 #clock-cells = <1>;
         };
@@ -66,6 +67,7 @@
                 reg-shift = <2>;
                 interrupts = <0 36 0x04>;
                 status = "disabled";
+                clocks = <&tegra_car 6>;
         };
 
         serial@70006040 {
@@ -74,6 +76,7 @@
                 reg-shift = <2>;
                 interrupts = <0 37 0x04>;
                 status = "disabled";
+                clocks = <&tegra_car 192>;
         };
 
         serial@70006200 {
@@ -82,6 +85,7 @@
                 reg-shift = <2>;
                 interrupts = <0 46 0x04>;
                 status = "disabled";
+                clocks = <&tegra_car 55>;
         };
 
         serial@70006300 {
@@ -90,17 +94,21 @@
                 reg-shift = <2>;
                 interrupts = <0 90 0x04>;
                 status = "disabled";
+                clocks = <&tegra_car 65>;
         };
 
         rtc {
                 compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc";
                 reg = <0x7000e000 0x100>;
                 interrupts = <0 2 0x04>;
+                clocks = <&tegra_car 4>;
         };
 
         pmc {
-                compatible = "nvidia,tegra114-pmc", "nvidia,tegra30-pmc";
+                compatible = "nvidia,tegra114-pmc";
                 reg = <0x7000e400 0x400>;
+                clocks = <&tegra_car 261>, <&clk32k_in>;
+                clock-names = "pclk", "clk32k_in";
         };
 
         iommu {
diff --git a/arch/arm/boot/dts/tegra20-colibri-512.dtsi b/arch/arm/boot/dts/tegra20-colibri-512.dtsi
index 444162090042..4e3afdef28a8 100644
--- a/arch/arm/boot/dts/tegra20-colibri-512.dtsi
+++ b/arch/arm/boot/dts/tegra20-colibri-512.dtsi
@@ -444,7 +444,20 @@
         };
 
         sdhci@c8000600 {
-                cd-gpios = <&gpio 23 0>; /* gpio PC7 */
+                cd-gpios = <&gpio 23 1>; /* gpio PC7 */
+        };
+
+        clocks {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                clk32k_in: clock {
+                        compatible = "fixed-clock";
+                        reg=<0>;
+                        #clock-cells = <0>;
+                        clock-frequency = <32768>;
+                };
         };
 
         sound {
diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts
index 61d027f03617..ae9d5a20834e 100644
--- a/arch/arm/boot/dts/tegra20-harmony.dts
+++ b/arch/arm/boot/dts/tegra20-harmony.dts
@@ -437,7 +437,7 @@
 
         sdhci@c8000200 {
                 status = "okay";
-                cd-gpios = <&gpio 69 0>; /* gpio PI5 */
+                cd-gpios = <&gpio 69 1>; /* gpio PI5 */
                 wp-gpios = <&gpio 57 0>; /* gpio PH1 */
                 power-gpios = <&gpio 155 0>; /* gpio PT3 */
                 bus-width = <4>;
@@ -445,12 +445,25 @@
 
         sdhci@c8000600 {
                 status = "okay";
-                cd-gpios = <&gpio 58 0>; /* gpio PH2 */
+                cd-gpios = <&gpio 58 1>; /* gpio PH2 */
                 wp-gpios = <&gpio 59 0>; /* gpio PH3 */
                 power-gpios = <&gpio 70 0>; /* gpio PI6 */
                 bus-width = <8>;
         };
 
+        clocks {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                clk32k_in: clock {
+                        compatible = "fixed-clock";
+                        reg=<0>;
+                        #clock-cells = <0>;
+                        clock-frequency = <32768>;
+                };
+        };
+
         kbc {
                 status = "okay";
                 nvidia,debounce-delay-ms = <2>;
diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts
index 54d6fce00a59..fd60940e4063 100644
--- a/arch/arm/boot/dts/tegra20-paz00.dts
+++ b/arch/arm/boot/dts/tegra20-paz00.dts
@@ -436,7 +436,7 @@
 
         sdhci@c8000000 {
                 status = "okay";
-                cd-gpios = <&gpio 173 0>; /* gpio PV5 */
+                cd-gpios = <&gpio 173 1>; /* gpio PV5 */
                 wp-gpios = <&gpio 57 0>;  /* gpio PH1 */
                 power-gpios = <&gpio 169 0>; /* gpio PV1 */
                 bus-width = <4>;
@@ -447,6 +447,19 @@
                 bus-width = <8>;
         };
 
+        clocks {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                clk32k_in: clock {
+                        compatible = "fixed-clock";
+                        reg=<0>;
+                        #clock-cells = <0>;
+                        clock-frequency = <32768>;
+                };
+        };
+
         gpio-keys {
                 compatible = "gpio-keys";
 
diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts
index 37b3a57ec0f1..4ee700a33ca5 100644
--- a/arch/arm/boot/dts/tegra20-seaboard.dts
+++ b/arch/arm/boot/dts/tegra20-seaboard.dts
@@ -584,7 +584,7 @@
 
         sdhci@c8000400 {
                 status = "okay";
-                cd-gpios = <&gpio 69 0>; /* gpio PI5 */
+                cd-gpios = <&gpio 69 1>; /* gpio PI5 */
                 wp-gpios = <&gpio 57 0>; /* gpio PH1 */
                 power-gpios = <&gpio 70 0>; /* gpio PI6 */
                 bus-width = <4>;
@@ -595,6 +595,19 @@
                 bus-width = <8>;
         };
 
+        clocks {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                clk32k_in: clock {
+                        compatible = "fixed-clock";
+                        reg=<0>;
+                        #clock-cells = <0>;
+                        clock-frequency = <32768>;
+                };
+        };
+
         gpio-keys {
                 compatible = "gpio-keys";
 
diff --git a/arch/arm/boot/dts/tegra20-tamonten.dtsi b/arch/arm/boot/dts/tegra20-tamonten.dtsi
index 4766abae7a72..c19025725918 100644
--- a/arch/arm/boot/dts/tegra20-tamonten.dtsi
+++ b/arch/arm/boot/dts/tegra20-tamonten.dtsi
@@ -465,12 +465,25 @@
         };
 
         sdhci@c8000600 {
-                cd-gpios = <&gpio 58 0>; /* gpio PH2 */
+                cd-gpios = <&gpio 58 1>; /* gpio PH2 */
                 wp-gpios = <&gpio 59 0>; /* gpio PH3 */
                 bus-width = <4>;
                 status = "okay";
         };
 
+        clocks {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                clk32k_in: clock {
+                        compatible = "fixed-clock";
+                        reg=<0>;
+                        #clock-cells = <0>;
+                        clock-frequency = <32768>;
+                };
+        };
+
         regulators {
                 compatible = "simple-bus";
 
diff --git a/arch/arm/boot/dts/tegra20-trimslice.dts b/arch/arm/boot/dts/tegra20-trimslice.dts
index 5d79e4fc49a6..a9f3f06580f5 100644
--- a/arch/arm/boot/dts/tegra20-trimslice.dts
+++ b/arch/arm/boot/dts/tegra20-trimslice.dts
@@ -325,11 +325,24 @@
 
         sdhci@c8000600 {
                 status = "okay";
-                cd-gpios = <&gpio 121 0>; /* gpio PP1 */
+                cd-gpios = <&gpio 121 1>; /* gpio PP1 */
                 wp-gpios = <&gpio 122 0>; /* gpio PP2 */
                 bus-width = <4>;
         };
 
+        clocks {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                clk32k_in: clock {
+                        compatible = "fixed-clock";
+                        reg=<0>;
+                        #clock-cells = <0>;
+                        clock-frequency = <32768>;
+                };
+        };
+
         poweroff {
                 compatible = "gpio-poweroff";
                 gpios = <&gpio 191 1>; /* gpio PX7, active low */
diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts
index 425c89000c20..f544806e9618 100644
--- a/arch/arm/boot/dts/tegra20-ventana.dts
+++ b/arch/arm/boot/dts/tegra20-ventana.dts
@@ -520,7 +520,7 @@
 
         sdhci@c8000400 {
                 status = "okay";
-                cd-gpios = <&gpio 69 0>; /* gpio PI5 */
+                cd-gpios = <&gpio 69 1>; /* gpio PI5 */
                 wp-gpios = <&gpio 57 0>; /* gpio PH1 */
                 power-gpios = <&gpio 70 0>; /* gpio PI6 */
                 bus-width = <4>;
@@ -531,6 +531,19 @@
                 bus-width = <8>;
         };
 
+        clocks {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                clk32k_in: clock {
+                        compatible = "fixed-clock";
+                        reg=<0>;
+                        #clock-cells = <0>;
+                        clock-frequency = <32768>;
+                };
+        };
+
         regulators {
                 compatible = "simple-bus";
                 #address-cells = <1>;
diff --git a/arch/arm/boot/dts/tegra20-whistler.dts b/arch/arm/boot/dts/tegra20-whistler.dts
index ea57c0f6dcce..258cf945f515 100644
--- a/arch/arm/boot/dts/tegra20-whistler.dts
+++ b/arch/arm/boot/dts/tegra20-whistler.dts
@@ -510,6 +510,7 @@
 
         sdhci@c8000400 {
                 status = "okay";
+                cd-gpios = <&gpio 69 1>; /* gpio PI5 */
                 wp-gpios = <&gpio 173 0>; /* gpio PV5 */
                 bus-width = <8>;
         };
@@ -519,6 +520,19 @@
                 bus-width = <8>;
         };
 
+        clocks {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                clk32k_in: clock {
+                        compatible = "fixed-clock";
+                        reg=<0>;
+                        #clock-cells = <0>;
+                        clock-frequency = <32768>;
+                };
+        };
+
         kbc {
                 status = "okay";
                 nvidia,debounce-delay-ms = <20>;
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 3d3f64d2111a..fc7febc2b386 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -145,6 +145,7 @@
                               0 1 0x04
                               0 41 0x04
                               0 42 0x04>;
+                clocks = <&tegra_car 5>;
         };
 
         tegra_car: clock {
@@ -304,6 +305,7 @@
                 compatible = "nvidia,tegra20-rtc";
                 reg = <0x7000e000 0x100>;
                 interrupts = <0 2 0x04>;
+                clocks = <&tegra_car 4>;
         };
 
         i2c@7000c000 {
@@ -416,6 +418,8 @@
         pmc {
                 compatible = "nvidia,tegra20-pmc";
                 reg = <0x7000e400 0x400>;
+                clocks = <&tegra_car 110>, <&clk32k_in>;
+                clock-names = "pclk", "clk32k_in";
         };
 
         memory-controller@7000f000 {
diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts
index 8ff2ff20e4a3..6248b2445b32 100644
--- a/arch/arm/boot/dts/tegra30-beaver.dts
+++ b/arch/arm/boot/dts/tegra30-beaver.dts
@@ -257,7 +257,7 @@
 
         sdhci@78000000 {
                 status = "okay";
-                cd-gpios = <&gpio 69 0>; /* gpio PI5 */
+                cd-gpios = <&gpio 69 1>; /* gpio PI5 */
                 wp-gpios = <&gpio 155 0>; /* gpio PT3 */
                 power-gpios = <&gpio 31 0>; /* gpio PD7 */
                 bus-width = <4>;
@@ -268,6 +268,19 @@
                 bus-width = <8>;
         };
 
+        clocks {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                clk32k_in: clock {
+                        compatible = "fixed-clock";
+                        reg=<0>;
+                        #clock-cells = <0>;
+                        clock-frequency = <32768>;
+                };
+        };
+
         regulators {
                 compatible = "simple-bus";
                 #address-cells = <1>;
diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi
index 17499272a4ef..65bf2b63174e 100644
--- a/arch/arm/boot/dts/tegra30-cardhu.dtsi
+++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi
@@ -311,7 +311,7 @@
 
         sdhci@78000000 {
                 status = "okay";
-                cd-gpios = <&gpio 69 0>; /* gpio PI5 */
+                cd-gpios = <&gpio 69 1>; /* gpio PI5 */
                 wp-gpios = <&gpio 155 0>; /* gpio PT3 */
                 power-gpios = <&gpio 31 0>; /* gpio PD7 */
                 bus-width = <4>;
@@ -322,6 +322,19 @@
                 bus-width = <8>;
         };
 
+        clocks {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                clk32k_in: clock {
+                        compatible = "fixed-clock";
+                        reg=<0>;
+                        #clock-cells = <0>;
+                        clock-frequency = <32768>;
+                };
+        };
+
         regulators {
                 compatible = "simple-bus";
                 #address-cells = <1>;
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index dbf46c272562..9fe7a92b4c85 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -148,6 +148,7 @@
                               0 42 0x04
                               0 121 0x04
                               0 122 0x04>;
+                clocks = <&tegra_car 5>;
         };
 
         tegra_car: clock {
@@ -291,6 +292,7 @@
                 compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc";
                 reg = <0x7000e000 0x100>;
                 interrupts = <0 2 0x04>;
+                clocks = <&tegra_car 4>;
         };
 
         i2c@7000c000 {
@@ -423,8 +425,10 @@
         };
 
         pmc {
-                compatible = "nvidia,tegra20-pmc", "nvidia,tegra30-pmc";
+                compatible = "nvidia,tegra30-pmc";
                 reg = <0x7000e400 0x400>;
+                clocks = <&tegra_car 218>, <&clk32k_in>;
+                clock-names = "pclk", "clk32k_in";
         };
 
         memory-controller {
diff --git a/arch/arm/boot/dts/versatile-ab.dts b/arch/arm/boot/dts/versatile-ab.dts
index e2fe3195c0d1..dde75ae8b4b1 100644
--- a/arch/arm/boot/dts/versatile-ab.dts
+++ b/arch/arm/boot/dts/versatile-ab.dts
@@ -121,6 +121,18 @@
                         interrupts = <0>;
                 };
 
+                timer@101e2000 {
+                        compatible = "arm,sp804", "arm,primecell";
+                        reg = <0x101e2000 0x1000>;
+                        interrupts = <4>;
+                };
+
+                timer@101e3000 {
+                        compatible = "arm,sp804", "arm,primecell";
+                        reg = <0x101e3000 0x1000>;
+                        interrupts = <5>;
+                };
+
                 gpio0: gpio@101e4000 {
                         compatible = "arm,pl061", "arm,primecell";
                         reg = <0x101e4000 0x1000>;
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca9.dts b/arch/arm/boot/dts/vexpress-v2p-ca9.dts
index 1420bb14d95c..62d9b225dcce 100644
--- a/arch/arm/boot/dts/vexpress-v2p-ca9.dts
+++ b/arch/arm/boot/dts/vexpress-v2p-ca9.dts
@@ -98,6 +98,7 @@
                              <0 49 4>;
                 clocks = <&oscclk2>, <&oscclk2>;
                 clock-names = "timclk", "apb_pclk";
+                status = "disabled";
         };
 
         watchdog@100e5000 {
diff --git a/arch/arm/boot/dts/vt8500.dtsi b/arch/arm/boot/dts/vt8500.dtsi
index cf31ced46602..e1c3926aca52 100644
--- a/arch/arm/boot/dts/vt8500.dtsi
+++ b/arch/arm/boot/dts/vt8500.dtsi
@@ -25,11 +25,13 @@
                         #interrupt-cells = <1>;
                 };
 
-                gpio: gpio-controller@d8110000 {
-                        compatible = "via,vt8500-gpio";
-                        gpio-controller;
+                pinctrl: pinctrl@d8110000 {
+                        compatible = "via,vt8500-pinctrl";
                         reg = <0xd8110000 0x10000>;
-                        #gpio-cells = <3>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
                 };
 
                 pmc@d8130000 {
diff --git a/arch/arm/boot/dts/wm8505.dtsi b/arch/arm/boot/dts/wm8505.dtsi
index e74a1c0fb9a2..bb92ef8ce665 100644
--- a/arch/arm/boot/dts/wm8505.dtsi
+++ b/arch/arm/boot/dts/wm8505.dtsi
@@ -40,11 +40,13 @@
                         interrupts = <56 57 58 59 60 61 62 63>;
                 };
 
-                gpio: gpio-controller@d8110000 {
-                        compatible = "wm,wm8505-gpio";
-                        gpio-controller;
+                pinctrl: pinctrl@d8110000 {
+                        compatible = "wm,wm8505-pinctrl";
                         reg = <0xd8110000 0x10000>;
-                        #gpio-cells = <3>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
                 };
 
                 pmc@d8130000 {
diff --git a/arch/arm/boot/dts/wm8650.dtsi b/arch/arm/boot/dts/wm8650.dtsi
index db3c0a12e052..bb4af580f40b 100644
--- a/arch/arm/boot/dts/wm8650.dtsi
+++ b/arch/arm/boot/dts/wm8650.dtsi
@@ -34,11 +34,13 @@
                         interrupts = <56 57 58 59 60 61 62 63>;
                 };
 
-                gpio: gpio-controller@d8110000 {
-                        compatible = "wm,wm8650-gpio";
-                        gpio-controller;
+                pinctrl: pinctrl@d8110000 {
+                        compatible = "wm,wm8650-pinctrl";
                         reg = <0xd8110000 0x10000>;
-                        #gpio-cells = <3>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
                 };
 
                 pmc@d8130000 {
diff --git a/arch/arm/boot/dts/wm8850.dtsi b/arch/arm/boot/dts/wm8850.dtsi
index e8cbfdc87bba..11cd180c58d3 100644
--- a/arch/arm/boot/dts/wm8850.dtsi
+++ b/arch/arm/boot/dts/wm8850.dtsi
@@ -41,11 +41,13 @@
                         interrupts = <56 57 58 59 60 61 62 63>;
                 };
 
-                gpio: gpio-controller@d8110000 {
-                        compatible = "wm,wm8650-gpio";
-                        gpio-controller;
+                pinctrl: pinctrl@d8110000 {
+                        compatible = "wm,wm8850-pinctrl";
                         reg = <0xd8110000 0x10000>;
-                        #gpio-cells = <3>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
                 };
 
                 pmc@d8130000 {
diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi
index 5914b5654591..51243db2e9e4 100644
--- a/arch/arm/boot/dts/zynq-7000.dtsi
+++ b/arch/arm/boot/dts/zynq-7000.dtsi
@@ -111,56 +111,23 @@
                 };
 
                 ttc0: ttc0@f8001000 {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        compatible = "xlnx,ttc";
+                        interrupt-parent = <&intc>;
+                        interrupts = < 0 10 4 0 11 4 0 12 4 >;
+                        compatible = "cdns,ttc";
                         reg = <0xF8001000 0x1000>;
                         clocks = <&cpu_clk 3>;
                         clock-names = "cpu_1x";
                         clock-ranges;
-
-                        ttc0_0: ttc0.0 {
-                                status = "disabled";
-                                reg = <0>;
-                                interrupts = <0 10 4>;
-                        };
-                        ttc0_1: ttc0.1 {
-                                status = "disabled";
-                                reg = <1>;
-                                interrupts = <0 11 4>;
-                        };
-                        ttc0_2: ttc0.2 {
-                                status = "disabled";
-                                reg = <2>;
-                                interrupts = <0 12 4>;
-                        };
                 };
 
                 ttc1: ttc1@f8002000 {
-                        #interrupt-parent = <&intc>;
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        compatible = "xlnx,ttc";
+                        interrupt-parent = <&intc>;
+                        interrupts = < 0 37 4 0 38 4 0 39 4 >;
+                        compatible = "cdns,ttc";
                         reg = <0xF8002000 0x1000>;
                         clocks = <&cpu_clk 3>;
                         clock-names = "cpu_1x";
                         clock-ranges;
-
-                        ttc1_0: ttc1.0 {
-                                status = "disabled";
-                                reg = <0>;
-                                interrupts = <0 37 4>;
-                        };
-                        ttc1_1: ttc1.1 {
-                                status = "disabled";
-                                reg = <1>;
-                                interrupts = <0 38 4>;
-                        };
-                        ttc1_2: ttc1.2 {
-                                status = "disabled";
-                                reg = <2>;
-                                interrupts = <0 39 4>;
-                        };
                 };
         };
 };
diff --git a/arch/arm/boot/dts/zynq-zc702.dts b/arch/arm/boot/dts/zynq-zc702.dts
index c772942a399a..86f44d5b0265 100644
--- a/arch/arm/boot/dts/zynq-zc702.dts
+++ b/arch/arm/boot/dts/zynq-zc702.dts
@@ -32,13 +32,3 @@
 &ps_clk {
         clock-frequency = <33333330>;
 };
-
-&ttc0_0 {
-        status = "ok";
-        compatible = "xlnx,ttc-counter-clocksource";
-};
-
-&ttc0_1 {
-        status = "ok";
-        compatible = "xlnx,ttc-counter-clockevent";
-};
diff --git a/arch/arm/common/timer-sp.c b/arch/arm/common/timer-sp.c
index 9d2d3ba339ff..ddc740769601 100644
--- a/arch/arm/common/timer-sp.c
+++ b/arch/arm/common/timer-sp.c
@@ -25,33 +25,29 @@
 #include <linux/interrupt.h>
 #include <linux/irq.h>
 #include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
 
 #include <asm/sched_clock.h>
 #include <asm/hardware/arm_timer.h>
+#include <asm/hardware/timer-sp.h>
 
-static long __init sp804_get_clock_rate(const char *name)
+static long __init sp804_get_clock_rate(struct clk *clk)
 {
-        struct clk *clk;
         long rate;
         int err;
 
-        clk = clk_get_sys("sp804", name);
-        if (IS_ERR(clk)) {
-                pr_err("sp804: %s clock not found: %d\n", name,
-                        (int)PTR_ERR(clk));
-                return PTR_ERR(clk);
-        }
-
         err = clk_prepare(clk);
         if (err) {
-                pr_err("sp804: %s clock failed to prepare: %d\n", name, err);
+                pr_err("sp804: clock failed to prepare: %d\n", err);
                 clk_put(clk);
                 return err;
         }
 
         err = clk_enable(clk);
         if (err) {
-                pr_err("sp804: %s clock failed to enable: %d\n", name, err);
+                pr_err("sp804: clock failed to enable: %d\n", err);
                 clk_unprepare(clk);
                 clk_put(clk);
                 return err;
@@ -59,7 +55,7 @@ static long __init sp804_get_clock_rate(const char *name)
 
         rate = clk_get_rate(clk);
         if (rate < 0) {
-                pr_err("sp804: %s clock failed to get rate: %ld\n", name, rate);
+                pr_err("sp804: clock failed to get rate: %ld\n", rate);
                 clk_disable(clk);
                 clk_unprepare(clk);
                 clk_put(clk);
@@ -77,9 +73,21 @@ static u32 sp804_read(void)
 
 void __init __sp804_clocksource_and_sched_clock_init(void __iomem *base,
                                                      const char *name,
+                                                     struct clk *clk,
                                                      int use_sched_clock)
 {
-        long rate = sp804_get_clock_rate(name);
+        long rate;
+
+        if (!clk) {
+                clk = clk_get_sys("sp804", name);
+                if (IS_ERR(clk)) {
+                        pr_err("sp804: clock not found: %d\n",
+                               (int)PTR_ERR(clk));
+                        return;
+                }
+        }
+
+        rate = sp804_get_clock_rate(clk);
 
         if (rate < 0)
                 return;
@@ -171,12 +179,20 @@ static struct irqaction sp804_timer_irq = {
         .dev_id         = &sp804_clockevent,
 };
 
-void __init sp804_clockevents_init(void __iomem *base, unsigned int irq,
-        const char *name)
+void __init __sp804_clockevents_init(void __iomem *base, unsigned int irq, struct clk *clk, const char *name)
 {
         struct clock_event_device *evt = &sp804_clockevent;
-        long rate = sp804_get_clock_rate(name);
+        long rate;
 
+        if (!clk)
+                clk = clk_get_sys("sp804", name);
+        if (IS_ERR(clk)) {
+                pr_err("sp804: %s clock not found: %d\n", name,
+                        (int)PTR_ERR(clk));
+                return;
+        }
+
+        rate = sp804_get_clock_rate(clk);
         if (rate < 0)
                 return;
 
@@ -186,6 +202,98 @@ void __init sp804_clockevents_init(void __iomem *base, unsigned int irq,
         evt->irq = irq;
         evt->cpumask = cpu_possible_mask;
 
+        writel(0, base + TIMER_CTRL);
+
         setup_irq(irq, &sp804_timer_irq);
         clockevents_config_and_register(evt, rate, 0xf, 0xffffffff);
 }
+
+static void __init sp804_of_init(struct device_node *np)
+{
+        static bool initialized = false;
+        void __iomem *base;
+        int irq;
+        u32 irq_num = 0;
+        struct clk *clk1, *clk2;
+        const char *name = of_get_property(np, "compatible", NULL);
+
+        base = of_iomap(np, 0);
+        if (WARN_ON(!base))
+                return;
+
+        /* Ensure timers are disabled */
+        writel(0, base + TIMER_CTRL);
+        writel(0, base + TIMER_2_BASE + TIMER_CTRL);
+
+        if (initialized || !of_device_is_available(np))
+                goto err;
+
+        clk1 = of_clk_get(np, 0);
+        if (IS_ERR(clk1))
+                clk1 = NULL;
+
+        /* Get the 2nd clock if the timer has 2 timer clocks */
+        if (of_count_phandle_with_args(np, "clocks", "#clock-cells") == 3) {
+                clk2 = of_clk_get(np, 1);
+                if (IS_ERR(clk2)) {
+                        pr_err("sp804: %s clock not found: %d\n", np->name,
+                                (int)PTR_ERR(clk2));
+                        goto err;
+                }
+        } else
+                clk2 = clk1;
+
+        irq = irq_of_parse_and_map(np, 0);
+        if (irq <= 0)
+                goto err;
+
+        of_property_read_u32(np, "arm,sp804-has-irq", &irq_num);
+        if (irq_num == 2) {
+                __sp804_clockevents_init(base + TIMER_2_BASE, irq, clk2, name);
+                __sp804_clocksource_and_sched_clock_init(base, name, clk1, 1);
+        } else {
+                __sp804_clockevents_init(base, irq, clk1 , name);
+                __sp804_clocksource_and_sched_clock_init(base + TIMER_2_BASE,
+                                                         name, clk2, 1);
+        }
+        initialized = true;
+
+        return;
+err:
+        iounmap(base);
+}
+CLOCKSOURCE_OF_DECLARE(sp804, "arm,sp804", sp804_of_init);
+
+static void __init integrator_cp_of_init(struct device_node *np)
+{
+        static int init_count = 0;
+        void __iomem *base;
+        int irq;
+        const char *name = of_get_property(np, "compatible", NULL);
+
+        base = of_iomap(np, 0);
+        if (WARN_ON(!base))
+                return;
+
+        /* Ensure timer is disabled */
+        writel(0, base + TIMER_CTRL);
+
+        if (init_count == 2 || !of_device_is_available(np))
+                goto err;
+
+        if (!init_count)
+                sp804_clocksource_init(base, name);
+        else {
+                irq = irq_of_parse_and_map(np, 0);
+                if (irq <= 0)
+                        goto err;
+
+                sp804_clockevents_init(base, irq, name);
+        }
+
+        init_count++;
+        return;
+err:
+        iounmap(base);
+}
+CLOCKSOURCE_OF_DECLARE(intcp, "arm,integrator-cp-timer", integrator_cp_of_init);
diff --git a/arch/arm/include/asm/arch_timer.h b/arch/arm/include/asm/arch_timer.h
index 7ade91d8cc6f..7c1bfc0aea0c 100644
--- a/arch/arm/include/asm/arch_timer.h
+++ b/arch/arm/include/asm/arch_timer.h
@@ -10,8 +10,7 @@
 #include <clocksource/arm_arch_timer.h>
 
 #ifdef CONFIG_ARM_ARCH_TIMER
-int arch_timer_of_register(void);
-int arch_timer_sched_clock_init(void);
+int arch_timer_arch_init(void);
 
 /*
  * These register accessors are marked inline so the compiler can
@@ -110,16 +109,6 @@ static inline void __cpuinit arch_counter_set_user_access(void)
 
         asm volatile("mcr p15, 0, %0, c14, c1, 0" : : "r" (cntkctl));
 }
-#else
-static inline int arch_timer_of_register(void)
-{
-        return -ENXIO;
-}
-
-static inline int arch_timer_sched_clock_init(void)
-{
-        return -ENXIO;
-}
 #endif
 
 #endif
diff --git a/arch/arm/include/asm/hardware/timer-sp.h b/arch/arm/include/asm/hardware/timer-sp.h
index 2dd9d3f83f29..bb28af7c32de 100644
--- a/arch/arm/include/asm/hardware/timer-sp.h
+++ b/arch/arm/include/asm/hardware/timer-sp.h
@@ -1,15 +1,23 @@
+struct clk;
+
 void __sp804_clocksource_and_sched_clock_init(void __iomem *,
-                                              const char *, int);
+                                              const char *, struct clk *, int);
+void __sp804_clockevents_init(void __iomem *, unsigned int,
+                              struct clk *, const char *);
 
 static inline void sp804_clocksource_init(void __iomem *base, const char *name)
 {
-        __sp804_clocksource_and_sched_clock_init(base, name, 0);
+        __sp804_clocksource_and_sched_clock_init(base, name, NULL, 0);
 }
 
 static inline void sp804_clocksource_and_sched_clock_init(void __iomem *base,
                                                           const char *name)
 {
-        __sp804_clocksource_and_sched_clock_init(base, name, 1);
+        __sp804_clocksource_and_sched_clock_init(base, name, NULL, 1);
 }
 
-void sp804_clockevents_init(void __iomem *, unsigned int, const char *);
+static inline void sp804_clockevents_init(void __iomem *base, unsigned int irq, const char *name)
+{
+        __sp804_clockevents_init(base, irq, NULL, name);
+
+}
diff --git a/arch/arm/include/asm/sched_clock.h b/arch/arm/include/asm/sched_clock.h
index e3f757263438..3d520ddca61b 100644
--- a/arch/arm/include/asm/sched_clock.h
+++ b/arch/arm/include/asm/sched_clock.h
@@ -11,4 +11,6 @@
 extern void sched_clock_postinit(void);
 extern void setup_sched_clock(u32 (*read)(void), int bits, unsigned long rate);
 
+extern unsigned long long (*sched_clock_func)(void);
+
 #endif
diff --git a/arch/arm/include/asm/smp_twd.h b/arch/arm/include/asm/smp_twd.h
index 0f01f4677bd2..7b2899c2f7fc 100644
--- a/arch/arm/include/asm/smp_twd.h
+++ b/arch/arm/include/asm/smp_twd.h
@@ -34,12 +34,4 @@ struct twd_local_timer name __initdata = {	\
 
 int twd_local_timer_register(struct twd_local_timer *);
 
-#ifdef CONFIG_HAVE_ARM_TWD
-void twd_local_timer_of_register(void);
-#else
-static inline void twd_local_timer_of_register(void)
-{
-}
-#endif
-
 #endif
diff --git a/arch/arm/kernel/arch_timer.c b/arch/arm/kernel/arch_timer.c
index d957a51435d8..59dcdced6e30 100644
--- a/arch/arm/kernel/arch_timer.c
+++ b/arch/arm/kernel/arch_timer.c
@@ -22,9 +22,11 @@ static unsigned long arch_timer_read_counter_long(void)
         return arch_timer_read_counter();
 }
 
-static u32 arch_timer_read_counter_u32(void)
+static u32 sched_clock_mult __read_mostly;
+
+static unsigned long long notrace arch_timer_sched_clock(void)
 {
-        return arch_timer_read_counter();
+        return arch_timer_read_counter() * sched_clock_mult;
 }
 
 static struct delay_timer arch_delay_timer;
@@ -37,25 +39,20 @@ static void __init arch_timer_delay_timer_register(void)
         register_current_timer_delay(&arch_delay_timer);
 }
 
-int __init arch_timer_of_register(void)
+int __init arch_timer_arch_init(void)
 {
-        int ret;
+        u32 arch_timer_rate = arch_timer_get_rate();
 
-        ret = arch_timer_init();
-        if (ret)
-                return ret;
+        if (arch_timer_rate == 0)
+                return -ENXIO;
 
         arch_timer_delay_timer_register();
 
-        return 0;
-}
-
-int __init arch_timer_sched_clock_init(void)
-{
-        if (arch_timer_get_rate() == 0)
-                return -ENXIO;
+        /* Cache the sched_clock multiplier to save a divide in the hot path. */
+        sched_clock_mult = NSEC_PER_SEC / arch_timer_rate;
+        sched_clock_func = arch_timer_sched_clock;
+        pr_info("sched_clock: ARM arch timer >56 bits at %ukHz, resolution %uns\n",
+                arch_timer_rate / 1000, sched_clock_mult);
 
-        setup_sched_clock(arch_timer_read_counter_u32,
-                          32, arch_timer_get_rate());
         return 0;
 }
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index 0f82098c9bfe..cd22d821bf74 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -562,21 +562,21 @@ ENDPROC(__und_usr)
         @ Fall-through from Thumb-2 __und_usr
         @
 #ifdef CONFIG_NEON
+        get_thread_info r10                     @ get current thread
         adr     r6, .LCneon_thumb_opcodes
         b       2f
 #endif
 call_fpe:
+        get_thread_info r10                     @ get current thread
 #ifdef CONFIG_NEON
         adr     r6, .LCneon_arm_opcodes
-2:
-        ldr     r7, [r6], #4                    @ mask value
-        cmp     r7, #0                          @ end mask?
-        beq     1f
-        and     r8, r0, r7
+2:      ldr     r5, [r6], #4                    @ mask value
         ldr     r7, [r6], #4                    @ opcode bits matching in mask
+        cmp     r5, #0                          @ end mask?
+        beq     1f
+        and     r8, r0, r5
         cmp     r8, r7                          @ NEON instruction?
         bne     2b
-        get_thread_info r10
         mov     r7, #1
         strb    r7, [r10, #TI_USED_CP + 10]     @ mark CP#10 as used
         strb    r7, [r10, #TI_USED_CP + 11]     @ mark CP#11 as used
@@ -586,7 +586,6 @@ call_fpe:
         tst     r0, #0x08000000                 @ only CDP/CPRT/LDC/STC have bit 27
         tstne   r0, #0x04000000                 @ bit 26 set on both ARM and Thumb-2
         moveq   pc, lr
-        get_thread_info r10                     @ get current thread
         and     r8, r0, #0x00000f00             @ mask out CP number
  THUMB( lsr     r8, r8, #8              )
         mov     r7, #1
diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
index 047d3e40e470..cbd0f51937cc 100644
--- a/arch/arm/kernel/process.c
+++ b/arch/arm/kernel/process.c
@@ -459,15 +459,16 @@ unsigned long arch_randomize_brk(struct mm_struct *mm)
  * atomic helpers and the signal restart code. Insert it into the
  * gate_vma so that it is visible through ptrace and /proc/<pid>/mem.
  */
-static struct vm_area_struct gate_vma;
+static struct vm_area_struct gate_vma = {
+        .vm_start       = 0xffff0000,
+        .vm_end         = 0xffff0000 + PAGE_SIZE,
+        .vm_flags       = VM_READ | VM_EXEC | VM_MAYREAD | VM_MAYEXEC,
+        .vm_mm          = &init_mm,
+};
 
 static int __init gate_vma_init(void)
 {
-        gate_vma.vm_start       = 0xffff0000;
-        gate_vma.vm_end         = 0xffff0000 + PAGE_SIZE;
-        gate_vma.vm_page_prot   = PAGE_READONLY_EXEC;
-        gate_vma.vm_flags       = VM_READ | VM_EXEC |
-                                  VM_MAYREAD | VM_MAYEXEC;
+        gate_vma.vm_page_prot = PAGE_READONLY_EXEC;
         return 0;
 }
 arch_initcall(gate_vma_init);
diff --git a/arch/arm/kernel/sched_clock.c b/arch/arm/kernel/sched_clock.c
index bd6f56b9ec21..880584852fca 100644
--- a/arch/arm/kernel/sched_clock.c
+++ b/arch/arm/kernel/sched_clock.c
@@ -20,6 +20,7 @@ struct clock_data {
         u64 epoch_ns;
         u32 epoch_cyc;
         u32 epoch_cyc_copy;
+        unsigned long rate;
         u32 mult;
         u32 shift;
         bool suspended;
@@ -113,11 +114,14 @@ void __init setup_sched_clock(u32 (*read)(void), int bits, unsigned long rate)
         u64 res, wrap;
         char r_unit;
 
+        if (cd.rate > rate)
+                return;
+
         BUG_ON(bits > 32);
         WARN_ON(!irqs_disabled());
-        WARN_ON(read_sched_clock != jiffy_sched_clock_read);
         read_sched_clock = read;
         sched_clock_mask = (1 << bits) - 1;
+        cd.rate = rate;
 
         /* calculate the mult/shift to convert counter ticks to ns. */
         clocks_calc_mult_shift(&cd.mult, &cd.shift, rate, NSEC_PER_SEC, 0);
@@ -161,12 +165,19 @@ void __init setup_sched_clock(u32 (*read)(void), int bits, unsigned long rate)
         pr_debug("Registered %pF as sched_clock source\n", read);
 }
 
-unsigned long long notrace sched_clock(void)
+static unsigned long long notrace sched_clock_32(void)
 {
         u32 cyc = read_sched_clock();
         return cyc_to_sched_clock(cyc, sched_clock_mask);
 }
 
+unsigned long long __read_mostly (*sched_clock_func)(void) = sched_clock_32;
+
+unsigned long long notrace sched_clock(void)
+{
+        return sched_clock_func();
+}
+
 void __init sched_clock_postinit(void)
 {
         /*
diff --git a/arch/arm/kernel/smp_twd.c b/arch/arm/kernel/smp_twd.c
index 3f2565037480..90525d9d290b 100644
--- a/arch/arm/kernel/smp_twd.c
+++ b/arch/arm/kernel/smp_twd.c
@@ -362,25 +362,13 @@ int __init twd_local_timer_register(struct twd_local_timer *tlt)
 }
 
 #ifdef CONFIG_OF
-const static struct of_device_id twd_of_match[] __initconst = {
-        { .compatible = "arm,cortex-a9-twd-timer",      },
-        { .compatible = "arm,cortex-a5-twd-timer",      },
-        { .compatible = "arm,arm11mp-twd-timer",        },
-        { },
-};
-
-void __init twd_local_timer_of_register(void)
+static void __init twd_local_timer_of_register(struct device_node *np)
 {
-        struct device_node *np;
         int err;
 
         if (!is_smp() || !setup_max_cpus)
                 return;
 
-        np = of_find_matching_node(NULL, twd_of_match);
-        if (!np)
-                return;
-
         twd_ppi = irq_of_parse_and_map(np, 0);
         if (!twd_ppi) {
                 err = -EINVAL;
@@ -398,4 +386,7 @@ void __init twd_local_timer_of_register(void)
 out:
         WARN(err, "twd_local_timer_of_register failed (%d)\n", err);
 }
+CLOCKSOURCE_OF_DECLARE(arm_twd_a9, "arm,cortex-a9-twd-timer", twd_local_timer_of_register);
+CLOCKSOURCE_OF_DECLARE(arm_twd_a5, "arm,cortex-a5-twd-timer", twd_local_timer_of_register);
+CLOCKSOURCE_OF_DECLARE(arm_twd_11mp, "arm,arm11mp-twd-timer", twd_local_timer_of_register);
 #endif
diff --git a/arch/arm/kernel/time.c b/arch/arm/kernel/time.c
index 955d92d265e5..abff4e9aaee0 100644
--- a/arch/arm/kernel/time.c
+++ b/arch/arm/kernel/time.c
@@ -22,6 +22,7 @@
 #include <linux/errno.h>
 #include <linux/profile.h>
 #include <linux/timer.h>
+#include <linux/clocksource.h>
 #include <linux/irq.h>
 
 #include <asm/thread_info.h>
@@ -115,6 +116,10 @@ int __init register_persistent_clock(clock_access_fn read_boot,
 
 void __init time_init(void)
 {
-        machine_desc->init_time();
+        if (machine_desc->init_time)
+                machine_desc->init_time();
+        else
+                clocksource_of_init();
+
         sched_clock_postinit();
 }
diff --git a/arch/arm/mach-at91/at91sam9261.c b/arch/arm/mach-at91/at91sam9261.c
index ac7a341bd0ff..25efb5ac30f1 100644
--- a/arch/arm/mach-at91/at91sam9261.c
+++ b/arch/arm/mach-at91/at91sam9261.c
@@ -169,6 +169,8 @@ static struct clk *periph_clocks[] __initdata = {
 };
 
 static struct clk_lookup periph_clocks_lookups[] = {
+        CLKDEV_CON_DEV_ID("hclk", "at91sam9261-lcdfb.0", &hck1),
+        CLKDEV_CON_DEV_ID("hclk", "at91sam9g10-lcdfb.0", &hck1),
         CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
         CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
         CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
diff --git a/arch/arm/mach-at91/at91sam9261_devices.c b/arch/arm/mach-at91/at91sam9261_devices.c
index 92e0f861084a..629ea5fc95cf 100644
--- a/arch/arm/mach-at91/at91sam9261_devices.c
+++ b/arch/arm/mach-at91/at91sam9261_devices.c
@@ -488,7 +488,6 @@ static struct resource lcdc_resources[] = {
 };
 
 static struct platform_device at91_lcdc_device = {
-        .name           = "atmel_lcdfb",
         .id             = 0,
         .dev            = {
                                 .dma_mask               = &lcdc_dmamask,
@@ -505,6 +504,11 @@ void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data)
                 return;
         }
 
+        if (cpu_is_at91sam9g10())
+                at91_lcdc_device.name = "at91sam9g10-lcdfb";
+        else
+                at91_lcdc_device.name = "at91sam9261-lcdfb";
+
 #if defined(CONFIG_FB_ATMEL_STN)
         at91_set_A_periph(AT91_PIN_PB0, 0);     /* LCDVSYNC */
         at91_set_A_periph(AT91_PIN_PB1, 0);     /* LCDHSYNC */
diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c
index 8e2d9f4a9a45..f44ffd2105a7 100644
--- a/arch/arm/mach-at91/at91sam9263.c
+++ b/arch/arm/mach-at91/at91sam9263.c
@@ -190,6 +190,7 @@ static struct clk_lookup periph_clocks_lookups[] = {
         CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.1", &ssc1_clk),
         CLKDEV_CON_DEV_ID("pclk", "fff98000.ssc", &ssc0_clk),
         CLKDEV_CON_DEV_ID("pclk", "fff9c000.ssc", &ssc1_clk),
+        CLKDEV_CON_DEV_ID("hclk", "at91sam9263-lcdfb.0", &lcdc_clk),
         CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.0", &mmc0_clk),
         CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.1", &mmc1_clk),
         CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
diff --git a/arch/arm/mach-at91/at91sam9263_devices.c b/arch/arm/mach-at91/at91sam9263_devices.c
index ed666f5cb01d..858c8aac2daf 100644
--- a/arch/arm/mach-at91/at91sam9263_devices.c
+++ b/arch/arm/mach-at91/at91sam9263_devices.c
@@ -848,7 +848,7 @@ static struct resource lcdc_resources[] = {
 };
 
 static struct platform_device at91_lcdc_device = {
-        .name           = "atmel_lcdfb",
+        .name           = "at91sam9263-lcdfb",
         .id             = 0,
         .dev            = {
                                 .dma_mask               = &lcdc_dmamask,
diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
index 4fcbe7b5b58d..dc49c2c45d49 100644
--- a/arch/arm/mach-at91/at91sam9g45.c
+++ b/arch/arm/mach-at91/at91sam9g45.c
@@ -228,6 +228,8 @@ static struct clk_lookup periph_clocks_lookups[] = {
         CLKDEV_CON_ID("hclk", &macb_clk),
         /* One additional fake clock for ohci */
         CLKDEV_CON_ID("ohci_clk", &uhphs_clk),
+        CLKDEV_CON_DEV_ID("hclk", "at91sam9g45-lcdfb.0", &lcdc_clk),
+        CLKDEV_CON_DEV_ID("hclk", "at91sam9g45es-lcdfb.0", &lcdc_clk),
         CLKDEV_CON_DEV_ID("ehci_clk", "atmel-ehci", &uhphs_clk),
         CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc", &utmi_clk),
         CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc", &udphs_clk),
diff --git a/arch/arm/mach-at91/at91sam9g45_devices.c b/arch/arm/mach-at91/at91sam9g45_devices.c
index 827c9f2a70fb..fe626d431b69 100644
--- a/arch/arm/mach-at91/at91sam9g45_devices.c
+++ b/arch/arm/mach-at91/at91sam9g45_devices.c
@@ -981,7 +981,6 @@ static struct resource lcdc_resources[] = {
 };
 
 static struct platform_device at91_lcdc_device = {
-        .name           = "atmel_lcdfb",
         .id             = 0,
         .dev            = {
                                 .dma_mask               = &lcdc_dmamask,
@@ -997,6 +996,11 @@ void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data)
         if (!data)
                 return;
 
+        if (cpu_is_at91sam9g45es())
+                at91_lcdc_device.name = "at91sam9g45es-lcdfb";
+        else
+                at91_lcdc_device.name = "at91sam9g45-lcdfb";
+
         at91_set_A_periph(AT91_PIN_PE0, 0);     /* LCDDPWR */
 
         at91_set_A_periph(AT91_PIN_PE2, 0);     /* LCDCC */
diff --git a/arch/arm/mach-at91/at91sam9rl.c b/arch/arm/mach-at91/at91sam9rl.c
index c39600764236..f77fae5591bc 100644
--- a/arch/arm/mach-at91/at91sam9rl.c
+++ b/arch/arm/mach-at91/at91sam9rl.c
@@ -179,6 +179,7 @@ static struct clk *periph_clocks[] __initdata = {
 };
 
 static struct clk_lookup periph_clocks_lookups[] = {
+        CLKDEV_CON_DEV_ID("hclk", "at91sam9rl-lcdfb.0", &lcdc_clk),
         CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc", &utmi_clk),
         CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc", &udphs_clk),
         CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
diff --git a/arch/arm/mach-at91/at91sam9rl_devices.c b/arch/arm/mach-at91/at91sam9rl_devices.c
index ddf223ff35c4..352468f265a9 100644
--- a/arch/arm/mach-at91/at91sam9rl_devices.c
+++ b/arch/arm/mach-at91/at91sam9rl_devices.c
@@ -514,7 +514,7 @@ static struct resource lcdc_resources[] = {
 };
 
 static struct platform_device at91_lcdc_device = {
-        .name           = "atmel_lcdfb",
+        .name           = "at91sam9rl-lcdfb",
         .id             = 0,
         .dev            = {
                                 .dma_mask               = &lcdc_dmamask,
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index 70f94c87479d..faca4326b46a 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -79,12 +79,6 @@ config SOC_EXYNOS5440
         help
           Enable EXYNOS5440 SoC support
 
-config EXYNOS4_MCT
-        bool
-        default y
-        help
-          Use MCT (Multi Core Timer) as kernel timers
-
 config EXYNOS_DEV_DMA
         bool
         help
@@ -276,8 +270,8 @@ config MACH_UNIVERSAL_C210
         select S5P_DEV_ONENAND
         select S5P_DEV_TV
         select S5P_GPIO_INT
-        select S5P_HRT
         select S5P_SETUP_MIPIPHY
+        select SAMSUNG_HRT
         help
           Machine support for Samsung Mobile Universal S5PC210 Reference
           Board.
@@ -406,6 +400,7 @@ config MACH_EXYNOS4_DT
         bool "Samsung Exynos4 Machine using device tree"
         depends on ARCH_EXYNOS4
         select ARM_AMBA
+        select CLKSRC_OF
         select CPU_EXYNOS4210
         select HAVE_SAMSUNG_KEYPAD if INPUT_KEYBOARD
         select PINCTRL
@@ -422,6 +417,7 @@ config MACH_EXYNOS5_DT
         default y
         depends on ARCH_EXYNOS5
         select ARM_AMBA
+        select CLKSRC_OF
         select USE_OF
         help
           Machine support for Samsung EXYNOS5 machine with device tree enabled.
diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
index 435757e57bb4..daf289b21486 100644
--- a/arch/arm/mach-exynos/Makefile
+++ b/arch/arm/mach-exynos/Makefile
@@ -26,8 +26,6 @@ obj-$(CONFIG_ARCH_EXYNOS)	+= pmu.o
 
 obj-$(CONFIG_SMP)               += platsmp.o headsmp.o
 
-obj-$(CONFIG_EXYNOS4_MCT)       += mct.o
-
 obj-$(CONFIG_HOTPLUG_CPU)       += hotplug.o
 
 # machine support
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index d63d399c7bae..db7dbd0eb6b4 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -257,11 +257,6 @@ static struct map_desc exynos5_iodesc[] __initdata = {
                 .length         = SZ_4K,
                 .type           = MT_DEVICE,
         }, {
-                .virtual        = (unsigned long)S5P_VA_SYSTIMER,
-                .pfn            = __phys_to_pfn(EXYNOS5_PA_SYSTIMER),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE,
-        }, {
                 .virtual        = (unsigned long)S5P_VA_SYSRAM,
                 .pfn            = __phys_to_pfn(EXYNOS5_PA_SYSRAM),
                 .length         = SZ_4K,
@@ -822,6 +817,7 @@ static int __init exynos_init_irq_eint(void)
         static const struct of_device_id exynos_pinctrl_ids[] = {
                 { .compatible = "samsung,exynos4210-pinctrl", },
                 { .compatible = "samsung,exynos4x12-pinctrl", },
+                { .compatible = "samsung,exynos5250-pinctrl", },
         };
         struct device_node *pctrl_np, *wkup_np;
         const char *wkup_compat = "samsung,exynos4210-wakeup-eint";
diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
index 9339bb8954be..3b186eaaaa7b 100644
--- a/arch/arm/mach-exynos/common.h
+++ b/arch/arm/mach-exynos/common.h
@@ -12,7 +12,7 @@
 #ifndef __ARCH_ARM_MACH_EXYNOS_COMMON_H
 #define __ARCH_ARM_MACH_EXYNOS_COMMON_H
 
-extern void exynos4_timer_init(void);
+extern void mct_init(void);
 
 struct map_desc;
 void exynos_init_io(struct map_desc *mach_desc, int size);
diff --git a/arch/arm/mach-exynos/include/mach/irqs.h b/arch/arm/mach-exynos/include/mach/irqs.h
index 1f4dc35cd4b9..c0e75d8dd737 100644
--- a/arch/arm/mach-exynos/include/mach/irqs.h
+++ b/arch/arm/mach-exynos/include/mach/irqs.h
@@ -30,8 +30,6 @@
 
 /* For EXYNOS4 and EXYNOS5 */
 
-#define EXYNOS_IRQ_MCT_LOCALTIMER       IRQ_PPI(12)
-
 #define EXYNOS_IRQ_EINT16_31            IRQ_SPI(32)
 
 /* For EXYNOS4 SoCs */
@@ -323,8 +321,6 @@
 #define EXYNOS5_IRQ_CEC                 IRQ_SPI(114)
 #define EXYNOS5_IRQ_SATA                IRQ_SPI(115)
 
-#define EXYNOS5_IRQ_MCT_L0              IRQ_SPI(120)
-#define EXYNOS5_IRQ_MCT_L1              IRQ_SPI(121)
 #define EXYNOS5_IRQ_MMC44               IRQ_SPI(123)
 #define EXYNOS5_IRQ_MDMA1               IRQ_SPI(124)
 #define EXYNOS5_IRQ_FIMC_LITE0          IRQ_SPI(125)
@@ -419,8 +415,6 @@
 #define EXYNOS5_IRQ_PMU_CPU1            COMBINER_IRQ(22, 4)
 
 #define EXYNOS5_IRQ_EINT0               COMBINER_IRQ(23, 0)
-#define EXYNOS5_IRQ_MCT_G0              COMBINER_IRQ(23, 3)
-#define EXYNOS5_IRQ_MCT_G1              COMBINER_IRQ(23, 4)
 
 #define EXYNOS5_IRQ_EINT1               COMBINER_IRQ(24, 0)
 #define EXYNOS5_IRQ_SYSMMU_LITE1_0      COMBINER_IRQ(24, 1)
diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
index 1df6abbf53b8..7f99b7b187d6 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -65,7 +65,6 @@
 #define EXYNOS5_PA_CMU                  0x10010000
 
 #define EXYNOS4_PA_SYSTIMER             0x10050000
-#define EXYNOS5_PA_SYSTIMER             0x101C0000
 
 #define EXYNOS4_PA_WATCHDOG             0x10060000
 #define EXYNOS5_PA_WATCHDOG             0x101D0000
diff --git a/arch/arm/mach-exynos/include/mach/regs-mct.h b/arch/arm/mach-exynos/include/mach/regs-mct.h
deleted file mode 100644
index 80dd02ad6d61..000000000000
--- a/arch/arm/mach-exynos/include/mach/regs-mct.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/* arch/arm/mach-exynos4/include/mach/regs-mct.h
- *
- * Copyright (c) 2011 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * EXYNOS4 MCT configutation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_REGS_MCT_H
-#define __ASM_ARCH_REGS_MCT_H __FILE__
-
-#include <mach/map.h>
-
-#define EXYNOS4_MCTREG(x)               (S5P_VA_SYSTIMER + (x))
-
-#define EXYNOS4_MCT_G_CNT_L             EXYNOS4_MCTREG(0x100)
-#define EXYNOS4_MCT_G_CNT_U             EXYNOS4_MCTREG(0x104)
-#define EXYNOS4_MCT_G_CNT_WSTAT         EXYNOS4_MCTREG(0x110)
-
-#define EXYNOS4_MCT_G_COMP0_L           EXYNOS4_MCTREG(0x200)
-#define EXYNOS4_MCT_G_COMP0_U           EXYNOS4_MCTREG(0x204)
-#define EXYNOS4_MCT_G_COMP0_ADD_INCR    EXYNOS4_MCTREG(0x208)
-
-#define EXYNOS4_MCT_G_TCON              EXYNOS4_MCTREG(0x240)
-
-#define EXYNOS4_MCT_G_INT_CSTAT         EXYNOS4_MCTREG(0x244)
-#define EXYNOS4_MCT_G_INT_ENB           EXYNOS4_MCTREG(0x248)
-#define EXYNOS4_MCT_G_WSTAT             EXYNOS4_MCTREG(0x24C)
-
-#define _EXYNOS4_MCT_L_BASE             EXYNOS4_MCTREG(0x300)
-#define EXYNOS4_MCT_L_BASE(x)           (_EXYNOS4_MCT_L_BASE + (0x100 * x))
-#define EXYNOS4_MCT_L_MASK              (0xffffff00)
-
-#define MCT_L_TCNTB_OFFSET              (0x00)
-#define MCT_L_ICNTB_OFFSET              (0x08)
-#define MCT_L_TCON_OFFSET               (0x20)
-#define MCT_L_INT_CSTAT_OFFSET          (0x30)
-#define MCT_L_INT_ENB_OFFSET            (0x34)
-#define MCT_L_WSTAT_OFFSET              (0x40)
-
-#define MCT_G_TCON_START                (1 << 8)
-#define MCT_G_TCON_COMP0_AUTO_INC       (1 << 1)
-#define MCT_G_TCON_COMP0_ENABLE         (1 << 0)
-
-#define MCT_L_TCON_INTERVAL_MODE        (1 << 2)
-#define MCT_L_TCON_INT_START            (1 << 1)
-#define MCT_L_TCON_TIMER_START          (1 << 0)
-
-#endif /* __ASM_ARCH_REGS_MCT_H */
diff --git a/arch/arm/mach-exynos/mach-armlex4210.c b/arch/arm/mach-exynos/mach-armlex4210.c
index 685f29173afa..3b1a34742679 100644
--- a/arch/arm/mach-exynos/mach-armlex4210.c
+++ b/arch/arm/mach-exynos/mach-armlex4210.c
@@ -202,6 +202,6 @@ MACHINE_START(ARMLEX4210, "ARMLEX4210")
         .map_io         = armlex4210_map_io,
         .init_machine   = armlex4210_machine_init,
         .init_late      = exynos_init_late,
-        .init_time      = exynos4_timer_init,
+        .init_time      = mct_init,
         .restart        = exynos4_restart,
 MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-exynos4-dt.c b/arch/arm/mach-exynos/mach-exynos4-dt.c
index 3358088c822a..c4ae108e192d 100644
--- a/arch/arm/mach-exynos/mach-exynos4-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos4-dt.c
@@ -13,6 +13,7 @@
 
 #include <linux/of_platform.h>
 #include <linux/serial_core.h>
+#include <linux/clocksource.h>
 
 #include <asm/mach/arch.h>
 #include <mach/map.h>
@@ -142,7 +143,7 @@ DT_MACHINE_START(EXYNOS4210_DT, "Samsung Exynos4 (Flattened Device Tree)")
         .map_io         = exynos4_dt_map_io,
         .init_machine   = exynos4_dt_machine_init,
         .init_late      = exynos_init_late,
-        .init_time      = exynos4_timer_init,
+        .init_time      = clocksource_of_init,
         .dt_compat      = exynos4_dt_compat,
         .restart        = exynos4_restart,
 MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c
index acaeb14db54b..be7eaac0df01 100644
--- a/arch/arm/mach-exynos/mach-exynos5-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
@@ -14,6 +14,7 @@
 #include <linux/serial_core.h>
 #include <linux/memblock.h>
 #include <linux/io.h>
+#include <linux/clocksource.h>
 
 #include <asm/mach/arch.h>
 #include <mach/map.h>
@@ -216,7 +217,6 @@ DT_MACHINE_START(EXYNOS5_DT, "SAMSUNG EXYNOS5 (Flattened Device Tree)")
         .map_io         = exynos5_dt_map_io,
         .init_machine   = exynos5_dt_machine_init,
         .init_late      = exynos_init_late,
-        .init_time      = exynos4_timer_init,
         .dt_compat      = exynos5_dt_compat,
         .restart        = exynos5_restart,
         .reserve        = exynos5_reserve,
diff --git a/arch/arm/mach-exynos/mach-nuri.c b/arch/arm/mach-exynos/mach-nuri.c
index 1ea79730187f..da3605d15110 100644
--- a/arch/arm/mach-exynos/mach-nuri.c
+++ b/arch/arm/mach-exynos/mach-nuri.c
@@ -1380,7 +1380,7 @@ MACHINE_START(NURI, "NURI")
         .map_io         = nuri_map_io,
         .init_machine   = nuri_machine_init,
         .init_late      = exynos_init_late,
-        .init_time      = exynos4_timer_init,
+        .init_time      = mct_init,
         .reserve        = &nuri_reserve,
         .restart        = exynos4_restart,
 MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-origen.c b/arch/arm/mach-exynos/mach-origen.c
index 579d2d171daa..1772cd284f4c 100644
--- a/arch/arm/mach-exynos/mach-origen.c
+++ b/arch/arm/mach-exynos/mach-origen.c
@@ -815,7 +815,7 @@ MACHINE_START(ORIGEN, "ORIGEN")
         .map_io         = origen_map_io,
         .init_machine   = origen_machine_init,
         .init_late      = exynos_init_late,
-        .init_time      = exynos4_timer_init,
+        .init_time      = mct_init,
         .reserve        = &origen_reserve,
         .restart        = exynos4_restart,
 MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-smdk4x12.c b/arch/arm/mach-exynos/mach-smdk4x12.c
index fe6149624b84..34a6356364eb 100644
--- a/arch/arm/mach-exynos/mach-smdk4x12.c
+++ b/arch/arm/mach-exynos/mach-smdk4x12.c
@@ -376,7 +376,7 @@ MACHINE_START(SMDK4212, "SMDK4212")
         .init_irq       = exynos4_init_irq,
         .map_io         = smdk4x12_map_io,
         .init_machine   = smdk4x12_machine_init,
-        .init_time      = exynos4_timer_init,
+        .init_time      = mct_init,
         .restart        = exynos4_restart,
         .reserve        = &smdk4x12_reserve,
 MACHINE_END
@@ -390,7 +390,7 @@ MACHINE_START(SMDK4412, "SMDK4412")
         .map_io         = smdk4x12_map_io,
         .init_machine   = smdk4x12_machine_init,
         .init_late      = exynos_init_late,
-        .init_time      = exynos4_timer_init,
+        .init_time      = mct_init,
         .restart        = exynos4_restart,
         .reserve        = &smdk4x12_reserve,
 MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-smdkv310.c b/arch/arm/mach-exynos/mach-smdkv310.c
index d71672922b19..893b14e8c62a 100644
--- a/arch/arm/mach-exynos/mach-smdkv310.c
+++ b/arch/arm/mach-exynos/mach-smdkv310.c
@@ -423,7 +423,7 @@ MACHINE_START(SMDKV310, "SMDKV310")
         .init_irq       = exynos4_init_irq,
         .map_io         = smdkv310_map_io,
         .init_machine   = smdkv310_machine_init,
-        .init_time      = exynos4_timer_init,
+        .init_time      = mct_init,
         .reserve        = &smdkv310_reserve,
         .restart        = exynos4_restart,
 MACHINE_END
@@ -436,7 +436,7 @@ MACHINE_START(SMDKC210, "SMDKC210")
         .map_io         = smdkv310_map_io,
         .init_machine   = smdkv310_machine_init,
         .init_late      = exynos_init_late,
-        .init_time      = exynos4_timer_init,
+        .init_time      = mct_init,
         .reserve        = &smdkv310_reserve,
         .restart        = exynos4_restart,
 MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-universal_c210.c b/arch/arm/mach-exynos/mach-universal_c210.c
index 497fcb793dc1..c870b0aaa5e0 100644
--- a/arch/arm/mach-exynos/mach-universal_c210.c
+++ b/arch/arm/mach-exynos/mach-universal_c210.c
@@ -41,7 +41,7 @@
 #include <plat/mfc.h>
 #include <plat/sdhci.h>
 #include <plat/fimc-core.h>
-#include <plat/s5p-time.h>
+#include <plat/samsung-time.h>
 #include <plat/camport.h>
 
 #include <mach/map.h>
@@ -1094,7 +1094,7 @@ static void __init universal_map_io(void)
         exynos_init_io(NULL, 0);
         s3c24xx_init_clocks(clk_xusbxti.rate);
         s3c24xx_init_uarts(universal_uartcfgs, ARRAY_SIZE(universal_uartcfgs));
-        s5p_set_timer_source(S5P_PWM2, S5P_PWM4);
+        samsung_set_timer_source(SAMSUNG_PWM2, SAMSUNG_PWM4);
 }
 
 static void s5p_tv_setup(void)
@@ -1152,7 +1152,7 @@ MACHINE_START(UNIVERSAL_C210, "UNIVERSAL_C210")
         .map_io         = universal_map_io,
         .init_machine   = universal_machine_init,
         .init_late      = exynos_init_late,
-        .init_time      = s5p_timer_init,
+        .init_time      = samsung_timer_init,
         .reserve        = &universal_reserve,
         .restart        = exynos4_restart,
 MACHINE_END
diff --git a/arch/arm/mach-exynos/mct.c b/arch/arm/mach-exynos/mct.c
deleted file mode 100644
index c9d6650f9b5d..000000000000
--- a/arch/arm/mach-exynos/mct.c
+++ /dev/null
@@ -1,485 +0,0 @@
-/* linux/arch/arm/mach-exynos4/mct.c
- *
- * Copyright (c) 2011 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * EXYNOS4 MCT(Multi-Core Timer) support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/sched.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/err.h>
-#include <linux/clk.h>
-#include <linux/clockchips.h>
-#include <linux/platform_device.h>
-#include <linux/delay.h>
-#include <linux/percpu.h>
-#include <linux/of.h>
-
-#include <asm/arch_timer.h>
-#include <asm/localtimer.h>
-
-#include <plat/cpu.h>
-
-#include <mach/map.h>
-#include <mach/irqs.h>
-#include <mach/regs-mct.h>
-#include <asm/mach/time.h>
-
-#define TICK_BASE_CNT   1
-
-enum {
-        MCT_INT_SPI,
-        MCT_INT_PPI
-};
-
-static unsigned long clk_rate;
-static unsigned int mct_int_type;
-
-struct mct_clock_event_device {
-        struct clock_event_device *evt;
-        void __iomem *base;
-        char name[10];
-};
-
-static void exynos4_mct_write(unsigned int value, void *addr)
-{
-        void __iomem *stat_addr;
-        u32 mask;
-        u32 i;
-
-        __raw_writel(value, addr);
-
-        if (likely(addr >= EXYNOS4_MCT_L_BASE(0))) {
-                u32 base = (u32) addr & EXYNOS4_MCT_L_MASK;
-                switch ((u32) addr & ~EXYNOS4_MCT_L_MASK) {
-                case (u32) MCT_L_TCON_OFFSET:
-                        stat_addr = (void __iomem *) base + MCT_L_WSTAT_OFFSET;
-                        mask = 1 << 3;          /* L_TCON write status */
-                        break;
-                case (u32) MCT_L_ICNTB_OFFSET:
-                        stat_addr = (void __iomem *) base + MCT_L_WSTAT_OFFSET;
-                        mask = 1 << 1;          /* L_ICNTB write status */
-                        break;
-                case (u32) MCT_L_TCNTB_OFFSET:
-                        stat_addr = (void __iomem *) base + MCT_L_WSTAT_OFFSET;
-                        mask = 1 << 0;          /* L_TCNTB write status */
-                        break;
-                default:
-                        return;
-                }
-        } else {
-                switch ((u32) addr) {
-                case (u32) EXYNOS4_MCT_G_TCON:
-                        stat_addr = EXYNOS4_MCT_G_WSTAT;
-                        mask = 1 << 16;         /* G_TCON write status */
-                        break;
-                case (u32) EXYNOS4_MCT_G_COMP0_L:
-                        stat_addr = EXYNOS4_MCT_G_WSTAT;
-                        mask = 1 << 0;          /* G_COMP0_L write status */
-                        break;
-                case (u32) EXYNOS4_MCT_G_COMP0_U:
-                        stat_addr = EXYNOS4_MCT_G_WSTAT;
-                        mask = 1 << 1;          /* G_COMP0_U write status */
-                        break;
-                case (u32) EXYNOS4_MCT_G_COMP0_ADD_INCR:
-                        stat_addr = EXYNOS4_MCT_G_WSTAT;
-                        mask = 1 << 2;          /* G_COMP0_ADD_INCR w status */
-                        break;
-                case (u32) EXYNOS4_MCT_G_CNT_L:
-                        stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
-                        mask = 1 << 0;          /* G_CNT_L write status */
-                        break;
-                case (u32) EXYNOS4_MCT_G_CNT_U:
-                        stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
-                        mask = 1 << 1;          /* G_CNT_U write status */
-                        break;
-                default:
-                        return;
-                }
-        }
-
-        /* Wait maximum 1 ms until written values are applied */
-        for (i = 0; i < loops_per_jiffy / 1000 * HZ; i++)
-                if (__raw_readl(stat_addr) & mask) {
-                        __raw_writel(mask, stat_addr);
-                        return;
-                }
-
-        panic("MCT hangs after writing %d (addr:0x%08x)\n", value, (u32)addr);
-}
-
-/* Clocksource handling */
-static void exynos4_mct_frc_start(u32 hi, u32 lo)
-{
-        u32 reg;
-
-        exynos4_mct_write(lo, EXYNOS4_MCT_G_CNT_L);
-        exynos4_mct_write(hi, EXYNOS4_MCT_G_CNT_U);
-
-        reg = __raw_readl(EXYNOS4_MCT_G_TCON);
-        reg |= MCT_G_TCON_START;
-        exynos4_mct_write(reg, EXYNOS4_MCT_G_TCON);
-}
-
-static cycle_t exynos4_frc_read(struct clocksource *cs)
-{
-        unsigned int lo, hi;
-        u32 hi2 = __raw_readl(EXYNOS4_MCT_G_CNT_U);
-
-        do {
-                hi = hi2;
-                lo = __raw_readl(EXYNOS4_MCT_G_CNT_L);
-                hi2 = __raw_readl(EXYNOS4_MCT_G_CNT_U);
-        } while (hi != hi2);
-
-        return ((cycle_t)hi << 32) | lo;
-}
-
-static void exynos4_frc_resume(struct clocksource *cs)
-{
-        exynos4_mct_frc_start(0, 0);
-}
-
-struct clocksource mct_frc = {
-        .name           = "mct-frc",
-        .rating         = 400,
-        .read           = exynos4_frc_read,
-        .mask           = CLOCKSOURCE_MASK(64),
-        .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
-        .resume         = exynos4_frc_resume,
-};
-
-static void __init exynos4_clocksource_init(void)
-{
-        exynos4_mct_frc_start(0, 0);
-
-        if (clocksource_register_hz(&mct_frc, clk_rate))
-                panic("%s: can't register clocksource\n", mct_frc.name);
-}
-
-static void exynos4_mct_comp0_stop(void)
-{
-        unsigned int tcon;
-
-        tcon = __raw_readl(EXYNOS4_MCT_G_TCON);
-        tcon &= ~(MCT_G_TCON_COMP0_ENABLE | MCT_G_TCON_COMP0_AUTO_INC);
-
-        exynos4_mct_write(tcon, EXYNOS4_MCT_G_TCON);
-        exynos4_mct_write(0, EXYNOS4_MCT_G_INT_ENB);
-}
-
-static void exynos4_mct_comp0_start(enum clock_event_mode mode,
-                                    unsigned long cycles)
-{
-        unsigned int tcon;
-        cycle_t comp_cycle;
-
-        tcon = __raw_readl(EXYNOS4_MCT_G_TCON);
-
-        if (mode == CLOCK_EVT_MODE_PERIODIC) {
-                tcon |= MCT_G_TCON_COMP0_AUTO_INC;
-                exynos4_mct_write(cycles, EXYNOS4_MCT_G_COMP0_ADD_INCR);
-        }
-
-        comp_cycle = exynos4_frc_read(&mct_frc) + cycles;
-        exynos4_mct_write((u32)comp_cycle, EXYNOS4_MCT_G_COMP0_L);
-        exynos4_mct_write((u32)(comp_cycle >> 32), EXYNOS4_MCT_G_COMP0_U);
-
-        exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_ENB);
-
-        tcon |= MCT_G_TCON_COMP0_ENABLE;
-        exynos4_mct_write(tcon , EXYNOS4_MCT_G_TCON);
-}
-
-static int exynos4_comp_set_next_event(unsigned long cycles,
-                                       struct clock_event_device *evt)
-{
-        exynos4_mct_comp0_start(evt->mode, cycles);
-
-        return 0;
-}
-
-static void exynos4_comp_set_mode(enum clock_event_mode mode,
-                                  struct clock_event_device *evt)
-{
-        unsigned long cycles_per_jiffy;
-        exynos4_mct_comp0_stop();
-
-        switch (mode) {
-        case CLOCK_EVT_MODE_PERIODIC:
-                cycles_per_jiffy =
-                        (((unsigned long long) NSEC_PER_SEC / HZ * evt->mult) >> evt->shift);
-                exynos4_mct_comp0_start(mode, cycles_per_jiffy);
-                break;
-
-        case CLOCK_EVT_MODE_ONESHOT:
-        case CLOCK_EVT_MODE_UNUSED:
-        case CLOCK_EVT_MODE_SHUTDOWN:
-        case CLOCK_EVT_MODE_RESUME:
-                break;
-        }
-}
-
-static struct clock_event_device mct_comp_device = {
-        .name           = "mct-comp",
-        .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
-        .rating         = 250,
-        .set_next_event = exynos4_comp_set_next_event,
-        .set_mode       = exynos4_comp_set_mode,
-};
-
-static irqreturn_t exynos4_mct_comp_isr(int irq, void *dev_id)
-{
-        struct clock_event_device *evt = dev_id;
-
-        exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_CSTAT);
-
-        evt->event_handler(evt);
-
-        return IRQ_HANDLED;
-}
-
-static struct irqaction mct_comp_event_irq = {
-        .name           = "mct_comp_irq",
-        .flags          = IRQF_TIMER | IRQF_IRQPOLL,
-        .handler        = exynos4_mct_comp_isr,
-        .dev_id         = &mct_comp_device,
-};
-
-static void exynos4_clockevent_init(void)
-{
-        mct_comp_device.cpumask = cpumask_of(0);
-        clockevents_config_and_register(&mct_comp_device, clk_rate,
-                                        0xf, 0xffffffff);
-
-        if (soc_is_exynos5250())
-                setup_irq(EXYNOS5_IRQ_MCT_G0, &mct_comp_event_irq);
-        else
-                setup_irq(EXYNOS4_IRQ_MCT_G0, &mct_comp_event_irq);
-}
-
-#ifdef CONFIG_LOCAL_TIMERS
-
-static DEFINE_PER_CPU(struct mct_clock_event_device, percpu_mct_tick);
-
-/* Clock event handling */
-static void exynos4_mct_tick_stop(struct mct_clock_event_device *mevt)
-{
-        unsigned long tmp;
-        unsigned long mask = MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START;
-        void __iomem *addr = mevt->base + MCT_L_TCON_OFFSET;
-
-        tmp = __raw_readl(addr);
-        if (tmp & mask) {
-                tmp &= ~mask;
-                exynos4_mct_write(tmp, addr);
-        }
-}
-
-static void exynos4_mct_tick_start(unsigned long cycles,
-                                   struct mct_clock_event_device *mevt)
-{
-        unsigned long tmp;
-
-        exynos4_mct_tick_stop(mevt);
-
-        tmp = (1 << 31) | cycles;       /* MCT_L_UPDATE_ICNTB */
-
-        /* update interrupt count buffer */
-        exynos4_mct_write(tmp, mevt->base + MCT_L_ICNTB_OFFSET);
-
-        /* enable MCT tick interrupt */
-        exynos4_mct_write(0x1, mevt->base + MCT_L_INT_ENB_OFFSET);
-
-        tmp = __raw_readl(mevt->base + MCT_L_TCON_OFFSET);
-        tmp |= MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START |
-               MCT_L_TCON_INTERVAL_MODE;
-        exynos4_mct_write(tmp, mevt->base + MCT_L_TCON_OFFSET);
-}
-
-static int exynos4_tick_set_next_event(unsigned long cycles,
-                                       struct clock_event_device *evt)
-{
-        struct mct_clock_event_device *mevt = this_cpu_ptr(&percpu_mct_tick);
-
-        exynos4_mct_tick_start(cycles, mevt);
-
-        return 0;
-}
-
-static inline void exynos4_tick_set_mode(enum clock_event_mode mode,
-                                         struct clock_event_device *evt)
-{
-        struct mct_clock_event_device *mevt = this_cpu_ptr(&percpu_mct_tick);
-        unsigned long cycles_per_jiffy;
-
-        exynos4_mct_tick_stop(mevt);
-
-        switch (mode) {
-        case CLOCK_EVT_MODE_PERIODIC:
-                cycles_per_jiffy =
-                        (((unsigned long long) NSEC_PER_SEC / HZ * evt->mult) >> evt->shift);
-                exynos4_mct_tick_start(cycles_per_jiffy, mevt);
-                break;
-
-        case CLOCK_EVT_MODE_ONESHOT:
-        case CLOCK_EVT_MODE_UNUSED:
-        case CLOCK_EVT_MODE_SHUTDOWN:
-        case CLOCK_EVT_MODE_RESUME:
-                break;
-        }
-}
-
-static int exynos4_mct_tick_clear(struct mct_clock_event_device *mevt)
-{
-        struct clock_event_device *evt = mevt->evt;
-
-        /*
-         * This is for supporting oneshot mode.
-         * Mct would generate interrupt periodically
-         * without explicit stopping.
-         */
-        if (evt->mode != CLOCK_EVT_MODE_PERIODIC)
-                exynos4_mct_tick_stop(mevt);
-
-        /* Clear the MCT tick interrupt */
-        if (__raw_readl(mevt->base + MCT_L_INT_CSTAT_OFFSET) & 1) {
-                exynos4_mct_write(0x1, mevt->base + MCT_L_INT_CSTAT_OFFSET);
-                return 1;
-        } else {
-                return 0;
-        }
-}
-
-static irqreturn_t exynos4_mct_tick_isr(int irq, void *dev_id)
-{
-        struct mct_clock_event_device *mevt = dev_id;
-        struct clock_event_device *evt = mevt->evt;
-
-        exynos4_mct_tick_clear(mevt);
-
-        evt->event_handler(evt);
-
-        return IRQ_HANDLED;
-}
-
-static struct irqaction mct_tick0_event_irq = {
-        .name           = "mct_tick0_irq",
-        .flags          = IRQF_TIMER | IRQF_NOBALANCING,
-        .handler        = exynos4_mct_tick_isr,
-};
-
-static struct irqaction mct_tick1_event_irq = {
-        .name           = "mct_tick1_irq",
-        .flags          = IRQF_TIMER | IRQF_NOBALANCING,
-        .handler        = exynos4_mct_tick_isr,
-};
-
-static int __cpuinit exynos4_local_timer_setup(struct clock_event_device *evt)
-{
-        struct mct_clock_event_device *mevt;
-        unsigned int cpu = smp_processor_id();
-        int mct_lx_irq;
-
-        mevt = this_cpu_ptr(&percpu_mct_tick);
-        mevt->evt = evt;
-
-        mevt->base = EXYNOS4_MCT_L_BASE(cpu);
-        sprintf(mevt->name, "mct_tick%d", cpu);
-
-        evt->name = mevt->name;
-        evt->cpumask = cpumask_of(cpu);
-        evt->set_next_event = exynos4_tick_set_next_event;
-        evt->set_mode = exynos4_tick_set_mode;
-        evt->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
-        evt->rating = 450;
-        clockevents_config_and_register(evt, clk_rate / (TICK_BASE_CNT + 1),
-                                        0xf, 0x7fffffff);
-
-        exynos4_mct_write(TICK_BASE_CNT, mevt->base + MCT_L_TCNTB_OFFSET);
-
-        if (mct_int_type == MCT_INT_SPI) {
-                if (cpu == 0) {
-                        mct_lx_irq = soc_is_exynos4210() ? EXYNOS4_IRQ_MCT_L0 :
-                                                EXYNOS5_IRQ_MCT_L0;
-                        mct_tick0_event_irq.dev_id = mevt;
-                        evt->irq = mct_lx_irq;
-                        setup_irq(mct_lx_irq, &mct_tick0_event_irq);
-                } else {
-                        mct_lx_irq = soc_is_exynos4210() ? EXYNOS4_IRQ_MCT_L1 :
-                                                EXYNOS5_IRQ_MCT_L1;
-                        mct_tick1_event_irq.dev_id = mevt;
-                        evt->irq = mct_lx_irq;
-                        setup_irq(mct_lx_irq, &mct_tick1_event_irq);
-                        irq_set_affinity(mct_lx_irq, cpumask_of(1));
-                }
-        } else {
-                enable_percpu_irq(EXYNOS_IRQ_MCT_LOCALTIMER, 0);
-        }
-
-        return 0;
-}
-
-static void exynos4_local_timer_stop(struct clock_event_device *evt)
-{
-        unsigned int cpu = smp_processor_id();
-        evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt);
-        if (mct_int_type == MCT_INT_SPI)
-                if (cpu == 0)
-                        remove_irq(evt->irq, &mct_tick0_event_irq);
-                else
-                        remove_irq(evt->irq, &mct_tick1_event_irq);
-        else
-                disable_percpu_irq(EXYNOS_IRQ_MCT_LOCALTIMER);
-}
-
-static struct local_timer_ops exynos4_mct_tick_ops __cpuinitdata = {
-        .setup  = exynos4_local_timer_setup,
-        .stop   = exynos4_local_timer_stop,
-};
-#endif /* CONFIG_LOCAL_TIMERS */
-
-static void __init exynos4_timer_resources(void)
-{
-        struct clk *mct_clk;
-        mct_clk = clk_get(NULL, "xtal");
-
-        clk_rate = clk_get_rate(mct_clk);
-
-#ifdef CONFIG_LOCAL_TIMERS
-        if (mct_int_type == MCT_INT_PPI) {
-                int err;
-
-                err = request_percpu_irq(EXYNOS_IRQ_MCT_LOCALTIMER,
-                                         exynos4_mct_tick_isr, "MCT",
-                                         &percpu_mct_tick);
-                WARN(err, "MCT: can't request IRQ %d (%d)\n",
-                     EXYNOS_IRQ_MCT_LOCALTIMER, err);
-        }
-
-        local_timer_register(&exynos4_mct_tick_ops);
-#endif /* CONFIG_LOCAL_TIMERS */
-}
-
-void __init exynos4_timer_init(void)
-{
-        if (soc_is_exynos5440()) {
-                arch_timer_of_register();
-                return;
-        }
-
-        if ((soc_is_exynos4210()) || (soc_is_exynos5250()))
-                mct_int_type = MCT_INT_SPI;
-        else
-                mct_int_type = MCT_INT_PPI;
-
-        exynos4_timer_resources();
-        exynos4_clocksource_init();
-        exynos4_clockevent_init();
-}
diff --git a/arch/arm/mach-highbank/highbank.c b/arch/arm/mach-highbank/highbank.c
index a4f9f50247d4..e7df2dd43a40 100644
--- a/arch/arm/mach-highbank/highbank.c
+++ b/arch/arm/mach-highbank/highbank.c
@@ -15,6 +15,7 @@
  */
 #include <linux/clk.h>
 #include <linux/clkdev.h>
+#include <linux/clocksource.h>
 #include <linux/dma-mapping.h>
 #include <linux/io.h>
 #include <linux/irq.h>
@@ -28,13 +29,9 @@
 #include <linux/amba/bus.h>
 #include <linux/clk-provider.h>
 
-#include <asm/arch_timer.h>
 #include <asm/cacheflush.h>
 #include <asm/cputype.h>
 #include <asm/smp_plat.h>
-#include <asm/smp_twd.h>
-#include <asm/hardware/arm_timer.h>
-#include <asm/hardware/timer-sp.h>
 #include <asm/hardware/cache-l2x0.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -91,38 +88,18 @@ static void __init highbank_init_irq(void)
 #endif
 }
 
-static struct clk_lookup lookup = {
-        .dev_id = "sp804",
-        .con_id = NULL,
-};
-
 static void __init highbank_timer_init(void)
 {
-        int irq;
         struct device_node *np;
-        void __iomem *timer_base;
 
         /* Map system registers */
         np = of_find_compatible_node(NULL, NULL, "calxeda,hb-sregs");
         sregs_base = of_iomap(np, 0);
         WARN_ON(!sregs_base);
 
-        np = of_find_compatible_node(NULL, NULL, "arm,sp804");
-        timer_base = of_iomap(np, 0);
-        WARN_ON(!timer_base);
-        irq = irq_of_parse_and_map(np, 0);
-
         of_clk_init(NULL);
-        lookup.clk = of_clk_get(np, 0);
-        clkdev_add(&lookup);
-
-        sp804_clocksource_and_sched_clock_init(timer_base + 0x20, "timer1");
-        sp804_clockevents_init(timer_base, irq, "timer0");
-
-        twd_local_timer_of_register();
 
-        arch_timer_of_register();
-        arch_timer_sched_clock_init();
+        clocksource_of_init();
 }
 
 static void highbank_power_off(void)
diff --git a/arch/arm/mach-imx/clk-busy.c b/arch/arm/mach-imx/clk-busy.c
index 1ab91b5209e6..85b728cc27ab 100644
--- a/arch/arm/mach-imx/clk-busy.c
+++ b/arch/arm/mach-imx/clk-busy.c
@@ -169,7 +169,7 @@ struct clk *imx_clk_busy_mux(const char *name, void __iomem *reg, u8 shift,
 
         busy->mux.reg = reg;
         busy->mux.shift = shift;
-        busy->mux.width = width;
+        busy->mux.mask = BIT(width) - 1;
         busy->mux.lock = &imx_ccm_lock;
         busy->mux_ops = &clk_mux_ops;
 
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index 9ffd103b27e4..b59ddcb57c78 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -12,6 +12,7 @@
 
 #include <linux/clk.h>
 #include <linux/clkdev.h>
+#include <linux/clocksource.h>
 #include <linux/cpu.h>
 #include <linux/delay.h>
 #include <linux/export.h>
@@ -28,11 +29,9 @@
 #include <linux/regmap.h>
 #include <linux/micrel_phy.h>
 #include <linux/mfd/syscon.h>
-#include <asm/smp_twd.h>
 #include <asm/hardware/cache-l2x0.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
-#include <asm/mach/time.h>
 #include <asm/system_misc.h>
 
 #include "common.h"
@@ -292,7 +291,7 @@ static void __init imx6q_init_irq(void)
 static void __init imx6q_timer_init(void)
 {
         mx6q_clocks_init();
-        twd_local_timer_of_register();
+        clocksource_of_init();
         imx_print_silicon_rev("i.MX6Q", imx6q_revision());
 }
 
diff --git a/arch/arm/mach-integrator/integrator_ap.c b/arch/arm/mach-integrator/integrator_ap.c
index ea961445e0e9..b23c8e4f28e8 100644
--- a/arch/arm/mach-integrator/integrator_ap.c
+++ b/arch/arm/mach-integrator/integrator_ap.c
@@ -536,16 +536,14 @@ static void __init ap_init_of(void)
                                            'A' + (ap_sc_id & 0x0f));
 
         soc_dev = soc_device_register(soc_dev_attr);
-        if (IS_ERR_OR_NULL(soc_dev)) {
+        if (IS_ERR(soc_dev)) {
                 kfree(soc_dev_attr->revision);
                 kfree(soc_dev_attr);
                 return;
         }
 
         parent = soc_device_to_device(soc_dev);
-
-        if (!IS_ERR_OR_NULL(parent))
-                integrator_init_sysfs(parent, ap_sc_id);
+        integrator_init_sysfs(parent, ap_sc_id);
 
         of_platform_populate(root, of_default_bus_match_table,
                         ap_auxdata_lookup, parent);
diff --git a/arch/arm/mach-integrator/integrator_cp.c b/arch/arm/mach-integrator/integrator_cp.c
index 2b0db82a5381..8c60fcb08a98 100644
--- a/arch/arm/mach-integrator/integrator_cp.c
+++ b/arch/arm/mach-integrator/integrator_cp.c
@@ -250,39 +250,6 @@ static void __init intcp_init_early(void)
 }
 
 #ifdef CONFIG_OF
-
-static void __init cp_of_timer_init(void)
-{
-        struct device_node *node;
-        const char *path;
-        void __iomem *base;
-        int err;
-        int irq;
-
-        err = of_property_read_string(of_aliases,
-                                "arm,timer-primary", &path);
-        if (WARN_ON(err))
-                return;
-        node = of_find_node_by_path(path);
-        base = of_iomap(node, 0);
-        if (WARN_ON(!base))
-                return;
-        writel(0, base + TIMER_CTRL);
-        sp804_clocksource_init(base, node->name);
-
-        err = of_property_read_string(of_aliases,
-                                "arm,timer-secondary", &path);
-        if (WARN_ON(err))
-                return;
-        node = of_find_node_by_path(path);
-        base = of_iomap(node, 0);
-        if (WARN_ON(!base))
-                return;
-        irq = irq_of_parse_and_map(node, 0);
-        writel(0, base + TIMER_CTRL);
-        sp804_clockevents_init(base, irq, node->name);
-}
-
 static const struct of_device_id fpga_irq_of_match[] __initconst = {
         { .compatible = "arm,versatile-fpga-irq", .data = fpga_irq_of_init, },
         { /* Sentinel */ }
@@ -360,17 +327,14 @@ static void __init intcp_init_of(void)
                                            'A' + (intcp_sc_id & 0x0f));
 
         soc_dev = soc_device_register(soc_dev_attr);
-        if (IS_ERR_OR_NULL(soc_dev)) {
+        if (IS_ERR(soc_dev)) {
                 kfree(soc_dev_attr->revision);
                 kfree(soc_dev_attr);
                 return;
         }
 
         parent = soc_device_to_device(soc_dev);
-
-        if (!IS_ERR_OR_NULL(parent))
-                integrator_init_sysfs(parent, intcp_sc_id);
-
+        integrator_init_sysfs(parent, intcp_sc_id);
         of_platform_populate(root, of_default_bus_match_table,
                         intcp_auxdata_lookup, parent);
 }
@@ -386,7 +350,6 @@ DT_MACHINE_START(INTEGRATOR_CP_DT, "ARM Integrator/CP (Device Tree)")
         .init_early     = intcp_init_early,
         .init_irq       = intcp_init_irq_of,
         .handle_irq     = fpga_handle_irq,
-        .init_time      = cp_of_timer_init,
         .init_machine   = intcp_init_of,
         .restart        = integrator_restart,
         .dt_compat      = intcp_dt_board_compat,
diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c
index 594c6335496e..23b004afa3f8 100644
--- a/arch/arm/mach-omap2/board-3430sdp.c
+++ b/arch/arm/mach-omap2/board-3430sdp.c
@@ -428,16 +428,23 @@ static void enable_board_wakeup_source(void)
                 OMAP_WAKEUP_EN | OMAP_PIN_INPUT_PULLUP);
 }
 
+static struct usbhs_phy_data phy_data[] __initdata = {
+        {
+                .port = 1,
+                .reset_gpio = 57,
+                .vcc_gpio = -EINVAL,
+        },
+        {
+                .port = 2,
+                .reset_gpio = 61,
+                .vcc_gpio = -EINVAL,
+        },
+};
+
 static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
 
         .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
         .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
-        .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
-
-        .phy_reset  = true,
-        .reset_gpio_port[0]  = 57,
-        .reset_gpio_port[1]  = 61,
-        .reset_gpio_port[2]  = -EINVAL
 };
 
 #ifdef CONFIG_OMAP_MUX
@@ -589,6 +596,8 @@ static void __init omap_3430sdp_init(void)
         board_flash_init(sdp_flash_partitions, chip_sel_3430, 0);
         sdp3430_display_init();
         enable_board_wakeup_source();
+
+        usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data));
         usbhs_init(&usbhs_bdata);
 }
 
diff --git a/arch/arm/mach-omap2/board-3630sdp.c b/arch/arm/mach-omap2/board-3630sdp.c
index 67447bd4564f..20d6d8189240 100644
--- a/arch/arm/mach-omap2/board-3630sdp.c
+++ b/arch/arm/mach-omap2/board-3630sdp.c
@@ -53,16 +53,23 @@ static void enable_board_wakeup_source(void)
                 OMAP_WAKEUP_EN | OMAP_PIN_INPUT_PULLUP);
 }
 
+static struct usbhs_phy_data phy_data[] __initdata = {
+        {
+                .port = 1,
+                .reset_gpio = 126,
+                .vcc_gpio = -EINVAL,
+        },
+        {
+                .port = 2,
+                .reset_gpio = 61,
+                .vcc_gpio = -EINVAL,
+        },
+};
+
 static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
 
         .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
         .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
-        .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
-
-        .phy_reset  = true,
-        .reset_gpio_port[0]  = 126,
-        .reset_gpio_port[1]  = 61,
-        .reset_gpio_port[2]  = -EINVAL
 };
 
 #ifdef CONFIG_OMAP_MUX
@@ -199,6 +206,8 @@ static void __init omap_sdp_init(void)
         board_smc91x_init();
         board_flash_init(sdp_flash_partitions, chip_sel_sdp, NAND_BUSWIDTH_16);
         enable_board_wakeup_source();
+
+        usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data));
         usbhs_init(&usbhs_bdata);
 }
 
diff --git a/arch/arm/mach-omap2/board-am3517crane.c b/arch/arm/mach-omap2/board-am3517crane.c
index 7d3358b2e593..fc53911d0d13 100644
--- a/arch/arm/mach-omap2/board-am3517crane.c
+++ b/arch/arm/mach-omap2/board-am3517crane.c
@@ -47,15 +47,17 @@ static struct omap_board_mux board_mux[] __initdata = {
 };
 #endif
 
+static struct usbhs_phy_data phy_data[] __initdata = {
+        {
+                .port = 1,
+                .reset_gpio = GPIO_USB_NRESET,
+                .vcc_gpio = GPIO_USB_POWER,
+                .vcc_polarity = 1,
+        },
+};
+
 static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
         .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
-        .port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED,
-        .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
-
-        .phy_reset  = true,
-        .reset_gpio_port[0]  = GPIO_USB_NRESET,
-        .reset_gpio_port[1]  = -EINVAL,
-        .reset_gpio_port[2]  = -EINVAL
 };
 
 static struct mtd_partition crane_nand_partitions[] = {
@@ -131,13 +133,7 @@ static void __init am3517_crane_init(void)
                 return;
         }
 
-        ret = gpio_request_one(GPIO_USB_POWER, GPIOF_OUT_INIT_HIGH,
-                               "usb_ehci_enable");
-        if (ret < 0) {
-                pr_err("Can not request GPIO %d\n", GPIO_USB_POWER);
-                return;
-        }
-
+        usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data));
         usbhs_init(&usbhs_bdata);
         am35xx_emac_init(AM35XX_DEFAULT_MDIO_FREQUENCY, 1);
 }
diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c
index 2b9eb3de7aa6..d63f14b534b5 100644
--- a/arch/arm/mach-omap2/board-am3517evm.c
+++ b/arch/arm/mach-omap2/board-am3517evm.c
@@ -213,6 +213,14 @@ static __init void am3517_evm_mcbsp1_init(void)
         omap_ctrl_writel(devconf0, OMAP2_CONTROL_DEVCONF0);
 }
 
+static struct usbhs_phy_data phy_data[] __initdata = {
+        {
+                .port = 1,
+                .reset_gpio = 57,
+                .vcc_gpio = -EINVAL,
+        },
+};
+
 static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
         .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
 #if defined(CONFIG_PANEL_SHARP_LQ043T1DG01) || \
@@ -221,12 +229,6 @@ static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
 #else
         .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
 #endif
-        .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
-
-        .phy_reset  = true,
-        .reset_gpio_port[0]  = 57,
-        .reset_gpio_port[1]  = -EINVAL,
-        .reset_gpio_port[2]  = -EINVAL
 };
 
 #ifdef CONFIG_OMAP_MUX
@@ -288,7 +290,6 @@ static struct omap2_hsmmc_info mmc[] = {
         {}      /* Terminator */
 };
 
-
 static void __init am3517_evm_init(void)
 {
         omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
@@ -300,6 +301,8 @@ static void __init am3517_evm_init(void)
 
         /* Configure GPIO for EHCI port */
         omap_mux_init_gpio(57, OMAP_PIN_OUTPUT);
+
+        usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data));
         usbhs_init(&usbhs_bdata);
         am3517_evm_hecc_init(&am3517_evm_hecc_pdata);
 
diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c
index 710e99da266c..ee6218c74807 100644
--- a/arch/arm/mach-omap2/board-cm-t35.c
+++ b/arch/arm/mach-omap2/board-cm-t35.c
@@ -376,15 +376,22 @@ static struct omap2_hsmmc_info mmc[] = {
         {}      /* Terminator */
 };
 
+static struct usbhs_phy_data phy_data[] __initdata = {
+        {
+                .port = 1,
+                .reset_gpio = OMAP_MAX_GPIO_LINES + 6,
+                .vcc_gpio = -EINVAL,
+        },
+        {
+                .port = 2,
+                .reset_gpio = OMAP_MAX_GPIO_LINES + 7,
+                .vcc_gpio = -EINVAL,
+        },
+};
+
 static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
         .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
         .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
-        .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
-
-        .phy_reset  = true,
-        .reset_gpio_port[0]  = OMAP_MAX_GPIO_LINES + 6,
-        .reset_gpio_port[1]  = OMAP_MAX_GPIO_LINES + 7,
-        .reset_gpio_port[2]  = -EINVAL
 };
 
 static void  __init cm_t35_init_usbh(void)
@@ -401,6 +408,7 @@ static void  __init cm_t35_init_usbh(void)
                 msleep(1);
         }
 
+        usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data));
         usbhs_init(&usbhs_bdata);
 }
 
diff --git a/arch/arm/mach-omap2/board-cm-t3517.c b/arch/arm/mach-omap2/board-cm-t3517.c
index a66da808cc4a..4eb5e6f2f7f5 100644
--- a/arch/arm/mach-omap2/board-cm-t3517.c
+++ b/arch/arm/mach-omap2/board-cm-t3517.c
@@ -188,15 +188,22 @@ static inline void cm_t3517_init_rtc(void) {}
 #define HSUSB2_RESET_GPIO       (147)
 #define USB_HUB_RESET_GPIO      (152)
 
+static struct usbhs_phy_data phy_data[] __initdata = {
+        {
+                .port = 1,
+                .reset_gpio = HSUSB1_RESET_GPIO,
+                .vcc_gpio = -EINVAL,
+        },
+        {
+                .port = 2,
+                .reset_gpio = HSUSB2_RESET_GPIO,
+                .vcc_gpio = -EINVAL,
+        },
+};
+
 static struct usbhs_omap_platform_data cm_t3517_ehci_pdata __initdata = {
         .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
         .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
-        .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
-
-        .phy_reset  = true,
-        .reset_gpio_port[0]  = HSUSB1_RESET_GPIO,
-        .reset_gpio_port[1]  = HSUSB2_RESET_GPIO,
-        .reset_gpio_port[2]  = -EINVAL,
 };
 
 static int __init cm_t3517_init_usbh(void)
@@ -213,6 +220,7 @@ static int __init cm_t3517_init_usbh(void)
                 msleep(1);
         }
 
+        usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data));
         usbhs_init(&cm_t3517_ehci_pdata);
 
         return 0;
@@ -324,6 +332,6 @@ MACHINE_START(CM_T3517, "Compulab CM-T3517")
         .handle_irq     = omap3_intc_handle_irq,
         .init_machine   = cm_t3517_init,
         .init_late      = am35xx_init_late,
-        .init_time      = omap3_gp_gptimer_timer_init,
+        .init_time      = omap3_gptimer_timer_init,
         .restart        = omap3xxx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c
index 34944cfdfbd9..576420544178 100644
--- a/arch/arm/mach-omap2/board-devkit8000.c
+++ b/arch/arm/mach-omap2/board-devkit8000.c
@@ -415,15 +415,7 @@ static struct platform_device *devkit8000_devices[] __initdata = {
 };
 
 static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
-
         .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
-        .port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED,
-        .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
-
-        .phy_reset  = true,
-        .reset_gpio_port[0]  = -EINVAL,
-        .reset_gpio_port[1]  = -EINVAL,
-        .reset_gpio_port[2]  = -EINVAL
 };
 
 #ifdef CONFIG_OMAP_MUX
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
index e54a48060198..78813b397209 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -140,7 +140,7 @@ DT_MACHINE_START(AM33XX_DT, "Generic AM33XX (Flattened Device Tree)")
         .init_irq       = omap_intc_of_init,
         .handle_irq     = omap3_intc_handle_irq,
         .init_machine   = omap_generic_init,
-        .init_time      = omap3_am33xx_gptimer_timer_init,
+        .init_time      = omap3_gptimer_timer_init,
         .dt_compat      = am33xx_boards_compat,
         .restart        = am33xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c
index e979d48270c9..b54562d1235e 100644
--- a/arch/arm/mach-omap2/board-igep0020.c
+++ b/arch/arm/mach-omap2/board-igep0020.c
@@ -527,26 +527,28 @@ static void __init igep_i2c_init(void)
         omap3_pmic_init("twl4030", &igep_twldata);
 }
 
+static struct usbhs_phy_data igep2_phy_data[] __initdata = {
+        {
+                .port = 1,
+                .reset_gpio = IGEP2_GPIO_USBH_NRESET,
+                .vcc_gpio = -EINVAL,
+        },
+};
+
+static struct usbhs_phy_data igep3_phy_data[] __initdata = {
+        {
+                .port = 2,
+                .reset_gpio = IGEP3_GPIO_USBH_NRESET,
+                .vcc_gpio = -EINVAL,
+        },
+};
+
 static struct usbhs_omap_platform_data igep2_usbhs_bdata __initdata = {
         .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
-        .port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED,
-        .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
-
-        .phy_reset = true,
-        .reset_gpio_port[0] = IGEP2_GPIO_USBH_NRESET,
-        .reset_gpio_port[1] = -EINVAL,
-        .reset_gpio_port[2] = -EINVAL,
 };
 
 static struct usbhs_omap_platform_data igep3_usbhs_bdata __initdata = {
-        .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
         .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
-        .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
-
-        .phy_reset = true,
-        .reset_gpio_port[0] = -EINVAL,
-        .reset_gpio_port[1] = IGEP3_GPIO_USBH_NRESET,
-        .reset_gpio_port[2] = -EINVAL,
 };
 
 #ifdef CONFIG_OMAP_MUX
@@ -642,8 +644,10 @@ static void __init igep_init(void)
         if (machine_is_igep0020()) {
                 omap_display_init(&igep2_dss_data);
                 igep2_init_smsc911x();
+                usbhs_init_phys(igep2_phy_data, ARRAY_SIZE(igep2_phy_data));
                 usbhs_init(&igep2_usbhs_bdata);
         } else {
+                usbhs_init_phys(igep3_phy_data, ARRAY_SIZE(igep3_phy_data));
                 usbhs_init(&igep3_usbhs_bdata);
         }
 }
diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
index 0ce91af753fa..6de78605c0af 100644
--- a/arch/arm/mach-omap2/board-omap3beagle.c
+++ b/arch/arm/mach-omap2/board-omap3beagle.c
@@ -33,6 +33,7 @@
 #include <linux/mtd/nand.h>
 #include <linux/mmc/host.h>
 #include <linux/usb/phy.h>
+#include <linux/usb/nop-usb-xceiv.h>
 
 #include <linux/regulator/machine.h>
 #include <linux/i2c/twl.h>
@@ -277,6 +278,21 @@ static struct regulator_consumer_supply beagle_vsim_supply[] = {
 
 static struct gpio_led gpio_leds[];
 
+/* PHY's VCC regulator might be added later, so flag that we need it */
+static struct nop_usb_xceiv_platform_data hsusb2_phy_data = {
+        .needs_vcc = true,
+};
+
+static struct usbhs_phy_data phy_data[] = {
+        {
+                .port = 2,
+                .reset_gpio = 147,
+                .vcc_gpio = -1,         /* updated in beagle_twl_gpio_setup */
+                .vcc_polarity = 1,      /* updated in beagle_twl_gpio_setup */
+                .platform_data = &hsusb2_phy_data,
+        },
+};
+
 static int beagle_twl_gpio_setup(struct device *dev,
                 unsigned gpio, unsigned ngpio)
 {
@@ -318,9 +334,11 @@ static int beagle_twl_gpio_setup(struct device *dev,
         }
         dvi_panel.power_down_gpio = beagle_config.dvi_pd_gpio;
 
-        gpio_request_one(gpio + TWL4030_GPIO_MAX, beagle_config.usb_pwr_level,
-                        "nEN_USB_PWR");
+        /* TWL4030_GPIO_MAX i.e. LED_GPO controls HS USB Port 2 power */
+        phy_data[0].vcc_gpio = gpio + TWL4030_GPIO_MAX;
+        phy_data[0].vcc_polarity = beagle_config.usb_pwr_level;
 
+        usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data));
         return 0;
 }
 
@@ -453,15 +471,7 @@ static struct platform_device *omap3_beagle_devices[] __initdata = {
 };
 
 static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
-
-        .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
         .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
-        .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
-
-        .phy_reset  = true,
-        .reset_gpio_port[0]  = -EINVAL,
-        .reset_gpio_port[1]  = 147,
-        .reset_gpio_port[2]  = -EINVAL
 };
 
 #ifdef CONFIG_OMAP_MUX
@@ -479,7 +489,7 @@ static int __init beagle_opp_init(void)
 
         /* Initialize the omap3 opp table if not already created. */
         r = omap3_opp_init();
-        if (IS_ERR_VALUE(r) && (r != -EEXIST)) {
+        if (r < 0 && (r != -EEXIST)) {
                 pr_err("%s: opp default init failed\n", __func__);
                 return r;
         }
@@ -543,7 +553,9 @@ static void __init omap3_beagle_init(void)
 
         usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
         usb_musb_init(NULL);
+
         usbhs_init(&usbhs_bdata);
+
         board_nand_init(omap3beagle_nand_partitions,
                         ARRAY_SIZE(omap3beagle_nand_partitions), NAND_CS,
                         NAND_BUSWIDTH_16, NULL);
diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
index 5eecc178f8bf..f76d0de7b406 100644
--- a/arch/arm/mach-omap2/board-omap3evm.c
+++ b/arch/arm/mach-omap2/board-omap3evm.c
@@ -466,7 +466,7 @@ struct wl12xx_platform_data omap3evm_wlan_data __initdata = {
 static struct regulator_consumer_supply omap3evm_vaux2_supplies[] = {
         REGULATOR_SUPPLY("VDD_CSIPHY1", "omap3isp"),    /* OMAP ISP */
         REGULATOR_SUPPLY("VDD_CSIPHY2", "omap3isp"),    /* OMAP ISP */
-        REGULATOR_SUPPLY("hsusb1", "ehci-omap.0"),
+        REGULATOR_SUPPLY("vcc", "nop_usb_xceiv.2"),     /* hsusb port 2 */
         REGULATOR_SUPPLY("vaux2", NULL),
 };
 
@@ -509,17 +509,16 @@ static int __init omap3_evm_i2c_init(void)
         return 0;
 }
 
-static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
+static struct usbhs_phy_data phy_data[] __initdata = {
+        {
+                .port = 2,
+                .reset_gpio = -1,       /* set at runtime */
+                .vcc_gpio = -EINVAL,
+        },
+};
 
-        .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
+static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
         .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
-        .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
-
-        .phy_reset  = true,
-        /* PHY reset GPIO will be runtime programmed based on EVM version */
-        .reset_gpio_port[0]  = -EINVAL,
-        .reset_gpio_port[1]  = -EINVAL,
-        .reset_gpio_port[2]  = -EINVAL
 };
 
 #ifdef CONFIG_OMAP_MUX
@@ -695,7 +694,7 @@ static void __init omap3_evm_init(void)
 
                 /* setup EHCI phy reset config */
                 omap_mux_init_gpio(21, OMAP_PIN_INPUT_PULLUP);
-                usbhs_bdata.reset_gpio_port[1] = 21;
+                phy_data[0].reset_gpio = 21;
 
                 /* EVM REV >= E can supply 500mA with EXTVBUS programming */
                 musb_board_data.power = 500;
@@ -703,10 +702,12 @@ static void __init omap3_evm_init(void)
         } else {
                 /* setup EHCI phy reset on MDC */
                 omap_mux_init_gpio(135, OMAP_PIN_OUTPUT);
-                usbhs_bdata.reset_gpio_port[1] = 135;
+                phy_data[0].reset_gpio = 135;
         }
         usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
         usb_musb_init(&musb_board_data);
+
+        usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data));
         usbhs_init(&usbhs_bdata);
         board_nand_init(omap3evm_nand_partitions,
                         ARRAY_SIZE(omap3evm_nand_partitions), NAND_CS,
diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c
index 533180f8bf41..28133d5b4fed 100644
--- a/arch/arm/mach-omap2/board-omap3pandora.c
+++ b/arch/arm/mach-omap2/board-omap3pandora.c
@@ -351,7 +351,7 @@ static struct regulator_consumer_supply pandora_vcc_lcd_supply[] = {
 };
 
 static struct regulator_consumer_supply pandora_usb_phy_supply[] = {
-        REGULATOR_SUPPLY("hsusb1", "ehci-omap.0"),
+        REGULATOR_SUPPLY("vcc", "nop_usb_xceiv.2"),     /* hsusb port 2 */
 };
 
 /* ads7846 on SPI and 2 nub controllers on I2C */
@@ -566,6 +566,14 @@ fail:
         printk(KERN_ERR "wl1251 board initialisation failed\n");
 }
 
+static struct usbhs_phy_data phy_data[] __initdata = {
+        {
+                .port = 2,
+                .reset_gpio = 16,
+                .vcc_gpio = -EINVAL,
+        },
+};
+
 static struct platform_device *omap3pandora_devices[] __initdata = {
         &pandora_leds_gpio,
         &pandora_keys_gpio,
@@ -574,15 +582,7 @@ static struct platform_device *omap3pandora_devices[] __initdata = {
 };
 
 static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
-
-        .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
         .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
-        .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
-
-        .phy_reset  = true,
-        .reset_gpio_port[0]  = -EINVAL,
-        .reset_gpio_port[1]  = 16,
-        .reset_gpio_port[2]  = -EINVAL
 };
 
 #ifdef CONFIG_OMAP_MUX
@@ -606,7 +606,10 @@ static void __init omap3pandora_init(void)
         spi_register_board_info(omap3pandora_spi_board_info,
                         ARRAY_SIZE(omap3pandora_spi_board_info));
         omap_ads7846_init(1, OMAP3_PANDORA_TS_GPIO, 0, NULL);
+
+        usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data));
         usbhs_init(&usbhs_bdata);
+
         usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
         usb_musb_init(NULL);
         gpmc_nand_init(&pandora_nand_data, NULL);
diff --git a/arch/arm/mach-omap2/board-omap3stalker.c b/arch/arm/mach-omap2/board-omap3stalker.c
index 5e63f0758cef..d37e6b187ae4 100644
--- a/arch/arm/mach-omap2/board-omap3stalker.c
+++ b/arch/arm/mach-omap2/board-omap3stalker.c
@@ -346,19 +346,20 @@ static int __init omap3_stalker_i2c_init(void)
 
 #define OMAP3_STALKER_TS_GPIO   175
 
+static struct usbhs_phy_data phy_data[] __initdata = {
+        {
+                .port = 2,
+                .reset_gpio = 21,
+                .vcc_gpio = -EINVAL,
+        },
+};
+
 static struct platform_device *omap3_stalker_devices[] __initdata = {
         &keys_gpio,
 };
 
 static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
-        .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
         .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
-        .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
-
-        .phy_reset = true,
-        .reset_gpio_port[0] = -EINVAL,
-        .reset_gpio_port[1] = 21,
-        .reset_gpio_port[2] = -EINVAL,
 };
 
 #ifdef CONFIG_OMAP_MUX
@@ -395,6 +396,8 @@ static void __init omap3_stalker_init(void)
         omap_sdrc_init(mt46h32m32lf6_sdrc_params, NULL);
         usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
         usb_musb_init(NULL);
+
+        usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data));
         usbhs_init(&usbhs_bdata);
         omap_ads7846_init(1, OMAP3_STALKER_TS_GPIO, 310, NULL);
 
diff --git a/arch/arm/mach-omap2/board-omap3touchbook.c b/arch/arm/mach-omap2/board-omap3touchbook.c
index bcd44fbcd877..7da48bc42bbf 100644
--- a/arch/arm/mach-omap2/board-omap3touchbook.c
+++ b/arch/arm/mach-omap2/board-omap3touchbook.c
@@ -305,21 +305,22 @@ static struct omap_board_mux board_mux[] __initdata = {
 };
 #endif
 
+static struct usbhs_phy_data phy_data[] __initdata = {
+        {
+                .port = 2,
+                .reset_gpio = 147,
+                .vcc_gpio = -EINVAL,
+        },
+};
+
 static struct platform_device *omap3_touchbook_devices[] __initdata = {
         &leds_gpio,
         &keys_gpio,
 };
 
 static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
-
         .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
         .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
-        .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
-
-        .phy_reset  = true,
-        .reset_gpio_port[0]  = -EINVAL,
-        .reset_gpio_port[1]  = 147,
-        .reset_gpio_port[2]  = -EINVAL
 };
 
 static void omap3_touchbook_poweroff(void)
@@ -368,6 +369,8 @@ static void __init omap3_touchbook_init(void)
         omap_ads7846_init(4, OMAP3_TS_GPIO, 310, &ads7846_pdata);
         usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
         usb_musb_init(NULL);
+
+        usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data));
         usbhs_init(&usbhs_bdata);
         board_nand_init(omap3touchbook_nand_partitions,
                         ARRAY_SIZE(omap3touchbook_nand_partitions), NAND_CS,
diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c
index b02c2f00609b..a71ad345f20d 100644
--- a/arch/arm/mach-omap2/board-omap4panda.c
+++ b/arch/arm/mach-omap2/board-omap4panda.c
@@ -31,6 +31,7 @@
 #include <linux/ti_wilink_st.h>
 #include <linux/usb/musb.h>
 #include <linux/usb/phy.h>
+#include <linux/usb/nop-usb-xceiv.h>
 #include <linux/wl12xx.h>
 #include <linux/irqchip/arm-gic.h>
 #include <linux/platform_data/omap-abe-twl6040.h>
@@ -132,6 +133,22 @@ static struct platform_device btwilink_device = {
         .id     = -1,
 };
 
+/* PHY device on HS USB Port 1 i.e. nop_usb_xceiv.1 */
+static struct nop_usb_xceiv_platform_data hsusb1_phy_data = {
+        /* FREF_CLK3 provides the 19.2 MHz reference clock to the PHY */
+        .clk_rate = 19200000,
+};
+
+static struct usbhs_phy_data phy_data[] __initdata = {
+        {
+                .port = 1,
+                .reset_gpio = GPIO_HUB_NRESET,
+                .vcc_gpio = GPIO_HUB_POWER,
+                .vcc_polarity = 1,
+                .platform_data = &hsusb1_phy_data,
+        },
+};
+
 static struct platform_device *panda_devices[] __initdata = {
         &leds_gpio,
         &wl1271_device,
@@ -142,49 +159,19 @@ static struct platform_device *panda_devices[] __initdata = {
 
 static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
         .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
-        .port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED,
-        .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
-        .phy_reset  = false,
-        .reset_gpio_port[0]  = -EINVAL,
-        .reset_gpio_port[1]  = -EINVAL,
-        .reset_gpio_port[2]  = -EINVAL
-};
-
-static struct gpio panda_ehci_gpios[] __initdata = {
-        { GPIO_HUB_POWER,       GPIOF_OUT_INIT_LOW,  "hub_power"  },
-        { GPIO_HUB_NRESET,      GPIOF_OUT_INIT_LOW,  "hub_nreset" },
 };
 
 static void __init omap4_ehci_init(void)
 {
         int ret;
-        struct clk *phy_ref_clk;
 
         /* FREF_CLK3 provides the 19.2 MHz reference clock to the PHY */
-        phy_ref_clk = clk_get(NULL, "auxclk3_ck");
-        if (IS_ERR(phy_ref_clk)) {
-                pr_err("Cannot request auxclk3\n");
-                return;
-        }
-        clk_set_rate(phy_ref_clk, 19200000);
-        clk_prepare_enable(phy_ref_clk);
-
-        /* disable the power to the usb hub prior to init and reset phy+hub */
-        ret = gpio_request_array(panda_ehci_gpios,
-                                 ARRAY_SIZE(panda_ehci_gpios));
-        if (ret) {
-                pr_err("Unable to initialize EHCI power/reset\n");
-                return;
-        }
-
-        gpio_export(GPIO_HUB_POWER, 0);
-        gpio_export(GPIO_HUB_NRESET, 0);
-        gpio_set_value(GPIO_HUB_NRESET, 1);
+        ret = clk_add_alias("main_clk", "nop_usb_xceiv.1", "auxclk3_ck", NULL);
+        if (ret)
+                pr_err("Failed to add main_clk alias to auxclk3_ck\n");
 
+        usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data));
         usbhs_init(&usbhs_bdata);
-
-        /* enable power to hub */
-        gpio_set_value(GPIO_HUB_POWER, 1);
 }
 
 static struct omap_musb_board_data musb_board_data = {
diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c
index f790ce5aaa34..4ca6b680aa72 100644
--- a/arch/arm/mach-omap2/board-overo.c
+++ b/arch/arm/mach-omap2/board-overo.c
@@ -428,14 +428,16 @@ static int __init overo_spi_init(void)
         return 0;
 }
 
+static struct usbhs_phy_data phy_data[] __initdata = {
+        {
+                .port = 2,
+                .reset_gpio = OVERO_GPIO_USBH_NRESET,
+                .vcc_gpio = -EINVAL,
+        },
+};
+
 static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
-        .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
         .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
-        .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
-        .phy_reset  = true,
-        .reset_gpio_port[0]  = -EINVAL,
-        .reset_gpio_port[1]  = OVERO_GPIO_USBH_NRESET,
-        .reset_gpio_port[2]  = -EINVAL
 };
 
 #ifdef CONFIG_OMAP_MUX
@@ -472,6 +474,8 @@ static void __init overo_init(void)
                         ARRAY_SIZE(overo_nand_partitions), NAND_CS, 0, NULL);
         usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
         usb_musb_init(NULL);
+
+        usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data));
         usbhs_init(&usbhs_bdata);
         overo_spi_init();
         overo_init_smsc911x();
diff --git a/arch/arm/mach-omap2/board-zoom.c b/arch/arm/mach-omap2/board-zoom.c
index 5e4d4c9fe61a..1a3dd865d8eb 100644
--- a/arch/arm/mach-omap2/board-zoom.c
+++ b/arch/arm/mach-omap2/board-zoom.c
@@ -92,14 +92,16 @@ static struct mtd_partition zoom_nand_partitions[] = {
         },
 };
 
+static struct usbhs_phy_data phy_data[] __initdata = {
+        {
+                .port = 2,
+                .reset_gpio = ZOOM3_EHCI_RESET_GPIO,
+                .vcc_gpio = -EINVAL,
+        },
+};
+
 static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
-        .port_mode[0]           = OMAP_USBHS_PORT_MODE_UNUSED,
         .port_mode[1]           = OMAP_EHCI_PORT_MODE_PHY,
-        .port_mode[2]           = OMAP_USBHS_PORT_MODE_UNUSED,
-        .phy_reset              = true,
-        .reset_gpio_port[0]     = -EINVAL,
-        .reset_gpio_port[1]     = ZOOM3_EHCI_RESET_GPIO,
-        .reset_gpio_port[2]     = -EINVAL,
 };
 
 static void __init omap_zoom_init(void)
@@ -109,6 +111,8 @@ static void __init omap_zoom_init(void)
         } else if (machine_is_omap_zoom3()) {
                 omap3_mux_init(board_mux, OMAP_PACKAGE_CBP);
                 omap_mux_init_gpio(ZOOM3_EHCI_RESET_GPIO, OMAP_PIN_OUTPUT);
+
+                usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data));
                 usbhs_init(&usbhs_bdata);
         }
 
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index e4ec3a69ee2e..2191f25ad21b 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -596,7 +596,7 @@ int __init omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name)
                 return -ENOENT;
 
         r = clk_set_rate(mpurate_ck, mpurate);
-        if (IS_ERR_VALUE(r)) {
+        if (r < 0) {
                 WARN(1, "clock: %s: unable to set MPU rate to %d: %d\n",
                      mpurate_ck_name, mpurate, r);
                 clk_put(mpurate_ck);
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index d6ba13e1c540..272490e72ee0 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -82,8 +82,7 @@ extern void omap2_init_common_infrastructure(void);
 extern void omap2_sync32k_timer_init(void);
 extern void omap3_sync32k_timer_init(void);
 extern void omap3_secure_sync32k_timer_init(void);
-extern void omap3_gp_gptimer_timer_init(void);
-extern void omap3_am33xx_gptimer_timer_init(void);
+extern void omap3_gptimer_timer_init(void);
 extern void omap4_local_timer_init(void);
 extern void omap5_realtime_timer_init(void);
 
diff --git a/arch/arm/mach-omap2/gpmc-nand.c b/arch/arm/mach-omap2/gpmc-nand.c
index afc1e8c32d6c..d9c27195caf0 100644
--- a/arch/arm/mach-omap2/gpmc-nand.c
+++ b/arch/arm/mach-omap2/gpmc-nand.c
@@ -74,14 +74,6 @@ static int omap2_nand_gpmc_retime(
         t.cs_wr_off = gpmc_t->cs_wr_off;
         t.wr_cycle = gpmc_t->wr_cycle;
 
-        /* Configure GPMC */
-        if (gpmc_nand_data->devsize == NAND_BUSWIDTH_16)
-                gpmc_cs_configure(gpmc_nand_data->cs, GPMC_CONFIG_DEV_SIZE, 1);
-        else
-                gpmc_cs_configure(gpmc_nand_data->cs, GPMC_CONFIG_DEV_SIZE, 0);
-        gpmc_cs_configure(gpmc_nand_data->cs,
-                        GPMC_CONFIG_DEV_TYPE, GPMC_DEVICETYPE_NAND);
-        gpmc_cs_configure(gpmc_nand_data->cs, GPMC_CONFIG_WP, 0);
         err = gpmc_cs_set_timings(gpmc_nand_data->cs, &t);
         if (err)
                 return err;
@@ -115,14 +107,18 @@ int gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data,
                    struct gpmc_timings *gpmc_t)
 {
         int err = 0;
+        struct gpmc_settings s;
         struct device *dev = &gpmc_nand_device.dev;
 
+        memset(&s, 0, sizeof(struct gpmc_settings));
+
         gpmc_nand_device.dev.platform_data = gpmc_nand_data;
 
         err = gpmc_cs_request(gpmc_nand_data->cs, NAND_IO_SIZE,
                                 (unsigned long *)&gpmc_nand_resource[0].start);
         if (err < 0) {
-                dev_err(dev, "Cannot request GPMC CS\n");
+                dev_err(dev, "Cannot request GPMC CS %d, error %d\n",
+                        gpmc_nand_data->cs, err);
                 return err;
         }
 
@@ -140,11 +136,31 @@ int gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data,
                         dev_err(dev, "Unable to set gpmc timings: %d\n", err);
                         return err;
                 }
-        }
 
-        /* Enable RD PIN Monitoring Reg */
-        if (gpmc_nand_data->dev_ready) {
-                gpmc_cs_configure(gpmc_nand_data->cs, GPMC_CONFIG_RDY_BSY, 1);
+                if (gpmc_nand_data->of_node) {
+                        gpmc_read_settings_dt(gpmc_nand_data->of_node, &s);
+                } else {
+                        s.device_nand = true;
+
+                        /* Enable RD PIN Monitoring Reg */
+                        if (gpmc_nand_data->dev_ready) {
+                                s.wait_on_read = true;
+                                s.wait_on_write = true;
+                        }
+                }
+
+                if (gpmc_nand_data->devsize == NAND_BUSWIDTH_16)
+                        s.device_width = GPMC_DEVWIDTH_16BIT;
+                else
+                        s.device_width = GPMC_DEVWIDTH_8BIT;
+
+                err = gpmc_cs_program_settings(gpmc_nand_data->cs, &s);
+                if (err < 0)
+                        goto out_free_cs;
+
+                err = gpmc_configure(GPMC_CONFIG_WP, 0);
+                if (err < 0)
+                        goto out_free_cs;
         }
 
         gpmc_update_nand_reg(&gpmc_nand_data->reg, gpmc_nand_data->cs);
diff --git a/arch/arm/mach-omap2/gpmc-onenand.c b/arch/arm/mach-omap2/gpmc-onenand.c
index fadd87435cd0..64b5a8346982 100644
--- a/arch/arm/mach-omap2/gpmc-onenand.c
+++ b/arch/arm/mach-omap2/gpmc-onenand.c
@@ -47,11 +47,23 @@ static struct platform_device gpmc_onenand_device = {
         .resource       = &gpmc_onenand_resource,
 };
 
-static struct gpmc_timings omap2_onenand_calc_async_timings(void)
+static struct gpmc_settings onenand_async = {
+        .device_width   = GPMC_DEVWIDTH_16BIT,
+        .mux_add_data   = GPMC_MUX_AD,
+};
+
+static struct gpmc_settings onenand_sync = {
+        .burst_read     = true,
+        .burst_wrap     = true,
+        .burst_len      = GPMC_BURST_16,
+        .device_width   = GPMC_DEVWIDTH_16BIT,
+        .mux_add_data   = GPMC_MUX_AD,
+        .wait_pin       = 0,
+};
+
+static void omap2_onenand_calc_async_timings(struct gpmc_timings *t)
 {
         struct gpmc_device_timings dev_t;
-        struct gpmc_timings t;
-
         const int t_cer = 15;
         const int t_avdp = 12;
         const int t_aavdh = 7;
@@ -64,7 +76,6 @@ static struct gpmc_timings omap2_onenand_calc_async_timings(void)
 
         memset(&dev_t, 0, sizeof(dev_t));
 
-        dev_t.mux = true;
         dev_t.t_avdp_r = max_t(int, t_avdp, t_cer) * 1000;
         dev_t.t_avdp_w = dev_t.t_avdp_r;
         dev_t.t_aavdh = t_aavdh * 1000;
@@ -76,19 +87,7 @@ static struct gpmc_timings omap2_onenand_calc_async_timings(void)
         dev_t.t_wpl = t_wpl * 1000;
         dev_t.t_wph = t_wph * 1000;
 
-        gpmc_calc_timings(&t, &dev_t);
-
-        return t;
-}
-
-static int gpmc_set_async_mode(int cs, struct gpmc_timings *t)
-{
-        /* Configure GPMC for asynchronous read */
-        gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1,
-                          GPMC_CONFIG1_DEVICESIZE_16 |
-                          GPMC_CONFIG1_MUXADDDATA);
-
-        return gpmc_cs_set_timings(cs, t);
+        gpmc_calc_timings(t, &onenand_async, &dev_t);
 }
 
 static void omap2_onenand_set_async_mode(void __iomem *onenand_base)
@@ -158,12 +157,11 @@ static int omap2_onenand_get_freq(struct omap_onenand_platform_data *cfg,
         return freq;
 }
 
-static struct gpmc_timings
-omap2_onenand_calc_sync_timings(struct omap_onenand_platform_data *cfg,
-                                int freq)
+static void omap2_onenand_calc_sync_timings(struct gpmc_timings *t,
+                                            unsigned int flags,
+                                            int freq)
 {
         struct gpmc_device_timings dev_t;
-        struct gpmc_timings t;
         const int t_cer  = 15;
         const int t_avdp = 12;
         const int t_cez  = 20; /* max of t_cez, t_oez */
@@ -172,9 +170,9 @@ omap2_onenand_calc_sync_timings(struct omap_onenand_platform_data *cfg,
         int min_gpmc_clk_period, t_ces, t_avds, t_avdh, t_ach, t_aavdh, t_rdyo;
         int div, gpmc_clk_ns;
 
-        if (cfg->flags & ONENAND_SYNC_READ)
+        if (flags & ONENAND_SYNC_READ)
                 onenand_flags = ONENAND_FLAG_SYNCREAD;
-        else if (cfg->flags & ONENAND_SYNC_READWRITE)
+        else if (flags & ONENAND_SYNC_READWRITE)
                 onenand_flags = ONENAND_FLAG_SYNCREAD | ONENAND_FLAG_SYNCWRITE;
 
         switch (freq) {
@@ -239,10 +237,11 @@ omap2_onenand_calc_sync_timings(struct omap_onenand_platform_data *cfg,
         /* Set synchronous read timings */
         memset(&dev_t, 0, sizeof(dev_t));
 
-        dev_t.mux = true;
-        dev_t.sync_read = true;
+        if (onenand_flags & ONENAND_FLAG_SYNCREAD)
+                onenand_sync.sync_read = true;
         if (onenand_flags & ONENAND_FLAG_SYNCWRITE) {
-                dev_t.sync_write = true;
+                onenand_sync.sync_write = true;
+                onenand_sync.burst_write = true;
         } else {
                 dev_t.t_avdp_w = max(t_avdp, t_cer) * 1000;
                 dev_t.t_wpl = t_wpl * 1000;
@@ -265,32 +264,7 @@ omap2_onenand_calc_sync_timings(struct omap_onenand_platform_data *cfg,
         dev_t.cyc_aavdh_oe = 1;
         dev_t.t_rdyo = t_rdyo * 1000 + min_gpmc_clk_period;
 
-        gpmc_calc_timings(&t, &dev_t);
-
-        return t;
-}
-
-static int gpmc_set_sync_mode(int cs, struct gpmc_timings *t)
-{
-        unsigned sync_read = onenand_flags & ONENAND_FLAG_SYNCREAD;
-        unsigned sync_write = onenand_flags & ONENAND_FLAG_SYNCWRITE;
-
-        /* Configure GPMC for synchronous read */
-        gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1,
-                          GPMC_CONFIG1_WRAPBURST_SUPP |
-                          GPMC_CONFIG1_READMULTIPLE_SUPP |
-                          (sync_read ? GPMC_CONFIG1_READTYPE_SYNC : 0) |
-                          (sync_write ? GPMC_CONFIG1_WRITEMULTIPLE_SUPP : 0) |
-                          (sync_write ? GPMC_CONFIG1_WRITETYPE_SYNC : 0) |
-                          GPMC_CONFIG1_PAGE_LEN(2) |
-                          (cpu_is_omap34xx() ? 0 :
-                                (GPMC_CONFIG1_WAIT_READ_MON |
-                                 GPMC_CONFIG1_WAIT_PIN_SEL(0))) |
-                          GPMC_CONFIG1_DEVICESIZE_16 |
-                          GPMC_CONFIG1_DEVICETYPE_NOR |
-                          GPMC_CONFIG1_MUXADDDATA);
-
-        return gpmc_cs_set_timings(cs, t);
+        gpmc_calc_timings(t, &onenand_sync, &dev_t);
 }
 
 static int omap2_onenand_setup_async(void __iomem *onenand_base)
@@ -298,12 +272,20 @@ static int omap2_onenand_setup_async(void __iomem *onenand_base)
         struct gpmc_timings t;
         int ret;
 
+        if (gpmc_onenand_data->of_node)
+                gpmc_read_settings_dt(gpmc_onenand_data->of_node,
+                                      &onenand_async);
+
         omap2_onenand_set_async_mode(onenand_base);
 
-        t = omap2_onenand_calc_async_timings();
+        omap2_onenand_calc_async_timings(&t);
+
+        ret = gpmc_cs_program_settings(gpmc_onenand_data->cs, &onenand_async);
+        if (ret < 0)
+                return ret;
 
-        ret = gpmc_set_async_mode(gpmc_onenand_data->cs, &t);
-        if (IS_ERR_VALUE(ret))
+        ret = gpmc_cs_set_timings(gpmc_onenand_data->cs, &t);
+        if (ret < 0)
                 return ret;
 
         omap2_onenand_set_async_mode(onenand_base);
@@ -322,10 +304,26 @@ static int omap2_onenand_setup_sync(void __iomem *onenand_base, int *freq_ptr)
                 set_onenand_cfg(onenand_base);
         }
 
-        t = omap2_onenand_calc_sync_timings(gpmc_onenand_data, freq);
+        if (gpmc_onenand_data->of_node) {
+                gpmc_read_settings_dt(gpmc_onenand_data->of_node,
+                                      &onenand_sync);
+        } else {
+                /*
+                 * FIXME: Appears to be legacy code from initial ONENAND commit.
+                 * Unclear what boards this is for and if this can be removed.
+                 */
+                if (!cpu_is_omap34xx())
+                        onenand_sync.wait_on_read = true;
+        }
+
+        omap2_onenand_calc_sync_timings(&t, gpmc_onenand_data->flags, freq);
 
-        ret = gpmc_set_sync_mode(gpmc_onenand_data->cs, &t);
-        if (IS_ERR_VALUE(ret))
+        ret = gpmc_cs_program_settings(gpmc_onenand_data->cs, &onenand_sync);
+        if (ret < 0)
+                return ret;
+
+        ret = gpmc_cs_set_timings(gpmc_onenand_data->cs, &t);
+        if (ret < 0)
                 return ret;
 
         set_onenand_cfg(onenand_base);
@@ -359,6 +357,7 @@ static int gpmc_onenand_setup(void __iomem *onenand_base, int *freq_ptr)
 void gpmc_onenand_init(struct omap_onenand_platform_data *_onenand_data)
 {
         int err;
+        struct device *dev = &gpmc_onenand_device.dev;
 
         gpmc_onenand_data = _onenand_data;
         gpmc_onenand_data->onenand_setup = gpmc_onenand_setup;
@@ -366,7 +365,7 @@ void gpmc_onenand_init(struct omap_onenand_platform_data *_onenand_data)
 
         if (cpu_is_omap24xx() &&
                         (gpmc_onenand_data->flags & ONENAND_SYNC_READWRITE)) {
-                printk(KERN_ERR "Onenand using only SYNC_READ on 24xx\n");
+                dev_warn(dev, "OneNAND using only SYNC_READ on 24xx\n");
                 gpmc_onenand_data->flags &= ~ONENAND_SYNC_READWRITE;
                 gpmc_onenand_data->flags |= ONENAND_SYNC_READ;
         }
@@ -379,7 +378,8 @@ void gpmc_onenand_init(struct omap_onenand_platform_data *_onenand_data)
         err = gpmc_cs_request(gpmc_onenand_data->cs, ONENAND_IO_SIZE,
                                 (unsigned long *)&gpmc_onenand_resource.start);
         if (err < 0) {
-                pr_err("%s: Cannot request GPMC CS\n", __func__);
+                dev_err(dev, "Cannot request GPMC CS %d, error %d\n",
+                        gpmc_onenand_data->cs, err);
                 return;
         }
 
@@ -387,7 +387,7 @@ void gpmc_onenand_init(struct omap_onenand_platform_data *_onenand_data)
                                                         ONENAND_IO_SIZE - 1;
 
         if (platform_device_register(&gpmc_onenand_device) < 0) {
-                pr_err("%s: Unable to register OneNAND device\n", __func__);
+                dev_err(dev, "Unable to register OneNAND device\n");
                 gpmc_cs_free(gpmc_onenand_data->cs);
                 return;
         }
diff --git a/arch/arm/mach-omap2/gpmc-smc91x.c b/arch/arm/mach-omap2/gpmc-smc91x.c
index 11d0b756f098..61a063595e66 100644
--- a/arch/arm/mach-omap2/gpmc-smc91x.c
+++ b/arch/arm/mach-omap2/gpmc-smc91x.c
@@ -49,6 +49,10 @@ static struct platform_device gpmc_smc91x_device = {
         .resource       = gpmc_smc91x_resources,
 };
 
+static struct gpmc_settings smc91x_settings = {
+        .device_width = GPMC_DEVWIDTH_16BIT,
+};
+
 /*
  * Set the gpmc timings for smc91c96. The timings are taken
  * from the data sheet available at:
@@ -67,18 +71,6 @@ static int smc91c96_gpmc_retime(void)
         const int t7 = 5;       /* Figure 12.4 write */
         const int t8 = 5;       /* Figure 12.4 write */
         const int t20 = 185;    /* Figure 12.2 read and 12.4 write */
-        u32 l;
-
-        l = GPMC_CONFIG1_DEVICESIZE_16;
-        if (gpmc_cfg->flags & GPMC_MUX_ADD_DATA)
-                l |= GPMC_CONFIG1_MUXADDDATA;
-        if (gpmc_cfg->flags & GPMC_READ_MON)
-                l |= GPMC_CONFIG1_WAIT_READ_MON;
-        if (gpmc_cfg->flags & GPMC_WRITE_MON)
-                l |= GPMC_CONFIG1_WAIT_WRITE_MON;
-        if (gpmc_cfg->wait_pin)
-                l |= GPMC_CONFIG1_WAIT_PIN_SEL(gpmc_cfg->wait_pin);
-        gpmc_cs_write_reg(gpmc_cfg->cs, GPMC_CS_CONFIG1, l);
 
         /*
          * FIXME: Calculate the address and data bus muxed timings.
@@ -104,7 +96,7 @@ static int smc91c96_gpmc_retime(void)
         dev_t.t_cez_w = t4_w * 1000;
         dev_t.t_wr_cycle = (t20 - t3) * 1000;
 
-        gpmc_calc_timings(&t, &dev_t);
+        gpmc_calc_timings(&t, &smc91x_settings, &dev_t);
 
         return gpmc_cs_set_timings(gpmc_cfg->cs, &t);
 }
@@ -133,6 +125,18 @@ void __init gpmc_smc91x_init(struct omap_smc91x_platform_data *board_data)
         gpmc_smc91x_resources[0].end = cs_mem_base + 0x30f;
         gpmc_smc91x_resources[1].flags |= (gpmc_cfg->flags & IRQF_TRIGGER_MASK);
 
+        if (gpmc_cfg->flags & GPMC_MUX_ADD_DATA)
+                smc91x_settings.mux_add_data = GPMC_MUX_AD;
+        if (gpmc_cfg->flags & GPMC_READ_MON)
+                smc91x_settings.wait_on_read = true;
+        if (gpmc_cfg->flags & GPMC_WRITE_MON)
+                smc91x_settings.wait_on_write = true;
+        if (gpmc_cfg->wait_pin)
+                smc91x_settings.wait_pin = gpmc_cfg->wait_pin;
+        ret = gpmc_cs_program_settings(gpmc_cfg->cs, &smc91x_settings);
+        if (ret < 0)
+                goto free1;
+
         if (gpmc_cfg->retime) {
                 ret = gpmc_cfg->retime();
                 if (ret != 0)
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index 410e1bac7815..ed946df5ad8a 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -26,6 +26,7 @@
 #include <linux/interrupt.h>
 #include <linux/platform_device.h>
 #include <linux/of.h>
+#include <linux/of_address.h>
 #include <linux/of_mtd.h>
 #include <linux/of_device.h>
 #include <linux/mtd/nand.h>
@@ -91,9 +92,7 @@
 #define GPMC_CS_SIZE            0x30
 #define GPMC_BCH_SIZE           0x10
 
-#define GPMC_MEM_START          0x00000000
 #define GPMC_MEM_END            0x3FFFFFFF
-#define BOOT_ROM_SPACE          0x100000        /* 1MB */
 
 #define GPMC_CHUNK_SHIFT        24              /* 16 MB */
 #define GPMC_SECTION_SHIFT      28              /* 128 MB */
@@ -107,6 +106,9 @@
 
 #define GPMC_HAS_WR_ACCESS              0x1
 #define GPMC_HAS_WR_DATA_MUX_BUS        0x2
+#define GPMC_HAS_MUX_AAD                0x4
+
+#define GPMC_NR_WAITPINS                4
 
 /* XXX: Only NAND irq has been considered,currently these are the only ones used
  */
@@ -153,6 +155,7 @@ static struct resource	gpmc_cs_mem[GPMC_CS_NUM];
 static DEFINE_SPINLOCK(gpmc_mem_lock);
 /* Define chip-selects as reserved by default until probe completes */
 static unsigned int gpmc_cs_map = ((1 << GPMC_CS_NUM) - 1);
+static unsigned int gpmc_nr_waitpins;
 static struct device *gpmc_dev;
 static int gpmc_irq;
 static resource_size_t phys_base, mem_size;
@@ -181,7 +184,7 @@ void gpmc_cs_write_reg(int cs, int idx, u32 val)
         __raw_writel(val, reg_addr);
 }
 
-u32 gpmc_cs_read_reg(int cs, int idx)
+static u32 gpmc_cs_read_reg(int cs, int idx)
 {
         void __iomem *reg_addr;
 
@@ -190,7 +193,7 @@ u32 gpmc_cs_read_reg(int cs, int idx)
 }
 
 /* TODO: Add support for gpmc_fck to clock framework and use it */
-unsigned long gpmc_get_fclk_period(void)
+static unsigned long gpmc_get_fclk_period(void)
 {
         unsigned long rate = clk_get_rate(gpmc_l3_clk);
 
@@ -205,7 +208,7 @@ unsigned long gpmc_get_fclk_period(void)
         return rate;
 }
 
-unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
+static unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
 {
         unsigned long tick_ps;
 
@@ -215,7 +218,7 @@ unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
         return (time_ns * 1000 + tick_ps - 1) / tick_ps;
 }
 
-unsigned int gpmc_ps_to_ticks(unsigned int time_ps)
+static unsigned int gpmc_ps_to_ticks(unsigned int time_ps)
 {
         unsigned long tick_ps;
 
@@ -230,13 +233,6 @@ unsigned int gpmc_ticks_to_ns(unsigned int ticks)
         return ticks * gpmc_get_fclk_period() / 1000;
 }
 
-unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns)
-{
-        unsigned long ticks = gpmc_ns_to_ticks(time_ns);
-
-        return ticks * gpmc_get_fclk_period() / 1000;
-}
-
 static unsigned int gpmc_ticks_to_ps(unsigned int ticks)
 {
         return ticks * gpmc_get_fclk_period();
@@ -405,11 +401,18 @@ int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t)
         return 0;
 }
 
-static void gpmc_cs_enable_mem(int cs, u32 base, u32 size)
+static int gpmc_cs_enable_mem(int cs, u32 base, u32 size)
 {
         u32 l;
         u32 mask;
 
+        /*
+         * Ensure that base address is aligned on a
+         * boundary equal to or greater than size.
+         */
+        if (base & (size - 1))
+                return -EINVAL;
+
         mask = (1 << GPMC_SECTION_SHIFT) - size;
         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
         l &= ~0x3f;
@@ -418,6 +421,8 @@ static void gpmc_cs_enable_mem(int cs, u32 base, u32 size)
         l |= ((mask >> GPMC_CHUNK_SHIFT) & 0x0f) << 8;
         l |= GPMC_CONFIG7_CSVALID;
         gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
+
+        return 0;
 }
 
 static void gpmc_cs_disable_mem(int cs)
@@ -448,22 +453,14 @@ static int gpmc_cs_mem_enabled(int cs)
         return l & GPMC_CONFIG7_CSVALID;
 }
 
-int gpmc_cs_set_reserved(int cs, int reserved)
+static void gpmc_cs_set_reserved(int cs, int reserved)
 {
-        if (cs > GPMC_CS_NUM)
-                return -ENODEV;
-
         gpmc_cs_map &= ~(1 << cs);
         gpmc_cs_map |= (reserved ? 1 : 0) << cs;
-
-        return 0;
 }
 
-int gpmc_cs_reserved(int cs)
+static bool gpmc_cs_reserved(int cs)
 {
-        if (cs > GPMC_CS_NUM)
-                return -ENODEV;
-
         return gpmc_cs_map & (1 << cs);
 }
 
@@ -510,6 +507,39 @@ static int gpmc_cs_delete_mem(int cs)
         return r;
 }
 
+/**
+ * gpmc_cs_remap - remaps a chip-select physical base address
+ * @cs:         chip-select to remap
+ * @base:       physical base address to re-map chip-select to
+ *
+ * Re-maps a chip-select to a new physical base address specified by
+ * "base". Returns 0 on success and appropriate negative error code
+ * on failure.
+ */
+static int gpmc_cs_remap(int cs, u32 base)
+{
+        int ret;
+        u32 old_base, size;
+
+        if (cs > GPMC_CS_NUM)
+                return -ENODEV;
+        gpmc_cs_get_memconf(cs, &old_base, &size);
+        if (base == old_base)
+                return 0;
+        gpmc_cs_disable_mem(cs);
+        ret = gpmc_cs_delete_mem(cs);
+        if (ret < 0)
+                return ret;
+        ret = gpmc_cs_insert_mem(cs, base, size);
+        if (ret < 0)
+                return ret;
+        ret = gpmc_cs_enable_mem(cs, base, size);
+        if (ret < 0)
+                return ret;
+
+        return 0;
+}
+
 int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
 {
         struct resource *res = &gpmc_cs_mem[cs];
@@ -535,7 +565,12 @@ int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
         if (r < 0)
                 goto out;
 
-        gpmc_cs_enable_mem(cs, res->start, resource_size(res));
+        r = gpmc_cs_enable_mem(cs, res->start, resource_size(res));
+        if (r < 0) {
+                release_resource(res);
+                goto out;
+        }
+
         *base = res->start;
         gpmc_cs_set_reserved(cs, 1);
 out:
@@ -561,16 +596,14 @@ void gpmc_cs_free(int cs)
 EXPORT_SYMBOL(gpmc_cs_free);
 
 /**
- * gpmc_cs_configure - write request to configure gpmc
- * @cs: chip select number
+ * gpmc_configure - write request to configure gpmc
  * @cmd: command type
  * @wval: value to write
  * @return status of the operation
  */
-int gpmc_cs_configure(int cs, int cmd, int wval)
+int gpmc_configure(int cmd, int wval)
 {
-        int err = 0;
-        u32 regval = 0;
+        u32 regval;
 
         switch (cmd) {
         case GPMC_ENABLE_IRQ:
@@ -590,43 +623,14 @@ int gpmc_cs_configure(int cs, int cmd, int wval)
                 gpmc_write_reg(GPMC_CONFIG, regval);
                 break;
 
-        case GPMC_CONFIG_RDY_BSY:
-                regval  = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
-                if (wval)
-                        regval |= WR_RD_PIN_MONITORING;
-                else
-                        regval &= ~WR_RD_PIN_MONITORING;
-                gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, regval);
-                break;
-
-        case GPMC_CONFIG_DEV_SIZE:
-                regval  = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
-
-                /* clear 2 target bits */
-                regval &= ~GPMC_CONFIG1_DEVICESIZE(3);
-
-                /* set the proper value */
-                regval |= GPMC_CONFIG1_DEVICESIZE(wval);
-
-                gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, regval);
-                break;
-
-        case GPMC_CONFIG_DEV_TYPE:
-                regval  = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
-                regval |= GPMC_CONFIG1_DEVICETYPE(wval);
-                if (wval == GPMC_DEVICETYPE_NOR)
-                        regval |= GPMC_CONFIG1_MUXADDDATA;
-                gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, regval);
-                break;
-
         default:
-                printk(KERN_ERR "gpmc_configure_cs: Not supported\n");
-                err = -EINVAL;
+                pr_err("%s: command not supported\n", __func__);
+                return -EINVAL;
         }
 
-        return err;
+        return 0;
 }
-EXPORT_SYMBOL(gpmc_cs_configure);
+EXPORT_SYMBOL(gpmc_configure);
 
 void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs)
 {
@@ -716,7 +720,7 @@ static int gpmc_setup_irq(void)
                 return -EINVAL;
 
         gpmc_irq_start = irq_alloc_descs(-1, 0, GPMC_NR_IRQ, 0);
-        if (IS_ERR_VALUE(gpmc_irq_start)) {
+        if (gpmc_irq_start < 0) {
                 pr_err("irq_alloc_descs failed\n");
                 return gpmc_irq_start;
         }
@@ -781,16 +785,16 @@ static void gpmc_mem_exit(void)
 
 }
 
-static int gpmc_mem_init(void)
+static void gpmc_mem_init(void)
 {
-        int cs, rc;
-        unsigned long boot_rom_space = 0;
+        int cs;
 
-        /* never allocate the first page, to facilitate bug detection;
-         * even if we didn't boot from ROM.
+        /*
+         * The first 1MB of GPMC address space is typically mapped to
+         * the internal ROM. Never allocate the first page, to
+         * facilitate bug detection; even if we didn't boot from ROM.
          */
-        boot_rom_space = BOOT_ROM_SPACE;
-        gpmc_mem_root.start = GPMC_MEM_START + boot_rom_space;
+        gpmc_mem_root.start = SZ_1M;
         gpmc_mem_root.end = GPMC_MEM_END;
 
         /* Reserve all regions that has been set up by bootloader */
@@ -800,16 +804,12 @@ static int gpmc_mem_init(void)
                 if (!gpmc_cs_mem_enabled(cs))
                         continue;
                 gpmc_cs_get_memconf(cs, &base, &size);
-                rc = gpmc_cs_insert_mem(cs, base, size);
-                if (IS_ERR_VALUE(rc)) {
-                        while (--cs >= 0)
-                                if (gpmc_cs_mem_enabled(cs))
-                                        gpmc_cs_delete_mem(cs);
-                        return rc;
+                if (gpmc_cs_insert_mem(cs, base, size)) {
+                        pr_warn("%s: disabling cs %d mapped at 0x%x-0x%x\n",
+                                __func__, cs, base, base + size);
+                        gpmc_cs_disable_mem(cs);
                 }
         }
-
-        return 0;
 }
 
 static u32 gpmc_round_ps_to_sync_clk(u32 time_ps, u32 sync_clk)
@@ -825,9 +825,9 @@ static u32 gpmc_round_ps_to_sync_clk(u32 time_ps, u32 sync_clk)
 
 /* XXX: can the cycles be avoided ? */
 static int gpmc_calc_sync_read_timings(struct gpmc_timings *gpmc_t,
-                                struct gpmc_device_timings *dev_t)
+                                       struct gpmc_device_timings *dev_t,
+                                       bool mux)
 {
-        bool mux = dev_t->mux;
         u32 temp;
 
         /* adv_rd_off */
@@ -880,9 +880,9 @@ static int gpmc_calc_sync_read_timings(struct gpmc_timings *gpmc_t,
 }
 
 static int gpmc_calc_sync_write_timings(struct gpmc_timings *gpmc_t,
-                                struct gpmc_device_timings *dev_t)
+                                        struct gpmc_device_timings *dev_t,
+                                        bool mux)
 {
-        bool mux = dev_t->mux;
         u32 temp;
 
         /* adv_wr_off */
@@ -942,9 +942,9 @@ static int gpmc_calc_sync_write_timings(struct gpmc_timings *gpmc_t,
 }
 
 static int gpmc_calc_async_read_timings(struct gpmc_timings *gpmc_t,
-                                struct gpmc_device_timings *dev_t)
+                                        struct gpmc_device_timings *dev_t,
+                                        bool mux)
 {
-        bool mux = dev_t->mux;
         u32 temp;
 
         /* adv_rd_off */
@@ -982,9 +982,9 @@ static int gpmc_calc_async_read_timings(struct gpmc_timings *gpmc_t,
 }
 
 static int gpmc_calc_async_write_timings(struct gpmc_timings *gpmc_t,
-                                struct gpmc_device_timings *dev_t)
+                                         struct gpmc_device_timings *dev_t,
+                                         bool mux)
 {
-        bool mux = dev_t->mux;
         u32 temp;
 
         /* adv_wr_off */
@@ -1054,7 +1054,8 @@ static int gpmc_calc_sync_common_timings(struct gpmc_timings *gpmc_t,
 }
 
 static int gpmc_calc_common_timings(struct gpmc_timings *gpmc_t,
-                        struct gpmc_device_timings *dev_t)
+                                    struct gpmc_device_timings *dev_t,
+                                    bool sync)
 {
         u32 temp;
 
@@ -1068,7 +1069,7 @@ static int gpmc_calc_common_timings(struct gpmc_timings *gpmc_t,
                                 gpmc_t->cs_on + dev_t->t_ce_avd);
         gpmc_t->adv_on = gpmc_round_ps_to_ticks(temp);
 
-        if (dev_t->sync_write || dev_t->sync_read)
+        if (sync)
                 gpmc_calc_sync_common_timings(gpmc_t, dev_t);
 
         return 0;
@@ -1103,21 +1104,29 @@ static void gpmc_convert_ps_to_ns(struct gpmc_timings *t)
 }
 
 int gpmc_calc_timings(struct gpmc_timings *gpmc_t,
-                        struct gpmc_device_timings *dev_t)
+                      struct gpmc_settings *gpmc_s,
+                      struct gpmc_device_timings *dev_t)
 {
+        bool mux = false, sync = false;
+
+        if (gpmc_s) {
+                mux = gpmc_s->mux_add_data ? true : false;
+                sync = (gpmc_s->sync_read || gpmc_s->sync_write);
+        }
+
         memset(gpmc_t, 0, sizeof(*gpmc_t));
 
-        gpmc_calc_common_timings(gpmc_t, dev_t);
+        gpmc_calc_common_timings(gpmc_t, dev_t, sync);
 
-        if (dev_t->sync_read)
-                gpmc_calc_sync_read_timings(gpmc_t, dev_t);
+        if (gpmc_s && gpmc_s->sync_read)
+                gpmc_calc_sync_read_timings(gpmc_t, dev_t, mux);
         else
-                gpmc_calc_async_read_timings(gpmc_t, dev_t);
+                gpmc_calc_async_read_timings(gpmc_t, dev_t, mux);
 
-        if (dev_t->sync_write)
-                gpmc_calc_sync_write_timings(gpmc_t, dev_t);
+        if (gpmc_s && gpmc_s->sync_write)
+                gpmc_calc_sync_write_timings(gpmc_t, dev_t, mux);
         else
-                gpmc_calc_async_write_timings(gpmc_t, dev_t);
+                gpmc_calc_async_write_timings(gpmc_t, dev_t, mux);
 
         /* TODO: remove, see function definition */
         gpmc_convert_ps_to_ns(gpmc_t);
@@ -1125,6 +1134,90 @@ int gpmc_calc_timings(struct gpmc_timings *gpmc_t,
         return 0;
 }
 
+/**
+ * gpmc_cs_program_settings - programs non-timing related settings
+ * @cs:         GPMC chip-select to program
+ * @p:          pointer to GPMC settings structure
+ *
+ * Programs non-timing related settings for a GPMC chip-select, such as
+ * bus-width, burst configuration, etc. Function should be called once
+ * for each chip-select that is being used and must be called before
+ * calling gpmc_cs_set_timings() as timing parameters in the CONFIG1
+ * register will be initialised to zero by this function. Returns 0 on
+ * success and appropriate negative error code on failure.
+ */
+int gpmc_cs_program_settings(int cs, struct gpmc_settings *p)
+{
+        u32 config1;
+
+        if ((!p->device_width) || (p->device_width > GPMC_DEVWIDTH_16BIT)) {
+                pr_err("%s: invalid width %d!", __func__, p->device_width);
+                return -EINVAL;
+        }
+
+        /* Address-data multiplexing not supported for NAND devices */
+        if (p->device_nand && p->mux_add_data) {
+                pr_err("%s: invalid configuration!\n", __func__);
+                return -EINVAL;
+        }
+
+        if ((p->mux_add_data > GPMC_MUX_AD) ||
+            ((p->mux_add_data == GPMC_MUX_AAD) &&
+             !(gpmc_capability & GPMC_HAS_MUX_AAD))) {
+                pr_err("%s: invalid multiplex configuration!\n", __func__);
+                return -EINVAL;
+        }
+
+        /* Page/burst mode supports lengths of 4, 8 and 16 bytes */
+        if (p->burst_read || p->burst_write) {
+                switch (p->burst_len) {
+                case GPMC_BURST_4:
+                case GPMC_BURST_8:
+                case GPMC_BURST_16:
+                        break;
+                default:
+                        pr_err("%s: invalid page/burst-length (%d)\n",
+                               __func__, p->burst_len);
+                        return -EINVAL;
+                }
+        }
+
+        if ((p->wait_on_read || p->wait_on_write) &&
+            (p->wait_pin > gpmc_nr_waitpins)) {
+                pr_err("%s: invalid wait-pin (%d)\n", __func__, p->wait_pin);
+                return -EINVAL;
+        }
+
+        config1 = GPMC_CONFIG1_DEVICESIZE((p->device_width - 1));
+
+        if (p->sync_read)
+                config1 |= GPMC_CONFIG1_READTYPE_SYNC;
+        if (p->sync_write)
+                config1 |= GPMC_CONFIG1_WRITETYPE_SYNC;
+        if (p->wait_on_read)
+                config1 |= GPMC_CONFIG1_WAIT_READ_MON;
+        if (p->wait_on_write)
+                config1 |= GPMC_CONFIG1_WAIT_WRITE_MON;
+        if (p->wait_on_read || p->wait_on_write)
+                config1 |= GPMC_CONFIG1_WAIT_PIN_SEL(p->wait_pin);
+        if (p->device_nand)
+                config1 |= GPMC_CONFIG1_DEVICETYPE(GPMC_DEVICETYPE_NAND);
+        if (p->mux_add_data)
+                config1 |= GPMC_CONFIG1_MUXTYPE(p->mux_add_data);
+        if (p->burst_read)
+                config1 |= GPMC_CONFIG1_READMULTIPLE_SUPP;
+        if (p->burst_write)
+                config1 |= GPMC_CONFIG1_WRITEMULTIPLE_SUPP;
+        if (p->burst_read || p->burst_write) {
+                config1 |= GPMC_CONFIG1_PAGE_LEN(p->burst_len >> 3);
+                config1 |= p->burst_wrap ? GPMC_CONFIG1_WRAPBURST_SUPP : 0;
+        }
+
+        gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, config1);
+
+        return 0;
+}
+
 #ifdef CONFIG_OF
 static struct of_device_id gpmc_dt_ids[] = {
         { .compatible = "ti,omap2420-gpmc" },
@@ -1136,70 +1229,110 @@ static struct of_device_id gpmc_dt_ids[] = {
 };
 MODULE_DEVICE_TABLE(of, gpmc_dt_ids);
 
+/**
+ * gpmc_read_settings_dt - read gpmc settings from device-tree
+ * @np:         pointer to device-tree node for a gpmc child device
+ * @p:          pointer to gpmc settings structure
+ *
+ * Reads the GPMC settings for a GPMC child device from device-tree and
+ * stores them in the GPMC settings structure passed. The GPMC settings
+ * structure is initialised to zero by this function and so any
+ * previously stored settings will be cleared.
+ */
+void gpmc_read_settings_dt(struct device_node *np, struct gpmc_settings *p)
+{
+        memset(p, 0, sizeof(struct gpmc_settings));
+
+        p->sync_read = of_property_read_bool(np, "gpmc,sync-read");
+        p->sync_write = of_property_read_bool(np, "gpmc,sync-write");
+        p->device_nand = of_property_read_bool(np, "gpmc,device-nand");
+        of_property_read_u32(np, "gpmc,device-width", &p->device_width);
+        of_property_read_u32(np, "gpmc,mux-add-data", &p->mux_add_data);
+
+        if (!of_property_read_u32(np, "gpmc,burst-length", &p->burst_len)) {
+                p->burst_wrap = of_property_read_bool(np, "gpmc,burst-wrap");
+                p->burst_read = of_property_read_bool(np, "gpmc,burst-read");
+                p->burst_write = of_property_read_bool(np, "gpmc,burst-write");
+                if (!p->burst_read && !p->burst_write)
+                        pr_warn("%s: page/burst-length set but not used!\n",
+                                __func__);
+        }
+
+        if (!of_property_read_u32(np, "gpmc,wait-pin", &p->wait_pin)) {
+                p->wait_on_read = of_property_read_bool(np,
+                                                        "gpmc,wait-on-read");
+                p->wait_on_write = of_property_read_bool(np,
+                                                         "gpmc,wait-on-write");
+                if (!p->wait_on_read && !p->wait_on_write)
+                        pr_warn("%s: read/write wait monitoring not enabled!\n",
+                                __func__);
+        }
+}
+
 static void __maybe_unused gpmc_read_timings_dt(struct device_node *np,
                                                 struct gpmc_timings *gpmc_t)
 {
-        u32 val;
+        struct gpmc_bool_timings *p;
+
+        if (!np || !gpmc_t)
+                return;
 
         memset(gpmc_t, 0, sizeof(*gpmc_t));
 
         /* minimum clock period for syncronous mode */
-        if (!of_property_read_u32(np, "gpmc,sync-clk", &val))
-                gpmc_t->sync_clk = val;
+        of_property_read_u32(np, "gpmc,sync-clk-ps", &gpmc_t->sync_clk);
 
         /* chip select timtings */
-        if (!of_property_read_u32(np, "gpmc,cs-on", &val))
-                gpmc_t->cs_on = val;
-
-        if (!of_property_read_u32(np, "gpmc,cs-rd-off", &val))
-                gpmc_t->cs_rd_off = val;
-
-        if (!of_property_read_u32(np, "gpmc,cs-wr-off", &val))
-                gpmc_t->cs_wr_off = val;
+        of_property_read_u32(np, "gpmc,cs-on-ns", &gpmc_t->cs_on);
+        of_property_read_u32(np, "gpmc,cs-rd-off-ns", &gpmc_t->cs_rd_off);
+        of_property_read_u32(np, "gpmc,cs-wr-off-ns", &gpmc_t->cs_wr_off);
 
         /* ADV signal timings */
-        if (!of_property_read_u32(np, "gpmc,adv-on", &val))
-                gpmc_t->adv_on = val;
-
-        if (!of_property_read_u32(np, "gpmc,adv-rd-off", &val))
-                gpmc_t->adv_rd_off = val;
-
-        if (!of_property_read_u32(np, "gpmc,adv-wr-off", &val))
-                gpmc_t->adv_wr_off = val;
+        of_property_read_u32(np, "gpmc,adv-on-ns", &gpmc_t->adv_on);
+        of_property_read_u32(np, "gpmc,adv-rd-off-ns", &gpmc_t->adv_rd_off);
+        of_property_read_u32(np, "gpmc,adv-wr-off-ns", &gpmc_t->adv_wr_off);
 
         /* WE signal timings */
-        if (!of_property_read_u32(np, "gpmc,we-on", &val))
-                gpmc_t->we_on = val;
-
-        if (!of_property_read_u32(np, "gpmc,we-off", &val))
-                gpmc_t->we_off = val;
+        of_property_read_u32(np, "gpmc,we-on-ns", &gpmc_t->we_on);
+        of_property_read_u32(np, "gpmc,we-off-ns", &gpmc_t->we_off);
 
         /* OE signal timings */
-        if (!of_property_read_u32(np, "gpmc,oe-on", &val))
-                gpmc_t->oe_on = val;
-
-        if (!of_property_read_u32(np, "gpmc,oe-off", &val))
-                gpmc_t->oe_off = val;
+        of_property_read_u32(np, "gpmc,oe-on-ns", &gpmc_t->oe_on);
+        of_property_read_u32(np, "gpmc,oe-off-ns", &gpmc_t->oe_off);
 
         /* access and cycle timings */
-        if (!of_property_read_u32(np, "gpmc,page-burst-access", &val))
-                gpmc_t->page_burst_access = val;
-
-        if (!of_property_read_u32(np, "gpmc,access", &val))
-                gpmc_t->access = val;
-
-        if (!of_property_read_u32(np, "gpmc,rd-cycle", &val))
-                gpmc_t->rd_cycle = val;
-
-        if (!of_property_read_u32(np, "gpmc,wr-cycle", &val))
-                gpmc_t->wr_cycle = val;
-
-        /* only for OMAP3430 */
-        if (!of_property_read_u32(np, "gpmc,wr-access", &val))
-                gpmc_t->wr_access = val;
-
-        if (!of_property_read_u32(np, "gpmc,wr-data-mux-bus", &val))
-                gpmc_t->wr_data_mux_bus = val;
+        of_property_read_u32(np, "gpmc,page-burst-access-ns",
+                             &gpmc_t->page_burst_access);
+        of_property_read_u32(np, "gpmc,access-ns", &gpmc_t->access);
+        of_property_read_u32(np, "gpmc,rd-cycle-ns", &gpmc_t->rd_cycle);
+        of_property_read_u32(np, "gpmc,wr-cycle-ns", &gpmc_t->wr_cycle);
+        of_property_read_u32(np, "gpmc,bus-turnaround-ns",
+                             &gpmc_t->bus_turnaround);
+        of_property_read_u32(np, "gpmc,cycle2cycle-delay-ns",
+                             &gpmc_t->cycle2cycle_delay);
+        of_property_read_u32(np, "gpmc,wait-monitoring-ns",
+                             &gpmc_t->wait_monitoring);
+        of_property_read_u32(np, "gpmc,clk-activation-ns",
+                             &gpmc_t->clk_activation);
+
+        /* only applicable to OMAP3+ */
+        of_property_read_u32(np, "gpmc,wr-access-ns", &gpmc_t->wr_access);
+        of_property_read_u32(np, "gpmc,wr-data-mux-bus-ns",
+                             &gpmc_t->wr_data_mux_bus);
+
+        /* bool timing parameters */
+        p = &gpmc_t->bool_timings;
+
+        p->cycle2cyclediffcsen =
+                of_property_read_bool(np, "gpmc,cycle2cycle-diffcsen");
+        p->cycle2cyclesamecsen =
+                of_property_read_bool(np, "gpmc,cycle2cycle-samecsen");
+        p->we_extra_delay = of_property_read_bool(np, "gpmc,we-extra-delay");
+        p->oe_extra_delay = of_property_read_bool(np, "gpmc,oe-extra-delay");
+        p->adv_extra_delay = of_property_read_bool(np, "gpmc,adv-extra-delay");
+        p->cs_extra_delay = of_property_read_bool(np, "gpmc,cs-extra-delay");
+        p->time_para_granularity =
+                of_property_read_bool(np, "gpmc,time-para-granularity");
 }
 
 #ifdef CONFIG_MTD_NAND
@@ -1295,6 +1428,81 @@ static int gpmc_probe_onenand_child(struct platform_device *pdev,
 }
 #endif
 
+/**
+ * gpmc_probe_generic_child - configures the gpmc for a child device
+ * @pdev:       pointer to gpmc platform device
+ * @child:      pointer to device-tree node for child device
+ *
+ * Allocates and configures a GPMC chip-select for a child device.
+ * Returns 0 on success and appropriate negative error code on failure.
+ */
+static int gpmc_probe_generic_child(struct platform_device *pdev,
+                                struct device_node *child)
+{
+        struct gpmc_settings gpmc_s;
+        struct gpmc_timings gpmc_t;
+        struct resource res;
+        unsigned long base;
+        int ret, cs;
+
+        if (of_property_read_u32(child, "reg", &cs) < 0) {
+                dev_err(&pdev->dev, "%s has no 'reg' property\n",
+                        child->full_name);
+                return -ENODEV;
+        }
+
+        if (of_address_to_resource(child, 0, &res) < 0) {
+                dev_err(&pdev->dev, "%s has malformed 'reg' property\n",
+                        child->full_name);
+                return -ENODEV;
+        }
+
+        ret = gpmc_cs_request(cs, resource_size(&res), &base);
+        if (ret < 0) {
+                dev_err(&pdev->dev, "cannot request GPMC CS %d\n", cs);
+                return ret;
+        }
+
+        /*
+         * FIXME: gpmc_cs_request() will map the CS to an arbitary
+         * location in the gpmc address space. When booting with
+         * device-tree we want the NOR flash to be mapped to the
+         * location specified in the device-tree blob. So remap the
+         * CS to this location. Once DT migration is complete should
+         * just make gpmc_cs_request() map a specific address.
+         */
+        ret = gpmc_cs_remap(cs, res.start);
+        if (ret < 0) {
+                dev_err(&pdev->dev, "cannot remap GPMC CS %d to 0x%x\n",
+                        cs, res.start);
+                goto err;
+        }
+
+        gpmc_read_settings_dt(child, &gpmc_s);
+
+        ret = of_property_read_u32(child, "bank-width", &gpmc_s.device_width);
+        if (ret < 0)
+                goto err;
+
+        ret = gpmc_cs_program_settings(cs, &gpmc_s);
+        if (ret < 0)
+                goto err;
+
+        gpmc_read_timings_dt(child, &gpmc_t);
+        gpmc_cs_set_timings(cs, &gpmc_t);
+
+        if (of_platform_device_create(child, NULL, &pdev->dev))
+                return 0;
+
+        dev_err(&pdev->dev, "failed to create gpmc child %s\n", child->name);
+        ret = -ENODEV;
+
+err:
+        gpmc_cs_free(cs);
+
+        return ret;
+}
+
 static int gpmc_probe_dt(struct platform_device *pdev)
 {
         int ret;
@@ -1305,6 +1513,13 @@ static int gpmc_probe_dt(struct platform_device *pdev)
         if (!of_id)
                 return 0;
 
+        ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-waitpins",
+                                   &gpmc_nr_waitpins);
+        if (ret < 0) {
+                pr_err("%s: number of wait pins not found!\n", __func__);
+                return ret;
+        }
+
         for_each_node_by_name(child, "nand") {
                 ret = gpmc_probe_nand_child(pdev, child);
                 if (ret < 0) {
@@ -1320,6 +1535,23 @@ static int gpmc_probe_dt(struct platform_device *pdev)
                         return ret;
                 }
         }
+
+        for_each_node_by_name(child, "nor") {
+                ret = gpmc_probe_generic_child(pdev, child);
+                if (ret < 0) {
+                        of_node_put(child);
+                        return ret;
+                }
+        }
+
+        for_each_node_by_name(child, "ethernet") {
+                ret = gpmc_probe_generic_child(pdev, child);
+                if (ret < 0) {
+                        of_node_put(child);
+                        return ret;
+                }
+        }
+
         return 0;
 }
 #else
@@ -1364,25 +1596,37 @@ static int gpmc_probe(struct platform_device *pdev)
         gpmc_dev = &pdev->dev;
 
         l = gpmc_read_reg(GPMC_REVISION);
+
+        /*
+         * FIXME: Once device-tree migration is complete the below flags
+         * should be populated based upon the device-tree compatible
+         * string. For now just use the IP revision. OMAP3+ devices have
+         * the wr_access and wr_data_mux_bus register fields. OMAP4+
+         * devices support the addr-addr-data multiplex protocol.
+         *
+         * GPMC IP revisions:
+         * - OMAP24xx                   = 2.0
+         * - OMAP3xxx                   = 5.0
+         * - OMAP44xx/54xx/AM335x       = 6.0
+         */
         if (GPMC_REVISION_MAJOR(l) > 0x4)
                 gpmc_capability = GPMC_HAS_WR_ACCESS | GPMC_HAS_WR_DATA_MUX_BUS;
+        if (GPMC_REVISION_MAJOR(l) > 0x5)
+                gpmc_capability |= GPMC_HAS_MUX_AAD;
         dev_info(gpmc_dev, "GPMC revision %d.%d\n", GPMC_REVISION_MAJOR(l),
                  GPMC_REVISION_MINOR(l));
 
-        rc = gpmc_mem_init();
-        if (IS_ERR_VALUE(rc)) {
-                clk_disable_unprepare(gpmc_l3_clk);
-                clk_put(gpmc_l3_clk);
-                dev_err(gpmc_dev, "failed to reserve memory\n");
-                return rc;
-        }
+        gpmc_mem_init();
 
-        if (IS_ERR_VALUE(gpmc_setup_irq()))
+        if (gpmc_setup_irq() < 0)
                 dev_warn(gpmc_dev, "gpmc_setup_irq failed\n");
 
         /* Now the GPMC is initialised, unreserve the chip-selects */
         gpmc_cs_map = 0;
 
+        if (!pdev->dev.of_node)
+                gpmc_nr_waitpins = GPMC_NR_WAITPINS;
+
         rc = gpmc_probe_dt(pdev);
         if (rc < 0) {
                 clk_disable_unprepare(gpmc_l3_clk);
diff --git a/arch/arm/mach-omap2/gpmc.h b/arch/arm/mach-omap2/gpmc.h
index fe0a844d5007..707f6d58edd5 100644
--- a/arch/arm/mach-omap2/gpmc.h
+++ b/arch/arm/mach-omap2/gpmc.h
@@ -58,7 +58,7 @@
 #define GPMC_CONFIG1_DEVICESIZE_16      GPMC_CONFIG1_DEVICESIZE(1)
 #define GPMC_CONFIG1_DEVICETYPE(val)    ((val & 3) << 10)
 #define GPMC_CONFIG1_DEVICETYPE_NOR     GPMC_CONFIG1_DEVICETYPE(0)
-#define GPMC_CONFIG1_MUXADDDATA         (1 << 9)
+#define GPMC_CONFIG1_MUXTYPE(val)       ((val & 3) << 8)
 #define GPMC_CONFIG1_TIME_PARA_GRAN     (1 << 4)
 #define GPMC_CONFIG1_FCLK_DIV(val)      (val & 3)
 #define GPMC_CONFIG1_FCLK_DIV2          (GPMC_CONFIG1_FCLK_DIV(1))
@@ -73,6 +73,13 @@
 #define GPMC_IRQ_FIFOEVENTENABLE        0x01
 #define GPMC_IRQ_COUNT_EVENT            0x02
 
+#define GPMC_BURST_4                    4       /* 4 word burst */
+#define GPMC_BURST_8                    8       /* 8 word burst */
+#define GPMC_BURST_16                   16      /* 16 word burst */
+#define GPMC_DEVWIDTH_8BIT              1       /* 8-bit device width */
+#define GPMC_DEVWIDTH_16BIT             2       /* 16-bit device width */
+#define GPMC_MUX_AAD                    1       /* Addr-Addr-Data multiplex */
+#define GPMC_MUX_AD                     2       /* Addr-Data multiplex */
 
 /* bool type time settings */
 struct gpmc_bool_timings {
@@ -178,10 +185,6 @@ struct gpmc_device_timings {
         u8 cyc_wpl;     /* write deassertion time in cycles */
         u32 cyc_iaa;    /* initial access time in cycles */
 
-        bool mux;       /* address & data muxed */
-        bool sync_write;/* synchronous write */
-        bool sync_read; /* synchronous read */
-
         /* extra delays */
         bool ce_xdelay;
         bool avd_xdelay;
@@ -189,28 +192,40 @@ struct gpmc_device_timings {
         bool we_xdelay;
 };
 
+struct gpmc_settings {
+        bool burst_wrap;        /* enables wrap bursting */
+        bool burst_read;        /* enables read page/burst mode */
+        bool burst_write;       /* enables write page/burst mode */
+        bool device_nand;       /* device is NAND */
+        bool sync_read;         /* enables synchronous reads */
+        bool sync_write;        /* enables synchronous writes */
+        bool wait_on_read;      /* monitor wait on reads */
+        bool wait_on_write;     /* monitor wait on writes */
+        u32 burst_len;          /* page/burst length */
+        u32 device_width;       /* device bus width (8 or 16 bit) */
+        u32 mux_add_data;       /* multiplex address & data */
+        u32 wait_pin;           /* wait-pin to be used */
+};
+
 extern int gpmc_calc_timings(struct gpmc_timings *gpmc_t,
-                                struct gpmc_device_timings *dev_t);
+                             struct gpmc_settings *gpmc_s,
+                             struct gpmc_device_timings *dev_t);
 
 extern void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs);
 extern int gpmc_get_client_irq(unsigned irq_config);
 
-extern unsigned int gpmc_ns_to_ticks(unsigned int time_ns);
-extern unsigned int gpmc_ps_to_ticks(unsigned int time_ps);
 extern unsigned int gpmc_ticks_to_ns(unsigned int ticks);
-extern unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns);
-extern unsigned long gpmc_get_fclk_period(void);
 
 extern void gpmc_cs_write_reg(int cs, int idx, u32 val);
-extern u32 gpmc_cs_read_reg(int cs, int idx);
 extern int gpmc_calc_divider(unsigned int sync_clk);
 extern int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t);
+extern int gpmc_cs_program_settings(int cs, struct gpmc_settings *p);
 extern int gpmc_cs_request(int cs, unsigned long size, unsigned long *base);
 extern void gpmc_cs_free(int cs);
-extern int gpmc_cs_set_reserved(int cs, int reserved);
-extern int gpmc_cs_reserved(int cs);
 extern void omap3_gpmc_save_context(void);
 extern void omap3_gpmc_restore_context(void);
-extern int gpmc_cs_configure(int cs, int cmd, int wval);
+extern int gpmc_configure(int cmd, int wval);
+extern void gpmc_read_settings_dt(struct device_node *np,
+                                  struct gpmc_settings *p);
 
 #endif
diff --git a/arch/arm/mach-omap2/omap_device.c b/arch/arm/mach-omap2/omap_device.c
index 381be7ac0c17..eeea4fa28fbc 100644
--- a/arch/arm/mach-omap2/omap_device.c
+++ b/arch/arm/mach-omap2/omap_device.c
@@ -131,7 +131,7 @@ static int omap_device_build_from_dt(struct platform_device *pdev)
         int oh_cnt, i, ret = 0;
 
         oh_cnt = of_property_count_strings(node, "ti,hwmods");
-        if (!oh_cnt || IS_ERR_VALUE(oh_cnt)) {
+        if (oh_cnt <= 0) {
                 dev_dbg(&pdev->dev, "No 'hwmods' to build omap_device\n");
                 return -ENODEV;
         }
@@ -815,20 +815,17 @@ struct device *omap_device_get_by_hwmod_name(const char *oh_name)
         }
 
         oh = omap_hwmod_lookup(oh_name);
-        if (IS_ERR_OR_NULL(oh)) {
+        if (!oh) {
                 WARN(1, "%s: no hwmod for %s\n", __func__,
                         oh_name);
-                return ERR_PTR(oh ? PTR_ERR(oh) : -ENODEV);
+                return ERR_PTR(-ENODEV);
         }
-        if (IS_ERR_OR_NULL(oh->od)) {
+        if (!oh->od) {
                 WARN(1, "%s: no omap_device for %s\n", __func__,
                         oh_name);
-                return ERR_PTR(oh->od ? PTR_ERR(oh->od) : -ENODEV);
+                return ERR_PTR(-ENODEV);
         }
 
-        if (IS_ERR_OR_NULL(oh->od->pdev))
-                return ERR_PTR(oh->od->pdev ? PTR_ERR(oh->od->pdev) : -ENODEV);
-
         return &oh->od->pdev->dev;
 }
 
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 5f33c2da6999..3f50f680372e 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -1662,7 +1662,7 @@ static int _deassert_hardreset(struct omap_hwmod *oh, const char *name)
                 return -ENOSYS;
 
         ret = _lookup_hardreset(oh, name, &ohri);
-        if (IS_ERR_VALUE(ret))
+        if (ret < 0)
                 return ret;
 
         if (oh->clkdm) {
@@ -2412,7 +2412,7 @@ static int __init _init(struct omap_hwmod *oh, void *data)
         _init_mpu_rt_base(oh, NULL);
 
         r = _init_clocks(oh, NULL);
-        if (IS_ERR_VALUE(r)) {
+        if (r < 0) {
                 WARN(1, "omap_hwmod: %s: couldn't init clocks\n", oh->name);
                 return -EINVAL;
         }
diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c
index 1edd000a8143..0b339861d751 100644
--- a/arch/arm/mach-omap2/pm-debug.c
+++ b/arch/arm/mach-omap2/pm-debug.c
@@ -217,7 +217,7 @@ static int __init pwrdms_setup(struct powerdomain *pwrdm, void *dir)
                 return 0;
 
         d = debugfs_create_dir(pwrdm->name, (struct dentry *)dir);
-        if (!(IS_ERR_OR_NULL(d)))
+        if (d)
                 (void) debugfs_create_file("suspend", S_IRUGO|S_IWUSR, d,
                         (void *)pwrdm, &pwrdm_suspend_fops);
 
@@ -261,8 +261,8 @@ static int __init pm_dbg_init(void)
                 return 0;
 
         d = debugfs_create_dir("pm_debug", NULL);
-        if (IS_ERR_OR_NULL(d))
-                return PTR_ERR(d);
+        if (!d)
+                return -EINVAL;
 
         (void) debugfs_create_file("count", S_IRUGO,
                 d, (void *)DEBUG_FILE_COUNTERS, &debug_fops);
diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c
index 89cad4a605dd..86babd740d41 100644
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -1180,7 +1180,7 @@ bool pwrdm_can_ever_lose_context(struct powerdomain *pwrdm)
 {
         int i;
 
-        if (IS_ERR_OR_NULL(pwrdm)) {
+        if (!pwrdm) {
                 pr_debug("powerdomain: %s: invalid powerdomain pointer\n",
                          __func__);
                 return 1;
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index d00d89c93f1c..fdf1c039062c 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -46,7 +46,6 @@
 #include <asm/smp_twd.h>
 #include <asm/sched_clock.h>
 
-#include <asm/arch_timer.h>
 #include "omap_hwmod.h"
 #include "omap_device.h"
 #include <plat/counter-32k.h>
@@ -57,16 +56,6 @@
 #include "common.h"
 #include "powerdomain.h"
 
-/* Parent clocks, eventually these will come from the clock framework */
-
-#define OMAP2_MPU_SOURCE        "sys_ck"
-#define OMAP3_MPU_SOURCE        OMAP2_MPU_SOURCE
-#define OMAP4_MPU_SOURCE        "sys_clkin_ck"
-#define OMAP5_MPU_SOURCE        "sys_clkin"
-#define OMAP2_32K_SOURCE        "func_32k_ck"
-#define OMAP3_32K_SOURCE        "omap_32k_fck"
-#define OMAP4_32K_SOURCE        "sys_32k_ck"
-
 #define REALTIME_COUNTER_BASE                           0x48243200
 #define INCREMENTER_NUMERATOR_OFFSET                    0x10
 #define INCREMENTER_DENUMERATOR_RELOAD_OFFSET           0x14
@@ -130,7 +119,6 @@ static void omap2_gp_timer_set_mode(enum clock_event_mode mode,
 }
 
 static struct clock_event_device clockevent_gpt = {
-        .name           = "gp_timer",
         .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
         .rating         = 300,
         .set_next_event = omap2_gp_timer_set_next_event,
@@ -171,6 +159,12 @@ static struct device_node * __init omap_get_timer_dt(struct of_device_id *match,
                 if (property && !of_get_property(np, property, NULL))
                         continue;
 
+                if (!property && (of_get_property(np, "ti,timer-alwon", NULL) ||
+                                  of_get_property(np, "ti,timer-dsp", NULL) ||
+                                  of_get_property(np, "ti,timer-pwm", NULL) ||
+                                  of_get_property(np, "ti,timer-secure", NULL)))
+                        continue;
+
                 of_add_property(np, &device_disabled);
                 return np;
         }
@@ -215,16 +209,17 @@ static u32 __init omap_dm_timer_get_errata(void)
 }
 
 static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
-                                                int gptimer_id,
-                                                const char *fck_source,
-                                                const char *property,
-                                                int posted)
+                                         const char *fck_source,
+                                         const char *property,
+                                         const char **timer_name,
+                                         int posted)
 {
         char name[10]; /* 10 = sizeof("gptXX_Xck0") */
         const char *oh_name;
         struct device_node *np;
         struct omap_hwmod *oh;
         struct resource irq, mem;
+        struct clk *src;
         int r = 0;
 
         if (of_have_populated_dt()) {
@@ -244,10 +239,10 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
 
                 of_node_put(np);
         } else {
-                if (omap_dm_timer_reserve_systimer(gptimer_id))
+                if (omap_dm_timer_reserve_systimer(timer->id))
                         return -ENODEV;
 
-                sprintf(name, "timer%d", gptimer_id);
+                sprintf(name, "timer%d", timer->id);
                 oh_name = name;
         }
 
@@ -255,6 +250,8 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
         if (!oh)
                 return -ENODEV;
 
+        *timer_name = oh->name;
+
         if (!of_have_populated_dt()) {
                 r = omap_hwmod_get_resource_byname(oh, IORESOURCE_IRQ, NULL,
                                                    &irq);
@@ -277,24 +274,24 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
         /* After the dmtimer is using hwmod these clocks won't be needed */
         timer->fclk = clk_get(NULL, omap_hwmod_get_main_clk(oh));
         if (IS_ERR(timer->fclk))
-                return -ENODEV;
+                return PTR_ERR(timer->fclk);
 
-        /* FIXME: Need to remove hard-coded test on timer ID */
-        if (gptimer_id != 12) {
-                struct clk *src;
-
-                src = clk_get(NULL, fck_source);
-                if (IS_ERR(src)) {
-                        r = -EINVAL;
-                } else {
-                        r = clk_set_parent(timer->fclk, src);
-                        if (IS_ERR_VALUE(r))
-                                pr_warn("%s: %s cannot set source\n",
-                                        __func__, oh->name);
+        src = clk_get(NULL, fck_source);
+        if (IS_ERR(src))
+                return PTR_ERR(src);
+
+        if (clk_get_parent(timer->fclk) != src) {
+                r = clk_set_parent(timer->fclk, src);
+                if (r < 0) {
+                        pr_warn("%s: %s cannot set source\n", __func__,
+                                oh->name);
                         clk_put(src);
+                        return r;
                 }
         }
 
+        clk_put(src);
+
         omap_hwmod_setup_one(oh_name);
         omap_hwmod_enable(oh);
         __omap_dm_timer_init_regs(timer);
@@ -318,6 +315,7 @@ static void __init omap2_gp_clockevent_init(int gptimer_id,
 {
         int res;
 
+        clkev.id = gptimer_id;
         clkev.errata = omap_dm_timer_get_errata();
 
         /*
@@ -327,8 +325,8 @@ static void __init omap2_gp_clockevent_init(int gptimer_id,
          */
         __omap_dm_timer_override_errata(&clkev, OMAP_TIMER_ERRATA_I103_I767);
 
-        res = omap_dm_timer_init_one(&clkev, gptimer_id, fck_source, property,
-                                     OMAP_TIMER_POSTED);
+        res = omap_dm_timer_init_one(&clkev, fck_source, property,
+                                     &clockevent_gpt.name, OMAP_TIMER_POSTED);
         BUG_ON(res);
 
         omap2_gp_timer_irq.dev_id = &clkev;
@@ -342,8 +340,8 @@ static void __init omap2_gp_clockevent_init(int gptimer_id,
                                         3, /* Timer internal resynch latency */
                                         0xffffffff);
 
-        pr_info("OMAP clockevent source: GPTIMER%d at %lu Hz\n",
-                gptimer_id, clkev.rate);
+        pr_info("OMAP clockevent source: %s at %lu Hz\n", clockevent_gpt.name,
+                clkev.rate);
 }
 
 /* Clocksource code */
@@ -360,7 +358,6 @@ static cycle_t clocksource_read_cycles(struct clocksource *cs)
 }
 
 static struct clocksource clocksource_gpt = {
-        .name           = "gp_timer",
         .rating         = 300,
         .read           = clocksource_read_cycles,
         .mask           = CLOCKSOURCE_MASK(32),
@@ -443,13 +440,16 @@ static int __init __maybe_unused omap2_sync32k_clocksource_init(void)
 }
 
 static void __init omap2_gptimer_clocksource_init(int gptimer_id,
-                                                const char *fck_source)
+                                                  const char *fck_source,
+                                                  const char *property)
 {
         int res;
 
+        clksrc.id = gptimer_id;
         clksrc.errata = omap_dm_timer_get_errata();
 
-        res = omap_dm_timer_init_one(&clksrc, gptimer_id, fck_source, NULL,
+        res = omap_dm_timer_init_one(&clksrc, fck_source, property,
+                                     &clocksource_gpt.name,
                                      OMAP_TIMER_NONPOSTED);
         BUG_ON(res);
 
@@ -462,8 +462,8 @@ static void __init omap2_gptimer_clocksource_init(int gptimer_id,
                 pr_err("Could not register clocksource %s\n",
                         clocksource_gpt.name);
         else
-                pr_info("OMAP clocksource: GPTIMER%d at %lu Hz\n",
-                        gptimer_id, clksrc.rate);
+                pr_info("OMAP clocksource: %s at %lu Hz\n",
+                        clocksource_gpt.name, clksrc.rate);
 }
 
 #ifdef CONFIG_SOC_HAS_REALTIME_COUNTER
@@ -488,7 +488,7 @@ static void __init realtime_counter_init(void)
                 pr_err("%s: ioremap failed\n", __func__);
                 return;
         }
-        sys_clk = clk_get(NULL, OMAP5_MPU_SOURCE);
+        sys_clk = clk_get(NULL, "sys_clkin");
         if (IS_ERR(sys_clk)) {
                 pr_err("%s: failed to get system clock handle\n", __func__);
                 iounmap(base);
@@ -545,18 +545,19 @@ static inline void __init realtime_counter_init(void)
 #endif
 
 #define OMAP_SYS_GP_TIMER_INIT(name, clkev_nr, clkev_src, clkev_prop,   \
-                               clksrc_nr, clksrc_src)                   \
+                               clksrc_nr, clksrc_src, clksrc_prop)      \
 void __init omap##name##_gptimer_timer_init(void)                       \
 {                                                                       \
         if (omap_clk_init)                                              \
                 omap_clk_init();                                        \
         omap_dmtimer_init();                                            \
         omap2_gp_clockevent_init((clkev_nr), clkev_src, clkev_prop);    \
-        omap2_gptimer_clocksource_init((clksrc_nr), clksrc_src);        \
+        omap2_gptimer_clocksource_init((clksrc_nr), clksrc_src,         \
+                                        clksrc_prop);                   \
 }
 
 #define OMAP_SYS_32K_TIMER_INIT(name, clkev_nr, clkev_src, clkev_prop,  \
-                                clksrc_nr, clksrc_src)                  \
+                                clksrc_nr, clksrc_src, clksrc_prop)     \
 void __init omap##name##_sync32k_timer_init(void)               \
 {                                                                       \
         if (omap_clk_init)                                              \
@@ -565,33 +566,35 @@ void __init omap##name##_sync32k_timer_init(void)		\
         omap2_gp_clockevent_init((clkev_nr), clkev_src, clkev_prop);    \
         /* Enable the use of clocksource="gp_timer" kernel parameter */ \
         if (use_gptimer_clksrc)                                         \
-                omap2_gptimer_clocksource_init((clksrc_nr), clksrc_src);\
+                omap2_gptimer_clocksource_init((clksrc_nr), clksrc_src, \
+                                                clksrc_prop);           \
         else                                                            \
                 omap2_sync32k_clocksource_init();                       \
 }
 
 #ifdef CONFIG_ARCH_OMAP2
-OMAP_SYS_32K_TIMER_INIT(2, 1, OMAP2_32K_SOURCE, "ti,timer-alwon",
-                        2, OMAP2_MPU_SOURCE);
+OMAP_SYS_32K_TIMER_INIT(2, 1, "timer_32k_ck", "ti,timer-alwon",
+                        2, "timer_sys_ck", NULL);
 #endif /* CONFIG_ARCH_OMAP2 */
 
 #ifdef CONFIG_ARCH_OMAP3
-OMAP_SYS_32K_TIMER_INIT(3, 1, OMAP3_32K_SOURCE, "ti,timer-alwon",
-                        2, OMAP3_MPU_SOURCE);
-OMAP_SYS_32K_TIMER_INIT(3_secure, 12, OMAP3_32K_SOURCE, "ti,timer-secure",
-                        2, OMAP3_MPU_SOURCE);
-OMAP_SYS_GP_TIMER_INIT(3_gp, 1, OMAP3_MPU_SOURCE, "ti,timer-alwon",
-                       2, OMAP3_MPU_SOURCE);
+OMAP_SYS_32K_TIMER_INIT(3, 1, "timer_32k_ck", "ti,timer-alwon",
+                        2, "timer_sys_ck", NULL);
+OMAP_SYS_32K_TIMER_INIT(3_secure, 12, "secure_32k_fck", "ti,timer-secure",
+                        2, "timer_sys_ck", NULL);
 #endif /* CONFIG_ARCH_OMAP3 */
 
-#ifdef CONFIG_SOC_AM33XX
-OMAP_SYS_GP_TIMER_INIT(3_am33xx, 1, OMAP4_MPU_SOURCE, "ti,timer-alwon",
-                       2, OMAP4_MPU_SOURCE);
-#endif /* CONFIG_SOC_AM33XX */
+#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM33XX)
+OMAP_SYS_GP_TIMER_INIT(3, 2, "timer_sys_ck", NULL,
+                       1, "timer_sys_ck", "ti,timer-alwon");
+#endif
+
+#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5)
+static OMAP_SYS_32K_TIMER_INIT(4, 1, "timer_32k_ck", "ti,timer-alwon",
+                               2, "sys_clkin_ck", NULL);
+#endif
 
 #ifdef CONFIG_ARCH_OMAP4
-OMAP_SYS_32K_TIMER_INIT(4, 1, OMAP4_32K_SOURCE, "ti,timer-alwon",
-                        2, OMAP4_MPU_SOURCE);
 #ifdef CONFIG_LOCAL_TIMERS
 static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, OMAP44XX_LOCAL_TWD_BASE, 29);
 void __init omap4_local_timer_init(void)
@@ -602,7 +605,7 @@ void __init omap4_local_timer_init(void)
                 int err;
 
                 if (of_have_populated_dt()) {
-                        twd_local_timer_of_register();
+                        clocksource_of_init();
                         return;
                 }
 
@@ -620,18 +623,12 @@ void __init omap4_local_timer_init(void)
 #endif /* CONFIG_ARCH_OMAP4 */
 
 #ifdef CONFIG_SOC_OMAP5
-OMAP_SYS_32K_TIMER_INIT(5, 1, OMAP4_32K_SOURCE, "ti,timer-alwon",
-                        2, OMAP5_MPU_SOURCE);
 void __init omap5_realtime_timer_init(void)
 {
-        int err;
-
-        omap5_sync32k_timer_init();
+        omap4_sync32k_timer_init();
         realtime_counter_init();
 
-        err = arch_timer_of_register();
-        if (err)
-                pr_err("%s: arch_timer_register failed %d\n", __func__, err);
+        clocksource_of_init();
 }
 #endif /* CONFIG_SOC_OMAP5 */
 
diff --git a/arch/arm/mach-omap2/usb-host.c b/arch/arm/mach-omap2/usb-host.c
index 5706bdccf45e..aa27d7f5cbb7 100644
--- a/arch/arm/mach-omap2/usb-host.c
+++ b/arch/arm/mach-omap2/usb-host.c
@@ -22,8 +22,12 @@
 #include <linux/platform_device.h>
 #include <linux/slab.h>
 #include <linux/dma-mapping.h>
-
-#include <asm/io.h>
+#include <linux/regulator/machine.h>
+#include <linux/regulator/fixed.h>
+#include <linux/string.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+#include <linux/usb/phy.h>
 
 #include "soc.h"
 #include "omap_device.h"
@@ -526,3 +530,155 @@ void __init usbhs_init(struct usbhs_omap_platform_data *pdata)
 }
 
 #endif
+
+/* Template for PHY regulators */
+static struct fixed_voltage_config hsusb_reg_config = {
+        /* .supply_name filled later */
+        .microvolts = 3300000,
+        .gpio = -1,             /* updated later */
+        .startup_delay = 70000, /* 70msec */
+        .enable_high = 1,       /* updated later */
+        .enabled_at_boot = 0,   /* keep in RESET */
+        /* .init_data filled later */
+};
+
+static const char *nop_name = "nop_usb_xceiv"; /* NOP PHY driver */
+static const char *reg_name = "reg-fixed-voltage"; /* Regulator driver */
+
+/**
+ * usbhs_add_regulator - Add a gpio based fixed voltage regulator device
+ * @name: name for the regulator
+ * @dev_id: device id of the device this regulator supplies power to
+ * @dev_supply: supply name that the device expects
+ * @gpio: GPIO number
+ * @polarity: 1 - Active high, 0 - Active low
+ */
+static int usbhs_add_regulator(char *name, char *dev_id, char *dev_supply,
+                                                int gpio, int polarity)
+{
+        struct regulator_consumer_supply *supplies;
+        struct regulator_init_data *reg_data;
+        struct fixed_voltage_config *config;
+        struct platform_device *pdev;
+        int ret;
+
+        supplies = kzalloc(sizeof(*supplies), GFP_KERNEL);
+        if (!supplies)
+                return -ENOMEM;
+
+        supplies->supply = dev_supply;
+        supplies->dev_name = dev_id;
+
+        reg_data = kzalloc(sizeof(*reg_data), GFP_KERNEL);
+        if (!reg_data)
+                return -ENOMEM;
+
+        reg_data->constraints.valid_ops_mask = REGULATOR_CHANGE_STATUS;
+        reg_data->consumer_supplies = supplies;
+        reg_data->num_consumer_supplies = 1;
+
+        config = kmemdup(&hsusb_reg_config, sizeof(hsusb_reg_config),
+                        GFP_KERNEL);
+        if (!config)
+                return -ENOMEM;
+
+        config->supply_name = name;
+        config->gpio = gpio;
+        config->enable_high = polarity;
+        config->init_data = reg_data;
+
+        /* create a regulator device */
+        pdev = kzalloc(sizeof(*pdev), GFP_KERNEL);
+        if (!pdev)
+                return -ENOMEM;
+
+        pdev->id = PLATFORM_DEVID_AUTO;
+        pdev->name = reg_name;
+        pdev->dev.platform_data = config;
+
+        ret = platform_device_register(pdev);
+        if (ret)
+                pr_err("%s: Failed registering regulator %s for %s\n",
+                                __func__, name, dev_id);
+
+        return ret;
+}
+
+int usbhs_init_phys(struct usbhs_phy_data *phy, int num_phys)
+{
+        char *rail_name;
+        int i, len;
+        struct platform_device *pdev;
+        char *phy_id;
+
+        /* the phy_id will be something like "nop_usb_xceiv.1" */
+        len = strlen(nop_name) + 3; /* 3 -> ".1" and NULL terminator */
+
+        for (i = 0; i < num_phys; i++) {
+
+                if (!phy->port) {
+                        pr_err("%s: Invalid port 0. Must start from 1\n",
+                                                __func__);
+                        continue;
+                }
+
+                /* do we need a NOP PHY device ? */
+                if (!gpio_is_valid(phy->reset_gpio) &&
+                        !gpio_is_valid(phy->vcc_gpio))
+                        continue;
+
+                /* create a NOP PHY device */
+                pdev = kzalloc(sizeof(*pdev), GFP_KERNEL);
+                if (!pdev)
+                        return -ENOMEM;
+
+                pdev->id = phy->port;
+                pdev->name = nop_name;
+                pdev->dev.platform_data = phy->platform_data;
+
+                phy_id = kmalloc(len, GFP_KERNEL);
+                if (!phy_id)
+                        return -ENOMEM;
+
+                scnprintf(phy_id, len, "nop_usb_xceiv.%d\n",
+                                        pdev->id);
+
+                if (platform_device_register(pdev)) {
+                        pr_err("%s: Failed to register device %s\n",
+                                __func__,  phy_id);
+                        continue;
+                }
+
+                usb_bind_phy("ehci-omap.0", phy->port - 1, phy_id);
+
+                /* Do we need RESET regulator ? */
+                if (gpio_is_valid(phy->reset_gpio)) {
+
+                        rail_name = kmalloc(13, GFP_KERNEL);
+                        if (!rail_name)
+                                return -ENOMEM;
+
+                        scnprintf(rail_name, 13, "hsusb%d_reset", phy->port);
+
+                        usbhs_add_regulator(rail_name, phy_id, "reset",
+                                                phy->reset_gpio, 1);
+                }
+
+                /* Do we need VCC regulator ? */
+                if (gpio_is_valid(phy->vcc_gpio)) {
+
+                        rail_name = kmalloc(13, GFP_KERNEL);
+                        if (!rail_name)
+                                return -ENOMEM;
+
+                        scnprintf(rail_name, 13, "hsusb%d_vcc", phy->port);
+
+                        usbhs_add_regulator(rail_name, phy_id, "vcc",
+                                        phy->vcc_gpio, phy->vcc_polarity);
+                }
+
+                phy++;
+        }
+
+        return 0;
+}
diff --git a/arch/arm/mach-omap2/usb-tusb6010.c b/arch/arm/mach-omap2/usb-tusb6010.c
index c5a3c6f9504e..e832bc7b8e2d 100644
--- a/arch/arm/mach-omap2/usb-tusb6010.c
+++ b/arch/arm/mach-omap2/usb-tusb6010.c
@@ -8,6 +8,7 @@
  * published by the Free Software Foundation.
  */
 
+#include <linux/err.h>
 #include <linux/string.h>
 #include <linux/types.h>
 #include <linux/errno.h>
@@ -26,6 +27,24 @@
 static u8               async_cs, sync_cs;
 static unsigned         refclk_psec;
 
+static struct gpmc_settings tusb_async = {
+        .wait_on_read   = true,
+        .wait_on_write  = true,
+        .device_width   = GPMC_DEVWIDTH_16BIT,
+        .mux_add_data   = GPMC_MUX_AD,
+};
+
+static struct gpmc_settings tusb_sync = {
+        .burst_read     = true,
+        .burst_write    = true,
+        .sync_read      = true,
+        .sync_write     = true,
+        .wait_on_read   = true,
+        .wait_on_write  = true,
+        .burst_len      = GPMC_BURST_16,
+        .device_width   = GPMC_DEVWIDTH_16BIT,
+        .mux_add_data   = GPMC_MUX_AD,
+};
 
 /* NOTE:  timings are from tusb 6010 datasheet Rev 1.8, 12-Sept 2006 */
 
@@ -37,8 +56,6 @@ static int tusb_set_async_mode(unsigned sysclk_ps)
 
         memset(&dev_t, 0, sizeof(dev_t));
 
-        dev_t.mux = true;
-
         dev_t.t_ceasu = 8 * 1000;
         dev_t.t_avdasu = t_acsnh_advnh - 7000;
         dev_t.t_ce_avd = 1000;
@@ -52,7 +69,7 @@ static int tusb_set_async_mode(unsigned sysclk_ps)
         dev_t.t_wpl = 300;
         dev_t.cyc_aavdh_we = 1;
 
-        gpmc_calc_timings(&t, &dev_t);
+        gpmc_calc_timings(&t, &tusb_async, &dev_t);
 
         return gpmc_cs_set_timings(async_cs, &t);
 }
@@ -65,10 +82,6 @@ static int tusb_set_sync_mode(unsigned sysclk_ps)
 
         memset(&dev_t, 0, sizeof(dev_t));
 
-        dev_t.mux = true;
-        dev_t.sync_read = true;
-        dev_t.sync_write = true;
-
         dev_t.clk = 11100;
         dev_t.t_bacc = 1000;
         dev_t.t_ces = 1000;
@@ -84,7 +97,7 @@ static int tusb_set_sync_mode(unsigned sysclk_ps)
         dev_t.cyc_wpl = 6;
         dev_t.t_ce_rdyz = 7000;
 
-        gpmc_calc_timings(&t, &dev_t);
+        gpmc_calc_timings(&t, &tusb_sync, &dev_t);
 
         return gpmc_cs_set_timings(sync_cs, &t);
 }
@@ -165,18 +178,12 @@ tusb6010_setup_interface(struct musb_hdrc_platform_data *data,
                 return status;
         }
         tusb_resources[0].end = tusb_resources[0].start + 0x9ff;
+        tusb_async.wait_pin = waitpin;
         async_cs = async;
-        gpmc_cs_write_reg(async, GPMC_CS_CONFIG1,
-                          GPMC_CONFIG1_PAGE_LEN(2)
-                        | GPMC_CONFIG1_WAIT_READ_MON
-                        | GPMC_CONFIG1_WAIT_WRITE_MON
-                        | GPMC_CONFIG1_WAIT_PIN_SEL(waitpin)
-                        | GPMC_CONFIG1_READTYPE_ASYNC
-                        | GPMC_CONFIG1_WRITETYPE_ASYNC
-                        | GPMC_CONFIG1_DEVICESIZE_16
-                        | GPMC_CONFIG1_DEVICETYPE_NOR
-                        | GPMC_CONFIG1_MUXADDDATA);
 
+        status = gpmc_cs_program_settings(async_cs, &tusb_async);
+        if (status < 0)
+                return status;
 
         /* SYNC region, primarily for DMA */
         status = gpmc_cs_request(sync, SZ_16M, (unsigned long *)
@@ -186,21 +193,12 @@ tusb6010_setup_interface(struct musb_hdrc_platform_data *data,
                 return status;
         }
         tusb_resources[1].end = tusb_resources[1].start + 0x9ff;
+        tusb_sync.wait_pin = waitpin;
         sync_cs = sync;
-        gpmc_cs_write_reg(sync, GPMC_CS_CONFIG1,
-                          GPMC_CONFIG1_READMULTIPLE_SUPP
-                        | GPMC_CONFIG1_READTYPE_SYNC
-                        | GPMC_CONFIG1_WRITEMULTIPLE_SUPP
-                        | GPMC_CONFIG1_WRITETYPE_SYNC
-                        | GPMC_CONFIG1_PAGE_LEN(2)
-                        | GPMC_CONFIG1_WAIT_READ_MON
-                        | GPMC_CONFIG1_WAIT_WRITE_MON
-                        | GPMC_CONFIG1_WAIT_PIN_SEL(waitpin)
-                        | GPMC_CONFIG1_DEVICESIZE_16
-                        | GPMC_CONFIG1_DEVICETYPE_NOR
-                        | GPMC_CONFIG1_MUXADDDATA
-                        /* fclk divider gets set later */
-                        );
+
+        status = gpmc_cs_program_settings(sync_cs, &tusb_sync);
+        if (status < 0)
+                return status;
 
         /* IRQ */
         status = gpio_request_one(irq, GPIOF_IN, "TUSB6010 irq");
diff --git a/arch/arm/mach-omap2/usb.h b/arch/arm/mach-omap2/usb.h
index 3319f5cf47a3..e7261ebcf7b0 100644
--- a/arch/arm/mach-omap2/usb.h
+++ b/arch/arm/mach-omap2/usb.h
@@ -53,8 +53,17 @@
 #define USBPHY_OTGSESSEND_EN    (1 << 20)
 #define USBPHY_DATA_POLARITY    (1 << 23)
 
+struct usbhs_phy_data {
+        int port;               /* 1 indexed port number */
+        int reset_gpio;
+        int vcc_gpio;
+        bool vcc_polarity;      /* 1 active high, 0 active low */
+        void *platform_data;
+};
+
 extern void usb_musb_init(struct omap_musb_board_data *board_data);
 extern void usbhs_init(struct usbhs_omap_platform_data *pdata);
+extern int usbhs_init_phys(struct usbhs_phy_data *phy, int num_phys);
 
 extern void am35x_musb_reset(void);
 extern void am35x_musb_phy_power(u8 on);
diff --git a/arch/arm/mach-s3c24xx/Kconfig b/arch/arm/mach-s3c24xx/Kconfig
index 37f513d1588e..0a8663c5f2ba 100644
--- a/arch/arm/mach-s3c24xx/Kconfig
+++ b/arch/arm/mach-s3c24xx/Kconfig
@@ -30,6 +30,7 @@ config CPU_S3C2410
         select S3C2410_CLOCK
         select S3C2410_CPUFREQ if CPU_FREQ_S3C24XX
         select S3C2410_PM if PM
+        select SAMSUNG_HRT
         help
           Support for S3C2410 and S3C2410A family from the S3C24XX line
           of Samsung Mobile CPUs.
@@ -41,6 +42,7 @@ config CPU_S3C2412
         select CPU_LLSERIAL_S3C2440
         select S3C2412_DMA if S3C24XX_DMA
         select S3C2412_PM if PM
+        select SAMSUNG_HRT
         help
           Support for the S3C2412 and S3C2413 SoCs from the S3C24XX line
 
@@ -53,6 +55,7 @@ config CPU_S3C2416
         select S3C2443_COMMON
         select S3C2443_DMA if S3C24XX_DMA
         select SAMSUNG_CLKSRC
+        select SAMSUNG_HRT
         help
           Support for the S3C2416 SoC from the S3C24XX line
 
@@ -63,6 +66,7 @@ config CPU_S3C2440
         select S3C2410_CLOCK
         select S3C2410_PM if PM
         select S3C2440_DMA if S3C24XX_DMA
+        select SAMSUNG_HRT
         help
           Support for S3C2440 Samsung Mobile CPU based systems.
 
@@ -72,6 +76,7 @@ config CPU_S3C2442
         select CPU_LLSERIAL_S3C2440
         select S3C2410_CLOCK
         select S3C2410_PM if PM
+        select SAMSUNG_HRT
         help
           Support for S3C2442 Samsung Mobile CPU based systems.
 
@@ -87,6 +92,7 @@ config CPU_S3C2443
         select S3C2443_COMMON
         select S3C2443_DMA if S3C24XX_DMA
         select SAMSUNG_CLKSRC
+        select SAMSUNG_HRT
         help
           Support for the S3C2443 SoC from the S3C24XX line
 
@@ -401,6 +407,7 @@ config S3C2412_DMA
 config S3C2412_PM
         bool
         select S3C2412_PM_SLEEP
+        select SAMSUNG_WAKEMASK
         help
           Internal config node to apply S3C2412 power management
 
diff --git a/arch/arm/mach-s3c24xx/Makefile b/arch/arm/mach-s3c24xx/Makefile
index af53d27d5c36..6f46ecfc8396 100644
--- a/arch/arm/mach-s3c24xx/Makefile
+++ b/arch/arm/mach-s3c24xx/Makefile
@@ -14,7 +14,7 @@ obj-				:=
 
 # core
 
-obj-y                           += common.o irq.o
+obj-y                           += common.o
 
 obj-$(CONFIG_CPU_S3C2410)       += s3c2410.o
 obj-$(CONFIG_S3C2410_CPUFREQ)   += cpufreq-s3c2410.o
@@ -22,7 +22,7 @@ obj-$(CONFIG_S3C2410_DMA)	+= dma-s3c2410.o
 obj-$(CONFIG_S3C2410_PLL)       += pll-s3c2410.o
 obj-$(CONFIG_S3C2410_PM)        += pm-s3c2410.o sleep-s3c2410.o
 
-obj-$(CONFIG_CPU_S3C2412)       += s3c2412.o irq-s3c2412.o clock-s3c2412.o
+obj-$(CONFIG_CPU_S3C2412)       += s3c2412.o clock-s3c2412.o
 obj-$(CONFIG_S3C2412_CPUFREQ)   += cpufreq-s3c2412.o
 obj-$(CONFIG_S3C2412_DMA)       += dma-s3c2412.o
 obj-$(CONFIG_S3C2412_PM)        += pm-s3c2412.o
@@ -31,9 +31,9 @@ obj-$(CONFIG_S3C2412_PM_SLEEP)	+= sleep-s3c2412.o
 obj-$(CONFIG_CPU_S3C2416)       += s3c2416.o clock-s3c2416.o
 obj-$(CONFIG_S3C2416_PM)        += pm-s3c2416.o
 
-obj-$(CONFIG_CPU_S3C2440)       += s3c2440.o irq-s3c2440.o clock-s3c2440.o
+obj-$(CONFIG_CPU_S3C2440)       += s3c2440.o clock-s3c2440.o
 obj-$(CONFIG_CPU_S3C2442)       += s3c2442.o
-obj-$(CONFIG_CPU_S3C244X)       += s3c244x.o irq-s3c244x.o clock-s3c244x.o
+obj-$(CONFIG_CPU_S3C244X)       += s3c244x.o clock-s3c244x.o
 obj-$(CONFIG_S3C2440_CPUFREQ)   += cpufreq-s3c2440.o
 obj-$(CONFIG_S3C2440_DMA)       += dma-s3c2440.o
 obj-$(CONFIG_S3C2440_PLL_12000000) += pll-s3c2440-12000000.o
diff --git a/arch/arm/mach-s3c24xx/bast-irq.c b/arch/arm/mach-s3c24xx/bast-irq.c
index c0daa9590b4c..cb1b791954de 100644
--- a/arch/arm/mach-s3c24xx/bast-irq.c
+++ b/arch/arm/mach-s3c24xx/bast-irq.c
@@ -34,8 +34,6 @@
 #include <mach/hardware.h>
 #include <mach/regs-irq.h>
 
-#include <plat/irq.h>
-
 #include "bast.h"
 
 #define irqdbf(x...)
diff --git a/arch/arm/mach-s3c24xx/clock-s3c2410.c b/arch/arm/mach-s3c24xx/clock-s3c2410.c
index 641266f3d152..34fffdf6fc1d 100644
--- a/arch/arm/mach-s3c24xx/clock-s3c2410.c
+++ b/arch/arm/mach-s3c24xx/clock-s3c2410.c
@@ -40,7 +40,6 @@
 #include <mach/regs-clock.h>
 #include <mach/regs-gpio.h>
 
-#include <plat/s3c2410.h>
 #include <plat/clock.h>
 #include <plat/cpu.h>
 
diff --git a/arch/arm/mach-s3c24xx/clock-s3c2412.c b/arch/arm/mach-s3c24xx/clock-s3c2412.c
index d10b695a9066..2cc017da88fe 100644
--- a/arch/arm/mach-s3c24xx/clock-s3c2412.c
+++ b/arch/arm/mach-s3c24xx/clock-s3c2412.c
@@ -41,7 +41,6 @@
 #include <mach/regs-clock.h>
 #include <mach/regs-gpio.h>
 
-#include <plat/s3c2412.h>
 #include <plat/clock.h>
 #include <plat/cpu.h>
 
diff --git a/arch/arm/mach-s3c24xx/clock-s3c2416.c b/arch/arm/mach-s3c24xx/clock-s3c2416.c
index 14a81c2317a4..036056cea57c 100644
--- a/arch/arm/mach-s3c24xx/clock-s3c2416.c
+++ b/arch/arm/mach-s3c24xx/clock-s3c2416.c
@@ -14,7 +14,6 @@
 #include <linux/init.h>
 #include <linux/clk.h>
 
-#include <plat/s3c2416.h>
 #include <plat/clock.h>
 #include <plat/clock-clksrc.h>
 #include <plat/cpu.h>
diff --git a/arch/arm/mach-s3c24xx/clock-s3c2443.c b/arch/arm/mach-s3c24xx/clock-s3c2443.c
index bdaba59b42dc..0a53051b0787 100644
--- a/arch/arm/mach-s3c24xx/clock-s3c2443.c
+++ b/arch/arm/mach-s3c24xx/clock-s3c2443.c
@@ -41,7 +41,6 @@
 
 #include <plat/cpu-freq.h>
 
-#include <plat/s3c2443.h>
 #include <plat/clock.h>
 #include <plat/clock-clksrc.h>
 #include <plat/cpu.h>
diff --git a/arch/arm/mach-s3c24xx/common-smdk.c b/arch/arm/mach-s3c24xx/common-smdk.c
index 3b2cf6db3634..404444dd3840 100644
--- a/arch/arm/mach-s3c24xx/common-smdk.c
+++ b/arch/arm/mach-s3c24xx/common-smdk.c
@@ -41,11 +41,12 @@
 
 #include <linux/platform_data/mtd-nand-s3c2410.h>
 
-#include <plat/common-smdk.h>
 #include <plat/gpio-cfg.h>
 #include <plat/devs.h>
 #include <plat/pm.h>
 
+#include "common-smdk.h"
+
 /* LED devices */
 
 static struct s3c24xx_led_platdata smdk_pdata_led4 = {
diff --git a/arch/arm/plat-samsung/include/plat/common-smdk.h b/arch/arm/mach-s3c24xx/common-smdk.h
index ba028f1ed30b..98f733e1cb42 100644
--- a/arch/arm/plat-samsung/include/plat/common-smdk.h
+++ b/arch/arm/mach-s3c24xx/common-smdk.h
@@ -1,5 +1,4 @@
-/* linux/arch/arm/plat-samsung/include/plat/common-smdk.h
- *
+/*
  * Copyright (c) 2006 Simtec Electronics
  *      Ben Dooks <ben@simtec.co.uk>
  *
diff --git a/arch/arm/mach-s3c24xx/common.c b/arch/arm/mach-s3c24xx/common.c
index 6bcf87f65f9e..d97533d21ac4 100644
--- a/arch/arm/mach-s3c24xx/common.c
+++ b/arch/arm/mach-s3c24xx/common.c
@@ -47,14 +47,11 @@
 #include <plat/cpu.h>
 #include <plat/devs.h>
 #include <plat/clock.h>
-#include <plat/s3c2410.h>
-#include <plat/s3c2412.h>
-#include <plat/s3c2416.h>
-#include <plat/s3c244x.h>
-#include <plat/s3c2443.h>
 #include <plat/cpu-freq.h>
 #include <plat/pll.h>
 
+#include "common.h"
+
 /* table of supported CPUs */
 
 static const char name_s3c2410[]  = "S3C2410";
diff --git a/arch/arm/mach-s3c24xx/common.h b/arch/arm/mach-s3c24xx/common.h
index ed6276fcaa3b..307c3714be55 100644
--- a/arch/arm/mach-s3c24xx/common.h
+++ b/arch/arm/mach-s3c24xx/common.h
@@ -12,8 +12,98 @@
 #ifndef __ARCH_ARM_MACH_S3C24XX_COMMON_H
 #define __ARCH_ARM_MACH_S3C24XX_COMMON_H __FILE__
 
-void s3c2410_restart(char mode, const char *cmd);
-void s3c244x_restart(char mode, const char *cmd);
+struct s3c2410_uartcfg;
+
+#ifdef CONFIG_CPU_S3C2410
+extern  int s3c2410_init(void);
+extern  int s3c2410a_init(void);
+extern void s3c2410_map_io(void);
+extern void s3c2410_init_uarts(struct s3c2410_uartcfg *cfg, int no);
+extern void s3c2410_init_clocks(int xtal);
+extern void s3c2410_restart(char mode, const char *cmd);
+extern void s3c2410_init_irq(void);
+#else
+#define s3c2410_init_clocks NULL
+#define s3c2410_init_uarts NULL
+#define s3c2410_map_io NULL
+#define s3c2410_init NULL
+#define s3c2410a_init NULL
+#endif
+
+#ifdef CONFIG_CPU_S3C2412
+extern  int s3c2412_init(void);
+extern void s3c2412_map_io(void);
+extern void s3c2412_init_uarts(struct s3c2410_uartcfg *cfg, int no);
+extern void s3c2412_init_clocks(int xtal);
+extern  int s3c2412_baseclk_add(void);
+extern void s3c2412_restart(char mode, const char *cmd);
+extern void s3c2412_init_irq(void);
+#else
+#define s3c2412_init_clocks NULL
+#define s3c2412_init_uarts NULL
+#define s3c2412_map_io NULL
+#define s3c2412_init NULL
+#endif
+
+#ifdef CONFIG_CPU_S3C2416
+extern  int s3c2416_init(void);
+extern void s3c2416_map_io(void);
+extern void s3c2416_init_uarts(struct s3c2410_uartcfg *cfg, int no);
+extern void s3c2416_init_clocks(int xtal);
+extern  int s3c2416_baseclk_add(void);
+extern void s3c2416_restart(char mode, const char *cmd);
+extern void s3c2416_init_irq(void);
+
+extern struct syscore_ops s3c2416_irq_syscore_ops;
+#else
+#define s3c2416_init_clocks NULL
+#define s3c2416_init_uarts NULL
+#define s3c2416_map_io NULL
+#define s3c2416_init NULL
+#endif
+
+#if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442)
+extern void s3c244x_map_io(void);
+extern void s3c244x_init_uarts(struct s3c2410_uartcfg *cfg, int no);
+extern void s3c244x_init_clocks(int xtal);
+extern void s3c244x_restart(char mode, const char *cmd);
+#else
+#define s3c244x_init_clocks NULL
+#define s3c244x_init_uarts NULL
+#endif
+
+#ifdef CONFIG_CPU_S3C2440
+extern  int s3c2440_init(void);
+extern void s3c2440_map_io(void);
+extern void s3c2440_init_irq(void);
+#else
+#define s3c2440_init NULL
+#define s3c2440_map_io NULL
+#endif
+
+#ifdef CONFIG_CPU_S3C2442
+extern  int s3c2442_init(void);
+extern void s3c2442_map_io(void);
+extern void s3c2442_init_irq(void);
+#else
+#define s3c2442_init NULL
+#define s3c2442_map_io NULL
+#endif
+
+#ifdef CONFIG_CPU_S3C2443
+extern  int s3c2443_init(void);
+extern void s3c2443_map_io(void);
+extern void s3c2443_init_uarts(struct s3c2410_uartcfg *cfg, int no);
+extern void s3c2443_init_clocks(int xtal);
+extern  int s3c2443_baseclk_add(void);
+extern void s3c2443_restart(char mode, const char *cmd);
+extern void s3c2443_init_irq(void);
+#else
+#define s3c2443_init_clocks NULL
+#define s3c2443_init_uarts NULL
+#define s3c2443_map_io NULL
+#define s3c2443_init NULL
+#endif
 
 extern struct syscore_ops s3c24xx_irq_syscore_ops;
 
diff --git a/arch/arm/mach-s3c24xx/dma-s3c2410.c b/arch/arm/mach-s3c24xx/dma-s3c2410.c
index 25d085adc93c..a6c94b820954 100644
--- a/arch/arm/mach-s3c24xx/dma-s3c2410.c
+++ b/arch/arm/mach-s3c24xx/dma-s3c2410.c
@@ -28,7 +28,6 @@
 #include <plat/regs-ac97.h>
 #include <plat/regs-dma.h>
 #include <mach/regs-lcd.h>
-#include <mach/regs-sdi.h>
 #include <plat/regs-iis.h>
 #include <plat/regs-spi.h>
 
diff --git a/arch/arm/mach-s3c24xx/dma-s3c2412.c b/arch/arm/mach-s3c24xx/dma-s3c2412.c
index d2408ba372cb..c0e8c3f5057e 100644
--- a/arch/arm/mach-s3c24xx/dma-s3c2412.c
+++ b/arch/arm/mach-s3c24xx/dma-s3c2412.c
@@ -28,7 +28,6 @@
 #include <plat/regs-ac97.h>
 #include <plat/regs-dma.h>
 #include <mach/regs-lcd.h>
-#include <mach/regs-sdi.h>
 #include <plat/regs-iis.h>
 #include <plat/regs-spi.h>
 
diff --git a/arch/arm/mach-s3c24xx/dma-s3c2440.c b/arch/arm/mach-s3c24xx/dma-s3c2440.c
index 0b86e74d104f..1c08eccd9425 100644
--- a/arch/arm/mach-s3c24xx/dma-s3c2440.c
+++ b/arch/arm/mach-s3c24xx/dma-s3c2440.c
@@ -28,7 +28,6 @@
 #include <plat/regs-ac97.h>
 #include <plat/regs-dma.h>
 #include <mach/regs-lcd.h>
-#include <mach/regs-sdi.h>
 #include <plat/regs-iis.h>
 #include <plat/regs-spi.h>
 
diff --git a/arch/arm/mach-s3c24xx/dma-s3c2443.c b/arch/arm/mach-s3c24xx/dma-s3c2443.c
index 05536254a3f8..000e4c69fce9 100644
--- a/arch/arm/mach-s3c24xx/dma-s3c2443.c
+++ b/arch/arm/mach-s3c24xx/dma-s3c2443.c
@@ -28,7 +28,6 @@
 #include <plat/regs-ac97.h>
 #include <plat/regs-dma.h>
 #include <mach/regs-lcd.h>
-#include <mach/regs-sdi.h>
 #include <plat/regs-iis.h>
 #include <plat/regs-spi.h>
 
diff --git a/arch/arm/mach-s3c24xx/include/mach/entry-macro.S b/arch/arm/mach-s3c24xx/include/mach/entry-macro.S
deleted file mode 100644
index 6a21beeba1da..000000000000
--- a/arch/arm/mach-s3c24xx/include/mach/entry-macro.S
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- * arch/arm/mach-s3c2410/include/mach/entry-macro.S
- *
- * Low-level IRQ helper macros for S3C2410-based platforms
- *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
-*/
-
-/* We have a problem that the INTOFFSET register does not always
- * show one interrupt. Occasionally we get two interrupts through
- * the prioritiser, and this causes the INTOFFSET register to show
- * what looks like the logical-or of the two interrupt numbers.
- *
- * Thanks to Klaus, Shannon, et al for helping to debug this problem
-*/
-
-#define INTPND          (0x10)
-#define INTOFFSET       (0x14)
-
-#include <mach/hardware.h>
-#include <asm/irq.h>
-
-        .macro  get_irqnr_preamble, base, tmp
-        .endm
-
-        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-
-                mov     \base, #S3C24XX_VA_IRQ
-
-                @@ try the interrupt offset register, since it is there
-
-                ldr     \irqstat, [\base, #INTPND ]
-                teq     \irqstat, #0
-                beq     1002f
-                ldr     \irqnr, [\base, #INTOFFSET ]
-                mov     \tmp, #1
-                tst     \irqstat, \tmp, lsl \irqnr
-                bne     1001f
-
-                @@ the number specified is not a valid irq, so try
-                @@ and work it out for ourselves
-
-                mov     \irqnr, #0              @@ start here
-
-                @@ work out which irq (if any) we got
-
-                movs    \tmp, \irqstat, lsl#16
-                addeq   \irqnr, \irqnr, #16
-                moveq   \irqstat, \irqstat, lsr#16
-                tst     \irqstat, #0xff
-                addeq   \irqnr, \irqnr, #8
-                moveq   \irqstat, \irqstat, lsr#8
-                tst     \irqstat, #0xf
-                addeq   \irqnr, \irqnr, #4
-                moveq   \irqstat, \irqstat, lsr#4
-                tst     \irqstat, #0x3
-                addeq   \irqnr, \irqnr, #2
-                moveq   \irqstat, \irqstat, lsr#2
-                tst     \irqstat, #0x1
-                addeq   \irqnr, \irqnr, #1
-
-                @@ we have the value
-1001:
-                adds    \irqnr, \irqnr, #IRQ_EINT0
-1002:
-                @@ exit here, Z flag unset if IRQ
-
-        .endm
diff --git a/arch/arm/mach-s3c24xx/include/mach/irqs.h b/arch/arm/mach-s3c24xx/include/mach/irqs.h
index b7a9f4d469e8..43cada8019b4 100644
--- a/arch/arm/mach-s3c24xx/include/mach/irqs.h
+++ b/arch/arm/mach-s3c24xx/include/mach/irqs.h
@@ -59,49 +59,53 @@
 #define IRQ_ADCPARENT  S3C2410_IRQ(31)
 
 /* interrupts generated from the external interrupts sources */
-#define IRQ_EINT4      S3C2410_IRQ(32)     /* 48 */
-#define IRQ_EINT5      S3C2410_IRQ(33)
-#define IRQ_EINT6      S3C2410_IRQ(34)
-#define IRQ_EINT7      S3C2410_IRQ(35)
-#define IRQ_EINT8      S3C2410_IRQ(36)
-#define IRQ_EINT9      S3C2410_IRQ(37)
-#define IRQ_EINT10     S3C2410_IRQ(38)
-#define IRQ_EINT11     S3C2410_IRQ(39)
-#define IRQ_EINT12     S3C2410_IRQ(40)
-#define IRQ_EINT13     S3C2410_IRQ(41)
-#define IRQ_EINT14     S3C2410_IRQ(42)
-#define IRQ_EINT15     S3C2410_IRQ(43)
-#define IRQ_EINT16     S3C2410_IRQ(44)
-#define IRQ_EINT17     S3C2410_IRQ(45)
-#define IRQ_EINT18     S3C2410_IRQ(46)
-#define IRQ_EINT19     S3C2410_IRQ(47)
-#define IRQ_EINT20     S3C2410_IRQ(48)     /* 64 */
-#define IRQ_EINT21     S3C2410_IRQ(49)
-#define IRQ_EINT22     S3C2410_IRQ(50)
-#define IRQ_EINT23     S3C2410_IRQ(51)
+#define IRQ_EINT0_2412 S3C2410_IRQ(32)
+#define IRQ_EINT1_2412 S3C2410_IRQ(33)
+#define IRQ_EINT2_2412 S3C2410_IRQ(34)
+#define IRQ_EINT3_2412 S3C2410_IRQ(35)
+#define IRQ_EINT4      S3C2410_IRQ(36)     /* 52 */
+#define IRQ_EINT5      S3C2410_IRQ(37)
+#define IRQ_EINT6      S3C2410_IRQ(38)
+#define IRQ_EINT7      S3C2410_IRQ(39)
+#define IRQ_EINT8      S3C2410_IRQ(40)
+#define IRQ_EINT9      S3C2410_IRQ(41)
+#define IRQ_EINT10     S3C2410_IRQ(42)
+#define IRQ_EINT11     S3C2410_IRQ(43)
+#define IRQ_EINT12     S3C2410_IRQ(44)
+#define IRQ_EINT13     S3C2410_IRQ(45)
+#define IRQ_EINT14     S3C2410_IRQ(46)
+#define IRQ_EINT15     S3C2410_IRQ(47)
+#define IRQ_EINT16     S3C2410_IRQ(48)
+#define IRQ_EINT17     S3C2410_IRQ(49)
+#define IRQ_EINT18     S3C2410_IRQ(50)
+#define IRQ_EINT19     S3C2410_IRQ(51)
+#define IRQ_EINT20     S3C2410_IRQ(52)     /* 68 */
+#define IRQ_EINT21     S3C2410_IRQ(53)
+#define IRQ_EINT22     S3C2410_IRQ(54)
+#define IRQ_EINT23     S3C2410_IRQ(55)
 
 #define IRQ_EINT_BIT(x) ((x) - IRQ_EINT4 + 4)
 #define IRQ_EINT(x)    (((x) >= 4) ? (IRQ_EINT4 + (x) - 4) : (IRQ_EINT0 + (x)))
 
-#define IRQ_LCD_FIFO   S3C2410_IRQ(52)
-#define IRQ_LCD_FRAME  S3C2410_IRQ(53)
+#define IRQ_LCD_FIFO   S3C2410_IRQ(56)
+#define IRQ_LCD_FRAME  S3C2410_IRQ(57)
 
 /* IRQs for the interal UARTs, and ADC
  * these need to be ordered in number of appearance in the
  * SUBSRC mask register
 */
 
-#define S3C2410_IRQSUB(x)       S3C2410_IRQ((x)+54)
+#define S3C2410_IRQSUB(x)       S3C2410_IRQ((x)+58)
 
-#define IRQ_S3CUART_RX0         S3C2410_IRQSUB(0)       /* 70 */
+#define IRQ_S3CUART_RX0         S3C2410_IRQSUB(0)       /* 74 */
 #define IRQ_S3CUART_TX0         S3C2410_IRQSUB(1)
 #define IRQ_S3CUART_ERR0        S3C2410_IRQSUB(2)
 
-#define IRQ_S3CUART_RX1         S3C2410_IRQSUB(3)       /* 73 */
+#define IRQ_S3CUART_RX1         S3C2410_IRQSUB(3)       /* 77 */
 #define IRQ_S3CUART_TX1         S3C2410_IRQSUB(4)
 #define IRQ_S3CUART_ERR1        S3C2410_IRQSUB(5)
 
-#define IRQ_S3CUART_RX2         S3C2410_IRQSUB(6)       /* 76 */
+#define IRQ_S3CUART_RX2         S3C2410_IRQSUB(6)       /* 80 */
 #define IRQ_S3CUART_TX2         S3C2410_IRQSUB(7)
 #define IRQ_S3CUART_ERR2        S3C2410_IRQSUB(8)
 
@@ -136,7 +140,7 @@
 
 /* second interrupt-register of s3c2416/s3c2450 */
 
-#define S3C2416_IRQ(x)          S3C2410_IRQ((x) + 54 + 29)
+#define S3C2416_IRQ(x)          S3C2410_IRQ((x) + 58 + 29)
 #define IRQ_S3C2416_2D          S3C2416_IRQ(0)
 #define IRQ_S3C2416_IIC1        S3C2416_IRQ(1)
 #define IRQ_S3C2416_RESERVED2   S3C2416_IRQ(2)
diff --git a/arch/arm/mach-s3c24xx/include/mach/regs-sdi.h b/arch/arm/mach-s3c24xx/include/mach/regs-sdi.h
deleted file mode 100644
index cbf2d8884e30..000000000000
--- a/arch/arm/mach-s3c24xx/include/mach/regs-sdi.h
+++ /dev/null
@@ -1,127 +0,0 @@
-/* arch/arm/mach-s3c2410/include/mach/regs-sdi.h
- *
- * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk>
- *                    http://www.simtec.co.uk/products/SWLINUX/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * S3C2410 MMC/SDIO register definitions
-*/
-
-#ifndef __ASM_ARM_REGS_SDI
-#define __ASM_ARM_REGS_SDI "regs-sdi.h"
-
-#define S3C2410_SDICON                (0x00)
-#define S3C2410_SDIPRE                (0x04)
-#define S3C2410_SDICMDARG             (0x08)
-#define S3C2410_SDICMDCON             (0x0C)
-#define S3C2410_SDICMDSTAT            (0x10)
-#define S3C2410_SDIRSP0               (0x14)
-#define S3C2410_SDIRSP1               (0x18)
-#define S3C2410_SDIRSP2               (0x1C)
-#define S3C2410_SDIRSP3               (0x20)
-#define S3C2410_SDITIMER              (0x24)
-#define S3C2410_SDIBSIZE              (0x28)
-#define S3C2410_SDIDCON               (0x2C)
-#define S3C2410_SDIDCNT               (0x30)
-#define S3C2410_SDIDSTA               (0x34)
-#define S3C2410_SDIFSTA               (0x38)
-
-#define S3C2410_SDIDATA               (0x3C)
-#define S3C2410_SDIIMSK               (0x40)
-
-#define S3C2440_SDIDATA               (0x40)
-#define S3C2440_SDIIMSK               (0x3C)
-
-#define S3C2440_SDICON_SDRESET        (1<<8)
-#define S3C2440_SDICON_MMCCLOCK       (1<<5)
-#define S3C2410_SDICON_BYTEORDER      (1<<4)
-#define S3C2410_SDICON_SDIOIRQ        (1<<3)
-#define S3C2410_SDICON_RWAITEN        (1<<2)
-#define S3C2410_SDICON_FIFORESET      (1<<1)
-#define S3C2410_SDICON_CLOCKTYPE      (1<<0)
-
-#define S3C2410_SDICMDCON_ABORT       (1<<12)
-#define S3C2410_SDICMDCON_WITHDATA    (1<<11)
-#define S3C2410_SDICMDCON_LONGRSP     (1<<10)
-#define S3C2410_SDICMDCON_WAITRSP     (1<<9)
-#define S3C2410_SDICMDCON_CMDSTART    (1<<8)
-#define S3C2410_SDICMDCON_SENDERHOST  (1<<6)
-#define S3C2410_SDICMDCON_INDEX       (0x3f)
-
-#define S3C2410_SDICMDSTAT_CRCFAIL    (1<<12)
-#define S3C2410_SDICMDSTAT_CMDSENT    (1<<11)
-#define S3C2410_SDICMDSTAT_CMDTIMEOUT (1<<10)
-#define S3C2410_SDICMDSTAT_RSPFIN     (1<<9)
-#define S3C2410_SDICMDSTAT_XFERING    (1<<8)
-#define S3C2410_SDICMDSTAT_INDEX      (0xff)
-
-#define S3C2440_SDIDCON_DS_BYTE       (0<<22)
-#define S3C2440_SDIDCON_DS_HALFWORD   (1<<22)
-#define S3C2440_SDIDCON_DS_WORD       (2<<22)
-#define S3C2410_SDIDCON_IRQPERIOD     (1<<21)
-#define S3C2410_SDIDCON_TXAFTERRESP   (1<<20)
-#define S3C2410_SDIDCON_RXAFTERCMD    (1<<19)
-#define S3C2410_SDIDCON_BUSYAFTERCMD  (1<<18)
-#define S3C2410_SDIDCON_BLOCKMODE     (1<<17)
-#define S3C2410_SDIDCON_WIDEBUS       (1<<16)
-#define S3C2410_SDIDCON_DMAEN         (1<<15)
-#define S3C2410_SDIDCON_STOP          (1<<14)
-#define S3C2440_SDIDCON_DATSTART      (1<<14)
-#define S3C2410_SDIDCON_DATMODE       (3<<12)
-#define S3C2410_SDIDCON_BLKNUM        (0x7ff)
-
-/* constants for S3C2410_SDIDCON_DATMODE */
-#define S3C2410_SDIDCON_XFER_READY    (0<<12)
-#define S3C2410_SDIDCON_XFER_CHKSTART (1<<12)
-#define S3C2410_SDIDCON_XFER_RXSTART  (2<<12)
-#define S3C2410_SDIDCON_XFER_TXSTART  (3<<12)
-
-#define S3C2410_SDIDCON_BLKNUM_MASK   (0xFFF)
-#define S3C2410_SDIDCNT_BLKNUM_SHIFT  (12)
-
-#define S3C2410_SDIDSTA_RDYWAITREQ    (1<<10)
-#define S3C2410_SDIDSTA_SDIOIRQDETECT (1<<9)
-#define S3C2410_SDIDSTA_FIFOFAIL      (1<<8)    /* reserved on 2440 */
-#define S3C2410_SDIDSTA_CRCFAIL       (1<<7)
-#define S3C2410_SDIDSTA_RXCRCFAIL     (1<<6)
-#define S3C2410_SDIDSTA_DATATIMEOUT   (1<<5)
-#define S3C2410_SDIDSTA_XFERFINISH    (1<<4)
-#define S3C2410_SDIDSTA_BUSYFINISH    (1<<3)
-#define S3C2410_SDIDSTA_SBITERR       (1<<2)    /* reserved on 2410a/2440 */
-#define S3C2410_SDIDSTA_TXDATAON      (1<<1)
-#define S3C2410_SDIDSTA_RXDATAON      (1<<0)
-
-#define S3C2440_SDIFSTA_FIFORESET      (1<<16)
-#define S3C2440_SDIFSTA_FIFOFAIL       (3<<14)  /* 3 is correct (2 bits) */
-#define S3C2410_SDIFSTA_TFDET          (1<<13)
-#define S3C2410_SDIFSTA_RFDET          (1<<12)
-#define S3C2410_SDIFSTA_TFHALF         (1<<11)
-#define S3C2410_SDIFSTA_TFEMPTY        (1<<10)
-#define S3C2410_SDIFSTA_RFLAST         (1<<9)
-#define S3C2410_SDIFSTA_RFFULL         (1<<8)
-#define S3C2410_SDIFSTA_RFHALF         (1<<7)
-#define S3C2410_SDIFSTA_COUNTMASK      (0x7f)
-
-#define S3C2410_SDIIMSK_RESPONSECRC    (1<<17)
-#define S3C2410_SDIIMSK_CMDSENT        (1<<16)
-#define S3C2410_SDIIMSK_CMDTIMEOUT     (1<<15)
-#define S3C2410_SDIIMSK_RESPONSEND     (1<<14)
-#define S3C2410_SDIIMSK_READWAIT       (1<<13)
-#define S3C2410_SDIIMSK_SDIOIRQ        (1<<12)
-#define S3C2410_SDIIMSK_FIFOFAIL       (1<<11)
-#define S3C2410_SDIIMSK_CRCSTATUS      (1<<10)
-#define S3C2410_SDIIMSK_DATACRC        (1<<9)
-#define S3C2410_SDIIMSK_DATATIMEOUT    (1<<8)
-#define S3C2410_SDIIMSK_DATAFINISH     (1<<7)
-#define S3C2410_SDIIMSK_BUSYFINISH     (1<<6)
-#define S3C2410_SDIIMSK_SBITERR        (1<<5)   /* reserved 2440/2410a */
-#define S3C2410_SDIIMSK_TXFIFOHALF     (1<<4)
-#define S3C2410_SDIIMSK_TXFIFOEMPTY    (1<<3)
-#define S3C2410_SDIIMSK_RXFIFOLAST     (1<<2)
-#define S3C2410_SDIIMSK_RXFIFOFULL     (1<<1)
-#define S3C2410_SDIIMSK_RXFIFOHALF     (1<<0)
-
-#endif /* __ASM_ARM_REGS_SDI */
diff --git a/arch/arm/mach-s3c24xx/irq-pm.c b/arch/arm/mach-s3c24xx/irq-pm.c
index e1199599873e..b91341ef2b2e 100644
--- a/arch/arm/mach-s3c24xx/irq-pm.c
+++ b/arch/arm/mach-s3c24xx/irq-pm.c
@@ -16,10 +16,15 @@
 #include <linux/interrupt.h>
 #include <linux/irq.h>
 #include <linux/syscore_ops.h>
+#include <linux/io.h>
 
 #include <plat/cpu.h>
 #include <plat/pm.h>
-#include <plat/irq.h>
+#include <plat/map-base.h>
+#include <plat/map-s3c.h>
+
+#include <mach/regs-irq.h>
+#include <mach/regs-gpio.h>
 
 #include <asm/irq.h>
 
diff --git a/arch/arm/mach-s3c24xx/irq-s3c2412.c b/arch/arm/mach-s3c24xx/irq-s3c2412.c
deleted file mode 100644
index 67d763178d3f..000000000000
--- a/arch/arm/mach-s3c24xx/irq-s3c2412.c
+++ /dev/null
@@ -1,215 +0,0 @@
-/* linux/arch/arm/mach-s3c2412/irq.c
- *
- * Copyright (c) 2006 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- *
-*/
-
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/interrupt.h>
-#include <linux/ioport.h>
-#include <linux/device.h>
-#include <linux/io.h>
-
-#include <mach/hardware.h>
-#include <asm/irq.h>
-
-#include <asm/mach/irq.h>
-
-#include <mach/regs-irq.h>
-#include <mach/regs-gpio.h>
-
-#include <plat/cpu.h>
-#include <plat/irq.h>
-#include <plat/pm.h>
-
-#include "s3c2412-power.h"
-
-#define INTMSK(start, end) ((1 << ((end) + 1 - (start))) - 1)
-#define INTMSK_SUB(start, end) (INTMSK(start, end) << ((start - S3C2410_IRQSUB(0))))
-
-/* the s3c2412 changes the behaviour of IRQ_EINT0 through IRQ_EINT3 by
- * having them turn up in both the INT* and the EINT* registers. Whilst
- * both show the status, they both now need to be acked when the IRQs
- * go off.
-*/
-
-static void
-s3c2412_irq_mask(struct irq_data *data)
-{
-        unsigned long bitval = 1UL << (data->irq - IRQ_EINT0);
-        unsigned long mask;
-
-        mask = __raw_readl(S3C2410_INTMSK);
-        __raw_writel(mask | bitval, S3C2410_INTMSK);
-
-        mask = __raw_readl(S3C2412_EINTMASK);
-        __raw_writel(mask | bitval, S3C2412_EINTMASK);
-}
-
-static inline void
-s3c2412_irq_ack(struct irq_data *data)
-{
-        unsigned long bitval = 1UL << (data->irq - IRQ_EINT0);
-
-        __raw_writel(bitval, S3C2412_EINTPEND);
-        __raw_writel(bitval, S3C2410_SRCPND);
-        __raw_writel(bitval, S3C2410_INTPND);
-}
-
-static inline void
-s3c2412_irq_maskack(struct irq_data *data)
-{
-        unsigned long bitval = 1UL << (data->irq - IRQ_EINT0);
-        unsigned long mask;
-
-        mask = __raw_readl(S3C2410_INTMSK);
-        __raw_writel(mask|bitval, S3C2410_INTMSK);
-
-        mask = __raw_readl(S3C2412_EINTMASK);
-        __raw_writel(mask | bitval, S3C2412_EINTMASK);
-
-        __raw_writel(bitval, S3C2412_EINTPEND);
-        __raw_writel(bitval, S3C2410_SRCPND);
-        __raw_writel(bitval, S3C2410_INTPND);
-}
-
-static void
-s3c2412_irq_unmask(struct irq_data *data)
-{
-        unsigned long bitval = 1UL << (data->irq - IRQ_EINT0);
-        unsigned long mask;
-
-        mask = __raw_readl(S3C2412_EINTMASK);
-        __raw_writel(mask & ~bitval, S3C2412_EINTMASK);
-
-        mask = __raw_readl(S3C2410_INTMSK);
-        __raw_writel(mask & ~bitval, S3C2410_INTMSK);
-}
-
-static struct irq_chip s3c2412_irq_eint0t4 = {
-        .irq_ack        = s3c2412_irq_ack,
-        .irq_mask       = s3c2412_irq_mask,
-        .irq_unmask     = s3c2412_irq_unmask,
-        .irq_set_wake   = s3c_irq_wake,
-        .irq_set_type   = s3c_irqext_type,
-};
-
-#define INTBIT(x)       (1 << ((x) - S3C2410_IRQSUB(0)))
-
-/* CF and SDI sub interrupts */
-
-static void s3c2412_irq_demux_cfsdi(unsigned int irq, struct irq_desc *desc)
-{
-        unsigned int subsrc, submsk;
-
-        subsrc = __raw_readl(S3C2410_SUBSRCPND);
-        submsk = __raw_readl(S3C2410_INTSUBMSK);
-
-        subsrc  &= ~submsk;
-
-        if (subsrc & INTBIT(IRQ_S3C2412_SDI))
-                generic_handle_irq(IRQ_S3C2412_SDI);
-
-        if (subsrc & INTBIT(IRQ_S3C2412_CF))
-                generic_handle_irq(IRQ_S3C2412_CF);
-}
-
-#define INTMSK_CFSDI    (1UL << (IRQ_S3C2412_CFSDI - IRQ_EINT0))
-#define SUBMSK_CFSDI    INTMSK_SUB(IRQ_S3C2412_SDI, IRQ_S3C2412_CF)
-
-static void s3c2412_irq_cfsdi_mask(struct irq_data *data)
-{
-        s3c_irqsub_mask(data->irq, INTMSK_CFSDI, SUBMSK_CFSDI);
-}
-
-static void s3c2412_irq_cfsdi_unmask(struct irq_data *data)
-{
-        s3c_irqsub_unmask(data->irq, INTMSK_CFSDI);
-}
-
-static void s3c2412_irq_cfsdi_ack(struct irq_data *data)
-{
-        s3c_irqsub_maskack(data->irq, INTMSK_CFSDI, SUBMSK_CFSDI);
-}
-
-static struct irq_chip s3c2412_irq_cfsdi = {
-        .name           = "s3c2412-cfsdi",
-        .irq_ack        = s3c2412_irq_cfsdi_ack,
-        .irq_mask       = s3c2412_irq_cfsdi_mask,
-        .irq_unmask     = s3c2412_irq_cfsdi_unmask,
-};
-
-static int s3c2412_irq_rtc_wake(struct irq_data *data, unsigned int state)
-{
-        unsigned long pwrcfg;
-
-        pwrcfg = __raw_readl(S3C2412_PWRCFG);
-        if (state)
-                pwrcfg &= ~S3C2412_PWRCFG_RTC_MASKIRQ;
-        else
-                pwrcfg |= S3C2412_PWRCFG_RTC_MASKIRQ;
-        __raw_writel(pwrcfg, S3C2412_PWRCFG);
-
-        return s3c_irq_chip.irq_set_wake(data, state);
-}
-
-static struct irq_chip s3c2412_irq_rtc_chip;
-
-static int s3c2412_irq_add(struct device *dev, struct subsys_interface *sif)
-{
-        unsigned int irqno;
-
-        for (irqno = IRQ_EINT0; irqno <= IRQ_EINT3; irqno++) {
-                irq_set_chip_and_handler(irqno, &s3c2412_irq_eint0t4,
-                                         handle_edge_irq);
-                set_irq_flags(irqno, IRQF_VALID);
-        }
-
-        /* add demux support for CF/SDI */
-
-        irq_set_chained_handler(IRQ_S3C2412_CFSDI, s3c2412_irq_demux_cfsdi);
-
-        for (irqno = IRQ_S3C2412_SDI; irqno <= IRQ_S3C2412_CF; irqno++) {
-                irq_set_chip_and_handler(irqno, &s3c2412_irq_cfsdi,
-                                         handle_level_irq);
-                set_irq_flags(irqno, IRQF_VALID);
-        }
-
-        /* change RTC IRQ's set wake method */
-
-        s3c2412_irq_rtc_chip = s3c_irq_chip;
-        s3c2412_irq_rtc_chip.irq_set_wake = s3c2412_irq_rtc_wake;
-
-        irq_set_chip(IRQ_RTC, &s3c2412_irq_rtc_chip);
-
-        return 0;
-}
-
-static struct subsys_interface s3c2412_irq_interface = {
-        .name           = "s3c2412_irq",
-        .subsys         = &s3c2412_subsys,
-        .add_dev        = s3c2412_irq_add,
-};
-
-static int s3c2412_irq_init(void)
-{
-        return subsys_interface_register(&s3c2412_irq_interface);
-}
-
-arch_initcall(s3c2412_irq_init);
diff --git a/arch/arm/mach-s3c24xx/irq-s3c2440.c b/arch/arm/mach-s3c24xx/irq-s3c2440.c
deleted file mode 100644
index 4a18cde439cc..000000000000
--- a/arch/arm/mach-s3c24xx/irq-s3c2440.c
+++ /dev/null
@@ -1,128 +0,0 @@
-/* linux/arch/arm/mach-s3c2440/irq.c
- *
- * Copyright (c) 2003-2004 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- *
-*/
-
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/interrupt.h>
-#include <linux/ioport.h>
-#include <linux/device.h>
-#include <linux/io.h>
-
-#include <mach/hardware.h>
-#include <asm/irq.h>
-
-#include <asm/mach/irq.h>
-
-#include <mach/regs-irq.h>
-#include <mach/regs-gpio.h>
-
-#include <plat/cpu.h>
-#include <plat/pm.h>
-#include <plat/irq.h>
-
-/* WDT/AC97 */
-
-static void s3c_irq_demux_wdtac97(unsigned int irq,
-                                  struct irq_desc *desc)
-{
-        unsigned int subsrc, submsk;
-
-        /* read the current pending interrupts, and the mask
-         * for what it is available */
-
-        subsrc = __raw_readl(S3C2410_SUBSRCPND);
-        submsk = __raw_readl(S3C2410_INTSUBMSK);
-
-        subsrc &= ~submsk;
-        subsrc >>= 13;
-        subsrc &= 3;
-
-        if (subsrc != 0) {
-                if (subsrc & 1) {
-                        generic_handle_irq(IRQ_S3C2440_WDT);
-                }
-                if (subsrc & 2) {
-                        generic_handle_irq(IRQ_S3C2440_AC97);
-                }
-        }
-}
-
-
-#define INTMSK_WDT       (1UL << (IRQ_WDT - IRQ_EINT0))
-
-static void
-s3c_irq_wdtac97_mask(struct irq_data *data)
-{
-        s3c_irqsub_mask(data->irq, INTMSK_WDT, 3 << 13);
-}
-
-static void
-s3c_irq_wdtac97_unmask(struct irq_data *data)
-{
-        s3c_irqsub_unmask(data->irq, INTMSK_WDT);
-}
-
-static void
-s3c_irq_wdtac97_ack(struct irq_data *data)
-{
-        s3c_irqsub_maskack(data->irq, INTMSK_WDT, 3 << 13);
-}
-
-static struct irq_chip s3c_irq_wdtac97 = {
-        .irq_mask       = s3c_irq_wdtac97_mask,
-        .irq_unmask     = s3c_irq_wdtac97_unmask,
-        .irq_ack        = s3c_irq_wdtac97_ack,
-};
-
-static int s3c2440_irq_add(struct device *dev, struct subsys_interface *sif)
-{
-        unsigned int irqno;
-
-        printk("S3C2440: IRQ Support\n");
-
-        /* add new chained handler for wdt, ac7 */
-
-        irq_set_chip_and_handler(IRQ_WDT, &s3c_irq_level_chip,
-                                 handle_level_irq);
-        irq_set_chained_handler(IRQ_WDT, s3c_irq_demux_wdtac97);
-
-        for (irqno = IRQ_S3C2440_WDT; irqno <= IRQ_S3C2440_AC97; irqno++) {
-                irq_set_chip_and_handler(irqno, &s3c_irq_wdtac97,
-                                         handle_level_irq);
-                set_irq_flags(irqno, IRQF_VALID);
-        }
-
-        return 0;
-}
-
-static struct subsys_interface s3c2440_irq_interface = {
-        .name           = "s3c2440_irq",
-        .subsys         = &s3c2440_subsys,
-        .add_dev        = s3c2440_irq_add,
-};
-
-static int s3c2440_irq_init(void)
-{
-        return subsys_interface_register(&s3c2440_irq_interface);
-}
-
-arch_initcall(s3c2440_irq_init);
-
diff --git a/arch/arm/mach-s3c24xx/irq-s3c244x.c b/arch/arm/mach-s3c24xx/irq-s3c244x.c
deleted file mode 100644
index 5fe8e58d3afd..000000000000
--- a/arch/arm/mach-s3c24xx/irq-s3c244x.c
+++ /dev/null
@@ -1,142 +0,0 @@
-/* linux/arch/arm/plat-s3c24xx/s3c244x-irq.c
- *
- * Copyright (c) 2003-2004 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- *
-*/
-
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/interrupt.h>
-#include <linux/ioport.h>
-#include <linux/device.h>
-#include <linux/io.h>
-
-#include <mach/hardware.h>
-#include <asm/irq.h>
-
-#include <asm/mach/irq.h>
-
-#include <mach/regs-irq.h>
-#include <mach/regs-gpio.h>
-
-#include <plat/cpu.h>
-#include <plat/pm.h>
-#include <plat/irq.h>
-
-/* camera irq */
-
-static void s3c_irq_demux_cam(unsigned int irq,
-                              struct irq_desc *desc)
-{
-        unsigned int subsrc, submsk;
-
-        /* read the current pending interrupts, and the mask
-         * for what it is available */
-
-        subsrc = __raw_readl(S3C2410_SUBSRCPND);
-        submsk = __raw_readl(S3C2410_INTSUBMSK);
-
-        subsrc &= ~submsk;
-        subsrc >>= 11;
-        subsrc &= 3;
-
-        if (subsrc != 0) {
-                if (subsrc & 1) {
-                        generic_handle_irq(IRQ_S3C2440_CAM_C);
-                }
-                if (subsrc & 2) {
-                        generic_handle_irq(IRQ_S3C2440_CAM_P);
-                }
-        }
-}
-
-#define INTMSK_CAM (1UL << (IRQ_CAM - IRQ_EINT0))
-
-static void
-s3c_irq_cam_mask(struct irq_data *data)
-{
-        s3c_irqsub_mask(data->irq, INTMSK_CAM, 3 << 11);
-}
-
-static void
-s3c_irq_cam_unmask(struct irq_data *data)
-{
-        s3c_irqsub_unmask(data->irq, INTMSK_CAM);
-}
-
-static void
-s3c_irq_cam_ack(struct irq_data *data)
-{
-        s3c_irqsub_maskack(data->irq, INTMSK_CAM, 3 << 11);
-}
-
-static struct irq_chip s3c_irq_cam = {
-        .irq_mask       = s3c_irq_cam_mask,
-        .irq_unmask     = s3c_irq_cam_unmask,
-        .irq_ack        = s3c_irq_cam_ack,
-};
-
-static int s3c244x_irq_add(struct device *dev, struct subsys_interface *sif)
-{
-        unsigned int irqno;
-
-        irq_set_chip_and_handler(IRQ_NFCON, &s3c_irq_level_chip,
-                                 handle_level_irq);
-        set_irq_flags(IRQ_NFCON, IRQF_VALID);
-
-        /* add chained handler for camera */
-
-        irq_set_chip_and_handler(IRQ_CAM, &s3c_irq_level_chip,
-                                 handle_level_irq);
-        irq_set_chained_handler(IRQ_CAM, s3c_irq_demux_cam);
-
-        for (irqno = IRQ_S3C2440_CAM_C; irqno <= IRQ_S3C2440_CAM_P; irqno++) {
-                irq_set_chip_and_handler(irqno, &s3c_irq_cam,
-                                         handle_level_irq);
-                set_irq_flags(irqno, IRQF_VALID);
-        }
-
-        return 0;
-}
-
-static struct subsys_interface s3c2440_irq_interface = {
-        .name           = "s3c2440_irq",
-        .subsys         = &s3c2440_subsys,
-        .add_dev        = s3c244x_irq_add,
-};
-
-static int s3c2440_irq_init(void)
-{
-        return subsys_interface_register(&s3c2440_irq_interface);
-}
-
-arch_initcall(s3c2440_irq_init);
-
-static struct subsys_interface s3c2442_irq_interface = {
-        .name           = "s3c2442_irq",
-        .subsys         = &s3c2442_subsys,
-        .add_dev        = s3c244x_irq_add,
-};
-
-
-static int s3c2442_irq_init(void)
-{
-        return subsys_interface_register(&s3c2442_irq_interface);
-}
-
-arch_initcall(s3c2442_irq_init);
diff --git a/arch/arm/mach-s3c24xx/irq.c b/arch/arm/mach-s3c24xx/irq.c
deleted file mode 100644
index cb9f5e011e73..000000000000
--- a/arch/arm/mach-s3c24xx/irq.c
+++ /dev/null
@@ -1,822 +0,0 @@
-/*
- * S3C24XX IRQ handling
- *
- * Copyright (c) 2003-2004 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- * Copyright (c) 2012 Heiko Stuebner <heiko@sntech.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
-*/
-
-#include <linux/init.h>
-#include <linux/slab.h>
-#include <linux/module.h>
-#include <linux/io.h>
-#include <linux/err.h>
-#include <linux/interrupt.h>
-#include <linux/ioport.h>
-#include <linux/device.h>
-#include <linux/irqdomain.h>
-
-#include <asm/mach/irq.h>
-
-#include <mach/regs-irq.h>
-#include <mach/regs-gpio.h>
-
-#include <plat/cpu.h>
-#include <plat/regs-irqtype.h>
-#include <plat/pm.h>
-#include <plat/irq.h>
-
-#define S3C_IRQTYPE_NONE        0
-#define S3C_IRQTYPE_EINT        1
-#define S3C_IRQTYPE_EDGE        2
-#define S3C_IRQTYPE_LEVEL       3
-
-struct s3c_irq_data {
-        unsigned int type;
-        unsigned long parent_irq;
-
-        /* data gets filled during init */
-        struct s3c_irq_intc *intc;
-        unsigned long sub_bits;
-        struct s3c_irq_intc *sub_intc;
-};
-
-/*
- * Sructure holding the controller data
- * @reg_pending         register holding pending irqs
- * @reg_intpnd          special register intpnd in main intc
- * @reg_mask            mask register
- * @domain              irq_domain of the controller
- * @parent              parent controller for ext and sub irqs
- * @irqs                irq-data, always s3c_irq_data[32]
- */
-struct s3c_irq_intc {
-        void __iomem            *reg_pending;
-        void __iomem            *reg_intpnd;
-        void __iomem            *reg_mask;
-        struct irq_domain       *domain;
-        struct s3c_irq_intc     *parent;
-        struct s3c_irq_data     *irqs;
-};
-
-static void s3c_irq_mask(struct irq_data *data)
-{
-        struct s3c_irq_intc *intc = data->domain->host_data;
-        struct s3c_irq_intc *parent_intc = intc->parent;
-        struct s3c_irq_data *irq_data = &intc->irqs[data->hwirq];
-        struct s3c_irq_data *parent_data;
-        unsigned long mask;
-        unsigned int irqno;
-
-        mask = __raw_readl(intc->reg_mask);
-        mask |= (1UL << data->hwirq);
-        __raw_writel(mask, intc->reg_mask);
-
-        if (parent_intc && irq_data->parent_irq) {
-                parent_data = &parent_intc->irqs[irq_data->parent_irq];
-
-                /* check to see if we need to mask the parent IRQ */
-                if ((mask & parent_data->sub_bits) == parent_data->sub_bits) {
-                        irqno = irq_find_mapping(parent_intc->domain,
-                                         irq_data->parent_irq);
-                        s3c_irq_mask(irq_get_irq_data(irqno));
-                }
-        }
-}
-
-static void s3c_irq_unmask(struct irq_data *data)
-{
-        struct s3c_irq_intc *intc = data->domain->host_data;
-        struct s3c_irq_intc *parent_intc = intc->parent;
-        struct s3c_irq_data *irq_data = &intc->irqs[data->hwirq];
-        unsigned long mask;
-        unsigned int irqno;
-
-        mask = __raw_readl(intc->reg_mask);
-        mask &= ~(1UL << data->hwirq);
-        __raw_writel(mask, intc->reg_mask);
-
-        if (parent_intc && irq_data->parent_irq) {
-                irqno = irq_find_mapping(parent_intc->domain,
-                                         irq_data->parent_irq);
-                s3c_irq_unmask(irq_get_irq_data(irqno));
-        }
-}
-
-static inline void s3c_irq_ack(struct irq_data *data)
-{
-        struct s3c_irq_intc *intc = data->domain->host_data;
-        unsigned long bitval = 1UL << data->hwirq;
-
-        __raw_writel(bitval, intc->reg_pending);
-        if (intc->reg_intpnd)
-                __raw_writel(bitval, intc->reg_intpnd);
-}
-
-static int s3c_irqext_type_set(void __iomem *gpcon_reg,
-                               void __iomem *extint_reg,
-                               unsigned long gpcon_offset,
-                               unsigned long extint_offset,
-                               unsigned int type)
-{
-        unsigned long newvalue = 0, value;
-
-        /* Set the GPIO to external interrupt mode */
-        value = __raw_readl(gpcon_reg);
-        value = (value & ~(3 << gpcon_offset)) | (0x02 << gpcon_offset);
-        __raw_writel(value, gpcon_reg);
-
-        /* Set the external interrupt to pointed trigger type */
-        switch (type)
-        {
-                case IRQ_TYPE_NONE:
-                        pr_warn("No edge setting!\n");
-                        break;
-
-                case IRQ_TYPE_EDGE_RISING:
-                        newvalue = S3C2410_EXTINT_RISEEDGE;
-                        break;
-
-                case IRQ_TYPE_EDGE_FALLING:
-                        newvalue = S3C2410_EXTINT_FALLEDGE;
-                        break;
-
-                case IRQ_TYPE_EDGE_BOTH:
-                        newvalue = S3C2410_EXTINT_BOTHEDGE;
-                        break;
-
-                case IRQ_TYPE_LEVEL_LOW:
-                        newvalue = S3C2410_EXTINT_LOWLEV;
-                        break;
-
-                case IRQ_TYPE_LEVEL_HIGH:
-                        newvalue = S3C2410_EXTINT_HILEV;
-                        break;
-
-                default:
-                        pr_err("No such irq type %d", type);
-                        return -EINVAL;
-        }
-
-        value = __raw_readl(extint_reg);
-        value = (value & ~(7 << extint_offset)) | (newvalue << extint_offset);
-        __raw_writel(value, extint_reg);
-
-        return 0;
-}
-
-/* FIXME: make static when it's out of plat-samsung/irq.h */
-int s3c_irqext_type(struct irq_data *data, unsigned int type)
-{
-        void __iomem *extint_reg;
-        void __iomem *gpcon_reg;
-        unsigned long gpcon_offset, extint_offset;
-
-        if ((data->hwirq >= 4) && (data->hwirq <= 7)) {
-                gpcon_reg = S3C2410_GPFCON;
-                extint_reg = S3C24XX_EXTINT0;
-                gpcon_offset = (data->hwirq) * 2;
-                extint_offset = (data->hwirq) * 4;
-        } else if ((data->hwirq >= 8) && (data->hwirq <= 15)) {
-                gpcon_reg = S3C2410_GPGCON;
-                extint_reg = S3C24XX_EXTINT1;
-                gpcon_offset = (data->hwirq - 8) * 2;
-                extint_offset = (data->hwirq - 8) * 4;
-        } else if ((data->hwirq >= 16) && (data->hwirq <= 23)) {
-                gpcon_reg = S3C2410_GPGCON;
-                extint_reg = S3C24XX_EXTINT2;
-                gpcon_offset = (data->hwirq - 8) * 2;
-                extint_offset = (data->hwirq - 16) * 4;
-        } else {
-                return -EINVAL;
-        }
-
-        return s3c_irqext_type_set(gpcon_reg, extint_reg, gpcon_offset,
-                                   extint_offset, type);
-}
-
-static int s3c_irqext0_type(struct irq_data *data, unsigned int type)
-{
-        void __iomem *extint_reg;
-        void __iomem *gpcon_reg;
-        unsigned long gpcon_offset, extint_offset;
-
-        if ((data->hwirq >= 0) && (data->hwirq <= 3)) {
-                gpcon_reg = S3C2410_GPFCON;
-                extint_reg = S3C24XX_EXTINT0;
-                gpcon_offset = (data->hwirq) * 2;
-                extint_offset = (data->hwirq) * 4;
-        } else {
-                return -EINVAL;
-        }
-
-        return s3c_irqext_type_set(gpcon_reg, extint_reg, gpcon_offset,
-                                   extint_offset, type);
-}
-
-struct irq_chip s3c_irq_chip = {
-        .name           = "s3c",
-        .irq_ack        = s3c_irq_ack,
-        .irq_mask       = s3c_irq_mask,
-        .irq_unmask     = s3c_irq_unmask,
-        .irq_set_wake   = s3c_irq_wake
-};
-
-struct irq_chip s3c_irq_level_chip = {
-        .name           = "s3c-level",
-        .irq_mask       = s3c_irq_mask,
-        .irq_unmask     = s3c_irq_unmask,
-        .irq_ack        = s3c_irq_ack,
-};
-
-static struct irq_chip s3c_irqext_chip = {
-        .name           = "s3c-ext",
-        .irq_mask       = s3c_irq_mask,
-        .irq_unmask     = s3c_irq_unmask,
-        .irq_ack        = s3c_irq_ack,
-        .irq_set_type   = s3c_irqext_type,
-        .irq_set_wake   = s3c_irqext_wake
-};
-
-static struct irq_chip s3c_irq_eint0t4 = {
-        .name           = "s3c-ext0",
-        .irq_ack        = s3c_irq_ack,
-        .irq_mask       = s3c_irq_mask,
-        .irq_unmask     = s3c_irq_unmask,
-        .irq_set_wake   = s3c_irq_wake,
-        .irq_set_type   = s3c_irqext0_type,
-};
-
-static void s3c_irq_demux(unsigned int irq, struct irq_desc *desc)
-{
-        struct irq_chip *chip = irq_desc_get_chip(desc);
-        struct s3c_irq_intc *intc = desc->irq_data.domain->host_data;
-        struct s3c_irq_data *irq_data = &intc->irqs[desc->irq_data.hwirq];
-        struct s3c_irq_intc *sub_intc = irq_data->sub_intc;
-        unsigned long src;
-        unsigned long msk;
-        unsigned int n;
-
-        chained_irq_enter(chip, desc);
-
-        src = __raw_readl(sub_intc->reg_pending);
-        msk = __raw_readl(sub_intc->reg_mask);
-
-        src &= ~msk;
-        src &= irq_data->sub_bits;
-
-        while (src) {
-                n = __ffs(src);
-                src &= ~(1 << n);
-                generic_handle_irq(irq_find_mapping(sub_intc->domain, n));
-        }
-
-        chained_irq_exit(chip, desc);
-}
-
-#ifdef CONFIG_FIQ
-/**
- * s3c24xx_set_fiq - set the FIQ routing
- * @irq: IRQ number to route to FIQ on processor.
- * @on: Whether to route @irq to the FIQ, or to remove the FIQ routing.
- *
- * Change the state of the IRQ to FIQ routing depending on @irq and @on. If
- * @on is true, the @irq is checked to see if it can be routed and the
- * interrupt controller updated to route the IRQ. If @on is false, the FIQ
- * routing is cleared, regardless of which @irq is specified.
- */
-int s3c24xx_set_fiq(unsigned int irq, bool on)
-{
-        u32 intmod;
-        unsigned offs;
-
-        if (on) {
-                offs = irq - FIQ_START;
-                if (offs > 31)
-                        return -EINVAL;
-
-                intmod = 1 << offs;
-        } else {
-                intmod = 0;
-        }
-
-        __raw_writel(intmod, S3C2410_INTMOD);
-        return 0;
-}
-
-EXPORT_SYMBOL_GPL(s3c24xx_set_fiq);
-#endif
-
-static int s3c24xx_irq_map(struct irq_domain *h, unsigned int virq,
-                                                        irq_hw_number_t hw)
-{
-        struct s3c_irq_intc *intc = h->host_data;
-        struct s3c_irq_data *irq_data = &intc->irqs[hw];
-        struct s3c_irq_intc *parent_intc;
-        struct s3c_irq_data *parent_irq_data;
-        unsigned int irqno;
-
-        if (!intc) {
-                pr_err("irq-s3c24xx: no controller found for hwirq %lu\n", hw);
-                return -EINVAL;
-        }
-
-        if (!irq_data) {
-                pr_err("irq-s3c24xx: no irq data found for hwirq %lu\n", hw);
-                return -EINVAL;
-        }
-
-        /* attach controller pointer to irq_data */
-        irq_data->intc = intc;
-
-        /* set handler and flags */
-        switch (irq_data->type) {
-        case S3C_IRQTYPE_NONE:
-                return 0;
-        case S3C_IRQTYPE_EINT:
-                if (irq_data->parent_irq)
-                        irq_set_chip_and_handler(virq, &s3c_irqext_chip,
-                                                 handle_edge_irq);
-                else
-                        irq_set_chip_and_handler(virq, &s3c_irq_eint0t4,
-                                                 handle_edge_irq);
-                break;
-        case S3C_IRQTYPE_EDGE:
-                if (irq_data->parent_irq ||
-                    intc->reg_pending == S3C2416_SRCPND2)
-                        irq_set_chip_and_handler(virq, &s3c_irq_level_chip,
-                                                 handle_edge_irq);
-                else
-                        irq_set_chip_and_handler(virq, &s3c_irq_chip,
-                                                 handle_edge_irq);
-                break;
-        case S3C_IRQTYPE_LEVEL:
-                if (irq_data->parent_irq)
-                        irq_set_chip_and_handler(virq, &s3c_irq_level_chip,
-                                                 handle_level_irq);
-                else
-                        irq_set_chip_and_handler(virq, &s3c_irq_chip,
-                                                 handle_level_irq);
-                break;
-        default:
-                pr_err("irq-s3c24xx: unsupported irqtype %d\n", irq_data->type);
-                return -EINVAL;
-        }
-        set_irq_flags(virq, IRQF_VALID);
-
-        if (irq_data->parent_irq) {
-                parent_intc = intc->parent;
-                if (!parent_intc) {
-                        pr_err("irq-s3c24xx: no parent controller found for hwirq %lu\n",
-                               hw);
-                        goto err;
-                }
-
-                parent_irq_data = &parent_intc->irqs[irq_data->parent_irq];
-                if (!irq_data) {
-                        pr_err("irq-s3c24xx: no irq data found for hwirq %lu\n",
-                               hw);
-                        goto err;
-                }
-
-                parent_irq_data->sub_intc = intc;
-                parent_irq_data->sub_bits |= (1UL << hw);
-
-                /* attach the demuxer to the parent irq */
-                irqno = irq_find_mapping(parent_intc->domain,
-                                         irq_data->parent_irq);
-                if (!irqno) {
-                        pr_err("irq-s3c24xx: could not find mapping for parent irq %lu\n",
-                               irq_data->parent_irq);
-                        goto err;
-                }
-                irq_set_chained_handler(irqno, s3c_irq_demux);
-        }
-
-        return 0;
-
-err:
-        set_irq_flags(virq, 0);
-
-        /* the only error can result from bad mapping data*/
-        return -EINVAL;
-}
-
-static struct irq_domain_ops s3c24xx_irq_ops = {
-        .map = s3c24xx_irq_map,
-        .xlate = irq_domain_xlate_twocell,
-};
-
-static void s3c24xx_clear_intc(struct s3c_irq_intc *intc)
-{
-        void __iomem *reg_source;
-        unsigned long pend;
-        unsigned long last;
-        int i;
-
-        /* if intpnd is set, read the next pending irq from there */
-        reg_source = intc->reg_intpnd ? intc->reg_intpnd : intc->reg_pending;
-
-        last = 0;
-        for (i = 0; i < 4; i++) {
-                pend = __raw_readl(reg_source);
-
-                if (pend == 0 || pend == last)
-                        break;
-
-                __raw_writel(pend, intc->reg_pending);
-                if (intc->reg_intpnd)
-                        __raw_writel(pend, intc->reg_intpnd);
-
-                pr_info("irq: clearing pending status %08x\n", (int)pend);
-                last = pend;
-        }
-}
-
-struct s3c_irq_intc *s3c24xx_init_intc(struct device_node *np,
-                                       struct s3c_irq_data *irq_data,
-                                       struct s3c_irq_intc *parent,
-                                       unsigned long address)
-{
-        struct s3c_irq_intc *intc;
-        void __iomem *base = (void *)0xf6000000; /* static mapping */
-        int irq_num;
-        int irq_start;
-        int irq_offset;
-        int ret;
-
-        intc = kzalloc(sizeof(struct s3c_irq_intc), GFP_KERNEL);
-        if (!intc)
-                return ERR_PTR(-ENOMEM);
-
-        intc->irqs = irq_data;
-
-        if (parent)
-                intc->parent = parent;
-
-        /* select the correct data for the controller.
-         * Need to hard code the irq num start and offset
-         * to preserve the static mapping for now
-         */
-        switch (address) {
-        case 0x4a000000:
-                pr_debug("irq: found main intc\n");
-                intc->reg_pending = base;
-                intc->reg_mask = base + 0x08;
-                intc->reg_intpnd = base + 0x10;
-                irq_num = 32;
-                irq_start = S3C2410_IRQ(0);
-                irq_offset = 0;
-                break;
-        case 0x4a000018:
-                pr_debug("irq: found subintc\n");
-                intc->reg_pending = base + 0x18;
-                intc->reg_mask = base + 0x1c;
-                irq_num = 29;
-                irq_start = S3C2410_IRQSUB(0);
-                irq_offset = 0;
-                break;
-        case 0x4a000040:
-                pr_debug("irq: found intc2\n");
-                intc->reg_pending = base + 0x40;
-                intc->reg_mask = base + 0x48;
-                intc->reg_intpnd = base + 0x50;
-                irq_num = 8;
-                irq_start = S3C2416_IRQ(0);
-                irq_offset = 0;
-                break;
-        case 0x560000a4:
-                pr_debug("irq: found eintc\n");
-                base = (void *)0xfd000000;
-
-                intc->reg_mask = base + 0xa4;
-                intc->reg_pending = base + 0x08;
-                irq_num = 20;
-                irq_start = S3C2410_IRQ(32);
-                irq_offset = 4;
-                break;
-        default:
-                pr_err("irq: unsupported controller address\n");
-                ret = -EINVAL;
-                goto err;
-        }
-
-        /* now that all the data is complete, init the irq-domain */
-        s3c24xx_clear_intc(intc);
-        intc->domain = irq_domain_add_legacy(np, irq_num, irq_start,
-                                             irq_offset, &s3c24xx_irq_ops,
-                                             intc);
-        if (!intc->domain) {
-                pr_err("irq: could not create irq-domain\n");
-                ret = -EINVAL;
-                goto err;
-        }
-
-        return intc;
-
-err:
-        kfree(intc);
-        return ERR_PTR(ret);
-}
-
-/* s3c24xx_init_irq
- *
- * Initialise S3C2410 IRQ system
-*/
-
-static struct s3c_irq_data init_base[32] = {
-        { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */
-        { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */
-        { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */
-        { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */
-        { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
-        { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
-        { .type = S3C_IRQTYPE_NONE, }, /* reserved */
-        { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
-        { .type = S3C_IRQTYPE_EDGE, }, /* TICK */
-        { .type = S3C_IRQTYPE_EDGE, }, /* WDT */
-        { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
-        { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
-        { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
-        { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
-        { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
-        { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
-        { .type = S3C_IRQTYPE_EDGE, }, /* LCD */
-        { .type = S3C_IRQTYPE_EDGE, }, /* DMA0 */
-        { .type = S3C_IRQTYPE_EDGE, }, /* DMA1 */
-        { .type = S3C_IRQTYPE_EDGE, }, /* DMA2 */
-        { .type = S3C_IRQTYPE_EDGE, }, /* DMA3 */
-        { .type = S3C_IRQTYPE_EDGE, }, /* SDI */
-        { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
-        { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
-        { .type = S3C_IRQTYPE_NONE, }, /* reserved */
-        { .type = S3C_IRQTYPE_EDGE, }, /* USBD */
-        { .type = S3C_IRQTYPE_EDGE, }, /* USBH */
-        { .type = S3C_IRQTYPE_EDGE, }, /* IIC */
-        { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
-        { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */
-        { .type = S3C_IRQTYPE_EDGE, }, /* RTC */
-        { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
-};
-
-static struct s3c_irq_data init_eint[32] = {
-        { .type = S3C_IRQTYPE_NONE, }, /* reserved */
-        { .type = S3C_IRQTYPE_NONE, }, /* reserved */
-        { .type = S3C_IRQTYPE_NONE, }, /* reserved */
-        { .type = S3C_IRQTYPE_NONE, }, /* reserved */
-        { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT4 */
-        { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT5 */
-        { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT6 */
-        { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT7 */
-        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT8 */
-        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT9 */
-        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT10 */
-        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT11 */
-        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT12 */
-        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT13 */
-        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT14 */
-        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT15 */
-        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT16 */
-        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT17 */
-        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT18 */
-        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT19 */
-        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT20 */
-        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT21 */
-        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT22 */
-        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT23 */
-};
-
-static struct s3c_irq_data init_subint[32] = {
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
-        { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
-        { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
-};
-
-void __init s3c24xx_init_irq(void)
-{
-        struct s3c_irq_intc *main_intc;
-
-#ifdef CONFIG_FIQ
-        init_FIQ(FIQ_START);
-#endif
-
-        main_intc = s3c24xx_init_intc(NULL, &init_base[0], NULL, 0x4a000000);
-        if (IS_ERR(main_intc)) {
-                pr_err("irq: could not create main interrupt controller\n");
-                return;
-        }
-
-        s3c24xx_init_intc(NULL, &init_subint[0], main_intc, 0x4a000018);
-        s3c24xx_init_intc(NULL, &init_eint[0], main_intc, 0x560000a4);
-}
-
-#ifdef CONFIG_CPU_S3C2416
-static struct s3c_irq_data init_s3c2416base[32] = {
-        { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */
-        { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */
-        { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */
-        { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */
-        { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
-        { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
-        { .type = S3C_IRQTYPE_NONE, }, /* reserved */
-        { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
-        { .type = S3C_IRQTYPE_EDGE, }, /* TICK */
-        { .type = S3C_IRQTYPE_LEVEL, }, /* WDT/AC97 */
-        { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
-        { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
-        { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
-        { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
-        { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
-        { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
-        { .type = S3C_IRQTYPE_LEVEL, }, /* LCD */
-        { .type = S3C_IRQTYPE_LEVEL, }, /* DMA */
-        { .type = S3C_IRQTYPE_LEVEL, }, /* UART3 */
-        { .type = S3C_IRQTYPE_NONE, }, /* reserved */
-        { .type = S3C_IRQTYPE_EDGE, }, /* SDI1 */
-        { .type = S3C_IRQTYPE_EDGE, }, /* SDI0 */
-        { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
-        { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
-        { .type = S3C_IRQTYPE_EDGE, }, /* NAND */
-        { .type = S3C_IRQTYPE_EDGE, }, /* USBD */
-        { .type = S3C_IRQTYPE_EDGE, }, /* USBH */
-        { .type = S3C_IRQTYPE_EDGE, }, /* IIC */
-        { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
-        { .type = S3C_IRQTYPE_NONE, },
-        { .type = S3C_IRQTYPE_EDGE, }, /* RTC */
-        { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
-};
-
-static struct s3c_irq_data init_s3c2416subint[32] = {
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
-        { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
-        { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
-        { .type = S3C_IRQTYPE_NONE }, /* reserved */
-        { .type = S3C_IRQTYPE_NONE }, /* reserved */
-        { .type = S3C_IRQTYPE_NONE }, /* reserved */
-        { .type = S3C_IRQTYPE_NONE }, /* reserved */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD2 */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD3 */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD4 */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA0 */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA1 */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA2 */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA3 */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA4 */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA5 */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-RX */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-TX */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-ERR */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* WDT */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* AC97 */
-};
-
-static struct s3c_irq_data init_s3c2416_second[32] = {
-        { .type = S3C_IRQTYPE_EDGE }, /* 2D */
-        { .type = S3C_IRQTYPE_EDGE }, /* IIC1 */
-        { .type = S3C_IRQTYPE_NONE }, /* reserved */
-        { .type = S3C_IRQTYPE_NONE }, /* reserved */
-        { .type = S3C_IRQTYPE_EDGE }, /* PCM0 */
-        { .type = S3C_IRQTYPE_EDGE }, /* PCM1 */
-        { .type = S3C_IRQTYPE_EDGE }, /* I2S0 */
-        { .type = S3C_IRQTYPE_EDGE }, /* I2S1 */
-};
-
-void __init s3c2416_init_irq(void)
-{
-        struct s3c_irq_intc *main_intc;
-
-        pr_info("S3C2416: IRQ Support\n");
-
-#ifdef CONFIG_FIQ
-        init_FIQ(FIQ_START);
-#endif
-
-        main_intc = s3c24xx_init_intc(NULL, &init_s3c2416base[0], NULL, 0x4a000000);
-        if (IS_ERR(main_intc)) {
-                pr_err("irq: could not create main interrupt controller\n");
-                return;
-        }
-
-        s3c24xx_init_intc(NULL, &init_eint[0], main_intc, 0x560000a4);
-        s3c24xx_init_intc(NULL, &init_s3c2416subint[0], main_intc, 0x4a000018);
-
-        s3c24xx_init_intc(NULL, &init_s3c2416_second[0], NULL, 0x4a000040);
-}
-
-#endif
-
-#ifdef CONFIG_CPU_S3C2443
-static struct s3c_irq_data init_s3c2443base[32] = {
-        { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */
-        { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */
-        { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */
-        { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */
-        { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
-        { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
-        { .type = S3C_IRQTYPE_LEVEL, }, /* CAM */
-        { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
-        { .type = S3C_IRQTYPE_EDGE, }, /* TICK */
-        { .type = S3C_IRQTYPE_LEVEL, }, /* WDT/AC97 */
-        { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
-        { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
-        { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
-        { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
-        { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
-        { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
-        { .type = S3C_IRQTYPE_LEVEL, }, /* LCD */
-        { .type = S3C_IRQTYPE_LEVEL, }, /* DMA */
-        { .type = S3C_IRQTYPE_LEVEL, }, /* UART3 */
-        { .type = S3C_IRQTYPE_EDGE, }, /* CFON */
-        { .type = S3C_IRQTYPE_EDGE, }, /* SDI1 */
-        { .type = S3C_IRQTYPE_EDGE, }, /* SDI0 */
-        { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
-        { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
-        { .type = S3C_IRQTYPE_EDGE, }, /* NAND */
-        { .type = S3C_IRQTYPE_EDGE, }, /* USBD */
-        { .type = S3C_IRQTYPE_EDGE, }, /* USBH */
-        { .type = S3C_IRQTYPE_EDGE, }, /* IIC */
-        { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
-        { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */
-        { .type = S3C_IRQTYPE_EDGE, }, /* RTC */
-        { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
-};
-
-
-static struct s3c_irq_data init_s3c2443subint[32] = {
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
-        { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
-        { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_C */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_P */
-        { .type = S3C_IRQTYPE_NONE }, /* reserved */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD1 */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD2 */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD3 */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD4 */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA0 */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA1 */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA2 */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA3 */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA4 */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA5 */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-RX */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-TX */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-ERR */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* WDT */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* AC97 */
-};
-
-void __init s3c2443_init_irq(void)
-{
-        struct s3c_irq_intc *main_intc;
-
-        pr_info("S3C2443: IRQ Support\n");
-
-#ifdef CONFIG_FIQ
-        init_FIQ(FIQ_START);
-#endif
-
-        main_intc = s3c24xx_init_intc(NULL, &init_s3c2443base[0], NULL, 0x4a000000);
-        if (IS_ERR(main_intc)) {
-                pr_err("irq: could not create main interrupt controller\n");
-                return;
-        }
-
-        s3c24xx_init_intc(NULL, &init_eint[0], main_intc, 0x560000a4);
-        s3c24xx_init_intc(NULL, &init_s3c2443subint[0], main_intc, 0x4a000018);
-}
-#endif
diff --git a/arch/arm/mach-s3c24xx/mach-amlm5900.c b/arch/arm/mach-s3c24xx/mach-amlm5900.c
index 0e0279e79150..e27b5c91b3db 100644
--- a/arch/arm/mach-s3c24xx/mach-amlm5900.c
+++ b/arch/arm/mach-s3c24xx/mach-amlm5900.c
@@ -63,6 +63,8 @@
 #include <linux/mtd/map.h>
 #include <linux/mtd/physmap.h>
 
+#include <plat/samsung-time.h>
+
 #include "common.h"
 
 static struct resource amlm5900_nor_resource =
@@ -160,6 +162,7 @@ static void __init amlm5900_map_io(void)
         s3c24xx_init_io(amlm5900_iodesc, ARRAY_SIZE(amlm5900_iodesc));
         s3c24xx_init_clocks(0);
         s3c24xx_init_uarts(amlm5900_uartcfgs, ARRAY_SIZE(amlm5900_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 #ifdef CONFIG_FB_S3C2410
@@ -235,8 +238,8 @@ static void __init amlm5900_init(void)
 MACHINE_START(AML_M5900, "AML_M5900")
         .atag_offset    = 0x100,
         .map_io         = amlm5900_map_io,
-        .init_irq       = s3c24xx_init_irq,
+        .init_irq       = s3c2410_init_irq,
         .init_machine   = amlm5900_init,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c2410_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-anubis.c b/arch/arm/mach-s3c24xx/mach-anubis.c
index bb595f15ce36..c1fb6c37867f 100644
--- a/arch/arm/mach-s3c24xx/mach-anubis.c
+++ b/arch/arm/mach-s3c24xx/mach-anubis.c
@@ -49,6 +49,7 @@
 #include <plat/devs.h>
 #include <plat/cpu.h>
 #include <linux/platform_data/asoc-s3c24xx_simtec.h>
+#include <plat/samsung-time.h>
 
 #include "anubis.h"
 #include "common.h"
@@ -410,6 +411,7 @@ static void __init anubis_map_io(void)
         s3c24xx_init_io(anubis_iodesc, ARRAY_SIZE(anubis_iodesc));
         s3c24xx_init_clocks(0);
         s3c24xx_init_uarts(anubis_uartcfgs, ARRAY_SIZE(anubis_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 
         /* check for the newer revision boards with large page nand */
 
@@ -443,7 +445,7 @@ MACHINE_START(ANUBIS, "Simtec-Anubis")
         .atag_offset    = 0x100,
         .map_io         = anubis_map_io,
         .init_machine   = anubis_init,
-        .init_irq       = s3c24xx_init_irq,
-        .init_time      = s3c24xx_timer_init,
+        .init_irq       = s3c2440_init_irq,
+        .init_time      = samsung_timer_init,
         .restart        = s3c244x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-at2440evb.c b/arch/arm/mach-s3c24xx/mach-at2440evb.c
index b4bc60c78ebb..6dfeeb7ef469 100644
--- a/arch/arm/mach-s3c24xx/mach-at2440evb.c
+++ b/arch/arm/mach-s3c24xx/mach-at2440evb.c
@@ -48,6 +48,7 @@
 #include <plat/devs.h>
 #include <plat/cpu.h>
 #include <linux/platform_data/mmc-s3cmci.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
 
@@ -192,6 +193,7 @@ static void __init at2440evb_map_io(void)
         s3c24xx_init_io(at2440evb_iodesc, ARRAY_SIZE(at2440evb_iodesc));
         s3c24xx_init_clocks(16934400);
         s3c24xx_init_uarts(at2440evb_uartcfgs, ARRAY_SIZE(at2440evb_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 static void __init at2440evb_init(void)
@@ -209,7 +211,7 @@ MACHINE_START(AT2440EVB, "AT2440EVB")
         .atag_offset    = 0x100,
         .map_io         = at2440evb_map_io,
         .init_machine   = at2440evb_init,
-        .init_irq       = s3c24xx_init_irq,
-        .init_time      = s3c24xx_timer_init,
+        .init_irq       = s3c2440_init_irq,
+        .init_time      = samsung_timer_init,
         .restart        = s3c244x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-bast.c b/arch/arm/mach-s3c24xx/mach-bast.c
index ca6618081041..22d6ae926d91 100644
--- a/arch/arm/mach-s3c24xx/mach-bast.c
+++ b/arch/arm/mach-s3c24xx/mach-bast.c
@@ -55,6 +55,7 @@
 #include <plat/devs.h>
 #include <plat/gpio-cfg.h>
 #include <plat/regs-serial.h>
+#include <plat/samsung-time.h>
 
 #include "bast.h"
 #include "common.h"
@@ -576,6 +577,7 @@ static void __init bast_map_io(void)
         s3c24xx_init_io(bast_iodesc, ARRAY_SIZE(bast_iodesc));
         s3c24xx_init_clocks(0);
         s3c24xx_init_uarts(bast_uartcfgs, ARRAY_SIZE(bast_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 static void __init bast_init(void)
@@ -603,8 +605,8 @@ MACHINE_START(BAST, "Simtec-BAST")
         /* Maintainer: Ben Dooks <ben@simtec.co.uk> */
         .atag_offset    = 0x100,
         .map_io         = bast_map_io,
-        .init_irq       = s3c24xx_init_irq,
+        .init_irq       = s3c2410_init_irq,
         .init_machine   = bast_init,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c2410_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-gta02.c b/arch/arm/mach-s3c24xx/mach-gta02.c
index a25e8c5a7b4c..13d8d073675a 100644
--- a/arch/arm/mach-s3c24xx/mach-gta02.c
+++ b/arch/arm/mach-s3c24xx/mach-gta02.c
@@ -81,6 +81,7 @@
 #include <plat/gpio-cfg.h>
 #include <plat/pm.h>
 #include <plat/regs-serial.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
 #include "gta02.h"
@@ -501,6 +502,7 @@ static void __init gta02_map_io(void)
         s3c24xx_init_io(gta02_iodesc, ARRAY_SIZE(gta02_iodesc));
         s3c24xx_init_clocks(12000000);
         s3c24xx_init_uarts(gta02_uartcfgs, ARRAY_SIZE(gta02_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 
@@ -587,8 +589,8 @@ MACHINE_START(NEO1973_GTA02, "GTA02")
         /* Maintainer: Nelson Castillo <arhuaco@freaks-unidos.net> */
         .atag_offset    = 0x100,
         .map_io         = gta02_map_io,
-        .init_irq       = s3c24xx_init_irq,
+        .init_irq       = s3c2442_init_irq,
         .init_machine   = gta02_machine_init,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c244x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-h1940.c b/arch/arm/mach-s3c24xx/mach-h1940.c
index 79bc0830d740..af4334d6b4d5 100644
--- a/arch/arm/mach-s3c24xx/mach-h1940.c
+++ b/arch/arm/mach-s3c24xx/mach-h1940.c
@@ -62,7 +62,7 @@
 #include <plat/pll.h>
 #include <plat/pm.h>
 #include <plat/regs-serial.h>
-
+#include <plat/samsung-time.h>
 
 #include "common.h"
 #include "h1940.h"
@@ -646,6 +646,7 @@ static void __init h1940_map_io(void)
         s3c24xx_init_io(h1940_iodesc, ARRAY_SIZE(h1940_iodesc));
         s3c24xx_init_clocks(0);
         s3c24xx_init_uarts(h1940_uartcfgs, ARRAY_SIZE(h1940_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 
         /* setup PM */
 
@@ -666,11 +667,6 @@ static void __init h1940_reserve(void)
         memblock_reserve(0x30081000, 0x1000);
 }
 
-static void __init h1940_init_irq(void)
-{
-        s3c24xx_init_irq();
-}
-
 static void __init h1940_init(void)
 {
         u32 tmp;
@@ -739,8 +735,8 @@ MACHINE_START(H1940, "IPAQ-H1940")
         .atag_offset    = 0x100,
         .map_io         = h1940_map_io,
         .reserve        = h1940_reserve,
-        .init_irq       = h1940_init_irq,
+        .init_irq       = s3c2410_init_irq,
         .init_machine   = h1940_init,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c2410_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-jive.c b/arch/arm/mach-s3c24xx/mach-jive.c
index 54e83c1f780c..a45fcd8ccf79 100644
--- a/arch/arm/mach-s3c24xx/mach-jive.c
+++ b/arch/arm/mach-s3c24xx/mach-jive.c
@@ -46,14 +46,15 @@
 #include <linux/mtd/nand_ecc.h>
 #include <linux/mtd/partitions.h>
 
-#include <plat/s3c2412.h>
 #include <plat/gpio-cfg.h>
 #include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
 #include <plat/pm.h>
 #include <linux/platform_data/usb-s3c2410_udc.h>
+#include <plat/samsung-time.h>
 
+#include "common.h"
 #include "s3c2412-power.h"
 
 static struct map_desc jive_iodesc[] __initdata = {
@@ -506,6 +507,7 @@ static void __init jive_map_io(void)
         s3c24xx_init_io(jive_iodesc, ARRAY_SIZE(jive_iodesc));
         s3c24xx_init_clocks(12000000);
         s3c24xx_init_uarts(jive_uartcfgs, ARRAY_SIZE(jive_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 static void jive_power_off(void)
@@ -658,9 +660,9 @@ MACHINE_START(JIVE, "JIVE")
         /* Maintainer: Ben Dooks <ben-linux@fluff.org> */
         .atag_offset    = 0x100,
 
-        .init_irq       = s3c24xx_init_irq,
+        .init_irq       = s3c2412_init_irq,
         .map_io         = jive_map_io,
         .init_machine   = jive_machine_init,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c2412_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-mini2440.c b/arch/arm/mach-s3c24xx/mach-mini2440.c
index 2865e5919f2c..a83db46320bc 100644
--- a/arch/arm/mach-s3c24xx/mach-mini2440.c
+++ b/arch/arm/mach-s3c24xx/mach-mini2440.c
@@ -56,6 +56,7 @@
 #include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
+#include <plat/samsung-time.h>
 
 #include <sound/s3c24xx_uda134x.h>
 
@@ -525,6 +526,7 @@ static void __init mini2440_map_io(void)
         s3c24xx_init_io(mini2440_iodesc, ARRAY_SIZE(mini2440_iodesc));
         s3c24xx_init_clocks(12000000);
         s3c24xx_init_uarts(mini2440_uartcfgs, ARRAY_SIZE(mini2440_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 /*
@@ -686,7 +688,7 @@ MACHINE_START(MINI2440, "MINI2440")
         .atag_offset    = 0x100,
         .map_io         = mini2440_map_io,
         .init_machine   = mini2440_init,
-        .init_irq       = s3c24xx_init_irq,
-        .init_time      = s3c24xx_timer_init,
+        .init_irq       = s3c2440_init_irq,
+        .init_time      = samsung_timer_init,
         .restart        = s3c244x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-n30.c b/arch/arm/mach-s3c24xx/mach-n30.c
index d9d04b240295..2cb46c37c920 100644
--- a/arch/arm/mach-s3c24xx/mach-n30.c
+++ b/arch/arm/mach-s3c24xx/mach-n30.c
@@ -48,8 +48,8 @@
 #include <plat/cpu.h>
 #include <plat/devs.h>
 #include <linux/platform_data/mmc-s3cmci.h>
-#include <plat/s3c2410.h>
 #include <linux/platform_data/usb-s3c2410_udc.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
 
@@ -536,6 +536,7 @@ static void __init n30_map_io(void)
         n30_hwinit();
         s3c24xx_init_clocks(0);
         s3c24xx_init_uarts(n30_uartcfgs, ARRAY_SIZE(n30_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 /* GPB3 is the line that controls the pull-up for the USB D+ line */
@@ -589,9 +590,9 @@ MACHINE_START(N30, "Acer-N30")
                                 Ben Dooks <ben-linux@fluff.org>
         */
         .atag_offset    = 0x100,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .init_machine   = n30_init,
-        .init_irq       = s3c24xx_init_irq,
+        .init_irq       = s3c2410_init_irq,
         .map_io         = n30_map_io,
         .restart        = s3c2410_restart,
 MACHINE_END
@@ -600,9 +601,9 @@ MACHINE_START(N35, "Acer-N35")
         /* Maintainer: Christer Weinigel <christer@weinigel.se>
         */
         .atag_offset    = 0x100,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .init_machine   = n30_init,
-        .init_irq       = s3c24xx_init_irq,
+        .init_irq       = s3c2410_init_irq,
         .map_io         = n30_map_io,
         .restart        = s3c2410_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-nexcoder.c b/arch/arm/mach-s3c24xx/mach-nexcoder.c
index a454e2461860..01f4354206f9 100644
--- a/arch/arm/mach-s3c24xx/mach-nexcoder.c
+++ b/arch/arm/mach-s3c24xx/mach-nexcoder.c
@@ -41,11 +41,10 @@
 #include <linux/platform_data/i2c-s3c2410.h>
 
 #include <plat/gpio-cfg.h>
-#include <plat/s3c2410.h>
-#include <plat/s3c244x.h>
 #include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
 
@@ -137,6 +136,7 @@ static void __init nexcoder_map_io(void)
         s3c24xx_init_io(nexcoder_iodesc, ARRAY_SIZE(nexcoder_iodesc));
         s3c24xx_init_clocks(0);
         s3c24xx_init_uarts(nexcoder_uartcfgs, ARRAY_SIZE(nexcoder_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 
         nexcoder_sensorboard_init();
 }
@@ -152,7 +152,7 @@ MACHINE_START(NEXCODER_2440, "NexVision - Nexcoder 2440")
         .atag_offset    = 0x100,
         .map_io         = nexcoder_map_io,
         .init_machine   = nexcoder_init,
-        .init_irq       = s3c24xx_init_irq,
-        .init_time      = s3c24xx_timer_init,
+        .init_irq       = s3c2440_init_irq,
+        .init_time      = samsung_timer_init,
         .restart        = s3c244x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-osiris.c b/arch/arm/mach-s3c24xx/mach-osiris.c
index ae2cbdf3e3ca..58d6fbe5bf1f 100644
--- a/arch/arm/mach-s3c24xx/mach-osiris.c
+++ b/arch/arm/mach-s3c24xx/mach-osiris.c
@@ -45,6 +45,7 @@
 #include <plat/devs.h>
 #include <plat/gpio-cfg.h>
 #include <plat/regs-serial.h>
+#include <plat/samsung-time.h>
 
 #include <mach/hardware.h>
 #include <mach/regs-gpio.h>
@@ -384,6 +385,7 @@ static void __init osiris_map_io(void)
         s3c24xx_init_io(osiris_iodesc, ARRAY_SIZE(osiris_iodesc));
         s3c24xx_init_clocks(0);
         s3c24xx_init_uarts(osiris_uartcfgs, ARRAY_SIZE(osiris_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 
         /* check for the newer revision boards with large page nand */
 
@@ -424,8 +426,8 @@ MACHINE_START(OSIRIS, "Simtec-OSIRIS")
         /* Maintainer: Ben Dooks <ben@simtec.co.uk> */
         .atag_offset    = 0x100,
         .map_io         = osiris_map_io,
-        .init_irq       = s3c24xx_init_irq,
+        .init_irq       = s3c2440_init_irq,
         .init_machine   = osiris_init,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c244x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-otom.c b/arch/arm/mach-s3c24xx/mach-otom.c
index 40a47d6c6a85..7e16b0740ec1 100644
--- a/arch/arm/mach-s3c24xx/mach-otom.c
+++ b/arch/arm/mach-s3c24xx/mach-otom.c
@@ -33,7 +33,7 @@
 #include <plat/cpu.h>
 #include <plat/devs.h>
 #include <plat/regs-serial.h>
-#include <plat/s3c2410.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
 #include "otom.h"
@@ -102,6 +102,7 @@ static void __init otom11_map_io(void)
         s3c24xx_init_io(otom11_iodesc, ARRAY_SIZE(otom11_iodesc));
         s3c24xx_init_clocks(0);
         s3c24xx_init_uarts(otom11_uartcfgs, ARRAY_SIZE(otom11_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 static void __init otom11_init(void)
@@ -115,7 +116,7 @@ MACHINE_START(OTOM, "Nex Vision - Otom 1.1")
         .atag_offset    = 0x100,
         .map_io         = otom11_map_io,
         .init_machine   = otom11_init,
-        .init_irq       = s3c24xx_init_irq,
-        .init_time      = s3c24xx_timer_init,
+        .init_irq       = s3c2410_init_irq,
+        .init_time      = samsung_timer_init,
         .restart        = s3c2410_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-qt2410.c b/arch/arm/mach-s3c24xx/mach-qt2410.c
index 56175f0941b1..f8feaeadb55a 100644
--- a/arch/arm/mach-s3c24xx/mach-qt2410.c
+++ b/arch/arm/mach-s3c24xx/mach-qt2410.c
@@ -55,13 +55,14 @@
 #include <linux/platform_data/usb-s3c2410_udc.h>
 #include <linux/platform_data/i2c-s3c2410.h>
 
-#include <plat/common-smdk.h>
 #include <plat/gpio-cfg.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
 #include <plat/pm.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
+#include "common-smdk.h"
 
 static struct map_desc qt2410_iodesc[] __initdata = {
         { 0xe0000000, __phys_to_pfn(S3C2410_CS3+0x01000000), SZ_1M, MT_DEVICE }
@@ -304,6 +305,7 @@ static void __init qt2410_map_io(void)
         s3c24xx_init_io(qt2410_iodesc, ARRAY_SIZE(qt2410_iodesc));
         s3c24xx_init_clocks(12*1000*1000);
         s3c24xx_init_uarts(smdk2410_uartcfgs, ARRAY_SIZE(smdk2410_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 static void __init qt2410_machine_init(void)
@@ -341,8 +343,8 @@ static void __init qt2410_machine_init(void)
 MACHINE_START(QT2410, "QT2410")
         .atag_offset    = 0x100,
         .map_io         = qt2410_map_io,
-        .init_irq       = s3c24xx_init_irq,
+        .init_irq       = s3c2410_init_irq,
         .init_machine   = qt2410_machine_init,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c2410_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-rx1950.c b/arch/arm/mach-s3c24xx/mach-rx1950.c
index 1f9ba2ae5288..e4d67a33ebee 100644
--- a/arch/arm/mach-s3c24xx/mach-rx1950.c
+++ b/arch/arm/mach-s3c24xx/mach-rx1950.c
@@ -58,6 +58,7 @@
 #include <plat/pm.h>
 #include <plat/regs-iic.h>
 #include <plat/regs-serial.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
 #include "h1940.h"
@@ -741,6 +742,7 @@ static void __init rx1950_map_io(void)
         s3c24xx_init_io(rx1950_iodesc, ARRAY_SIZE(rx1950_iodesc));
         s3c24xx_init_clocks(16934000);
         s3c24xx_init_uarts(rx1950_uartcfgs, ARRAY_SIZE(rx1950_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 
         /* setup PM */
 
@@ -811,8 +813,8 @@ MACHINE_START(RX1950, "HP iPAQ RX1950")
         .atag_offset = 0x100,
         .map_io = rx1950_map_io,
         .reserve        = rx1950_reserve,
-        .init_irq = s3c24xx_init_irq,
+        .init_irq       = s3c2442_init_irq,
         .init_machine = rx1950_init_machine,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c244x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-rx3715.c b/arch/arm/mach-s3c24xx/mach-rx3715.c
index f20418a2fb1b..3bc6231d0a1f 100644
--- a/arch/arm/mach-s3c24xx/mach-rx3715.c
+++ b/arch/arm/mach-s3c24xx/mach-rx3715.c
@@ -49,6 +49,7 @@
 #include <plat/devs.h>
 #include <plat/pm.h>
 #include <plat/regs-serial.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
 #include "h1940.h"
@@ -179,6 +180,7 @@ static void __init rx3715_map_io(void)
         s3c24xx_init_io(rx3715_iodesc, ARRAY_SIZE(rx3715_iodesc));
         s3c24xx_init_clocks(16934000);
         s3c24xx_init_uarts(rx3715_uartcfgs, ARRAY_SIZE(rx3715_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 /* H1940 and RX3715 need to reserve this for suspend */
@@ -188,11 +190,6 @@ static void __init rx3715_reserve(void)
         memblock_reserve(0x30081000, 0x1000);
 }
 
-static void __init rx3715_init_irq(void)
-{
-        s3c24xx_init_irq();
-}
-
 static void __init rx3715_init_machine(void)
 {
 #ifdef CONFIG_PM_H1940
@@ -210,8 +207,8 @@ MACHINE_START(RX3715, "IPAQ-RX3715")
         .atag_offset    = 0x100,
         .map_io         = rx3715_map_io,
         .reserve        = rx3715_reserve,
-        .init_irq       = rx3715_init_irq,
+        .init_irq       = s3c2440_init_irq,
         .init_machine   = rx3715_init_machine,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c244x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-smdk2410.c b/arch/arm/mach-s3c24xx/mach-smdk2410.c
index e184bfa9613a..a773789e4f38 100644
--- a/arch/arm/mach-s3c24xx/mach-smdk2410.c
+++ b/arch/arm/mach-s3c24xx/mach-smdk2410.c
@@ -51,10 +51,10 @@
 
 #include <plat/devs.h>
 #include <plat/cpu.h>
-
-#include <plat/common-smdk.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
+#include "common-smdk.h"
 
 static struct map_desc smdk2410_iodesc[] __initdata = {
   /* nothing here yet */
@@ -101,6 +101,7 @@ static void __init smdk2410_map_io(void)
         s3c24xx_init_io(smdk2410_iodesc, ARRAY_SIZE(smdk2410_iodesc));
         s3c24xx_init_clocks(0);
         s3c24xx_init_uarts(smdk2410_uartcfgs, ARRAY_SIZE(smdk2410_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 static void __init smdk2410_init(void)
@@ -115,8 +116,8 @@ MACHINE_START(SMDK2410, "SMDK2410") /* @TODO: request a new identifier and switc
         /* Maintainer: Jonas Dietsche */
         .atag_offset    = 0x100,
         .map_io         = smdk2410_map_io,
-        .init_irq       = s3c24xx_init_irq,
+        .init_irq       = s3c2410_init_irq,
         .init_machine   = smdk2410_init,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c2410_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-smdk2413.c b/arch/arm/mach-s3c24xx/mach-smdk2413.c
index 86d7847c9d45..8146e920f10d 100644
--- a/arch/arm/mach-s3c24xx/mach-smdk2413.c
+++ b/arch/arm/mach-s3c24xx/mach-smdk2413.c
@@ -41,13 +41,13 @@
 #include <linux/platform_data/i2c-s3c2410.h>
 #include <mach/fb.h>
 
-#include <plat/s3c2410.h>
-#include <plat/s3c2412.h>
 #include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
+#include <plat/samsung-time.h>
 
-#include <plat/common-smdk.h>
+#include "common.h"
+#include "common-smdk.h"
 
 static struct map_desc smdk2413_iodesc[] __initdata = {
 };
@@ -106,6 +106,7 @@ static void __init smdk2413_map_io(void)
         s3c24xx_init_io(smdk2413_iodesc, ARRAY_SIZE(smdk2413_iodesc));
         s3c24xx_init_clocks(12000000);
         s3c24xx_init_uarts(smdk2413_uartcfgs, ARRAY_SIZE(smdk2413_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 static void __init smdk2413_machine_init(void)
@@ -129,10 +130,10 @@ MACHINE_START(S3C2413, "S3C2413")
         .atag_offset    = 0x100,
 
         .fixup          = smdk2413_fixup,
-        .init_irq       = s3c24xx_init_irq,
+        .init_irq       = s3c2412_init_irq,
         .map_io         = smdk2413_map_io,
         .init_machine   = smdk2413_machine_init,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c2412_restart,
 MACHINE_END
 
@@ -141,10 +142,10 @@ MACHINE_START(SMDK2412, "SMDK2412")
         .atag_offset    = 0x100,
 
         .fixup          = smdk2413_fixup,
-        .init_irq       = s3c24xx_init_irq,
+        .init_irq       = s3c2412_init_irq,
         .map_io         = smdk2413_map_io,
         .init_machine   = smdk2413_machine_init,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c2412_restart,
 MACHINE_END
 
@@ -153,9 +154,9 @@ MACHINE_START(SMDK2413, "SMDK2413")
         .atag_offset    = 0x100,
 
         .fixup          = smdk2413_fixup,
-        .init_irq       = s3c24xx_init_irq,
+        .init_irq       = s3c2412_init_irq,
         .map_io         = smdk2413_map_io,
         .init_machine   = smdk2413_machine_init,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c2412_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-smdk2416.c b/arch/arm/mach-s3c24xx/mach-smdk2416.c
index ebb2e61f3d07..cb46847c66b4 100644
--- a/arch/arm/mach-s3c24xx/mach-smdk2416.c
+++ b/arch/arm/mach-s3c24xx/mach-smdk2416.c
@@ -42,7 +42,6 @@
 #include <linux/platform_data/leds-s3c24xx.h>
 #include <linux/platform_data/i2c-s3c2410.h>
 
-#include <plat/s3c2416.h>
 #include <plat/gpio-cfg.h>
 #include <plat/clock.h>
 #include <plat/devs.h>
@@ -51,10 +50,12 @@
 #include <plat/sdhci.h>
 #include <linux/platform_data/usb-s3c2410_udc.h>
 #include <linux/platform_data/s3c-hsudc.h>
+#include <plat/samsung-time.h>
 
 #include <plat/fb.h>
 
-#include <plat/common-smdk.h>
+#include "common.h"
+#include "common-smdk.h"
 
 static struct map_desc smdk2416_iodesc[] __initdata = {
         /* ISA IO Space map (memory space selected by A24) */
@@ -221,6 +222,7 @@ static void __init smdk2416_map_io(void)
         s3c24xx_init_io(smdk2416_iodesc, ARRAY_SIZE(smdk2416_iodesc));
         s3c24xx_init_clocks(12000000);
         s3c24xx_init_uarts(smdk2416_uartcfgs, ARRAY_SIZE(smdk2416_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 static void __init smdk2416_machine_init(void)
@@ -253,6 +255,6 @@ MACHINE_START(SMDK2416, "SMDK2416")
         .init_irq       = s3c2416_init_irq,
         .map_io         = smdk2416_map_io,
         .init_machine   = smdk2416_machine_init,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c2416_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-smdk2440.c b/arch/arm/mach-s3c24xx/mach-smdk2440.c
index 08cc38c8a4ae..de2e5d39a847 100644
--- a/arch/arm/mach-s3c24xx/mach-smdk2440.c
+++ b/arch/arm/mach-s3c24xx/mach-smdk2440.c
@@ -38,15 +38,13 @@
 #include <mach/fb.h>
 #include <linux/platform_data/i2c-s3c2410.h>
 
-#include <plat/s3c2410.h>
-#include <plat/s3c244x.h>
 #include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
-
-#include <plat/common-smdk.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
+#include "common-smdk.h"
 
 static struct map_desc smdk2440_iodesc[] __initdata = {
         /* ISA IO Space map (memory space selected by A24) */
@@ -163,6 +161,7 @@ static void __init smdk2440_map_io(void)
         s3c24xx_init_io(smdk2440_iodesc, ARRAY_SIZE(smdk2440_iodesc));
         s3c24xx_init_clocks(16934400);
         s3c24xx_init_uarts(smdk2440_uartcfgs, ARRAY_SIZE(smdk2440_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 static void __init smdk2440_machine_init(void)
@@ -178,9 +177,9 @@ MACHINE_START(S3C2440, "SMDK2440")
         /* Maintainer: Ben Dooks <ben-linux@fluff.org> */
         .atag_offset    = 0x100,
 
-        .init_irq       = s3c24xx_init_irq,
+        .init_irq       = s3c2440_init_irq,
         .map_io         = smdk2440_map_io,
         .init_machine   = smdk2440_machine_init,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c244x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-smdk2443.c b/arch/arm/mach-s3c24xx/mach-smdk2443.c
index fc65d74d3c73..9435c3bef18a 100644
--- a/arch/arm/mach-s3c24xx/mach-smdk2443.c
+++ b/arch/arm/mach-s3c24xx/mach-smdk2443.c
@@ -38,13 +38,13 @@
 #include <mach/fb.h>
 #include <linux/platform_data/i2c-s3c2410.h>
 
-#include <plat/s3c2410.h>
-#include <plat/s3c2443.h>
 #include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
+#include <plat/samsung-time.h>
 
-#include <plat/common-smdk.h>
+#include "common.h"
+#include "common-smdk.h"
 
 static struct map_desc smdk2443_iodesc[] __initdata = {
         /* ISA IO Space map (memory space selected by A24) */
@@ -122,6 +122,7 @@ static void __init smdk2443_map_io(void)
         s3c24xx_init_io(smdk2443_iodesc, ARRAY_SIZE(smdk2443_iodesc));
         s3c24xx_init_clocks(12000000);
         s3c24xx_init_uarts(smdk2443_uartcfgs, ARRAY_SIZE(smdk2443_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 static void __init smdk2443_machine_init(void)
@@ -143,6 +144,6 @@ MACHINE_START(SMDK2443, "SMDK2443")
         .init_irq       = s3c2443_init_irq,
         .map_io         = smdk2443_map_io,
         .init_machine   = smdk2443_machine_init,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c2443_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-tct_hammer.c b/arch/arm/mach-s3c24xx/mach-tct_hammer.c
index 24b3d79e7b2c..7fad8f055cab 100644
--- a/arch/arm/mach-s3c24xx/mach-tct_hammer.c
+++ b/arch/arm/mach-s3c24xx/mach-tct_hammer.c
@@ -53,6 +53,7 @@
 #include <linux/mtd/partitions.h>
 #include <linux/mtd/map.h>
 #include <linux/mtd/physmap.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
 
@@ -136,6 +137,7 @@ static void __init tct_hammer_map_io(void)
         s3c24xx_init_io(tct_hammer_iodesc, ARRAY_SIZE(tct_hammer_iodesc));
         s3c24xx_init_clocks(0);
         s3c24xx_init_uarts(tct_hammer_uartcfgs, ARRAY_SIZE(tct_hammer_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 static void __init tct_hammer_init(void)
@@ -147,8 +149,8 @@ static void __init tct_hammer_init(void)
 MACHINE_START(TCT_HAMMER, "TCT_HAMMER")
         .atag_offset    = 0x100,
         .map_io         = tct_hammer_map_io,
-        .init_irq       = s3c24xx_init_irq,
+        .init_irq       = s3c2410_init_irq,
         .init_machine   = tct_hammer_init,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c2410_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-vr1000.c b/arch/arm/mach-s3c24xx/mach-vr1000.c
index ec42d1e4e465..42e7187fed60 100644
--- a/arch/arm/mach-s3c24xx/mach-vr1000.c
+++ b/arch/arm/mach-s3c24xx/mach-vr1000.c
@@ -45,6 +45,7 @@
 #include <plat/cpu.h>
 #include <plat/devs.h>
 #include <plat/regs-serial.h>
+#include <plat/samsung-time.h>
 
 #include "bast.h"
 #include "common.h"
@@ -332,6 +333,7 @@ static void __init vr1000_map_io(void)
         s3c24xx_init_io(vr1000_iodesc, ARRAY_SIZE(vr1000_iodesc));
         s3c24xx_init_clocks(0);
         s3c24xx_init_uarts(vr1000_uartcfgs, ARRAY_SIZE(vr1000_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 static void __init vr1000_init(void)
@@ -353,7 +355,7 @@ MACHINE_START(VR1000, "Thorcom-VR1000")
         .atag_offset    = 0x100,
         .map_io         = vr1000_map_io,
         .init_machine   = vr1000_init,
-        .init_irq       = s3c24xx_init_irq,
-        .init_time      = s3c24xx_timer_init,
+        .init_irq       = s3c2410_init_irq,
+        .init_time      = samsung_timer_init,
         .restart        = s3c2410_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-vstms.c b/arch/arm/mach-s3c24xx/mach-vstms.c
index 3e2bfddc9df1..b66588428ec9 100644
--- a/arch/arm/mach-s3c24xx/mach-vstms.c
+++ b/arch/arm/mach-s3c24xx/mach-vstms.c
@@ -41,12 +41,12 @@
 #include <linux/platform_data/i2c-s3c2410.h>
 #include <linux/platform_data/mtd-nand-s3c2410.h>
 
-#include <plat/s3c2410.h>
-#include <plat/s3c2412.h>
 #include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
+#include <plat/samsung-time.h>
 
+#include "common.h"
 
 static struct map_desc vstms_iodesc[] __initdata = {
 };
@@ -143,6 +143,7 @@ static void __init vstms_map_io(void)
         s3c24xx_init_io(vstms_iodesc, ARRAY_SIZE(vstms_iodesc));
         s3c24xx_init_clocks(12000000);
         s3c24xx_init_uarts(vstms_uartcfgs, ARRAY_SIZE(vstms_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 static void __init vstms_init(void)
@@ -157,9 +158,9 @@ MACHINE_START(VSTMS, "VSTMS")
         .atag_offset    = 0x100,
 
         .fixup          = vstms_fixup,
-        .init_irq       = s3c24xx_init_irq,
+        .init_irq       = s3c2412_init_irq,
         .init_machine   = vstms_init,
         .map_io         = vstms_map_io,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c2412_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/pm-s3c2412.c b/arch/arm/mach-s3c24xx/pm-s3c2412.c
index 668a78a8b195..d75f95e487ee 100644
--- a/arch/arm/mach-s3c24xx/pm-s3c2412.c
+++ b/arch/arm/mach-s3c24xx/pm-s3c2412.c
@@ -29,7 +29,7 @@
 
 #include <plat/cpu.h>
 #include <plat/pm.h>
-#include <plat/s3c2412.h>
+#include <plat/wakeup-mask.h>
 
 #include "regs-dsc.h"
 #include "s3c2412-power.h"
@@ -52,8 +52,15 @@ static int s3c2412_cpu_suspend(unsigned long arg)
         return 1; /* Aborting suspend */
 }
 
+/* mapping of interrupts to parts of the wakeup mask */
+static struct samsung_wakeup_mask wake_irqs[] = {
+        { .irq = IRQ_RTC,       .bit = S3C2412_PWRCFG_RTC_MASKIRQ, },
+};
+
 static void s3c2412_pm_prepare(void)
 {
+        samsung_sync_wakemask(S3C2412_PWRCFG,
+                              wake_irqs, ARRAY_SIZE(wake_irqs));
 }
 
 static int s3c2412_pm_add(struct device *dev, struct subsys_interface *sif)
diff --git a/arch/arm/mach-s3c24xx/s3c2410.c b/arch/arm/mach-s3c24xx/s3c2410.c
index 9ebef95da721..d850ea5adac2 100644
--- a/arch/arm/mach-s3c24xx/s3c2410.c
+++ b/arch/arm/mach-s3c24xx/s3c2410.c
@@ -37,7 +37,6 @@
 #include <mach/regs-clock.h>
 #include <plat/regs-serial.h>
 
-#include <plat/s3c2410.h>
 #include <plat/cpu.h>
 #include <plat/devs.h>
 #include <plat/clock.h>
diff --git a/arch/arm/mach-s3c24xx/s3c2412.c b/arch/arm/mach-s3c24xx/s3c2412.c
index 0d592159a5c3..0f864d4c97de 100644
--- a/arch/arm/mach-s3c24xx/s3c2412.c
+++ b/arch/arm/mach-s3c24xx/s3c2412.c
@@ -44,7 +44,6 @@
 #include <plat/pm.h>
 #include <plat/regs-serial.h>
 #include <plat/regs-spi.h>
-#include <plat/s3c2412.h>
 
 #include "common.h"
 #include "regs-dsc.h"
diff --git a/arch/arm/mach-s3c24xx/s3c2416.c b/arch/arm/mach-s3c24xx/s3c2416.c
index e30476db0295..b9c5d382dafb 100644
--- a/arch/arm/mach-s3c24xx/s3c2416.c
+++ b/arch/arm/mach-s3c24xx/s3c2416.c
@@ -50,7 +50,6 @@
 #include <plat/gpio-core.h>
 #include <plat/gpio-cfg.h>
 #include <plat/gpio-cfg-helpers.h>
-#include <plat/s3c2416.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
 #include <plat/sdhci.h>
diff --git a/arch/arm/mach-s3c24xx/s3c2440.c b/arch/arm/mach-s3c24xx/s3c2440.c
index 559e394e8989..5f9d6569475d 100644
--- a/arch/arm/mach-s3c24xx/s3c2440.c
+++ b/arch/arm/mach-s3c24xx/s3c2440.c
@@ -33,7 +33,6 @@
 
 #include <plat/devs.h>
 #include <plat/cpu.h>
-#include <plat/s3c244x.h>
 #include <plat/pm.h>
 
 #include <plat/gpio-core.h>
diff --git a/arch/arm/mach-s3c24xx/s3c2442.c b/arch/arm/mach-s3c24xx/s3c2442.c
index f732826c2359..6819961f6b19 100644
--- a/arch/arm/mach-s3c24xx/s3c2442.c
+++ b/arch/arm/mach-s3c24xx/s3c2442.c
@@ -44,7 +44,6 @@
 
 #include <plat/clock.h>
 #include <plat/cpu.h>
-#include <plat/s3c244x.h>
 #include <plat/pm.h>
 
 #include <plat/gpio-core.h>
diff --git a/arch/arm/mach-s3c24xx/s3c2443.c b/arch/arm/mach-s3c24xx/s3c2443.c
index 165b6a6b3daa..8328cd65bf3d 100644
--- a/arch/arm/mach-s3c24xx/s3c2443.c
+++ b/arch/arm/mach-s3c24xx/s3c2443.c
@@ -36,7 +36,6 @@
 #include <plat/gpio-core.h>
 #include <plat/gpio-cfg.h>
 #include <plat/gpio-cfg-helpers.h>
-#include <plat/s3c2443.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
 #include <plat/fb-core.h>
diff --git a/arch/arm/mach-s3c24xx/s3c244x.c b/arch/arm/mach-s3c24xx/s3c244x.c
index ad2671baa910..2a35edb67354 100644
--- a/arch/arm/mach-s3c24xx/s3c244x.c
+++ b/arch/arm/mach-s3c24xx/s3c244x.c
@@ -37,8 +37,6 @@
 #include <plat/regs-serial.h>
 #include <mach/regs-gpio.h>
 
-#include <plat/s3c2410.h>
-#include <plat/s3c244x.h>
 #include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
diff --git a/arch/arm/mach-s3c64xx/Kconfig b/arch/arm/mach-s3c64xx/Kconfig
index 131c86284711..283cb77d4721 100644
--- a/arch/arm/mach-s3c64xx/Kconfig
+++ b/arch/arm/mach-s3c64xx/Kconfig
@@ -17,11 +17,13 @@ config PLAT_S3C64XX
 # Configuration options for the S3C6410 CPU
 
 config CPU_S3C6400
+        select SAMSUNG_HRT
         bool
         help
           Enable S3C6400 CPU support
 
 config CPU_S3C6410
+        select SAMSUNG_HRT
         bool
         help
           Enable S3C6410 CPU support
diff --git a/arch/arm/mach-s3c64xx/mach-anw6410.c b/arch/arm/mach-s3c64xx/mach-anw6410.c
index 728eef3296b2..35e3f54574ef 100644
--- a/arch/arm/mach-s3c64xx/mach-anw6410.c
+++ b/arch/arm/mach-s3c64xx/mach-anw6410.c
@@ -49,6 +49,7 @@
 #include <plat/devs.h>
 #include <plat/cpu.h>
 #include <mach/regs-gpio.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
 #include "regs-modem.h"
@@ -208,6 +209,7 @@ static void __init anw6410_map_io(void)
         s3c64xx_init_io(anw6410_iodesc, ARRAY_SIZE(anw6410_iodesc));
         s3c24xx_init_clocks(12000000);
         s3c24xx_init_uarts(anw6410_uartcfgs, ARRAY_SIZE(anw6410_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 
         anw6410_lcd_mode_set();
 }
@@ -232,6 +234,6 @@ MACHINE_START(ANW6410, "A&W6410")
         .map_io         = anw6410_map_io,
         .init_machine   = anw6410_machine_init,
         .init_late      = s3c64xx_init_late,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c64xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c64xx/mach-crag6410.c b/arch/arm/mach-s3c64xx/mach-crag6410.c
index 1acf02bace57..8ad88ace795a 100644
--- a/arch/arm/mach-s3c64xx/mach-crag6410.c
+++ b/arch/arm/mach-s3c64xx/mach-crag6410.c
@@ -64,6 +64,7 @@
 #include <plat/adc.h>
 #include <linux/platform_data/i2c-s3c2410.h>
 #include <plat/pm.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
 #include "crag6410.h"
@@ -744,6 +745,7 @@ static void __init crag6410_map_io(void)
         s3c64xx_init_io(NULL, 0);
         s3c24xx_init_clocks(12000000);
         s3c24xx_init_uarts(crag6410_uartcfgs, ARRAY_SIZE(crag6410_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 
         /* LCD type and Bypass set by bootloader */
 }
@@ -868,6 +870,6 @@ MACHINE_START(WLF_CRAGG_6410, "Wolfson Cragganmore 6410")
         .map_io         = crag6410_map_io,
         .init_machine   = crag6410_machine_init,
         .init_late      = s3c64xx_init_late,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c64xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c64xx/mach-hmt.c b/arch/arm/mach-s3c64xx/mach-hmt.c
index 7212eb9cfeb9..5b7f357d8c22 100644
--- a/arch/arm/mach-s3c64xx/mach-hmt.c
+++ b/arch/arm/mach-s3c64xx/mach-hmt.c
@@ -41,6 +41,7 @@
 #include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
 
@@ -248,6 +249,7 @@ static void __init hmt_map_io(void)
         s3c64xx_init_io(hmt_iodesc, ARRAY_SIZE(hmt_iodesc));
         s3c24xx_init_clocks(12000000);
         s3c24xx_init_uarts(hmt_uartcfgs, ARRAY_SIZE(hmt_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 static void __init hmt_machine_init(void)
@@ -275,6 +277,6 @@ MACHINE_START(HMT, "Airgoo-HMT")
         .map_io         = hmt_map_io,
         .init_machine   = hmt_machine_init,
         .init_late      = s3c64xx_init_late,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c64xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c64xx/mach-mini6410.c b/arch/arm/mach-s3c64xx/mach-mini6410.c
index 4b41fcdaa7b6..fc043e3ecdf8 100644
--- a/arch/arm/mach-s3c64xx/mach-mini6410.c
+++ b/arch/arm/mach-s3c64xx/mach-mini6410.c
@@ -41,6 +41,7 @@
 
 #include <video/platform_lcd.h>
 #include <video/samsung_fimd.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
 #include "regs-modem.h"
@@ -232,6 +233,7 @@ static void __init mini6410_map_io(void)
         s3c64xx_init_io(NULL, 0);
         s3c24xx_init_clocks(12000000);
         s3c24xx_init_uarts(mini6410_uartcfgs, ARRAY_SIZE(mini6410_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 
         /* set the LCD type */
         tmp = __raw_readl(S3C64XX_SPCON);
@@ -354,6 +356,6 @@ MACHINE_START(MINI6410, "MINI6410")
         .map_io         = mini6410_map_io,
         .init_machine   = mini6410_machine_init,
         .init_late      = s3c64xx_init_late,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c64xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c64xx/mach-ncp.c b/arch/arm/mach-s3c64xx/mach-ncp.c
index 8d3cedd995ff..7e2c3908f1f8 100644
--- a/arch/arm/mach-s3c64xx/mach-ncp.c
+++ b/arch/arm/mach-s3c64xx/mach-ncp.c
@@ -43,6 +43,7 @@
 #include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
 
@@ -87,6 +88,7 @@ static void __init ncp_map_io(void)
         s3c64xx_init_io(ncp_iodesc, ARRAY_SIZE(ncp_iodesc));
         s3c24xx_init_clocks(12000000);
         s3c24xx_init_uarts(ncp_uartcfgs, ARRAY_SIZE(ncp_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 static void __init ncp_machine_init(void)
@@ -103,6 +105,6 @@ MACHINE_START(NCP, "NCP")
         .map_io         = ncp_map_io,
         .init_machine   = ncp_machine_init,
         .init_late      = s3c64xx_init_late,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c64xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c64xx/mach-real6410.c b/arch/arm/mach-s3c64xx/mach-real6410.c
index fa12bd21ad82..8bed37b3d5ac 100644
--- a/arch/arm/mach-s3c64xx/mach-real6410.c
+++ b/arch/arm/mach-s3c64xx/mach-real6410.c
@@ -42,6 +42,7 @@
 
 #include <video/platform_lcd.h>
 #include <video/samsung_fimd.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
 #include "regs-modem.h"
@@ -211,6 +212,7 @@ static void __init real6410_map_io(void)
         s3c64xx_init_io(NULL, 0);
         s3c24xx_init_clocks(12000000);
         s3c24xx_init_uarts(real6410_uartcfgs, ARRAY_SIZE(real6410_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 
         /* set the LCD type */
         tmp = __raw_readl(S3C64XX_SPCON);
@@ -333,6 +335,6 @@ MACHINE_START(REAL6410, "REAL6410")
         .map_io         = real6410_map_io,
         .init_machine   = real6410_machine_init,
         .init_late      = s3c64xx_init_late,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c64xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c64xx/mach-smartq.c b/arch/arm/mach-s3c64xx/mach-smartq.c
index fc3e9b32e26f..58ac99041274 100644
--- a/arch/arm/mach-s3c64xx/mach-smartq.c
+++ b/arch/arm/mach-s3c64xx/mach-smartq.c
@@ -38,6 +38,7 @@
 #include <linux/platform_data/touchscreen-s3c2410.h>
 
 #include <video/platform_lcd.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
 #include "regs-modem.h"
@@ -378,6 +379,7 @@ void __init smartq_map_io(void)
         s3c64xx_init_io(smartq_iodesc, ARRAY_SIZE(smartq_iodesc));
         s3c24xx_init_clocks(12000000);
         s3c24xx_init_uarts(smartq_uartcfgs, ARRAY_SIZE(smartq_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 
         smartq_lcd_mode_set();
 }
diff --git a/arch/arm/mach-s3c64xx/mach-smartq5.c b/arch/arm/mach-s3c64xx/mach-smartq5.c
index ca2afcfce573..8aca5daf3d05 100644
--- a/arch/arm/mach-s3c64xx/mach-smartq5.c
+++ b/arch/arm/mach-s3c64xx/mach-smartq5.c
@@ -28,6 +28,7 @@
 #include <plat/devs.h>
 #include <plat/fb.h>
 #include <plat/gpio-cfg.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
 #include "mach-smartq.h"
@@ -155,6 +156,6 @@ MACHINE_START(SMARTQ5, "SmartQ 5")
         .map_io         = smartq_map_io,
         .init_machine   = smartq5_machine_init,
         .init_late      = s3c64xx_init_late,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c64xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c64xx/mach-smartq7.c b/arch/arm/mach-s3c64xx/mach-smartq7.c
index 37bb0c632a5e..a052e107c0b4 100644
--- a/arch/arm/mach-s3c64xx/mach-smartq7.c
+++ b/arch/arm/mach-s3c64xx/mach-smartq7.c
@@ -28,6 +28,7 @@
 #include <plat/devs.h>
 #include <plat/fb.h>
 #include <plat/gpio-cfg.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
 #include "mach-smartq.h"
@@ -171,6 +172,6 @@ MACHINE_START(SMARTQ7, "SmartQ 7")
         .map_io         = smartq_map_io,
         .init_machine   = smartq7_machine_init,
         .init_late      = s3c64xx_init_late,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c64xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c64xx/mach-smdk6400.c b/arch/arm/mach-s3c64xx/mach-smdk6400.c
index a392869c8342..d70c0843aea2 100644
--- a/arch/arm/mach-s3c64xx/mach-smdk6400.c
+++ b/arch/arm/mach-s3c64xx/mach-smdk6400.c
@@ -35,6 +35,7 @@
 #include <plat/devs.h>
 #include <plat/cpu.h>
 #include <linux/platform_data/i2c-s3c2410.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
 
@@ -66,6 +67,7 @@ static void __init smdk6400_map_io(void)
         s3c64xx_init_io(smdk6400_iodesc, ARRAY_SIZE(smdk6400_iodesc));
         s3c24xx_init_clocks(12000000);
         s3c24xx_init_uarts(smdk6400_uartcfgs, ARRAY_SIZE(smdk6400_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 static struct platform_device *smdk6400_devices[] __initdata = {
@@ -92,6 +94,6 @@ MACHINE_START(SMDK6400, "SMDK6400")
         .map_io         = smdk6400_map_io,
         .init_machine   = smdk6400_machine_init,
         .init_late      = s3c64xx_init_late,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c64xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c64xx/mach-smdk6410.c b/arch/arm/mach-s3c64xx/mach-smdk6410.c
index ba7544e2d04d..bd3295a19ad7 100644
--- a/arch/arm/mach-s3c64xx/mach-smdk6410.c
+++ b/arch/arm/mach-s3c64xx/mach-smdk6410.c
@@ -69,6 +69,7 @@
 #include <linux/platform_data/touchscreen-s3c2410.h>
 #include <plat/keypad.h>
 #include <plat/backlight.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
 #include "regs-modem.h"
@@ -634,6 +635,7 @@ static void __init smdk6410_map_io(void)
         s3c64xx_init_io(smdk6410_iodesc, ARRAY_SIZE(smdk6410_iodesc));
         s3c24xx_init_clocks(12000000);
         s3c24xx_init_uarts(smdk6410_uartcfgs, ARRAY_SIZE(smdk6410_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 
         /* set the LCD type */
 
@@ -702,6 +704,6 @@ MACHINE_START(SMDK6410, "SMDK6410")
         .map_io         = smdk6410_map_io,
         .init_machine   = smdk6410_machine_init,
         .init_late      = s3c64xx_init_late,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c64xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s5p64x0/Kconfig b/arch/arm/mach-s5p64x0/Kconfig
index e8742cb7ddd9..5a707bdb9ea0 100644
--- a/arch/arm/mach-s5p64x0/Kconfig
+++ b/arch/arm/mach-s5p64x0/Kconfig
@@ -9,16 +9,16 @@ if ARCH_S5P64X0
 
 config CPU_S5P6440
         bool
-        select S5P_HRT
         select S5P_SLEEP if PM
         select SAMSUNG_DMADEV
+        select SAMSUNG_HRT
         select SAMSUNG_WAKEMASK if PM
         help
           Enable S5P6440 CPU support
 
 config CPU_S5P6450
         bool
-        select S5P_HRT
+        select SAMSUNG_HRT
         select S5P_SLEEP if PM
         select SAMSUNG_DMADEV
         select SAMSUNG_WAKEMASK if PM
diff --git a/arch/arm/mach-s5p64x0/mach-smdk6440.c b/arch/arm/mach-s5p64x0/mach-smdk6440.c
index e23723a5a214..73f71a698a34 100644
--- a/arch/arm/mach-s5p64x0/mach-smdk6440.c
+++ b/arch/arm/mach-s5p64x0/mach-smdk6440.c
@@ -48,7 +48,7 @@
 #include <plat/pll.h>
 #include <plat/adc.h>
 #include <linux/platform_data/touchscreen-s3c2410.h>
-#include <plat/s5p-time.h>
+#include <plat/samsung-time.h>
 #include <plat/backlight.h>
 #include <plat/fb.h>
 #include <plat/sdhci.h>
@@ -229,7 +229,7 @@ static void __init smdk6440_map_io(void)
         s5p64x0_init_io(NULL, 0);
         s3c24xx_init_clocks(12000000);
         s3c24xx_init_uarts(smdk6440_uartcfgs, ARRAY_SIZE(smdk6440_uartcfgs));
-        s5p_set_timer_source(S5P_PWM3, S5P_PWM4);
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 static void s5p6440_set_lcd_interface(void)
@@ -273,6 +273,6 @@ MACHINE_START(SMDK6440, "SMDK6440")
         .init_irq       = s5p6440_init_irq,
         .map_io         = smdk6440_map_io,
         .init_machine   = smdk6440_machine_init,
-        .init_time      = s5p_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s5p64x0_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s5p64x0/mach-smdk6450.c b/arch/arm/mach-s5p64x0/mach-smdk6450.c
index ca10963a959e..18303e12019f 100644
--- a/arch/arm/mach-s5p64x0/mach-smdk6450.c
+++ b/arch/arm/mach-s5p64x0/mach-smdk6450.c
@@ -48,7 +48,7 @@
 #include <plat/pll.h>
 #include <plat/adc.h>
 #include <linux/platform_data/touchscreen-s3c2410.h>
-#include <plat/s5p-time.h>
+#include <plat/samsung-time.h>
 #include <plat/backlight.h>
 #include <plat/fb.h>
 #include <plat/sdhci.h>
@@ -248,7 +248,7 @@ static void __init smdk6450_map_io(void)
         s5p64x0_init_io(NULL, 0);
         s3c24xx_init_clocks(19200000);
         s3c24xx_init_uarts(smdk6450_uartcfgs, ARRAY_SIZE(smdk6450_uartcfgs));
-        s5p_set_timer_source(S5P_PWM3, S5P_PWM4);
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 static void s5p6450_set_lcd_interface(void)
@@ -292,6 +292,6 @@ MACHINE_START(SMDK6450, "SMDK6450")
         .init_irq       = s5p6450_init_irq,
         .map_io         = smdk6450_map_io,
         .init_machine   = smdk6450_machine_init,
-        .init_time      = s5p_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s5p64x0_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s5pc100/Kconfig b/arch/arm/mach-s5pc100/Kconfig
index 15170be97a74..2f456a4533ba 100644
--- a/arch/arm/mach-s5pc100/Kconfig
+++ b/arch/arm/mach-s5pc100/Kconfig
@@ -11,6 +11,7 @@ config CPU_S5PC100
         bool
         select S5P_EXT_INT
         select SAMSUNG_DMADEV
+        select SAMSUNG_HRT
         help
           Enable S5PC100 CPU support
 
diff --git a/arch/arm/mach-s5pc100/mach-smdkc100.c b/arch/arm/mach-s5pc100/mach-smdkc100.c
index 185a19583898..8c880f76f274 100644
--- a/arch/arm/mach-s5pc100/mach-smdkc100.c
+++ b/arch/arm/mach-s5pc100/mach-smdkc100.c
@@ -51,6 +51,7 @@
 #include <linux/platform_data/touchscreen-s3c2410.h>
 #include <linux/platform_data/asoc-s3c.h>
 #include <plat/backlight.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
 
@@ -221,6 +222,7 @@ static void __init smdkc100_map_io(void)
         s5pc100_init_io(NULL, 0);
         s3c24xx_init_clocks(12000000);
         s3c24xx_init_uarts(smdkc100_uartcfgs, ARRAY_SIZE(smdkc100_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 static void __init smdkc100_machine_init(void)
@@ -255,6 +257,6 @@ MACHINE_START(SMDKC100, "SMDKC100")
         .init_irq       = s5pc100_init_irq,
         .map_io         = smdkc100_map_io,
         .init_machine   = smdkc100_machine_init,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s5pc100_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s5pv210/Kconfig b/arch/arm/mach-s5pv210/Kconfig
index 92ad72f0ef98..0963283a7c5d 100644
--- a/arch/arm/mach-s5pv210/Kconfig
+++ b/arch/arm/mach-s5pv210/Kconfig
@@ -12,10 +12,10 @@ if ARCH_S5PV210
 config CPU_S5PV210
         bool
         select S5P_EXT_INT
-        select S5P_HRT
         select S5P_PM if PM
         select S5P_SLEEP if PM
         select SAMSUNG_DMADEV
+        select SAMSUNG_HRT
         help
           Enable S5PV210 CPU support
 
diff --git a/arch/arm/mach-s5pv210/mach-aquila.c b/arch/arm/mach-s5pv210/mach-aquila.c
index 11900a8e88a3..ed2b85485b9d 100644
--- a/arch/arm/mach-s5pv210/mach-aquila.c
+++ b/arch/arm/mach-s5pv210/mach-aquila.c
@@ -38,7 +38,7 @@
 #include <plat/fb.h>
 #include <plat/fimc-core.h>
 #include <plat/sdhci.h>
-#include <plat/s5p-time.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
 
@@ -651,7 +651,7 @@ static void __init aquila_map_io(void)
         s5pv210_init_io(NULL, 0);
         s3c24xx_init_clocks(24000000);
         s3c24xx_init_uarts(aquila_uartcfgs, ARRAY_SIZE(aquila_uartcfgs));
-        s5p_set_timer_source(S5P_PWM3, S5P_PWM4);
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 static void __init aquila_machine_init(void)
@@ -686,6 +686,6 @@ MACHINE_START(AQUILA, "Aquila")
         .init_irq       = s5pv210_init_irq,
         .map_io         = aquila_map_io,
         .init_machine   = aquila_machine_init,
-        .init_time      = s5p_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s5pv210_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s5pv210/mach-goni.c b/arch/arm/mach-s5pv210/mach-goni.c
index e373de44a8b6..30b24ad84f49 100644
--- a/arch/arm/mach-s5pv210/mach-goni.c
+++ b/arch/arm/mach-s5pv210/mach-goni.c
@@ -47,7 +47,7 @@
 #include <plat/keypad.h>
 #include <plat/sdhci.h>
 #include <plat/clock.h>
-#include <plat/s5p-time.h>
+#include <plat/samsung-time.h>
 #include <plat/mfc.h>
 #include <plat/camport.h>
 
@@ -908,7 +908,7 @@ static void __init goni_map_io(void)
         s5pv210_init_io(NULL, 0);
         s3c24xx_init_clocks(clk_xusbxti.rate);
         s3c24xx_init_uarts(goni_uartcfgs, ARRAY_SIZE(goni_uartcfgs));
-        s5p_set_timer_source(S5P_PWM3, S5P_PWM4);
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 static void __init goni_reserve(void)
@@ -973,7 +973,7 @@ MACHINE_START(GONI, "GONI")
         .init_irq       = s5pv210_init_irq,
         .map_io         = goni_map_io,
         .init_machine   = goni_machine_init,
-        .init_time      = s5p_timer_init,
+        .init_time      = samsung_timer_init,
         .reserve        = &goni_reserve,
         .restart        = s5pv210_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s5pv210/mach-smdkc110.c b/arch/arm/mach-s5pv210/mach-smdkc110.c
index 28bd0248a3e2..7c0ed07a78a3 100644
--- a/arch/arm/mach-s5pv210/mach-smdkc110.c
+++ b/arch/arm/mach-s5pv210/mach-smdkc110.c
@@ -29,7 +29,7 @@
 #include <linux/platform_data/ata-samsung_cf.h>
 #include <linux/platform_data/i2c-s3c2410.h>
 #include <plat/pm.h>
-#include <plat/s5p-time.h>
+#include <plat/samsung-time.h>
 #include <plat/mfc.h>
 
 #include "common.h"
@@ -120,7 +120,7 @@ static void __init smdkc110_map_io(void)
         s5pv210_init_io(NULL, 0);
         s3c24xx_init_clocks(24000000);
         s3c24xx_init_uarts(smdkv210_uartcfgs, ARRAY_SIZE(smdkv210_uartcfgs));
-        s5p_set_timer_source(S5P_PWM3, S5P_PWM4);
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 static void __init smdkc110_reserve(void)
@@ -153,7 +153,7 @@ MACHINE_START(SMDKC110, "SMDKC110")
         .init_irq       = s5pv210_init_irq,
         .map_io         = smdkc110_map_io,
         .init_machine   = smdkc110_machine_init,
-        .init_time      = s5p_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s5pv210_restart,
         .reserve        = &smdkc110_reserve,
 MACHINE_END
diff --git a/arch/arm/mach-s5pv210/mach-smdkv210.c b/arch/arm/mach-s5pv210/mach-smdkv210.c
index 3c73f36869bb..d50b6f124465 100644
--- a/arch/arm/mach-s5pv210/mach-smdkv210.c
+++ b/arch/arm/mach-s5pv210/mach-smdkv210.c
@@ -44,7 +44,7 @@
 #include <plat/keypad.h>
 #include <plat/pm.h>
 #include <plat/fb.h>
-#include <plat/s5p-time.h>
+#include <plat/samsung-time.h>
 #include <plat/backlight.h>
 #include <plat/mfc.h>
 #include <plat/clock.h>
@@ -285,7 +285,7 @@ static void __init smdkv210_map_io(void)
         s5pv210_init_io(NULL, 0);
         s3c24xx_init_clocks(clk_xusbxti.rate);
         s3c24xx_init_uarts(smdkv210_uartcfgs, ARRAY_SIZE(smdkv210_uartcfgs));
-        s5p_set_timer_source(S5P_PWM2, S5P_PWM4);
+        samsung_set_timer_source(SAMSUNG_PWM2, SAMSUNG_PWM4);
 }
 
 static void __init smdkv210_reserve(void)
@@ -329,7 +329,7 @@ MACHINE_START(SMDKV210, "SMDKV210")
         .init_irq       = s5pv210_init_irq,
         .map_io         = smdkv210_map_io,
         .init_machine   = smdkv210_machine_init,
-        .init_time      = s5p_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s5pv210_restart,
         .reserve        = &smdkv210_reserve,
 MACHINE_END
diff --git a/arch/arm/mach-s5pv210/mach-torbreck.c b/arch/arm/mach-s5pv210/mach-torbreck.c
index 2d4c5531819c..579afe89842a 100644
--- a/arch/arm/mach-s5pv210/mach-torbreck.c
+++ b/arch/arm/mach-s5pv210/mach-torbreck.c
@@ -26,7 +26,7 @@
 #include <plat/devs.h>
 #include <plat/cpu.h>
 #include <linux/platform_data/i2c-s3c2410.h>
-#include <plat/s5p-time.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
 
@@ -106,7 +106,7 @@ static void __init torbreck_map_io(void)
         s5pv210_init_io(NULL, 0);
         s3c24xx_init_clocks(24000000);
         s3c24xx_init_uarts(torbreck_uartcfgs, ARRAY_SIZE(torbreck_uartcfgs));
-        s5p_set_timer_source(S5P_PWM3, S5P_PWM4);
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 static void __init torbreck_machine_init(void)
@@ -130,6 +130,6 @@ MACHINE_START(TORBRECK, "TORBRECK")
         .init_irq       = s5pv210_init_irq,
         .map_io         = torbreck_map_io,
         .init_machine   = torbreck_machine_init,
-        .init_time      = s5p_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s5pv210_restart,
 MACHINE_END
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index 9255546e7bf6..75d413c004b6 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -16,6 +16,7 @@ config ARCH_SH73A0
         select CPU_V7
         select I2C
         select SH_CLK_CPG
+        select RENESAS_INTC_IRQPIN
 
 config ARCH_R8A7740
         bool "R-Mobile A1 (R8A77400)"
@@ -31,6 +32,7 @@ config ARCH_R8A7779
         select SH_CLK_CPG
         select USB_ARCH_HAS_EHCI
         select USB_ARCH_HAS_OHCI
+        select RENESAS_INTC_IRQPIN
 
 config ARCH_EMEV2
         bool "Emma Mobile EV2"
diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile
index e1fac57514b9..b646ff4d742a 100644
--- a/arch/arm/mach-shmobile/Makefile
+++ b/arch/arm/mach-shmobile/Makefile
@@ -14,10 +14,9 @@ obj-$(CONFIG_ARCH_EMEV2)	+= setup-emev2.o clock-emev2.o
 
 # SMP objects
 smp-y                           := platsmp.o headsmp.o
-smp-$(CONFIG_HOTPLUG_CPU)       += hotplug.o
-smp-$(CONFIG_ARCH_SH73A0)       += smp-sh73a0.o headsmp-sh73a0.o
-smp-$(CONFIG_ARCH_R8A7779)      += smp-r8a7779.o
-smp-$(CONFIG_ARCH_EMEV2)        += smp-emev2.o
+smp-$(CONFIG_ARCH_SH73A0)       += smp-sh73a0.o headsmp-scu.o
+smp-$(CONFIG_ARCH_R8A7779)      += smp-r8a7779.o headsmp-scu.o
+smp-$(CONFIG_ARCH_EMEV2)        += smp-emev2.o headsmp-scu.o
 
 # IRQ objects
 obj-$(CONFIG_ARCH_SH7372)       += entry-intc.o
diff --git a/arch/arm/mach-shmobile/board-kzm9d.c b/arch/arm/mach-shmobile/board-kzm9d.c
index c254782aa727..c016ccd92433 100644
--- a/arch/arm/mach-shmobile/board-kzm9d.c
+++ b/arch/arm/mach-shmobile/board-kzm9d.c
@@ -90,6 +90,5 @@ DT_MACHINE_START(KZM9D_DT, "kzm9d")
         .init_irq       = emev2_init_irq,
         .init_machine   = kzm9d_add_standard_devices,
         .init_late      = shmobile_init_late,
-        .init_time      = shmobile_timer_init,
         .dt_compat      = kzm9d_boards_compat_dt,
 MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-kzm9g.c b/arch/arm/mach-shmobile/board-kzm9g.c
index 7f3a6b7e7b7c..d34d12ae496b 100644
--- a/arch/arm/mach-shmobile/board-kzm9g.c
+++ b/arch/arm/mach-shmobile/board-kzm9g.c
@@ -81,7 +81,7 @@ static struct resource smsc9221_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = intcs_evt2irq(0x260), /* IRQ3 */
+                .start  = irq_pin(3), /* IRQ3 */
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -115,7 +115,7 @@ static struct resource usb_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = intcs_evt2irq(0x220), /* IRQ1 */
+                .start  = irq_pin(1), /* IRQ1 */
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -138,7 +138,7 @@ struct usbhs_private {
         struct renesas_usbhs_platform_info info;
 };
 
-#define IRQ15                   intcs_evt2irq(0x03e0)
+#define IRQ15                   irq_pin(15)
 #define USB_PHY_MODE            (1 << 4)
 #define USB_PHY_INT_EN          ((1 << 3) | (1 << 2))
 #define USB_PHY_ON              (1 << 1)
@@ -563,25 +563,25 @@ static struct i2c_board_info i2c0_devices[] = {
         },
         {
                 I2C_BOARD_INFO("ak8975", 0x0c),
-                .irq = intcs_evt2irq(0x3380), /* IRQ28 */
+                .irq = irq_pin(28), /* IRQ28 */
         },
         {
                 I2C_BOARD_INFO("adxl34x", 0x1d),
-                .irq = intcs_evt2irq(0x3340), /* IRQ26 */
+                .irq = irq_pin(26), /* IRQ26 */
         },
 };
 
 static struct i2c_board_info i2c1_devices[] = {
         {
                 I2C_BOARD_INFO("st1232-ts", 0x55),
-                .irq = intcs_evt2irq(0x300), /* IRQ8 */
+                .irq = irq_pin(8), /* IRQ8 */
         },
 };
 
 static struct i2c_board_info i2c3_devices[] = {
         {
                 I2C_BOARD_INFO("pcf8575", 0x20),
-                .irq            = intcs_evt2irq(0x3260), /* IRQ19 */
+                .irq = irq_pin(19), /* IRQ19 */
                 .platform_data = &pcf8575_pdata,
         },
 };
diff --git a/arch/arm/mach-shmobile/clock-r8a7740.c b/arch/arm/mach-shmobile/clock-r8a7740.c
index 19ce885a3b43..1feb9a2286a8 100644
--- a/arch/arm/mach-shmobile/clock-r8a7740.c
+++ b/arch/arm/mach-shmobile/clock-r8a7740.c
@@ -593,29 +593,42 @@ static struct clk_lookup lookups[] = {
         CLKDEV_DEV_ID("sh_mobile_ceu.1",        &mstp_clks[MSTP128]),
 
         CLKDEV_DEV_ID("sh-sci.4",               &mstp_clks[MSTP200]),
+        CLKDEV_DEV_ID("e6c80000.sci",           &mstp_clks[MSTP200]),
         CLKDEV_DEV_ID("sh-sci.3",               &mstp_clks[MSTP201]),
+        CLKDEV_DEV_ID("e6c70000.sci",           &mstp_clks[MSTP201]),
         CLKDEV_DEV_ID("sh-sci.2",               &mstp_clks[MSTP202]),
+        CLKDEV_DEV_ID("e6c60000.sci",           &mstp_clks[MSTP202]),
         CLKDEV_DEV_ID("sh-sci.1",               &mstp_clks[MSTP203]),
+        CLKDEV_DEV_ID("e6c50000.sci",           &mstp_clks[MSTP203]),
         CLKDEV_DEV_ID("sh-sci.0",               &mstp_clks[MSTP204]),
+        CLKDEV_DEV_ID("e6c40000.sci",           &mstp_clks[MSTP204]),
         CLKDEV_DEV_ID("sh-sci.8",               &mstp_clks[MSTP206]),
+        CLKDEV_DEV_ID("e6c30000.sci",           &mstp_clks[MSTP206]),
         CLKDEV_DEV_ID("sh-sci.5",               &mstp_clks[MSTP207]),
+        CLKDEV_DEV_ID("e6cb0000.sci",           &mstp_clks[MSTP207]),
         CLKDEV_DEV_ID("sh-dma-engine.3",        &mstp_clks[MSTP214]),
         CLKDEV_DEV_ID("sh-dma-engine.2",        &mstp_clks[MSTP216]),
         CLKDEV_DEV_ID("sh-dma-engine.1",        &mstp_clks[MSTP217]),
         CLKDEV_DEV_ID("sh-dma-engine.0",        &mstp_clks[MSTP218]),
         CLKDEV_DEV_ID("sh-sci.7",               &mstp_clks[MSTP222]),
+        CLKDEV_DEV_ID("e6cd0000.sci",           &mstp_clks[MSTP222]),
         CLKDEV_DEV_ID("sh-sci.6",               &mstp_clks[MSTP230]),
+        CLKDEV_DEV_ID("e6cc0000.sci",           &mstp_clks[MSTP230]),
 
         CLKDEV_DEV_ID("sh_cmt.10",              &mstp_clks[MSTP329]),
         CLKDEV_DEV_ID("sh_fsi2",                &mstp_clks[MSTP328]),
         CLKDEV_DEV_ID("i2c-sh_mobile.1",        &mstp_clks[MSTP323]),
         CLKDEV_DEV_ID("renesas_usbhs",          &mstp_clks[MSTP320]),
         CLKDEV_DEV_ID("sh_mobile_sdhi.0",       &mstp_clks[MSTP314]),
+        CLKDEV_DEV_ID("e6850000.sdhi",          &mstp_clks[MSTP314]),
         CLKDEV_DEV_ID("sh_mobile_sdhi.1",       &mstp_clks[MSTP313]),
+        CLKDEV_DEV_ID("e6860000.sdhi",          &mstp_clks[MSTP313]),
         CLKDEV_DEV_ID("sh_mmcif",               &mstp_clks[MSTP312]),
+        CLKDEV_DEV_ID("e6bd0000.mmcif",         &mstp_clks[MSTP312]),
         CLKDEV_DEV_ID("sh-eth",                 &mstp_clks[MSTP309]),
 
         CLKDEV_DEV_ID("sh_mobile_sdhi.2",       &mstp_clks[MSTP415]),
+        CLKDEV_DEV_ID("e6870000.sdhi",          &mstp_clks[MSTP415]),
 
         /* ICK */
         CLKDEV_ICK_ID("host",   "renesas_usbhs",        &mstp_clks[MSTP416]),
diff --git a/arch/arm/mach-shmobile/clock-r8a7779.c b/arch/arm/mach-shmobile/clock-r8a7779.c
index 1db36537255c..d9edeaf66007 100644
--- a/arch/arm/mach-shmobile/clock-r8a7779.c
+++ b/arch/arm/mach-shmobile/clock-r8a7779.c
@@ -87,7 +87,8 @@ static struct clk div4_clks[DIV4_NR] = {
 };
 
 enum { MSTP323, MSTP322, MSTP321, MSTP320,
-        MSTP101, MSTP100,
+        MSTP115,
+        MSTP103, MSTP101, MSTP100,
         MSTP030,
         MSTP029, MSTP028, MSTP027, MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021,
         MSTP016, MSTP015, MSTP014,
@@ -99,6 +100,8 @@ static struct clk mstp_clks[MSTP_NR] = {
         [MSTP322] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 22, 0), /* SDHI1 */
         [MSTP321] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 21, 0), /* SDHI2 */
         [MSTP320] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 20, 0), /* SDHI3 */
+        [MSTP115] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 15, 0), /* SATA */
+        [MSTP103] = SH_CLK_MSTP32(&div4_clks[DIV4_S], MSTPCR1,  3, 0), /* DU */
         [MSTP101] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1,  1, 0), /* USB2 */
         [MSTP100] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1,  0, 0), /* USB0/1 */
         [MSTP030] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 30, 0), /* I2C0 */
@@ -156,6 +159,8 @@ static struct clk_lookup lookups[] = {
         CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
 
         /* MSTP32 clocks */
+        CLKDEV_DEV_ID("sata_rcar", &mstp_clks[MSTP115]), /* SATA */
+        CLKDEV_DEV_ID("fc600000.sata", &mstp_clks[MSTP115]), /* SATA w/DT */
         CLKDEV_DEV_ID("ehci-platform.1", &mstp_clks[MSTP101]), /* USB EHCI port2 */
         CLKDEV_DEV_ID("ohci-platform.1", &mstp_clks[MSTP101]), /* USB OHCI port2 */
         CLKDEV_DEV_ID("ehci-platform.0", &mstp_clks[MSTP100]), /* USB EHCI port0/1 */
@@ -180,6 +185,7 @@ static struct clk_lookup lookups[] = {
         CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP322]), /* SDHI1 */
         CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP321]), /* SDHI2 */
         CLKDEV_DEV_ID("sh_mobile_sdhi.3", &mstp_clks[MSTP320]), /* SDHI3 */
+        CLKDEV_DEV_ID("rcar-du.0", &mstp_clks[MSTP103]), /* DU */
 };
 
 void __init r8a7779_clock_init(void)
diff --git a/arch/arm/mach-shmobile/clock-sh73a0.c b/arch/arm/mach-shmobile/clock-sh73a0.c
index afa5423a0f93..71843dd39e16 100644
--- a/arch/arm/mach-shmobile/clock-sh73a0.c
+++ b/arch/arm/mach-shmobile/clock-sh73a0.c
@@ -265,12 +265,12 @@ enum { DIV4_I, DIV4_ZG, DIV4_M3, DIV4_B, DIV4_M1, DIV4_M2,
 
 static struct clk div4_clks[DIV4_NR] = {
         [DIV4_I] = DIV4(FRQCRA, 20, 0xdff, CLK_ENABLE_ON_INIT),
-        [DIV4_ZG] = DIV4(FRQCRA, 16, 0xd7f, CLK_ENABLE_ON_INIT),
+        [DIV4_ZG] = SH_CLK_DIV4(&pll0_clk, FRQCRA, 16, 0xd7f, CLK_ENABLE_ON_INIT),
         [DIV4_M3] = DIV4(FRQCRA, 12, 0x1dff, CLK_ENABLE_ON_INIT),
         [DIV4_B] = DIV4(FRQCRA, 8, 0xdff, CLK_ENABLE_ON_INIT),
         [DIV4_M1] = DIV4(FRQCRA, 4, 0x1dff, 0),
         [DIV4_M2] = DIV4(FRQCRA, 0, 0x1dff, 0),
-        [DIV4_Z] = DIV4(FRQCRB, 24, 0x97f, 0),
+        [DIV4_Z] = SH_CLK_DIV4(&pll0_clk, FRQCRB, 24, 0x97f, 0),
         [DIV4_ZTR] = DIV4(FRQCRB, 20, 0xdff, 0),
         [DIV4_ZT] = DIV4(FRQCRB, 16, 0xdff, 0),
         [DIV4_ZX] = DIV4(FRQCRB, 12, 0xdff, 0),
@@ -581,10 +581,13 @@ static struct clk_lookup lookups[] = {
         CLKDEV_DEV_ID("e6822000.i2c", &mstp_clks[MSTP323]), /* I2C1 */
         CLKDEV_DEV_ID("renesas_usbhs", &mstp_clks[MSTP322]), /* USB */
         CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]), /* SDHI0 */
+        CLKDEV_DEV_ID("ee100000.sdhi", &mstp_clks[MSTP314]), /* SDHI0 */
         CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]), /* SDHI1 */
+        CLKDEV_DEV_ID("ee120000.sdhi", &mstp_clks[MSTP313]), /* SDHI1 */
         CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP312]), /* MMCIF0 */
         CLKDEV_DEV_ID("e6bd0000.mmcif", &mstp_clks[MSTP312]), /* MMCIF0 */
         CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP311]), /* SDHI2 */
+        CLKDEV_DEV_ID("ee140000.sdhi", &mstp_clks[MSTP311]), /* SDHI2 */
         CLKDEV_DEV_ID("leds-renesas-tpu.12", &mstp_clks[MSTP303]), /* TPU1 */
         CLKDEV_DEV_ID("leds-renesas-tpu.21", &mstp_clks[MSTP302]), /* TPU2 */
         CLKDEV_DEV_ID("leds-renesas-tpu.30", &mstp_clks[MSTP301]), /* TPU3 */
diff --git a/arch/arm/mach-shmobile/headsmp-sh73a0.S b/arch/arm/mach-shmobile/headsmp-scu.S
index bec4c0d9b713..7d113f898e7f 100644
--- a/arch/arm/mach-shmobile/headsmp-sh73a0.S
+++ b/arch/arm/mach-shmobile/headsmp-scu.S
@@ -1,5 +1,5 @@
 /*
- * SMP support for SoC sh73a0
+ * Shared SCU setup for mach-shmobile
  *
  * Copyright (C) 2012 Bastian Hecht
  *
@@ -35,11 +35,12 @@
  * the physical address as the MMU is still turned off.
  */
         .align  12
-ENTRY(sh73a0_secondary_vector)
+ENTRY(shmobile_secondary_vector_scu)
         mrc     p15, 0, r0, c0, c0, 5   @ read MIPDR
         and     r0, r0, #3              @ mask out cpu ID
         lsl     r0, r0, #3              @ we will shift by cpu_id * 8 bits
-        mov     r1, #0xf0000000         @ SCU base address
+        ldr     r1, 2f
+        ldr     r1, [r1]                @ SCU base address
         ldr     r2, [r1, #8]            @ SCU Power Status Register
         mov     r3, #3
         bic     r2, r2, r3, lsl r0      @ Clear bits of our CPU (Run Mode)
@@ -47,4 +48,10 @@ ENTRY(sh73a0_secondary_vector)
 
         ldr     pc, 1f
 1:      .long shmobile_invalidate_start - PAGE_OFFSET + PLAT_PHYS_OFFSET
-ENDPROC(sh73a0_secondary_vector)
+2:      .long shmobile_scu_base - PAGE_OFFSET + PLAT_PHYS_OFFSET
+ENDPROC(shmobile_secondary_vector_scu)
+
+        .text
+        .globl  shmobile_scu_base
+shmobile_scu_base:
+        .space  4
diff --git a/arch/arm/mach-shmobile/hotplug.c b/arch/arm/mach-shmobile/hotplug.c
deleted file mode 100644
index a1524e3367b0..000000000000
--- a/arch/arm/mach-shmobile/hotplug.c
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
- * SMP support for R-Mobile / SH-Mobile
- *
- * Copyright (C) 2010  Magnus Damm
- *
- * Based on realview, Copyright (C) 2002 ARM Ltd, All Rights Reserved
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/kernel.h>
-#include <linux/errno.h>
-#include <linux/smp.h>
-#include <linux/cpumask.h>
-#include <linux/delay.h>
-#include <linux/of.h>
-#include <mach/common.h>
-#include <mach/r8a7779.h>
-#include <mach/emev2.h>
-#include <asm/cacheflush.h>
-#include <asm/mach-types.h>
-
-static cpumask_t dead_cpus;
-
-void shmobile_cpu_die(unsigned int cpu)
-{
-        /* hardware shutdown code running on the CPU that is being offlined */
-        flush_cache_all();
-        dsb();
-
-        /* notify platform_cpu_kill() that hardware shutdown is finished */
-        cpumask_set_cpu(cpu, &dead_cpus);
-
-        /* wait for SoC code in platform_cpu_kill() to shut off CPU core
-         * power. CPU bring up starts from the reset vector.
-         */
-        while (1) {
-                /*
-                 * here's the WFI
-                 */
-                asm(".word      0xe320f003\n"
-                    :
-                    :
-                    : "memory", "cc");
-        }
-}
-
-int shmobile_cpu_disable(unsigned int cpu)
-{
-        cpumask_clear_cpu(cpu, &dead_cpus);
-        /*
-         * we don't allow CPU 0 to be shutdown (it is still too special
-         * e.g. clock tick interrupts)
-         */
-        return cpu == 0 ? -EPERM : 0;
-}
-
-int shmobile_cpu_disable_any(unsigned int cpu)
-{
-        cpumask_clear_cpu(cpu, &dead_cpus);
-        return 0;
-}
-
-int shmobile_cpu_is_dead(unsigned int cpu)
-{
-        return cpumask_test_cpu(cpu, &dead_cpus);
-}
diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h
index e48606d8a2be..03f73def2fc6 100644
--- a/arch/arm/mach-shmobile/include/mach/common.h
+++ b/arch/arm/mach-shmobile/include/mach/common.h
@@ -8,6 +8,7 @@ extern void shmobile_setup_delay(unsigned int max_cpu_core_mhz,
 struct twd_local_timer;
 extern void shmobile_setup_console(void);
 extern void shmobile_secondary_vector(void);
+extern void shmobile_secondary_vector_scu(void);
 struct clk;
 extern int shmobile_clk_init(void);
 extern void shmobile_handle_irq_intc(struct pt_regs *);
@@ -33,23 +34,23 @@ extern int sh7372_do_idle_sysc(unsigned long sleep_mode);
 extern struct clk sh7372_extal1_clk;
 extern struct clk sh7372_extal2_clk;
 
+extern void sh73a0_init_delay(void);
 extern void sh73a0_init_irq(void);
 extern void sh73a0_init_irq_dt(void);
 extern void sh73a0_map_io(void);
 extern void sh73a0_earlytimer_init(void);
 extern void sh73a0_add_early_devices(void);
-extern void sh73a0_add_early_devices_dt(void);
 extern void sh73a0_add_standard_devices(void);
 extern void sh73a0_add_standard_devices_dt(void);
 extern void sh73a0_clock_init(void);
 extern void sh73a0_pinmux_init(void);
 extern void sh73a0_pm_init(void);
-extern void sh73a0_secondary_vector(void);
 extern struct clk sh73a0_extal1_clk;
 extern struct clk sh73a0_extal2_clk;
 extern struct clk sh73a0_extcki_clk;
 extern struct clk sh73a0_extalr_clk;
 
+extern void r8a7740_meram_workaround(void);
 extern void r8a7740_init_irq(void);
 extern void r8a7740_map_io(void);
 extern void r8a7740_add_early_devices(void);
@@ -58,16 +59,18 @@ extern void r8a7740_clock_init(u8 md_ck);
 extern void r8a7740_pinmux_init(void);
 extern void r8a7740_pm_init(void);
 
+extern void r8a7779_init_delay(void);
 extern void r8a7779_init_irq(void);
+extern void r8a7779_init_irq_extpin(int irlm);
+extern void r8a7779_init_irq_dt(void);
 extern void r8a7779_map_io(void);
 extern void r8a7779_earlytimer_init(void);
 extern void r8a7779_add_early_devices(void);
 extern void r8a7779_add_standard_devices(void);
+extern void r8a7779_add_standard_devices_dt(void);
 extern void r8a7779_clock_init(void);
 extern void r8a7779_pinmux_init(void);
 extern void r8a7779_pm_init(void);
-extern void r8a7740_meram_workaround(void);
-
 extern void r8a7779_register_twd(void);
 
 #ifdef CONFIG_SUSPEND
@@ -82,16 +85,7 @@ int shmobile_cpuidle_init(void);
 static inline int shmobile_cpuidle_init(void) { return 0; }
 #endif
 
-extern void shmobile_cpu_die(unsigned int cpu);
-extern int shmobile_cpu_disable(unsigned int cpu);
-extern int shmobile_cpu_disable_any(unsigned int cpu);
-
-#ifdef CONFIG_HOTPLUG_CPU
-extern int shmobile_cpu_is_dead(unsigned int cpu);
-#else
-static inline int shmobile_cpu_is_dead(unsigned int cpu) { return 1; }
-#endif
-
+extern void __iomem *shmobile_scu_base;
 extern void shmobile_smp_init_cpus(unsigned int ncores);
 
 static inline void __init shmobile_init_late(void)
diff --git a/arch/arm/mach-shmobile/include/mach/irqs.h b/arch/arm/mach-shmobile/include/mach/irqs.h
index 06a5da3c3050..b2074e2acb15 100644
--- a/arch/arm/mach-shmobile/include/mach/irqs.h
+++ b/arch/arm/mach-shmobile/include/mach/irqs.h
@@ -5,10 +5,15 @@
 
 /* GIC */
 #define gic_spi(nr)             ((nr) + 32)
+#define gic_iid(nr)             (nr) /* ICCIAR / interrupt ID */
 
 /* INTCS */
 #define INTCS_VECT_BASE         0x3400
 #define INTCS_VECT(n, vect)     INTC_VECT((n), INTCS_VECT_BASE + (vect))
 #define intcs_evt2irq(evt)      evt2irq(INTCS_VECT_BASE + (evt))
 
+/* External IRQ pins */
+#define IRQPIN_BASE             2000
+#define irq_pin(nr)             ((nr) + IRQPIN_BASE)
+
 #endif /* __ASM_MACH_IRQS_H */
diff --git a/arch/arm/mach-shmobile/intc-r8a7779.c b/arch/arm/mach-shmobile/intc-r8a7779.c
index 8807c27f71f9..b86dc8908724 100644
--- a/arch/arm/mach-shmobile/intc-r8a7779.c
+++ b/arch/arm/mach-shmobile/intc-r8a7779.c
@@ -19,12 +19,16 @@
  */
 #include <linux/kernel.h>
 #include <linux/init.h>
+#include <linux/platform_device.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>
 #include <linux/io.h>
 #include <linux/irqchip/arm-gic.h>
+#include <linux/platform_data/irq-renesas-intc-irqpin.h>
+#include <linux/irqchip.h>
 #include <mach/common.h>
 #include <mach/intc.h>
+#include <mach/irqs.h>
 #include <mach/r8a7779.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -38,18 +42,61 @@
 #define INT2NTSR0 IOMEM(0xfe700060)
 #define INT2NTSR1 IOMEM(0xfe700064)
 
+static struct renesas_intc_irqpin_config irqpin0_platform_data = {
+        .irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */
+        .sense_bitfield_width = 2,
+};
+
+static struct resource irqpin0_resources[] = {
+        DEFINE_RES_MEM(0xfe78001c, 4), /* ICR1 */
+        DEFINE_RES_MEM(0xfe780010, 4), /* INTPRI */
+        DEFINE_RES_MEM(0xfe780024, 4), /* INTREQ */
+        DEFINE_RES_MEM(0xfe780044, 4), /* INTMSK0 */
+        DEFINE_RES_MEM(0xfe780064, 4), /* INTMSKCLR0 */
+        DEFINE_RES_IRQ(gic_spi(27)), /* IRQ0 */
+        DEFINE_RES_IRQ(gic_spi(28)), /* IRQ1 */
+        DEFINE_RES_IRQ(gic_spi(29)), /* IRQ2 */
+        DEFINE_RES_IRQ(gic_spi(30)), /* IRQ3 */
+};
+
+static struct platform_device irqpin0_device = {
+        .name           = "renesas_intc_irqpin",
+        .id             = 0,
+        .resource       = irqpin0_resources,
+        .num_resources  = ARRAY_SIZE(irqpin0_resources),
+        .dev            = {
+                .platform_data  = &irqpin0_platform_data,
+        },
+};
+
+void __init r8a7779_init_irq_extpin(int irlm)
+{
+        void __iomem *icr0 = ioremap_nocache(0xfe780000, PAGE_SIZE);
+        unsigned long tmp;
+
+        if (icr0) {
+                tmp = ioread32(icr0);
+                if (irlm)
+                        tmp |= 1 << 23; /* IRQ0 -> IRQ3 as individual pins */
+                else
+                        tmp &= ~(1 << 23); /* IRL mode - not supported */
+                tmp |= (1 << 21); /* LVLMODE = 1 */
+                iowrite32(tmp, icr0);
+                iounmap(icr0);
+
+                if (irlm)
+                        platform_device_register(&irqpin0_device);
+        } else
+                pr_warn("r8a7779: unable to setup external irq pin mode\n");
+}
+
 static int r8a7779_set_wake(struct irq_data *data, unsigned int on)
 {
         return 0; /* always allow wakeup */
 }
 
-void __init r8a7779_init_irq(void)
+static void __init r8a7779_init_irq_common(void)
 {
-        void __iomem *gic_dist_base = IOMEM(0xf0001000);
-        void __iomem *gic_cpu_base = IOMEM(0xf0000100);
-
-        /* use GIC to handle interrupts */
-        gic_init(0, 29, gic_dist_base, gic_cpu_base);
         gic_arch_extn.irq_set_wake = r8a7779_set_wake;
 
         /* route all interrupts to ARM */
@@ -63,3 +110,22 @@ void __init r8a7779_init_irq(void)
         __raw_writel(0xbffffffc, INT2SMSKCR3);
         __raw_writel(0x003fee3f, INT2SMSKCR4);
 }
+
+void __init r8a7779_init_irq(void)
+{
+        void __iomem *gic_dist_base = IOMEM(0xf0001000);
+        void __iomem *gic_cpu_base = IOMEM(0xf0000100);
+
+        /* use GIC to handle interrupts */
+        gic_init(0, 29, gic_dist_base, gic_cpu_base);
+
+        r8a7779_init_irq_common();
+}
+
+#ifdef CONFIG_OF
+void __init r8a7779_init_irq_dt(void)
+{
+        irqchip_init();
+        r8a7779_init_irq_common();
+}
+#endif
diff --git a/arch/arm/mach-shmobile/intc-sh73a0.c b/arch/arm/mach-shmobile/intc-sh73a0.c
index 91faba666d46..19a26f4579b3 100644
--- a/arch/arm/mach-shmobile/intc-sh73a0.c
+++ b/arch/arm/mach-shmobile/intc-sh73a0.c
@@ -260,108 +260,6 @@ static int sh73a0_set_wake(struct irq_data *data, unsigned int on)
         return 0; /* always allow wakeup */
 }
 
-#define RELOC_BASE 0x1200
-
-/* INTCA IRQ pins at INTCS + RELOC_BASE to make space for GIC+INTC handling */
-#define INTCS_VECT_RELOC(n, vect) INTCS_VECT((n), (vect) + RELOC_BASE)
-
-INTC_IRQ_PINS_32(intca_irq_pins, 0xe6900000,
-                 INTCS_VECT_RELOC, "sh73a0-intca-irq-pins");
-
-static int to_gic_irq(struct irq_data *data)
-{
-        unsigned int vect = irq2evt(data->irq) - INTCS_VECT_BASE;
-
-        if (vect >= 0x3200)
-                vect -= 0x3000;
-        else
-                vect -= 0x0200;
-
-        return gic_spi((vect >> 5) + 1);
-}
-
-static int to_intca_reloc_irq(struct irq_data *data)
-{
-        return data->irq + (RELOC_BASE >> 5);
-}
-
-#define irq_cb(cb, irq) irq_get_chip(irq)->cb(irq_get_irq_data(irq))
-#define irq_cbp(cb, irq, p...) irq_get_chip(irq)->cb(irq_get_irq_data(irq), p)
-
-static void intca_gic_enable(struct irq_data *data)
-{
-        irq_cb(irq_unmask, to_intca_reloc_irq(data));
-        irq_cb(irq_unmask, to_gic_irq(data));
-}
-
-static void intca_gic_disable(struct irq_data *data)
-{
-        irq_cb(irq_mask, to_gic_irq(data));
-        irq_cb(irq_mask, to_intca_reloc_irq(data));
-}
-
-static void intca_gic_mask_ack(struct irq_data *data)
-{
-        irq_cb(irq_mask, to_gic_irq(data));
-        irq_cb(irq_mask_ack, to_intca_reloc_irq(data));
-}
-
-static void intca_gic_eoi(struct irq_data *data)
-{
-        irq_cb(irq_eoi, to_gic_irq(data));
-}
-
-static int intca_gic_set_type(struct irq_data *data, unsigned int type)
-{
-        return irq_cbp(irq_set_type, to_intca_reloc_irq(data), type);
-}
-
-#ifdef CONFIG_SMP
-static int intca_gic_set_affinity(struct irq_data *data,
-                                  const struct cpumask *cpumask,
-                                  bool force)
-{
-        return irq_cbp(irq_set_affinity, to_gic_irq(data), cpumask, force);
-}
-#endif
-
-struct irq_chip intca_gic_irq_chip = {
-        .name                   = "INTCA-GIC",
-        .irq_mask               = intca_gic_disable,
-        .irq_unmask             = intca_gic_enable,
-        .irq_mask_ack           = intca_gic_mask_ack,
-        .irq_eoi                = intca_gic_eoi,
-        .irq_enable             = intca_gic_enable,
-        .irq_disable            = intca_gic_disable,
-        .irq_shutdown           = intca_gic_disable,
-        .irq_set_type           = intca_gic_set_type,
-        .irq_set_wake           = sh73a0_set_wake,
-#ifdef CONFIG_SMP
-        .irq_set_affinity       = intca_gic_set_affinity,
-#endif
-};
-
-static int to_intc_vect(int irq)
-{
-        unsigned int irq_pin = irq - gic_spi(1);
-        unsigned int offs;
-
-        if (irq_pin < 16)
-                offs = 0x0200;
-        else
-                offs = 0x3000;
-
-        return offs + (irq_pin << 5);
-}
-
-static irqreturn_t sh73a0_irq_pin_demux(int irq, void *dev_id)
-{
-        generic_handle_irq(intcs_evt2irq(to_intc_vect(irq)));
-        return IRQ_HANDLED;
-}
-
-static struct irqaction sh73a0_irq_pin_cascade[32];
-
 #define PINTER0_PHYS 0xe69000a0
 #define PINTER1_PHYS 0xe69000a4
 #define PINTER0_VIRT IOMEM(0xe69000a0)
@@ -422,13 +320,11 @@ void __init sh73a0_init_irq(void)
         void __iomem *gic_dist_base = IOMEM(0xf0001000);
         void __iomem *gic_cpu_base = IOMEM(0xf0000100);
         void __iomem *intevtsa = ioremap_nocache(0xffd20100, PAGE_SIZE);
-        int k, n;
 
         gic_init(0, 29, gic_dist_base, gic_cpu_base);
         gic_arch_extn.irq_set_wake = sh73a0_set_wake;
 
         register_intc_controller(&intcs_desc);
-        register_intc_controller(&intca_irq_pins_desc);
         register_intc_controller(&intc_pint0_desc);
         register_intc_controller(&intc_pint1_desc);
 
@@ -438,19 +334,6 @@ void __init sh73a0_init_irq(void)
         sh73a0_intcs_cascade.dev_id = intevtsa;
         setup_irq(gic_spi(50), &sh73a0_intcs_cascade);
 
-        /* IRQ pins require special handling through INTCA and GIC */
-        for (k = 0; k < 32; k++) {
-                sh73a0_irq_pin_cascade[k].name = "INTCA-GIC cascade";
-                sh73a0_irq_pin_cascade[k].handler = sh73a0_irq_pin_demux;
-                setup_irq(gic_spi(1 + k), &sh73a0_irq_pin_cascade[k]);
-
-                n = intcs_evt2irq(to_intc_vect(gic_spi(1 + k)));
-                WARN_ON(irq_alloc_desc_at(n, numa_node_id()) != n);
-                irq_set_chip_and_handler_name(n, &intca_gic_irq_chip,
-                                              handle_level_irq, "level");
-                set_irq_flags(n, IRQF_VALID); /* yuck */
-        }
-
         /* PINT pins are sanely tied to the GIC as SPI */
         sh73a0_pint0_cascade.name = "PINT0 cascade";
         sh73a0_pint0_cascade.handler = sh73a0_pint0_demux;
@@ -460,11 +343,3 @@ void __init sh73a0_init_irq(void)
         sh73a0_pint1_cascade.handler = sh73a0_pint1_demux;
         setup_irq(gic_spi(34), &sh73a0_pint1_cascade);
 }
-
-#ifdef CONFIG_OF
-void __init sh73a0_init_irq_dt(void)
-{
-        irqchip_init();
-        gic_arch_extn.irq_set_wake = sh73a0_set_wake;
-}
-#endif
diff --git a/arch/arm/mach-shmobile/setup-emev2.c b/arch/arm/mach-shmobile/setup-emev2.c
index 47662a581c0a..899a86c31ec9 100644
--- a/arch/arm/mach-shmobile/setup-emev2.c
+++ b/arch/arm/mach-shmobile/setup-emev2.c
@@ -404,7 +404,7 @@ void __init emev2_add_standard_devices(void)
                              ARRAY_SIZE(emev2_late_devices));
 }
 
-void __init emev2_init_delay(void)
+static void __init emev2_init_delay(void)
 {
         shmobile_setup_delay(533, 1, 3); /* Cortex-A9 @ 533MHz */
 }
@@ -439,7 +439,7 @@ static const struct of_dev_auxdata emev2_auxdata_lookup[] __initconst = {
         { }
 };
 
-void __init emev2_add_standard_devices_dt(void)
+static void __init emev2_add_standard_devices_dt(void)
 {
         of_platform_populate(NULL, of_default_bus_match_table,
                              emev2_auxdata_lookup, NULL);
@@ -456,7 +456,6 @@ DT_MACHINE_START(EMEV2_DT, "Generic Emma Mobile EV2 (Flattened Device Tree)")
         .nr_irqs        = NR_IRQS_LEGACY,
         .init_irq       = irqchip_init,
         .init_machine   = emev2_add_standard_devices_dt,
-        .init_time      = shmobile_timer_init,
         .dt_compat      = emev2_boards_compat_dt,
 MACHINE_END
 
diff --git a/arch/arm/mach-shmobile/setup-r8a7740.c b/arch/arm/mach-shmobile/setup-r8a7740.c
index 8b85d4d8fab6..104b474a2ccf 100644
--- a/arch/arm/mach-shmobile/setup-r8a7740.c
+++ b/arch/arm/mach-shmobile/setup-r8a7740.c
@@ -906,7 +906,6 @@ DT_MACHINE_START(R8A7740_DT, "Generic R8A7740 (Flattened Device Tree)")
         .init_irq       = r8a7740_init_irq,
         .handle_irq     = shmobile_handle_irq_intc,
         .init_machine   = r8a7740_add_standard_devices_dt,
-        .init_time      = shmobile_timer_init,
         .dt_compat      = r8a7740_boards_compat_dt,
 MACHINE_END
 
diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c
index c54ff9b29fe5..042df35e71a0 100644
--- a/arch/arm/mach-shmobile/setup-r8a7779.c
+++ b/arch/arm/mach-shmobile/setup-r8a7779.c
@@ -21,6 +21,7 @@
 #include <linux/init.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>
+#include <linux/of_platform.h>
 #include <linux/platform_device.h>
 #include <linux/delay.h>
 #include <linux/input.h>
@@ -28,6 +29,7 @@
 #include <linux/serial_sci.h>
 #include <linux/sh_intc.h>
 #include <linux/sh_timer.h>
+#include <linux/dma-mapping.h>
 #include <mach/hardware.h>
 #include <mach/irqs.h>
 #include <mach/r8a7779.h>
@@ -91,7 +93,7 @@ static struct plat_sci_port scif0_platform_data = {
         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
         .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
-        .irqs           = SCIx_IRQ_MUXED(gic_spi(88)),
+        .irqs           = SCIx_IRQ_MUXED(gic_iid(0x78)),
 };
 
 static struct platform_device scif0_device = {
@@ -108,7 +110,7 @@ static struct plat_sci_port scif1_platform_data = {
         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
         .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
-        .irqs           = SCIx_IRQ_MUXED(gic_spi(89)),
+        .irqs           = SCIx_IRQ_MUXED(gic_iid(0x79)),
 };
 
 static struct platform_device scif1_device = {
@@ -125,7 +127,7 @@ static struct plat_sci_port scif2_platform_data = {
         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
         .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
-        .irqs           = SCIx_IRQ_MUXED(gic_spi(90)),
+        .irqs           = SCIx_IRQ_MUXED(gic_iid(0x7a)),
 };
 
 static struct platform_device scif2_device = {
@@ -142,7 +144,7 @@ static struct plat_sci_port scif3_platform_data = {
         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
         .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
-        .irqs           = SCIx_IRQ_MUXED(gic_spi(91)),
+        .irqs           = SCIx_IRQ_MUXED(gic_iid(0x7b)),
 };
 
 static struct platform_device scif3_device = {
@@ -159,7 +161,7 @@ static struct plat_sci_port scif4_platform_data = {
         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
         .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
-        .irqs           = SCIx_IRQ_MUXED(gic_spi(92)),
+        .irqs           = SCIx_IRQ_MUXED(gic_iid(0x7c)),
 };
 
 static struct platform_device scif4_device = {
@@ -176,7 +178,7 @@ static struct plat_sci_port scif5_platform_data = {
         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
         .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
-        .irqs           = SCIx_IRQ_MUXED(gic_spi(93)),
+        .irqs           = SCIx_IRQ_MUXED(gic_iid(0x7d)),
 };
 
 static struct platform_device scif5_device = {
@@ -203,7 +205,7 @@ static struct resource tmu00_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = gic_spi(32),
+                .start  = gic_iid(0x40),
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -233,7 +235,7 @@ static struct resource tmu01_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = gic_spi(33),
+                .start  = gic_iid(0x41),
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -255,7 +257,7 @@ static struct resource rcar_i2c0_res[] = {
                 .end    = 0xffc70fff,
                 .flags  = IORESOURCE_MEM,
         }, {
-                .start  = gic_spi(79),
+                .start  = gic_iid(0x6f),
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -273,7 +275,7 @@ static struct resource rcar_i2c1_res[] = {
                 .end    = 0xffc71fff,
                 .flags  = IORESOURCE_MEM,
         }, {
-                .start  = gic_spi(82),
+                .start  = gic_iid(0x72),
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -291,7 +293,7 @@ static struct resource rcar_i2c2_res[] = {
                 .end    = 0xffc72fff,
                 .flags  = IORESOURCE_MEM,
         }, {
-                .start  = gic_spi(80),
+                .start  = gic_iid(0x70),
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -309,7 +311,7 @@ static struct resource rcar_i2c3_res[] = {
                 .end    = 0xffc73fff,
                 .flags  = IORESOURCE_MEM,
         }, {
-                .start  = gic_spi(81),
+                .start  = gic_iid(0x71),
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -321,7 +323,31 @@ static struct platform_device i2c3_device = {
         .num_resources  = ARRAY_SIZE(rcar_i2c3_res),
 };
 
-static struct platform_device *r8a7779_early_devices[] __initdata = {
+static struct resource sata_resources[] = {
+        [0] = {
+                .name   = "rcar-sata",
+                .start  = 0xfc600000,
+                .end    = 0xfc601fff,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = gic_iid(0x84),
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device sata_device = {
+        .name           = "sata_rcar",
+        .id             = -1,
+        .resource       = sata_resources,
+        .num_resources  = ARRAY_SIZE(sata_resources),
+        .dev            = {
+                .dma_mask               = &sata_device.dev.coherent_dma_mask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        },
+};
+
+static struct platform_device *r8a7779_devices_dt[] __initdata = {
         &scif0_device,
         &scif1_device,
         &scif2_device,
@@ -330,13 +356,14 @@ static struct platform_device *r8a7779_early_devices[] __initdata = {
         &scif5_device,
         &tmu00_device,
         &tmu01_device,
+};
+
+static struct platform_device *r8a7779_late_devices[] __initdata = {
         &i2c0_device,
         &i2c1_device,
         &i2c2_device,
         &i2c3_device,
-};
-
-static struct platform_device *r8a7779_late_devices[] __initdata = {
+        &sata_device,
 };
 
 void __init r8a7779_add_standard_devices(void)
@@ -349,8 +376,8 @@ void __init r8a7779_add_standard_devices(void)
 
         r8a7779_init_pm_domains();
 
-        platform_add_devices(r8a7779_early_devices,
-                            ARRAY_SIZE(r8a7779_early_devices));
+        platform_add_devices(r8a7779_devices_dt,
+                            ARRAY_SIZE(r8a7779_devices_dt));
         platform_add_devices(r8a7779_late_devices,
                             ARRAY_SIZE(r8a7779_late_devices));
 }
@@ -367,8 +394,8 @@ void __init r8a7779_earlytimer_init(void)
 
 void __init r8a7779_add_early_devices(void)
 {
-        early_platform_add_devices(r8a7779_early_devices,
-                                   ARRAY_SIZE(r8a7779_early_devices));
+        early_platform_add_devices(r8a7779_devices_dt,
+                                   ARRAY_SIZE(r8a7779_devices_dt));
 
         /* Early serial console setup is not included here due to
          * memory map collisions. The SCIF serial ports in r8a7779
@@ -386,3 +413,40 @@ void __init r8a7779_add_early_devices(void)
          * command line in case of the marzen board.
          */
 }
+
+#ifdef CONFIG_USE_OF
+void __init r8a7779_init_delay(void)
+{
+        shmobile_setup_delay(1000, 2, 4); /* Cortex-A9 @ 1000MHz */
+}
+
+static const struct of_dev_auxdata r8a7779_auxdata_lookup[] __initconst = {
+        {},
+};
+
+void __init r8a7779_add_standard_devices_dt(void)
+{
+        /* clocks are setup late during boot in the case of DT */
+        r8a7779_clock_init();
+
+        platform_add_devices(r8a7779_devices_dt,
+                             ARRAY_SIZE(r8a7779_devices_dt));
+        of_platform_populate(NULL, of_default_bus_match_table,
+                             r8a7779_auxdata_lookup, NULL);
+}
+
+static const char *r8a7779_compat_dt[] __initdata = {
+        "renesas,r8a7779",
+        NULL,
+};
+
+DT_MACHINE_START(R8A7779_DT, "Generic R8A7779 (Flattened Device Tree)")
+        .map_io         = r8a7779_map_io,
+        .init_early     = r8a7779_init_delay,
+        .nr_irqs        = NR_IRQS_LEGACY,
+        .init_irq       = r8a7779_init_irq_dt,
+        .init_machine   = r8a7779_add_standard_devices_dt,
+        .init_time      = shmobile_timer_init,
+        .dt_compat      = r8a7779_compat_dt,
+MACHINE_END
+#endif /* CONFIG_USE_OF */
diff --git a/arch/arm/mach-shmobile/setup-sh7372.c b/arch/arm/mach-shmobile/setup-sh7372.c
index 59c7146bf66f..5502d624aca6 100644
--- a/arch/arm/mach-shmobile/setup-sh7372.c
+++ b/arch/arm/mach-shmobile/setup-sh7372.c
@@ -1175,7 +1175,6 @@ DT_MACHINE_START(SH7372_DT, "Generic SH7372 (Flattened Device Tree)")
         .init_irq       = sh7372_init_irq,
         .handle_irq     = shmobile_handle_irq_intc,
         .init_machine   = sh7372_add_standard_devices_dt,
-        .init_time      = shmobile_timer_init,
         .dt_compat      = sh7372_boards_compat_dt,
 MACHINE_END
 
diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c
index bdab575f88bc..fdf3894b1cc3 100644
--- a/arch/arm/mach-shmobile/setup-sh73a0.c
+++ b/arch/arm/mach-shmobile/setup-sh73a0.c
@@ -22,6 +22,7 @@
 #include <linux/init.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>
+#include <linux/irqchip.h>
 #include <linux/platform_device.h>
 #include <linux/of_platform.h>
 #include <linux/delay.h>
@@ -32,6 +33,7 @@
 #include <linux/sh_intc.h>
 #include <linux/sh_timer.h>
 #include <linux/platform_data/sh_ipmmu.h>
+#include <linux/platform_data/irq-renesas-intc-irqpin.h>
 #include <mach/dma-register.h>
 #include <mach/hardware.h>
 #include <mach/irqs.h>
@@ -810,7 +812,128 @@ static struct platform_device ipmmu_device = {
         .num_resources  = ARRAY_SIZE(ipmmu_resources),
 };
 
-static struct platform_device *sh73a0_early_devices_dt[] __initdata = {
+static struct renesas_intc_irqpin_config irqpin0_platform_data = {
+        .irq_base = irq_pin(0), /* IRQ0 -> IRQ7 */
+};
+
+static struct resource irqpin0_resources[] = {
+        DEFINE_RES_MEM(0xe6900000, 4), /* ICR1A */
+        DEFINE_RES_MEM(0xe6900010, 4), /* INTPRI00A */
+        DEFINE_RES_MEM(0xe6900020, 1), /* INTREQ00A */
+        DEFINE_RES_MEM(0xe6900040, 1), /* INTMSK00A */
+        DEFINE_RES_MEM(0xe6900060, 1), /* INTMSKCLR00A */
+        DEFINE_RES_IRQ(gic_spi(1)), /* IRQ0 */
+        DEFINE_RES_IRQ(gic_spi(2)), /* IRQ1 */
+        DEFINE_RES_IRQ(gic_spi(3)), /* IRQ2 */
+        DEFINE_RES_IRQ(gic_spi(4)), /* IRQ3 */
+        DEFINE_RES_IRQ(gic_spi(5)), /* IRQ4 */
+        DEFINE_RES_IRQ(gic_spi(6)), /* IRQ5 */
+        DEFINE_RES_IRQ(gic_spi(7)), /* IRQ6 */
+        DEFINE_RES_IRQ(gic_spi(8)), /* IRQ7 */
+};
+
+static struct platform_device irqpin0_device = {
+        .name           = "renesas_intc_irqpin",
+        .id             = 0,
+        .resource       = irqpin0_resources,
+        .num_resources  = ARRAY_SIZE(irqpin0_resources),
+        .dev            = {
+                .platform_data  = &irqpin0_platform_data,
+        },
+};
+
+static struct renesas_intc_irqpin_config irqpin1_platform_data = {
+        .irq_base = irq_pin(8), /* IRQ8 -> IRQ15 */
+        .control_parent = true, /* Disable spurious IRQ10 */
+};
+
+static struct resource irqpin1_resources[] = {
+        DEFINE_RES_MEM(0xe6900004, 4), /* ICR2A */
+        DEFINE_RES_MEM(0xe6900014, 4), /* INTPRI10A */
+        DEFINE_RES_MEM(0xe6900024, 1), /* INTREQ10A */
+        DEFINE_RES_MEM(0xe6900044, 1), /* INTMSK10A */
+        DEFINE_RES_MEM(0xe6900064, 1), /* INTMSKCLR10A */
+        DEFINE_RES_IRQ(gic_spi(9)), /* IRQ8 */
+        DEFINE_RES_IRQ(gic_spi(10)), /* IRQ9 */
+        DEFINE_RES_IRQ(gic_spi(11)), /* IRQ10 */
+        DEFINE_RES_IRQ(gic_spi(12)), /* IRQ11 */
+        DEFINE_RES_IRQ(gic_spi(13)), /* IRQ12 */
+        DEFINE_RES_IRQ(gic_spi(14)), /* IRQ13 */
+        DEFINE_RES_IRQ(gic_spi(15)), /* IRQ14 */
+        DEFINE_RES_IRQ(gic_spi(16)), /* IRQ15 */
+};
+
+static struct platform_device irqpin1_device = {
+        .name           = "renesas_intc_irqpin",
+        .id             = 1,
+        .resource       = irqpin1_resources,
+        .num_resources  = ARRAY_SIZE(irqpin1_resources),
+        .dev            = {
+                .platform_data  = &irqpin1_platform_data,
+        },
+};
+
+static struct renesas_intc_irqpin_config irqpin2_platform_data = {
+        .irq_base = irq_pin(16), /* IRQ16 -> IRQ23 */
+};
+
+static struct resource irqpin2_resources[] = {
+        DEFINE_RES_MEM(0xe6900008, 4), /* ICR3A */
+        DEFINE_RES_MEM(0xe6900018, 4), /* INTPRI20A */
+        DEFINE_RES_MEM(0xe6900028, 1), /* INTREQ20A */
+        DEFINE_RES_MEM(0xe6900048, 1), /* INTMSK20A */
+        DEFINE_RES_MEM(0xe6900068, 1), /* INTMSKCLR20A */
+        DEFINE_RES_IRQ(gic_spi(17)), /* IRQ16 */
+        DEFINE_RES_IRQ(gic_spi(18)), /* IRQ17 */
+        DEFINE_RES_IRQ(gic_spi(19)), /* IRQ18 */
+        DEFINE_RES_IRQ(gic_spi(20)), /* IRQ19 */
+        DEFINE_RES_IRQ(gic_spi(21)), /* IRQ20 */
+        DEFINE_RES_IRQ(gic_spi(22)), /* IRQ21 */
+        DEFINE_RES_IRQ(gic_spi(23)), /* IRQ22 */
+        DEFINE_RES_IRQ(gic_spi(24)), /* IRQ23 */
+};
+
+static struct platform_device irqpin2_device = {
+        .name           = "renesas_intc_irqpin",
+        .id             = 2,
+        .resource       = irqpin2_resources,
+        .num_resources  = ARRAY_SIZE(irqpin2_resources),
+        .dev            = {
+                .platform_data  = &irqpin2_platform_data,
+        },
+};
+
+static struct renesas_intc_irqpin_config irqpin3_platform_data = {
+        .irq_base = irq_pin(24), /* IRQ24 -> IRQ31 */
+};
+
+static struct resource irqpin3_resources[] = {
+        DEFINE_RES_MEM(0xe690000c, 4), /* ICR4A */
+        DEFINE_RES_MEM(0xe690001c, 4), /* INTPRI30A */
+        DEFINE_RES_MEM(0xe690002c, 1), /* INTREQ30A */
+        DEFINE_RES_MEM(0xe690004c, 1), /* INTMSK30A */
+        DEFINE_RES_MEM(0xe690006c, 1), /* INTMSKCLR30A */
+        DEFINE_RES_IRQ(gic_spi(25)), /* IRQ24 */
+        DEFINE_RES_IRQ(gic_spi(26)), /* IRQ25 */
+        DEFINE_RES_IRQ(gic_spi(27)), /* IRQ26 */
+        DEFINE_RES_IRQ(gic_spi(28)), /* IRQ27 */
+        DEFINE_RES_IRQ(gic_spi(29)), /* IRQ28 */
+        DEFINE_RES_IRQ(gic_spi(30)), /* IRQ29 */
+        DEFINE_RES_IRQ(gic_spi(31)), /* IRQ30 */
+        DEFINE_RES_IRQ(gic_spi(32)), /* IRQ31 */
+};
+
+static struct platform_device irqpin3_device = {
+        .name           = "renesas_intc_irqpin",
+        .id             = 3,
+        .resource       = irqpin3_resources,
+        .num_resources  = ARRAY_SIZE(irqpin3_resources),
+        .dev            = {
+                .platform_data  = &irqpin3_platform_data,
+        },
+};
+
+static struct platform_device *sh73a0_devices_dt[] __initdata = {
         &scif0_device,
         &scif1_device,
         &scif2_device,
@@ -838,6 +961,10 @@ static struct platform_device *sh73a0_late_devices[] __initdata = {
         &dma0_device,
         &mpdma0_device,
         &pmu_device,
+        &irqpin0_device,
+        &irqpin1_device,
+        &irqpin2_device,
+        &irqpin3_device,
 };
 
 #define SRCR2          IOMEM(0xe61580b0)
@@ -847,8 +974,8 @@ void __init sh73a0_add_standard_devices(void)
         /* Clear software reset bit on SY-DMAC module */
         __raw_writel(__raw_readl(SRCR2) & ~(1 << 18), SRCR2);
 
-        platform_add_devices(sh73a0_early_devices_dt,
-                            ARRAY_SIZE(sh73a0_early_devices_dt));
+        platform_add_devices(sh73a0_devices_dt,
+                            ARRAY_SIZE(sh73a0_devices_dt));
         platform_add_devices(sh73a0_early_devices,
                             ARRAY_SIZE(sh73a0_early_devices));
         platform_add_devices(sh73a0_late_devices,
@@ -867,8 +994,8 @@ void __init sh73a0_earlytimer_init(void)
 
 void __init sh73a0_add_early_devices(void)
 {
-        early_platform_add_devices(sh73a0_early_devices_dt,
-                                   ARRAY_SIZE(sh73a0_early_devices_dt));
+        early_platform_add_devices(sh73a0_devices_dt,
+                                   ARRAY_SIZE(sh73a0_devices_dt));
         early_platform_add_devices(sh73a0_early_devices,
                                    ARRAY_SIZE(sh73a0_early_devices));
 
@@ -878,23 +1005,9 @@ void __init sh73a0_add_early_devices(void)
 
 #ifdef CONFIG_USE_OF
 
-/* Please note that the clock initialisation shcheme used in
- * sh73a0_add_early_devices_dt() and sh73a0_add_standard_devices_dt()
- * does not work with SMP as there is a yet to be resolved lock-up in
- * workqueue initialisation.
- *
- * CONFIG_SMP should be disabled when using this code.
- */
-
-void __init sh73a0_add_early_devices_dt(void)
+void __init sh73a0_init_delay(void)
 {
         shmobile_setup_delay(1196, 44, 46); /* Cortex-A9 @ 1196MHz */
-
-        early_platform_add_devices(sh73a0_early_devices_dt,
-                                   ARRAY_SIZE(sh73a0_early_devices_dt));
-
-        /* setup early console here as well */
-        shmobile_setup_console();
 }
 
 static const struct of_dev_auxdata sh73a0_auxdata_lookup[] __initconst = {
@@ -906,8 +1019,8 @@ void __init sh73a0_add_standard_devices_dt(void)
         /* clocks are setup late during boot in the case of DT */
         sh73a0_clock_init();
 
-        platform_add_devices(sh73a0_early_devices_dt,
-                             ARRAY_SIZE(sh73a0_early_devices_dt));
+        platform_add_devices(sh73a0_devices_dt,
+                             ARRAY_SIZE(sh73a0_devices_dt));
         of_platform_populate(NULL, of_default_bus_match_table,
                              sh73a0_auxdata_lookup, NULL);
 }
@@ -918,12 +1031,12 @@ static const char *sh73a0_boards_compat_dt[] __initdata = {
 };
 
 DT_MACHINE_START(SH73A0_DT, "Generic SH73A0 (Flattened Device Tree)")
+        .smp            = smp_ops(sh73a0_smp_ops),
         .map_io         = sh73a0_map_io,
-        .init_early     = sh73a0_add_early_devices_dt,
+        .init_early     = sh73a0_init_delay,
         .nr_irqs        = NR_IRQS_LEGACY,
-        .init_irq       = sh73a0_init_irq_dt,
+        .init_irq       = irqchip_init,
         .init_machine   = sh73a0_add_standard_devices_dt,
-        .init_time      = shmobile_timer_init,
         .dt_compat      = sh73a0_boards_compat_dt,
 MACHINE_END
 #endif /* CONFIG_USE_OF */
diff --git a/arch/arm/mach-shmobile/smp-emev2.c b/arch/arm/mach-shmobile/smp-emev2.c
index 953eb1f9388d..8225c16b371b 100644
--- a/arch/arm/mach-shmobile/smp-emev2.c
+++ b/arch/arm/mach-shmobile/smp-emev2.c
@@ -28,63 +28,9 @@
 #include <mach/emev2.h>
 #include <asm/smp_plat.h>
 #include <asm/smp_scu.h>
-#include <asm/cacheflush.h>
 
 #define EMEV2_SCU_BASE 0x1e000000
 
-static DEFINE_SPINLOCK(scu_lock);
-static void __iomem *scu_base;
-
-static void modify_scu_cpu_psr(unsigned long set, unsigned long clr)
-{
-        unsigned long tmp;
-
-        /* we assume this code is running on a different cpu
-         * than the one that is changing coherency setting */
-        spin_lock(&scu_lock);
-        tmp = readl(scu_base + 8);
-        tmp &= ~clr;
-        tmp |= set;
-        writel(tmp, scu_base + 8);
-        spin_unlock(&scu_lock);
-
-}
-
-static unsigned int __init emev2_get_core_count(void)
-{
-        if (!scu_base) {
-                scu_base = ioremap(EMEV2_SCU_BASE, PAGE_SIZE);
-                emev2_clock_init(); /* need ioremapped SMU */
-        }
-
-        WARN_ON_ONCE(!scu_base);
-
-        return scu_base ? scu_get_core_count(scu_base) : 1;
-}
-
-static int emev2_platform_cpu_kill(unsigned int cpu)
-{
-        return 0; /* not supported yet */
-}
-
-static int __maybe_unused emev2_cpu_kill(unsigned int cpu)
-{
-        int k;
-
-        /* this function is running on another CPU than the offline target,
-         * here we need wait for shutdown code in platform_cpu_die() to
-         * finish before asking SoC-specific code to power off the CPU core.
-         */
-        for (k = 0; k < 1000; k++) {
-                if (shmobile_cpu_is_dead(cpu))
-                        return emev2_platform_cpu_kill(cpu);
-                mdelay(1);
-        }
-
-        return 0;
-}
-
-
 static void __cpuinit emev2_secondary_init(unsigned int cpu)
 {
         gic_secondary_init(0);
@@ -92,31 +38,30 @@ static void __cpuinit emev2_secondary_init(unsigned int cpu)
 
 static int __cpuinit emev2_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
-        cpu = cpu_logical_map(cpu);
-
-        /* enable cache coherency */
-        modify_scu_cpu_psr(0, 3 << (cpu * 8));
-
-        /* Tell ROM loader about our vector (in headsmp.S) */
-        emev2_set_boot_vector(__pa(shmobile_secondary_vector));
-
-        arch_send_wakeup_ipi_mask(cpumask_of(cpu));
+        arch_send_wakeup_ipi_mask(cpumask_of(cpu_logical_map(cpu)));
         return 0;
 }
 
 static void __init emev2_smp_prepare_cpus(unsigned int max_cpus)
 {
-        int cpu = cpu_logical_map(0);
+        scu_enable(shmobile_scu_base);
 
-        scu_enable(scu_base);
+        /* Tell ROM loader about our vector (in headsmp-scu.S) */
+        emev2_set_boot_vector(__pa(shmobile_secondary_vector_scu));
 
-        /* enable cache coherency on CPU0 */
-        modify_scu_cpu_psr(0, 3 << (cpu * 8));
+        /* enable cache coherency on booting CPU */
+        scu_power_mode(shmobile_scu_base, SCU_PM_NORMAL);
 }
 
 static void __init emev2_smp_init_cpus(void)
 {
-        unsigned int ncores = emev2_get_core_count();
+        unsigned int ncores;
+
+        /* setup EMEV2 specific SCU base */
+        shmobile_scu_base = ioremap(EMEV2_SCU_BASE, PAGE_SIZE);
+        emev2_clock_init(); /* need ioremapped SMU */
+
+        ncores = shmobile_scu_base ? scu_get_core_count(shmobile_scu_base) : 1;
 
         shmobile_smp_init_cpus(ncores);
 }
@@ -126,9 +71,4 @@ struct smp_operations emev2_smp_ops __initdata = {
         .smp_prepare_cpus       = emev2_smp_prepare_cpus,
         .smp_secondary_init     = emev2_secondary_init,
         .smp_boot_secondary     = emev2_boot_secondary,
-#ifdef CONFIG_HOTPLUG_CPU
-        .cpu_kill               = emev2_cpu_kill,
-        .cpu_die                = shmobile_cpu_die,
-        .cpu_disable            = shmobile_cpu_disable,
-#endif
 };
diff --git a/arch/arm/mach-shmobile/smp-r8a7779.c b/arch/arm/mach-shmobile/smp-r8a7779.c
index 3a4acf23edcf..ea4535a5c4e2 100644
--- a/arch/arm/mach-shmobile/smp-r8a7779.c
+++ b/arch/arm/mach-shmobile/smp-r8a7779.c
@@ -26,11 +26,13 @@
 #include <linux/irqchip/arm-gic.h>
 #include <mach/common.h>
 #include <mach/r8a7779.h>
+#include <asm/cacheflush.h>
 #include <asm/smp_plat.h>
 #include <asm/smp_scu.h>
 #include <asm/smp_twd.h>
 
 #define AVECR IOMEM(0xfe700040)
+#define R8A7779_SCU_BASE 0xf0000000
 
 static struct r8a7779_pm_ch r8a7779_ch_cpu1 = {
         .chan_offs = 0x40, /* PWRSR0 .. PWRER0 */
@@ -56,44 +58,14 @@ static struct r8a7779_pm_ch *r8a7779_ch_cpu[4] = {
         [3] = &r8a7779_ch_cpu3,
 };
 
-static void __iomem *scu_base_addr(void)
-{
-        return (void __iomem *)0xf0000000;
-}
-
-static DEFINE_SPINLOCK(scu_lock);
-static unsigned long tmp;
-
 #ifdef CONFIG_HAVE_ARM_TWD
-static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, 0xf0000600, 29);
-
+static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, R8A7779_SCU_BASE + 0x600, 29);
 void __init r8a7779_register_twd(void)
 {
         twd_local_timer_register(&twd_local_timer);
 }
 #endif
 
-static void modify_scu_cpu_psr(unsigned long set, unsigned long clr)
-{
-        void __iomem *scu_base = scu_base_addr();
-
-        spin_lock(&scu_lock);
-        tmp = __raw_readl(scu_base + 8);
-        tmp &= ~clr;
-        tmp |= set;
-        spin_unlock(&scu_lock);
-
-        /* disable cache coherency after releasing the lock */
-        __raw_writel(tmp, scu_base + 8);
-}
-
-static unsigned int __init r8a7779_get_core_count(void)
-{
-        void __iomem *scu_base = scu_base_addr();
-
-        return scu_get_core_count(scu_base);
-}
-
 static int r8a7779_platform_cpu_kill(unsigned int cpu)
 {
         struct r8a7779_pm_ch *ch = NULL;
@@ -101,9 +73,6 @@ static int r8a7779_platform_cpu_kill(unsigned int cpu)
 
         cpu = cpu_logical_map(cpu);
 
-        /* disable cache coherency */
-        modify_scu_cpu_psr(3 << (cpu * 8), 0);
-
         if (cpu < ARRAY_SIZE(r8a7779_ch_cpu))
                 ch = r8a7779_ch_cpu[cpu];
 
@@ -113,25 +82,6 @@ static int r8a7779_platform_cpu_kill(unsigned int cpu)
         return ret ? ret : 1;
 }
 
-static int __maybe_unused r8a7779_cpu_kill(unsigned int cpu)
-{
-        int k;
-
-        /* this function is running on another CPU than the offline target,
-         * here we need wait for shutdown code in platform_cpu_die() to
-         * finish before asking SoC-specific code to power off the CPU core.
-         */
-        for (k = 0; k < 1000; k++) {
-                if (shmobile_cpu_is_dead(cpu))
-                        return r8a7779_platform_cpu_kill(cpu);
-
-                mdelay(1);
-        }
-
-        return 0;
-}
-
-
 static void __cpuinit r8a7779_secondary_init(unsigned int cpu)
 {
         gic_secondary_init(0);
@@ -144,9 +94,6 @@ static int __cpuinit r8a7779_boot_secondary(unsigned int cpu, struct task_struct
 
         cpu = cpu_logical_map(cpu);
 
-        /* enable cache coherency */
-        modify_scu_cpu_psr(0, 3 << (cpu * 8));
-
         if (cpu < ARRAY_SIZE(r8a7779_ch_cpu))
                 ch = r8a7779_ch_cpu[cpu];
 
@@ -158,15 +105,13 @@ static int __cpuinit r8a7779_boot_secondary(unsigned int cpu, struct task_struct
 
 static void __init r8a7779_smp_prepare_cpus(unsigned int max_cpus)
 {
-        int cpu = cpu_logical_map(0);
+        scu_enable(shmobile_scu_base);
 
-        scu_enable(scu_base_addr());
+        /* Map the reset vector (in headsmp-scu.S) */
+        __raw_writel(__pa(shmobile_secondary_vector_scu), AVECR);
 
-        /* Map the reset vector (in headsmp.S) */
-        __raw_writel(__pa(shmobile_secondary_vector), AVECR);
-
-        /* enable cache coherency on CPU0 */
-        modify_scu_cpu_psr(0, 3 << (cpu * 8));
+        /* enable cache coherency on booting CPU */
+        scu_power_mode(shmobile_scu_base, SCU_PM_NORMAL);
 
         r8a7779_pm_init();
 
@@ -178,10 +123,60 @@ static void __init r8a7779_smp_prepare_cpus(unsigned int max_cpus)
 
 static void __init r8a7779_smp_init_cpus(void)
 {
-        unsigned int ncores = r8a7779_get_core_count();
+        /* setup r8a7779 specific SCU base */
+        shmobile_scu_base = IOMEM(R8A7779_SCU_BASE);
+
+        shmobile_smp_init_cpus(scu_get_core_count(shmobile_scu_base));
+}
 
-        shmobile_smp_init_cpus(ncores);
+#ifdef CONFIG_HOTPLUG_CPU
+static int r8a7779_scu_psr_core_disabled(int cpu)
+{
+        unsigned long mask = 3 << (cpu * 8);
+
+        if ((__raw_readl(shmobile_scu_base + 8) & mask) == mask)
+                return 1;
+
+        return 0;
+}
+
+static int r8a7779_cpu_kill(unsigned int cpu)
+{
+        int k;
+
+        /* this function is running on another CPU than the offline target,
+         * here we need wait for shutdown code in platform_cpu_die() to
+         * finish before asking SoC-specific code to power off the CPU core.
+         */
+        for (k = 0; k < 1000; k++) {
+                if (r8a7779_scu_psr_core_disabled(cpu))
+                        return r8a7779_platform_cpu_kill(cpu);
+
+                mdelay(1);
+        }
+
+        return 0;
+}
+
+static void r8a7779_cpu_die(unsigned int cpu)
+{
+        dsb();
+        flush_cache_all();
+
+        /* disable cache coherency */
+        scu_power_mode(shmobile_scu_base, SCU_PM_POWEROFF);
+
+        /* Endless loop until power off from r8a7779_cpu_kill() */
+        while (1)
+                cpu_do_idle();
+}
+
+static int r8a7779_cpu_disable(unsigned int cpu)
+{
+        /* only CPU1->3 have power domains, do not allow hotplug of CPU0 */
+        return cpu == 0 ? -EPERM : 0;
 }
+#endif /* CONFIG_HOTPLUG_CPU */
 
 struct smp_operations r8a7779_smp_ops  __initdata = {
         .smp_init_cpus          = r8a7779_smp_init_cpus,
@@ -190,7 +185,7 @@ struct smp_operations r8a7779_smp_ops  __initdata = {
         .smp_boot_secondary     = r8a7779_boot_secondary,
 #ifdef CONFIG_HOTPLUG_CPU
         .cpu_kill               = r8a7779_cpu_kill,
-        .cpu_die                = shmobile_cpu_die,
-        .cpu_disable            = shmobile_cpu_disable,
+        .cpu_die                = r8a7779_cpu_die,
+        .cpu_disable            = r8a7779_cpu_disable,
 #endif
 };
diff --git a/arch/arm/mach-shmobile/smp-sh73a0.c b/arch/arm/mach-shmobile/smp-sh73a0.c
index acb46a94ccdf..5ae502b16437 100644
--- a/arch/arm/mach-shmobile/smp-sh73a0.c
+++ b/arch/arm/mach-shmobile/smp-sh73a0.c
@@ -39,26 +39,16 @@
 
 #define PSTR_SHUTDOWN_MODE      3
 
-static void __iomem *scu_base_addr(void)
-{
-        return (void __iomem *)0xf0000000;
-}
+#define SH73A0_SCU_BASE 0xf0000000
 
 #ifdef CONFIG_HAVE_ARM_TWD
-static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, 0xf0000600, 29);
+static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, SH73A0_SCU_BASE + 0x600, 29);
 void __init sh73a0_register_twd(void)
 {
         twd_local_timer_register(&twd_local_timer);
 }
 #endif
 
-static unsigned int __init sh73a0_get_core_count(void)
-{
-        void __iomem *scu_base = scu_base_addr();
-
-        return scu_get_core_count(scu_base);
-}
-
 static void __cpuinit sh73a0_secondary_init(unsigned int cpu)
 {
         gic_secondary_init(0);
@@ -78,21 +68,22 @@ static int __cpuinit sh73a0_boot_secondary(unsigned int cpu, struct task_struct
 
 static void __init sh73a0_smp_prepare_cpus(unsigned int max_cpus)
 {
-        scu_enable(scu_base_addr());
+        scu_enable(shmobile_scu_base);
 
-        /* Map the reset vector (in headsmp-sh73a0.S) */
+        /* Map the reset vector (in headsmp-scu.S) */
         __raw_writel(0, APARMBAREA);      /* 4k */
-        __raw_writel(__pa(sh73a0_secondary_vector), SBAR);
+        __raw_writel(__pa(shmobile_secondary_vector_scu), SBAR);
 
         /* enable cache coherency on booting CPU */
-        scu_power_mode(scu_base_addr(), SCU_PM_NORMAL);
+        scu_power_mode(shmobile_scu_base, SCU_PM_NORMAL);
 }
 
 static void __init sh73a0_smp_init_cpus(void)
 {
-        unsigned int ncores = sh73a0_get_core_count();
+        /* setup sh73a0 specific SCU base */
+        shmobile_scu_base = IOMEM(SH73A0_SCU_BASE);
 
-        shmobile_smp_init_cpus(ncores);
+        shmobile_smp_init_cpus(scu_get_core_count(shmobile_scu_base));
 }
 
 #ifdef CONFIG_HOTPLUG_CPU
@@ -128,11 +119,16 @@ static void sh73a0_cpu_die(unsigned int cpu)
         flush_cache_all();
 
         /* Set power off mode. This takes the CPU out of the MP cluster */
-        scu_power_mode(scu_base_addr(), SCU_PM_POWEROFF);
+        scu_power_mode(shmobile_scu_base, SCU_PM_POWEROFF);
 
         /* Enter shutdown mode */
         cpu_do_idle();
 }
+
+static int sh73a0_cpu_disable(unsigned int cpu)
+{
+        return 0; /* CPU0 and CPU1 supported */
+}
 #endif /* CONFIG_HOTPLUG_CPU */
 
 struct smp_operations sh73a0_smp_ops __initdata = {
@@ -143,6 +139,6 @@ struct smp_operations sh73a0_smp_ops __initdata = {
 #ifdef CONFIG_HOTPLUG_CPU
         .cpu_kill               = sh73a0_cpu_kill,
         .cpu_die                = sh73a0_cpu_die,
-        .cpu_disable            = shmobile_cpu_disable_any,
+        .cpu_disable            = sh73a0_cpu_disable,
 #endif
 };
diff --git a/arch/arm/mach-shmobile/timer.c b/arch/arm/mach-shmobile/timer.c
index 3d16d4dff01b..f321dbeb2379 100644
--- a/arch/arm/mach-shmobile/timer.c
+++ b/arch/arm/mach-shmobile/timer.c
@@ -19,10 +19,8 @@
  *
  */
 #include <linux/platform_device.h>
+#include <linux/clocksource.h>
 #include <linux/delay.h>
-#include <asm/arch_timer.h>
-#include <asm/mach/time.h>
-#include <asm/smp_twd.h>
 
 void __init shmobile_setup_delay(unsigned int max_cpu_core_mhz,
                                  unsigned int mult, unsigned int div)
@@ -63,6 +61,5 @@ void __init shmobile_earlytimer_init(void)
 
 void __init shmobile_timer_init(void)
 {
-        arch_timer_of_register();
-        arch_timer_sched_clock_init();
+        clocksource_of_init();
 }
diff --git a/arch/arm/mach-spear/spear13xx.c b/arch/arm/mach-spear/spear13xx.c
index 3975916666a0..3621599c38ad 100644
--- a/arch/arm/mach-spear/spear13xx.c
+++ b/arch/arm/mach-spear/spear13xx.c
@@ -15,13 +15,13 @@
 
 #include <linux/amba/pl022.h>
 #include <linux/clk.h>
+#include <linux/clocksource.h>
 #include <linux/err.h>
 #include <linux/of.h>
 #include <asm/hardware/cache-l2x0.h>
 #include <asm/mach/map.h>
-#include <asm/smp_twd.h>
-#include "generic.h"
 #include <mach/spear.h>
+#include "generic.h"
 
 void __init spear13xx_l2x0_init(void)
 {
@@ -122,5 +122,5 @@ void __init spear13xx_timer_init(void)
         clk_put(pclk);
 
         spear_setup_of_timer();
-        twd_local_timer_of_register();
+        clocksource_of_init();
 }
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index f6b46ae2b7f8..e40326d0e29f 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -10,6 +10,7 @@ obj-y					+= pm.o
 obj-y                                   += reset.o
 obj-y                                   += reset-handler.o
 obj-y                                   += sleep.o
+obj-y                                   += tegra.o
 obj-$(CONFIG_CPU_IDLE)                  += cpuidle.o
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += tegra20_speedo.o
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += tegra2_emc.o
@@ -27,9 +28,7 @@ obj-$(CONFIG_HOTPLUG_CPU)               += hotplug.o
 obj-$(CONFIG_CPU_FREQ)                  += cpu-tegra.o
 obj-$(CONFIG_TEGRA_PCI)                 += pcie.o
 
-obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += board-dt-tegra20.o
-obj-$(CONFIG_ARCH_TEGRA_3x_SOC)         += board-dt-tegra30.o
-obj-$(CONFIG_ARCH_TEGRA_114_SOC)        += board-dt-tegra114.o
+obj-$(CONFIG_ARCH_TEGRA_114_SOC)        += tegra114_speedo.o
 ifeq ($(CONFIG_CPU_IDLE),y)
 obj-$(CONFIG_ARCH_TEGRA_114_SOC)        += cpuidle-tegra114.o
 endif
diff --git a/arch/arm/mach-tegra/board-dt-tegra114.c b/arch/arm/mach-tegra/board-dt-tegra114.c
deleted file mode 100644
index 085d63637b62..000000000000
--- a/arch/arm/mach-tegra/board-dt-tegra114.c
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * NVIDIA Tegra114 device tree board support
- *
- * Copyright (C) 2013 NVIDIA Corporation
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/of.h>
-#include <linux/of_platform.h>
-#include <linux/clocksource.h>
-
-#include <asm/mach/arch.h>
-
-#include "board.h"
-#include "common.h"
-
-static void __init tegra114_dt_init(void)
-{
-        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
-}
-
-static const char * const tegra114_dt_board_compat[] = {
-        "nvidia,tegra114",
-        NULL,
-};
-
-DT_MACHINE_START(TEGRA114_DT, "NVIDIA Tegra114 (Flattened Device Tree)")
-        .smp            = smp_ops(tegra_smp_ops),
-        .map_io         = tegra_map_common_io,
-        .init_early     = tegra114_init_early,
-        .init_irq       = tegra_dt_init_irq,
-        .init_time      = clocksource_of_init,
-        .init_machine   = tegra114_dt_init,
-        .init_late      = tegra_init_late,
-        .restart        = tegra_assert_system_reset,
-        .dt_compat      = tegra114_dt_board_compat,
-MACHINE_END
diff --git a/arch/arm/mach-tegra/board-dt-tegra30.c b/arch/arm/mach-tegra/board-dt-tegra30.c
deleted file mode 100644
index bf68567e549d..000000000000
--- a/arch/arm/mach-tegra/board-dt-tegra30.c
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
- * arch/arm/mach-tegra/board-dt-tegra30.c
- *
- * NVIDIA Tegra30 device tree board support
- *
- * Copyright (C) 2011 NVIDIA Corporation
- *
- * Derived from:
- *
- * arch/arm/mach-tegra/board-dt-tegra20.c
- *
- * Copyright (C) 2010 Secret Lab Technologies, Ltd.
- * Copyright (C) 2010 Google, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/clocksource.h>
-#include <linux/kernel.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_fdt.h>
-#include <linux/of_irq.h>
-#include <linux/of_platform.h>
-
-#include <asm/mach/arch.h>
-
-#include "board.h"
-#include "common.h"
-#include "iomap.h"
-
-static void __init tegra30_dt_init(void)
-{
-        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
-}
-
-static const char *tegra30_dt_board_compat[] = {
-        "nvidia,tegra30",
-        NULL
-};
-
-DT_MACHINE_START(TEGRA30_DT, "NVIDIA Tegra30 (Flattened Device Tree)")
-        .smp            = smp_ops(tegra_smp_ops),
-        .map_io         = tegra_map_common_io,
-        .init_early     = tegra30_init_early,
-        .init_irq       = tegra_dt_init_irq,
-        .init_time      = clocksource_of_init,
-        .init_machine   = tegra30_dt_init,
-        .init_late      = tegra_init_late,
-        .restart        = tegra_assert_system_reset,
-        .dt_compat      = tegra30_dt_board_compat,
-MACHINE_END
diff --git a/arch/arm/mach-tegra/board-harmony-pcie.c b/arch/arm/mach-tegra/board-harmony-pcie.c
index 3cdc1bb8254c..035b240b9e15 100644
--- a/arch/arm/mach-tegra/board-harmony-pcie.c
+++ b/arch/arm/mach-tegra/board-harmony-pcie.c
@@ -56,13 +56,17 @@ int __init harmony_pcie_init(void)
         gpio_direction_output(en_vdd_1v05, 1);
 
         regulator = regulator_get(NULL, "vdd_ldo0,vddio_pex_clk");
-        if (IS_ERR_OR_NULL(regulator)) {
-                pr_err("%s: regulator_get failed: %d\n", __func__,
-                       (int)PTR_ERR(regulator));
+        if (IS_ERR(regulator)) {
+                err = PTR_ERR(regulator);
+                pr_err("%s: regulator_get failed: %d\n", __func__, err);
                 goto err_reg;
         }
 
-        regulator_enable(regulator);
+        err = regulator_enable(regulator);
+        if (err) {
+                pr_err("%s: regulator_enable failed: %d\n", __func__, err);
+                goto err_en;
+        }
 
         err = tegra_pcie_init(true, true);
         if (err) {
@@ -74,6 +78,7 @@ int __init harmony_pcie_init(void)
 
 err_pcie:
         regulator_disable(regulator);
+err_en:
         regulator_put(regulator);
 err_reg:
         gpio_free(en_vdd_1v05);
diff --git a/arch/arm/mach-tegra/board.h b/arch/arm/mach-tegra/board.h
index 86851c81a350..60431de585ca 100644
--- a/arch/arm/mach-tegra/board.h
+++ b/arch/arm/mach-tegra/board.h
@@ -26,9 +26,7 @@
 
 void tegra_assert_system_reset(char mode, const char *cmd);
 
-void __init tegra20_init_early(void);
-void __init tegra30_init_early(void);
-void __init tegra114_init_early(void);
+void __init tegra_init_early(void);
 void __init tegra_map_common_io(void);
 void __init tegra_init_irq(void);
 void __init tegra_dt_init_irq(void);
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
index 5449a3f2977b..eb1f3c8c74cc 100644
--- a/arch/arm/mach-tegra/common.c
+++ b/arch/arm/mach-tegra/common.c
@@ -33,6 +33,7 @@
 #include "common.h"
 #include "fuse.h"
 #include "iomap.h"
+#include "irq.h"
 #include "pmc.h"
 #include "apbio.h"
 #include "sleep.h"
@@ -61,8 +62,10 @@ u32 tegra_uart_config[4] = {
 void __init tegra_dt_init_irq(void)
 {
         tegra_clocks_init();
+        tegra_pmc_init();
         tegra_init_irq();
         irqchip_init();
+        tegra_legacy_irq_syscore_init();
 }
 #endif
 
@@ -94,40 +97,18 @@ static void __init tegra_init_cache(void)
 
 }
 
-static void __init tegra_init_early(void)
+void __init tegra_init_early(void)
 {
         tegra_cpu_reset_handler_init();
         tegra_apb_io_init();
         tegra_init_fuse();
         tegra_init_cache();
-        tegra_pmc_init();
         tegra_powergate_init();
+        tegra_hotplug_init();
 }
 
-#ifdef CONFIG_ARCH_TEGRA_2x_SOC
-void __init tegra20_init_early(void)
-{
-        tegra_init_early();
-        tegra20_hotplug_init();
-}
-#endif
-
-#ifdef CONFIG_ARCH_TEGRA_3x_SOC
-void __init tegra30_init_early(void)
-{
-        tegra_init_early();
-        tegra30_hotplug_init();
-}
-#endif
-
-#ifdef CONFIG_ARCH_TEGRA_114_SOC
-void __init tegra114_init_early(void)
-{
-        tegra_init_early();
-}
-#endif
-
 void __init tegra_init_late(void)
 {
+        tegra_init_suspend();
         tegra_powergate_debugfs_init();
 }
diff --git a/arch/arm/mach-tegra/cpuidle-tegra20.c b/arch/arm/mach-tegra/cpuidle-tegra20.c
index 825ced4f7a40..8bbbdebed882 100644
--- a/arch/arm/mach-tegra/cpuidle-tegra20.c
+++ b/arch/arm/mach-tegra/cpuidle-tegra20.c
@@ -130,10 +130,6 @@ static bool tegra20_cpu_cluster_power_down(struct cpuidle_device *dev,
                                            struct cpuidle_driver *drv,
                                            int index)
 {
-        struct cpuidle_state *state = &drv->states[index];
-        u32 cpu_on_time = state->exit_latency;
-        u32 cpu_off_time = state->target_residency - state->exit_latency;
-
         while (tegra20_cpu_is_resettable_soon())
                 cpu_relax();
 
@@ -142,7 +138,7 @@ static bool tegra20_cpu_cluster_power_down(struct cpuidle_device *dev,
 
         clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &dev->cpu);
 
-        tegra_idle_lp2_last(cpu_on_time, cpu_off_time);
+        tegra_idle_lp2_last();
 
         clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &dev->cpu);
 
diff --git a/arch/arm/mach-tegra/cpuidle-tegra30.c b/arch/arm/mach-tegra/cpuidle-tegra30.c
index 8b50cf4ddd6f..c0931c8bb3e5 100644
--- a/arch/arm/mach-tegra/cpuidle-tegra30.c
+++ b/arch/arm/mach-tegra/cpuidle-tegra30.c
@@ -72,10 +72,6 @@ static bool tegra30_cpu_cluster_power_down(struct cpuidle_device *dev,
                                            struct cpuidle_driver *drv,
                                            int index)
 {
-        struct cpuidle_state *state = &drv->states[index];
-        u32 cpu_on_time = state->exit_latency;
-        u32 cpu_off_time = state->target_residency - state->exit_latency;
-
         /* All CPUs entering LP2 is not working.
          * Don't let CPU0 enter LP2 when any secondary CPU is online.
          */
@@ -86,7 +82,7 @@ static bool tegra30_cpu_cluster_power_down(struct cpuidle_device *dev,
 
         clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &dev->cpu);
 
-        tegra_idle_lp2_last(cpu_on_time, cpu_off_time);
+        tegra_idle_lp2_last();
 
         clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &dev->cpu);
 
@@ -102,12 +98,8 @@ static bool tegra30_cpu_core_power_down(struct cpuidle_device *dev,
 
         smp_wmb();
 
-        save_cpu_arch_register();
-
         cpu_suspend(0, tegra30_sleep_cpu_secondary_finish);
 
-        restore_cpu_arch_register();
-
         clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &dev->cpu);
 
         return true;
diff --git a/arch/arm/mach-tegra/fuse.c b/arch/arm/mach-tegra/fuse.c
index f7db0782a6b6..e035cd284a6e 100644
--- a/arch/arm/mach-tegra/fuse.c
+++ b/arch/arm/mach-tegra/fuse.c
@@ -2,6 +2,7 @@
  * arch/arm/mach-tegra/fuse.c
  *
  * Copyright (C) 2010 Google, Inc.
+ * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
  *
  * Author:
  *      Colin Cross <ccross@android.com>
@@ -137,6 +138,9 @@ void tegra_init_fuse(void)
                 tegra_fuse_spare_bit = TEGRA30_FUSE_SPARE_BIT;
                 tegra_init_speedo_data = &tegra30_init_speedo_data;
                 break;
+        case TEGRA114:
+                tegra_init_speedo_data = &tegra114_init_speedo_data;
+                break;
         default:
                 pr_warn("Tegra: unknown chip id %d\n", tegra_chip_id);
                 tegra_fuse_spare_bit = TEGRA20_FUSE_SPARE_BIT;
diff --git a/arch/arm/mach-tegra/fuse.h b/arch/arm/mach-tegra/fuse.h
index da78434678c7..aacc00d05980 100644
--- a/arch/arm/mach-tegra/fuse.h
+++ b/arch/arm/mach-tegra/fuse.h
@@ -1,5 +1,6 @@
 /*
  * Copyright (C) 2010 Google, Inc.
+ * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
  *
  * Author:
  *      Colin Cross <ccross@android.com>
@@ -66,4 +67,10 @@ void tegra30_init_speedo_data(void);
 static inline void tegra30_init_speedo_data(void) {}
 #endif
 
+#ifdef CONFIG_ARCH_TEGRA_114_SOC
+void tegra114_init_speedo_data(void);
+#else
+static inline void tegra114_init_speedo_data(void) {}
+#endif
+
 #endif
diff --git a/arch/arm/mach-tegra/headsmp.S b/arch/arm/mach-tegra/headsmp.S
index fd473f2b4c3d..045c16f2dd51 100644
--- a/arch/arm/mach-tegra/headsmp.S
+++ b/arch/arm/mach-tegra/headsmp.S
@@ -7,8 +7,5 @@
 
 ENTRY(tegra_secondary_startup)
         bl      v7_invalidate_l1
-        /* Enable coresight */
-        mov32   r0, 0xC5ACCE55
-        mcr     p14, 0, r0, c7, c12, 6
         b       secondary_startup
 ENDPROC(tegra_secondary_startup)
diff --git a/arch/arm/mach-tegra/hotplug.c b/arch/arm/mach-tegra/hotplug.c
index a599f6e36dea..8da9f78475da 100644
--- a/arch/arm/mach-tegra/hotplug.c
+++ b/arch/arm/mach-tegra/hotplug.c
@@ -1,8 +1,7 @@
 /*
- *
  *  Copyright (C) 2002 ARM Ltd.
  *  All Rights Reserved
- *  Copyright (c) 2010, 2012 NVIDIA Corporation. All rights reserved.
+ *  Copyright (c) 2010, 2012-2013, NVIDIA Corporation. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -15,6 +14,7 @@
 #include <asm/cacheflush.h>
 #include <asm/smp_plat.h>
 
+#include "fuse.h"
 #include "sleep.h"
 
 static void (*tegra_hotplug_shutdown)(void);
@@ -56,18 +56,13 @@ int tegra_cpu_disable(unsigned int cpu)
         return cpu == 0 ? -EPERM : 0;
 }
 
-#ifdef CONFIG_ARCH_TEGRA_2x_SOC
-extern void tegra20_hotplug_shutdown(void);
-void __init tegra20_hotplug_init(void)
+void __init tegra_hotplug_init(void)
 {
-        tegra_hotplug_shutdown = tegra20_hotplug_shutdown;
-}
-#endif
+        if (!IS_ENABLED(CONFIG_HOTPLUG_CPU))
+                return;
 
-#ifdef CONFIG_ARCH_TEGRA_3x_SOC
-extern void tegra30_hotplug_shutdown(void);
-void __init tegra30_hotplug_init(void)
-{
-        tegra_hotplug_shutdown = tegra30_hotplug_shutdown;
+        if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) && tegra_chip_id == TEGRA20)
+                tegra_hotplug_shutdown = tegra20_hotplug_shutdown;
+        if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) && tegra_chip_id == TEGRA30)
+                tegra_hotplug_shutdown = tegra30_hotplug_shutdown;
 }
-#endif
diff --git a/arch/arm/mach-tegra/irq.c b/arch/arm/mach-tegra/irq.c
index 1952e82797cc..0de4eed1493d 100644
--- a/arch/arm/mach-tegra/irq.c
+++ b/arch/arm/mach-tegra/irq.c
@@ -4,7 +4,7 @@
  * Author:
  *      Colin Cross <ccross@android.com>
  *
- * Copyright (C) 2010, NVIDIA Corporation
+ * Copyright (C) 2010,2013, NVIDIA Corporation
  *
  * This software is licensed under the terms of the GNU General Public
  * License version 2, as published by the Free Software Foundation, and
@@ -23,6 +23,7 @@
 #include <linux/io.h>
 #include <linux/of.h>
 #include <linux/irqchip/arm-gic.h>
+#include <linux/syscore_ops.h>
 
 #include "board.h"
 #include "iomap.h"
@@ -43,6 +44,7 @@
 #define ICTLR_COP_IEP_CLASS     0x3c
 
 #define FIRST_LEGACY_IRQ 32
+#define TEGRA_MAX_NUM_ICTLRS    5
 
 #define SGI_MASK 0xFFFF
 
@@ -56,6 +58,15 @@ static void __iomem *ictlr_reg_base[] = {
         IO_ADDRESS(TEGRA_QUINARY_ICTLR_BASE),
 };
 
+#ifdef CONFIG_PM_SLEEP
+static u32 cop_ier[TEGRA_MAX_NUM_ICTLRS];
+static u32 cop_iep[TEGRA_MAX_NUM_ICTLRS];
+static u32 cpu_ier[TEGRA_MAX_NUM_ICTLRS];
+static u32 cpu_iep[TEGRA_MAX_NUM_ICTLRS];
+
+static u32 ictlr_wake_mask[TEGRA_MAX_NUM_ICTLRS];
+#endif
+
 bool tegra_pending_sgi(void)
 {
         u32 pending_set;
@@ -125,6 +136,87 @@ static int tegra_retrigger(struct irq_data *d)
         return 1;
 }
 
+#ifdef CONFIG_PM_SLEEP
+static int tegra_set_wake(struct irq_data *d, unsigned int enable)
+{
+        u32 irq = d->irq;
+        u32 index, mask;
+
+        if (irq < FIRST_LEGACY_IRQ ||
+                irq >= FIRST_LEGACY_IRQ + num_ictlrs * 32)
+                return -EINVAL;
+
+        index = ((irq - FIRST_LEGACY_IRQ) / 32);
+        mask = BIT((irq - FIRST_LEGACY_IRQ) % 32);
+        if (enable)
+                ictlr_wake_mask[index] |= mask;
+        else
+                ictlr_wake_mask[index] &= ~mask;
+
+        return 0;
+}
+
+static int tegra_legacy_irq_suspend(void)
+{
+        unsigned long flags;
+        int i;
+
+        local_irq_save(flags);
+        for (i = 0; i < num_ictlrs; i++) {
+                void __iomem *ictlr = ictlr_reg_base[i];
+                /* Save interrupt state */
+                cpu_ier[i] = readl_relaxed(ictlr + ICTLR_CPU_IER);
+                cpu_iep[i] = readl_relaxed(ictlr + ICTLR_CPU_IEP_CLASS);
+                cop_ier[i] = readl_relaxed(ictlr + ICTLR_COP_IER);
+                cop_iep[i] = readl_relaxed(ictlr + ICTLR_COP_IEP_CLASS);
+
+                /* Disable COP interrupts */
+                writel_relaxed(~0ul, ictlr + ICTLR_COP_IER_CLR);
+
+                /* Disable CPU interrupts */
+                writel_relaxed(~0ul, ictlr + ICTLR_CPU_IER_CLR);
+
+                /* Enable the wakeup sources of ictlr */
+                writel_relaxed(ictlr_wake_mask[i], ictlr + ICTLR_CPU_IER_SET);
+        }
+        local_irq_restore(flags);
+
+        return 0;
+}
+
+static void tegra_legacy_irq_resume(void)
+{
+        unsigned long flags;
+        int i;
+
+        local_irq_save(flags);
+        for (i = 0; i < num_ictlrs; i++) {
+                void __iomem *ictlr = ictlr_reg_base[i];
+                writel_relaxed(cpu_iep[i], ictlr + ICTLR_CPU_IEP_CLASS);
+                writel_relaxed(~0ul, ictlr + ICTLR_CPU_IER_CLR);
+                writel_relaxed(cpu_ier[i], ictlr + ICTLR_CPU_IER_SET);
+                writel_relaxed(cop_iep[i], ictlr + ICTLR_COP_IEP_CLASS);
+                writel_relaxed(~0ul, ictlr + ICTLR_COP_IER_CLR);
+                writel_relaxed(cop_ier[i], ictlr + ICTLR_COP_IER_SET);
+        }
+        local_irq_restore(flags);
+}
+
+static struct syscore_ops tegra_legacy_irq_syscore_ops = {
+        .suspend = tegra_legacy_irq_suspend,
+        .resume = tegra_legacy_irq_resume,
+};
+
+int tegra_legacy_irq_syscore_init(void)
+{
+        register_syscore_ops(&tegra_legacy_irq_syscore_ops);
+
+        return 0;
+}
+#else
+#define tegra_set_wake NULL
+#endif
+
 void __init tegra_init_irq(void)
 {
         int i;
@@ -150,6 +242,8 @@ void __init tegra_init_irq(void)
         gic_arch_extn.irq_mask = tegra_mask;
         gic_arch_extn.irq_unmask = tegra_unmask;
         gic_arch_extn.irq_retrigger = tegra_retrigger;
+        gic_arch_extn.irq_set_wake = tegra_set_wake;
+        gic_arch_extn.flags = IRQCHIP_MASK_ON_SUSPEND;
 
         /*
          * Check if there is a devicetree present, since the GIC will be
diff --git a/arch/arm/mach-tegra/irq.h b/arch/arm/mach-tegra/irq.h
index 5142649bba05..bc05ce5613fb 100644
--- a/arch/arm/mach-tegra/irq.h
+++ b/arch/arm/mach-tegra/irq.h
@@ -19,4 +19,10 @@
 
 bool tegra_pending_sgi(void);
 
+#ifdef CONFIG_PM_SLEEP
+int tegra_legacy_irq_syscore_init(void);
+#else
+static inline int tegra_legacy_irq_syscore_init(void) { return 0; }
+#endif
+
 #endif
diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c
index 2c6b3d55213b..516aab28fe34 100644
--- a/arch/arm/mach-tegra/platsmp.c
+++ b/arch/arm/mach-tegra/platsmp.c
@@ -26,22 +26,16 @@
 #include <asm/smp_scu.h>
 #include <asm/smp_plat.h>
 
-#include <mach/powergate.h>
-
 #include "fuse.h"
 #include "flowctrl.h"
 #include "reset.h"
+#include "pmc.h"
 
 #include "common.h"
 #include "iomap.h"
 
-extern void tegra_secondary_startup(void);
-
 static cpumask_t tegra_cpu_init_mask;
 
-#define EVP_CPU_RESET_VECTOR \
-        (IO_ADDRESS(TEGRA_EXCEPTION_VECTORS_BASE) + 0x100)
-
 static void __cpuinit tegra_secondary_init(unsigned int cpu)
 {
         /*
@@ -54,25 +48,43 @@ static void __cpuinit tegra_secondary_init(unsigned int cpu)
         cpumask_set_cpu(cpu, &tegra_cpu_init_mask);
 }
 
-static int tegra20_power_up_cpu(unsigned int cpu)
+
+static int tegra20_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
-        /* Enable the CPU clock. */
-        tegra_enable_cpu_clock(cpu);
+        cpu = cpu_logical_map(cpu);
+
+        /*
+         * Force the CPU into reset. The CPU must remain in reset when
+         * the flow controller state is cleared (which will cause the
+         * flow controller to stop driving reset if the CPU has been
+         * power-gated via the flow controller). This will have no
+         * effect on first boot of the CPU since it should already be
+         * in reset.
+         */
+        tegra_put_cpu_in_reset(cpu);
 
-        /* Clear flow controller CSR. */
-        flowctrl_write_cpu_csr(cpu, 0);
+        /*
+         * Unhalt the CPU. If the flow controller was used to
+         * power-gate the CPU this will cause the flow controller to
+         * stop driving reset. The CPU will remain in reset because the
+         * clock and reset block is now driving reset.
+         */
+        flowctrl_write_cpu_halt(cpu, 0);
 
+        tegra_enable_cpu_clock(cpu);
+        flowctrl_write_cpu_csr(cpu, 0); /* Clear flow controller CSR. */
+        tegra_cpu_out_of_reset(cpu);
         return 0;
 }
 
-static int tegra30_power_up_cpu(unsigned int cpu)
+static int tegra30_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
-        int ret, pwrgateid;
+        int ret;
         unsigned long timeout;
 
-        pwrgateid = tegra_cpu_powergate_id(cpu);
-        if (pwrgateid < 0)
-                return pwrgateid;
+        cpu = cpu_logical_map(cpu);
+        tegra_put_cpu_in_reset(cpu);
+        flowctrl_write_cpu_halt(cpu, 0);
 
         /*
          * The power up sequence of cold boot CPU and warm boot CPU
@@ -85,13 +97,13 @@ static int tegra30_power_up_cpu(unsigned int cpu)
          * the IO clamps.
          * For cold boot CPU, do not wait. After the cold boot CPU be
          * booted, it will run to tegra_secondary_init() and set
-         * tegra_cpu_init_mask which influences what tegra30_power_up_cpu()
+         * tegra_cpu_init_mask which influences what tegra30_boot_secondary()
          * next time around.
          */
         if (cpumask_test_cpu(cpu, &tegra_cpu_init_mask)) {
                 timeout = jiffies + msecs_to_jiffies(50);
                 do {
-                        if (!tegra_powergate_is_powered(pwrgateid))
+                        if (tegra_pmc_cpu_is_powered(cpu))
                                 goto remove_clamps;
                         udelay(10);
                 } while (time_before(jiffies, timeout));
@@ -103,14 +115,14 @@ static int tegra30_power_up_cpu(unsigned int cpu)
          * be un-gated by un-toggling the power gate register
          * manually.
          */
-        if (!tegra_powergate_is_powered(pwrgateid)) {
-                ret = tegra_powergate_power_on(pwrgateid);
+        if (!tegra_pmc_cpu_is_powered(cpu)) {
+                ret = tegra_pmc_cpu_power_on(cpu);
                 if (ret)
                         return ret;
 
                 /* Wait for the power to come up. */
                 timeout = jiffies + msecs_to_jiffies(100);
-                while (tegra_powergate_is_powered(pwrgateid)) {
+                while (tegra_pmc_cpu_is_powered(cpu)) {
                         if (time_after(jiffies, timeout))
                                 return -ETIMEDOUT;
                         udelay(10);
@@ -123,57 +135,34 @@ remove_clamps:
         udelay(10);
 
         /* Remove I/O clamps. */
-        ret = tegra_powergate_remove_clamping(pwrgateid);
-        udelay(10);
+        ret = tegra_pmc_cpu_remove_clamping(cpu);
+        if (ret)
+                return ret;
 
-        /* Clear flow controller CSR. */
-        flowctrl_write_cpu_csr(cpu, 0);
+        udelay(10);
 
+        flowctrl_write_cpu_csr(cpu, 0); /* Clear flow controller CSR. */
+        tegra_cpu_out_of_reset(cpu);
         return 0;
 }
 
-static int __cpuinit tegra_boot_secondary(unsigned int cpu, struct task_struct *idle)
+static int tegra114_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
-        int status;
-
         cpu = cpu_logical_map(cpu);
+        return tegra_pmc_cpu_power_on(cpu);
+}
 
-        /*
-         * Force the CPU into reset. The CPU must remain in reset when the
-         * flow controller state is cleared (which will cause the flow
-         * controller to stop driving reset if the CPU has been power-gated
-         * via the flow controller). This will have no effect on first boot
-         * of the CPU since it should already be in reset.
-         */
-        tegra_put_cpu_in_reset(cpu);
-
-        /*
-         * Unhalt the CPU. If the flow controller was used to power-gate the
-         * CPU this will cause the flow controller to stop driving reset.
-         * The CPU will remain in reset because the clock and reset block
-         * is now driving reset.
-         */
-        flowctrl_write_cpu_halt(cpu, 0);
-
-        switch (tegra_chip_id) {
-        case TEGRA20:
-                status = tegra20_power_up_cpu(cpu);
-                break;
-        case TEGRA30:
-                status = tegra30_power_up_cpu(cpu);
-                break;
-        default:
-                status = -EINVAL;
-                break;
-        }
-
-        if (status)
-                goto done;
-
-        /* Take the CPU out of reset. */
-        tegra_cpu_out_of_reset(cpu);
-done:
-        return status;
+static int __cpuinit tegra_boot_secondary(unsigned int cpu,
+                                          struct task_struct *idle)
+{
+        if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) && tegra_chip_id == TEGRA20)
+                return tegra20_boot_secondary(cpu, idle);
+        if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) && tegra_chip_id == TEGRA30)
+                return tegra30_boot_secondary(cpu, idle);
+        if (IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) && tegra_chip_id == TEGRA114)
+                return tegra114_boot_secondary(cpu, idle);
+
+        return -EINVAL;
 }
 
 static void __init tegra_smp_prepare_cpus(unsigned int max_cpus)
diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c
index 523604de666f..d0b7400e4606 100644
--- a/arch/arm/mach-tegra/pm.c
+++ b/arch/arm/mach-tegra/pm.c
@@ -22,7 +22,7 @@
 #include <linux/cpumask.h>
 #include <linux/delay.h>
 #include <linux/cpu_pm.h>
-#include <linux/clk.h>
+#include <linux/suspend.h>
 #include <linux/err.h>
 #include <linux/clk/tegra.h>
 
@@ -37,67 +37,13 @@
 #include "reset.h"
 #include "flowctrl.h"
 #include "fuse.h"
+#include "pmc.h"
 #include "sleep.h"
 
-#define TEGRA_POWER_CPU_PWRREQ_OE       (1 << 16)  /* CPU pwr req enable */
-
-#define PMC_CTRL                0x0
-#define PMC_CPUPWRGOOD_TIMER    0xc8
-#define PMC_CPUPWROFF_TIMER     0xcc
-
 #ifdef CONFIG_PM_SLEEP
-static unsigned int g_diag_reg;
 static DEFINE_SPINLOCK(tegra_lp2_lock);
-static void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
-static struct clk *tegra_pclk;
 void (*tegra_tear_down_cpu)(void);
 
-void save_cpu_arch_register(void)
-{
-        /* read diagnostic register */
-        asm("mrc p15, 0, %0, c15, c0, 1" : "=r"(g_diag_reg) : : "cc");
-        return;
-}
-
-void restore_cpu_arch_register(void)
-{
-        /* write diagnostic register */
-        asm("mcr p15, 0, %0, c15, c0, 1" : : "r"(g_diag_reg) : "cc");
-        return;
-}
-
-static void set_power_timers(unsigned long us_on, unsigned long us_off)
-{
-        unsigned long long ticks;
-        unsigned long long pclk;
-        unsigned long rate;
-        static unsigned long tegra_last_pclk;
-
-        if (tegra_pclk == NULL) {
-                tegra_pclk = clk_get_sys(NULL, "pclk");
-                WARN_ON(IS_ERR(tegra_pclk));
-        }
-
-        rate = clk_get_rate(tegra_pclk);
-
-        if (WARN_ON_ONCE(rate <= 0))
-                pclk = 100000000;
-        else
-                pclk = rate;
-
-        if ((rate != tegra_last_pclk)) {
-                ticks = (us_on * pclk) + 999999ull;
-                do_div(ticks, 1000000);
-                writel((unsigned long)ticks, pmc + PMC_CPUPWRGOOD_TIMER);
-
-                ticks = (us_off * pclk) + 999999ull;
-                do_div(ticks, 1000000);
-                writel((unsigned long)ticks, pmc + PMC_CPUPWROFF_TIMER);
-                wmb();
-        }
-        tegra_last_pclk = pclk;
-}
-
 /*
  * restore_cpu_complex
  *
@@ -119,8 +65,6 @@ static void restore_cpu_complex(void)
         tegra_cpu_clock_resume();
 
         flowctrl_cpu_suspend_exit(cpu);
-
-        restore_cpu_arch_register();
 }
 
 /*
@@ -145,8 +89,6 @@ static void suspend_cpu_complex(void)
         tegra_cpu_clock_suspend();
 
         flowctrl_cpu_suspend_enter(cpu);
-
-        save_cpu_arch_register();
 }
 
 void tegra_clear_cpu_in_lp2(int phy_cpu_id)
@@ -197,16 +139,9 @@ static int tegra_sleep_cpu(unsigned long v2p)
         return 0;
 }
 
-void tegra_idle_lp2_last(u32 cpu_on_time, u32 cpu_off_time)
+void tegra_idle_lp2_last(void)
 {
-        u32 mode;
-
-        /* Only the last cpu down does the final suspend steps */
-        mode = readl(pmc + PMC_CTRL);
-        mode |= TEGRA_POWER_CPU_PWRREQ_OE;
-        writel(mode, pmc + PMC_CTRL);
-
-        set_power_timers(cpu_on_time, cpu_off_time);
+        tegra_pmc_pm_set(TEGRA_SUSPEND_LP2);
 
         cpu_cluster_pm_enter();
         suspend_cpu_complex();
@@ -216,4 +151,81 @@ void tegra_idle_lp2_last(u32 cpu_on_time, u32 cpu_off_time)
         restore_cpu_complex();
         cpu_cluster_pm_exit();
 }
+
+enum tegra_suspend_mode tegra_pm_validate_suspend_mode(
+                                enum tegra_suspend_mode mode)
+{
+        /* Tegra114 didn't support any suspending mode yet. */
+        if (tegra_chip_id == TEGRA114)
+                return TEGRA_SUSPEND_NONE;
+
+        /*
+         * The Tegra devices only support suspending to LP2 currently.
+         */
+        if (mode > TEGRA_SUSPEND_LP2)
+                return TEGRA_SUSPEND_LP2;
+
+        return mode;
+}
+
+static const char *lp_state[TEGRA_MAX_SUSPEND_MODE] = {
+        [TEGRA_SUSPEND_NONE] = "none",
+        [TEGRA_SUSPEND_LP2] = "LP2",
+        [TEGRA_SUSPEND_LP1] = "LP1",
+        [TEGRA_SUSPEND_LP0] = "LP0",
+};
+
+static int __cpuinit tegra_suspend_enter(suspend_state_t state)
+{
+        enum tegra_suspend_mode mode = tegra_pmc_get_suspend_mode();
+
+        if (WARN_ON(mode < TEGRA_SUSPEND_NONE ||
+                    mode >= TEGRA_MAX_SUSPEND_MODE))
+                return -EINVAL;
+
+        pr_info("Entering suspend state %s\n", lp_state[mode]);
+
+        tegra_pmc_pm_set(mode);
+
+        local_fiq_disable();
+
+        suspend_cpu_complex();
+        switch (mode) {
+        case TEGRA_SUSPEND_LP2:
+                tegra_set_cpu_in_lp2(0);
+                break;
+        default:
+                break;
+        }
+
+        cpu_suspend(PHYS_OFFSET - PAGE_OFFSET, &tegra_sleep_cpu);
+
+        switch (mode) {
+        case TEGRA_SUSPEND_LP2:
+                tegra_clear_cpu_in_lp2(0);
+                break;
+        default:
+                break;
+        }
+        restore_cpu_complex();
+
+        local_fiq_enable();
+
+        return 0;
+}
+
+static const struct platform_suspend_ops tegra_suspend_ops = {
+        .valid          = suspend_valid_only_mem,
+        .enter          = tegra_suspend_enter,
+};
+
+void __init tegra_init_suspend(void)
+{
+        if (tegra_pmc_get_suspend_mode() == TEGRA_SUSPEND_NONE)
+                return;
+
+        tegra_pmc_suspend_init();
+
+        suspend_set_ops(&tegra_suspend_ops);
+}
 #endif
diff --git a/arch/arm/mach-tegra/pm.h b/arch/arm/mach-tegra/pm.h
index 787335cc964c..9d2d038bf12e 100644
--- a/arch/arm/mach-tegra/pm.h
+++ b/arch/arm/mach-tegra/pm.h
@@ -21,6 +21,8 @@
 #ifndef _MACH_TEGRA_PM_H_
 #define _MACH_TEGRA_PM_H_
 
+#include "pmc.h"
+
 extern unsigned long l2x0_saved_regs_addr;
 
 void save_cpu_arch_register(void);
@@ -29,7 +31,20 @@ void restore_cpu_arch_register(void);
 void tegra_clear_cpu_in_lp2(int phy_cpu_id);
 bool tegra_set_cpu_in_lp2(int phy_cpu_id);
 
-void tegra_idle_lp2_last(u32 cpu_on_time, u32 cpu_off_time);
+void tegra_idle_lp2_last(void);
 extern void (*tegra_tear_down_cpu)(void);
 
+#ifdef CONFIG_PM_SLEEP
+enum tegra_suspend_mode tegra_pm_validate_suspend_mode(
+                                enum tegra_suspend_mode mode);
+void tegra_init_suspend(void);
+#else
+enum tegra_suspend_mode tegra_pm_validate_suspend_mode(
+                                enum tegra_suspend_mode mode)
+{
+        return TEGRA_SUSPEND_NONE;
+}
+static inline void tegra_init_suspend(void) {}
+#endif
+
 #endif /* _MACH_TEGRA_PM_H_ */
diff --git a/arch/arm/mach-tegra/pmc.c b/arch/arm/mach-tegra/pmc.c
index d4fdb5fcec20..32360e540ce6 100644
--- a/arch/arm/mach-tegra/pmc.c
+++ b/arch/arm/mach-tegra/pmc.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
+ * Copyright (C) 2012,2013 NVIDIA CORPORATION. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -16,59 +16,313 @@
  */
 
 #include <linux/kernel.h>
+#include <linux/clk.h>
 #include <linux/io.h>
 #include <linux/of.h>
+#include <linux/of_address.h>
 
-#include "iomap.h"
+#include "fuse.h"
+#include "pm.h"
+#include "pmc.h"
+#include "sleep.h"
 
-#define PMC_CTRL                0x0
-#define PMC_CTRL_INTR_LOW       (1 << 17)
+#define TEGRA_POWER_EFFECT_LP0          (1 << 14)  /* LP0 when CPU pwr gated */
+#define TEGRA_POWER_CPU_PWRREQ_POLARITY (1 << 15)  /* CPU pwr req polarity */
+#define TEGRA_POWER_CPU_PWRREQ_OE       (1 << 16)  /* CPU pwr req enable */
+
+#define PMC_CTRL                        0x0
+#define PMC_CTRL_INTR_LOW               (1 << 17)
+#define PMC_PWRGATE_TOGGLE              0x30
+#define PMC_PWRGATE_TOGGLE_START        (1 << 8)
+#define PMC_REMOVE_CLAMPING             0x34
+#define PMC_PWRGATE_STATUS              0x38
+
+#define PMC_CPUPWRGOOD_TIMER    0xc8
+#define PMC_CPUPWROFF_TIMER     0xcc
+
+#define TEGRA_POWERGATE_PCIE    3
+#define TEGRA_POWERGATE_VDEC    4
+#define TEGRA_POWERGATE_CPU1    9
+#define TEGRA_POWERGATE_CPU2    10
+#define TEGRA_POWERGATE_CPU3    11
+
+static u8 tegra_cpu_domains[] = {
+        0xFF,                   /* not available for CPU0 */
+        TEGRA_POWERGATE_CPU1,
+        TEGRA_POWERGATE_CPU2,
+        TEGRA_POWERGATE_CPU3,
+};
+static DEFINE_SPINLOCK(tegra_powergate_lock);
+
+static void __iomem *tegra_pmc_base;
+static bool tegra_pmc_invert_interrupt;
+static struct clk *tegra_pclk;
+
+struct pmc_pm_data {
+        u32 cpu_good_time;      /* CPU power good time in uS */
+        u32 cpu_off_time;       /* CPU power off time in uS */
+        u32 core_osc_time;      /* Core power good osc time in uS */
+        u32 core_pmu_time;      /* Core power good pmu time in uS */
+        u32 core_off_time;      /* Core power off time in uS */
+        bool corereq_high;      /* Core power request active-high */
+        bool sysclkreq_high;    /* System clock request active-high */
+        bool combined_req;      /* Combined pwr req for CPU & Core */
+        bool cpu_pwr_good_en;   /* CPU power good signal is enabled */
+        u32 lp0_vec_phy_addr;   /* The phy addr of LP0 warm boot code */
+        u32 lp0_vec_size;       /* The size of LP0 warm boot code */
+        enum tegra_suspend_mode suspend_mode;
+};
+static struct pmc_pm_data pmc_pm_data;
 
 static inline u32 tegra_pmc_readl(u32 reg)
 {
-        return readl(IO_ADDRESS(TEGRA_PMC_BASE + reg));
+        return readl(tegra_pmc_base + reg);
 }
 
 static inline void tegra_pmc_writel(u32 val, u32 reg)
 {
-        writel(val, IO_ADDRESS(TEGRA_PMC_BASE + reg));
+        writel(val, tegra_pmc_base + reg);
+}
+
+static int tegra_pmc_get_cpu_powerdomain_id(int cpuid)
+{
+        if (cpuid <= 0 || cpuid >= num_possible_cpus())
+                return -EINVAL;
+        return tegra_cpu_domains[cpuid];
+}
+
+static bool tegra_pmc_powergate_is_powered(int id)
+{
+        return (tegra_pmc_readl(PMC_PWRGATE_STATUS) >> id) & 1;
+}
+
+static int tegra_pmc_powergate_set(int id, bool new_state)
+{
+        bool old_state;
+        unsigned long flags;
+
+        spin_lock_irqsave(&tegra_powergate_lock, flags);
+
+        old_state = tegra_pmc_powergate_is_powered(id);
+        WARN_ON(old_state == new_state);
+
+        tegra_pmc_writel(PMC_PWRGATE_TOGGLE_START | id, PMC_PWRGATE_TOGGLE);
+
+        spin_unlock_irqrestore(&tegra_powergate_lock, flags);
+
+        return 0;
+}
+
+static int tegra_pmc_powergate_remove_clamping(int id)
+{
+        u32 mask;
+
+        /*
+         * Tegra has a bug where PCIE and VDE clamping masks are
+         * swapped relatively to the partition ids.
+         */
+        if (id ==  TEGRA_POWERGATE_VDEC)
+                mask = (1 << TEGRA_POWERGATE_PCIE);
+        else if (id == TEGRA_POWERGATE_PCIE)
+                mask = (1 << TEGRA_POWERGATE_VDEC);
+        else
+                mask = (1 << id);
+
+        tegra_pmc_writel(mask, PMC_REMOVE_CLAMPING);
+
+        return 0;
+}
+
+bool tegra_pmc_cpu_is_powered(int cpuid)
+{
+        int id;
+
+        id = tegra_pmc_get_cpu_powerdomain_id(cpuid);
+        if (id < 0)
+                return false;
+        return tegra_pmc_powergate_is_powered(id);
 }
 
-#ifdef CONFIG_OF
+int tegra_pmc_cpu_power_on(int cpuid)
+{
+        int id;
+
+        id = tegra_pmc_get_cpu_powerdomain_id(cpuid);
+        if (id < 0)
+                return id;
+        return tegra_pmc_powergate_set(id, true);
+}
+
+int tegra_pmc_cpu_remove_clamping(int cpuid)
+{
+        int id;
+
+        id = tegra_pmc_get_cpu_powerdomain_id(cpuid);
+        if (id < 0)
+                return id;
+        return tegra_pmc_powergate_remove_clamping(id);
+}
+
+#ifdef CONFIG_PM_SLEEP
+static void set_power_timers(u32 us_on, u32 us_off, unsigned long rate)
+{
+        unsigned long long ticks;
+        unsigned long long pclk;
+        static unsigned long tegra_last_pclk;
+
+        if (WARN_ON_ONCE(rate <= 0))
+                pclk = 100000000;
+        else
+                pclk = rate;
+
+        if ((rate != tegra_last_pclk)) {
+                ticks = (us_on * pclk) + 999999ull;
+                do_div(ticks, 1000000);
+                tegra_pmc_writel((unsigned long)ticks, PMC_CPUPWRGOOD_TIMER);
+
+                ticks = (us_off * pclk) + 999999ull;
+                do_div(ticks, 1000000);
+                tegra_pmc_writel((unsigned long)ticks, PMC_CPUPWROFF_TIMER);
+                wmb();
+        }
+        tegra_last_pclk = pclk;
+}
+
+enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void)
+{
+        return pmc_pm_data.suspend_mode;
+}
+
+void tegra_pmc_pm_set(enum tegra_suspend_mode mode)
+{
+        u32 reg;
+        unsigned long rate = 0;
+
+        reg = tegra_pmc_readl(PMC_CTRL);
+        reg |= TEGRA_POWER_CPU_PWRREQ_OE;
+        reg &= ~TEGRA_POWER_EFFECT_LP0;
+
+        switch (mode) {
+        case TEGRA_SUSPEND_LP2:
+                rate = clk_get_rate(tegra_pclk);
+                break;
+        default:
+                break;
+        }
+
+        set_power_timers(pmc_pm_data.cpu_good_time, pmc_pm_data.cpu_off_time,
+                         rate);
+
+        tegra_pmc_writel(reg, PMC_CTRL);
+}
+
+void tegra_pmc_suspend_init(void)
+{
+        u32 reg;
+
+        /* Always enable CPU power request */
+        reg = tegra_pmc_readl(PMC_CTRL);
+        reg |= TEGRA_POWER_CPU_PWRREQ_OE;
+        tegra_pmc_writel(reg, PMC_CTRL);
+}
+#endif
+
 static const struct of_device_id matches[] __initconst = {
+        { .compatible = "nvidia,tegra114-pmc" },
+        { .compatible = "nvidia,tegra30-pmc" },
         { .compatible = "nvidia,tegra20-pmc" },
         { }
 };
-#endif
 
-void __init tegra_pmc_init(void)
+static void tegra_pmc_parse_dt(void)
 {
-        /*
-         * For now, Harmony is the only board that uses the PMC, and it wants
-         * the signal inverted. Seaboard would too if it used the PMC.
-         * Hopefully by the time other boards want to use the PMC, everything
-         * will be device-tree, or they also want it inverted.
-         */
-        bool invert_interrupt = true;
-        u32 val;
+        struct device_node *np;
+        u32 prop;
+        enum tegra_suspend_mode suspend_mode;
+        u32 core_good_time[2] = {0, 0};
+        u32 lp0_vec[2] = {0, 0};
 
-#ifdef CONFIG_OF
-        if (of_have_populated_dt()) {
-                struct device_node *np;
+        np = of_find_matching_node(NULL, matches);
+        BUG_ON(!np);
 
-                invert_interrupt = false;
+        tegra_pmc_base = of_iomap(np, 0);
 
-                np = of_find_matching_node(NULL, matches);
-                if (np) {
-                        if (of_find_property(np, "nvidia,invert-interrupt",
-                                                NULL))
-                                invert_interrupt = true;
+        tegra_pmc_invert_interrupt = of_property_read_bool(np,
+                                     "nvidia,invert-interrupt");
+        tegra_pclk = of_clk_get_by_name(np, "pclk");
+        WARN_ON(IS_ERR(tegra_pclk));
+
+        /* Grabbing the power management configurations */
+        if (of_property_read_u32(np, "nvidia,suspend-mode", &prop)) {
+                suspend_mode = TEGRA_SUSPEND_NONE;
+        } else {
+                switch (prop) {
+                case 0:
+                        suspend_mode = TEGRA_SUSPEND_LP0;
+                        break;
+                case 1:
+                        suspend_mode = TEGRA_SUSPEND_LP1;
+                        break;
+                case 2:
+                        suspend_mode = TEGRA_SUSPEND_LP2;
+                        break;
+                default:
+                        suspend_mode = TEGRA_SUSPEND_NONE;
+                        break;
                 }
         }
-#endif
+        suspend_mode = tegra_pm_validate_suspend_mode(suspend_mode);
+
+        if (of_property_read_u32(np, "nvidia,cpu-pwr-good-time", &prop))
+                suspend_mode = TEGRA_SUSPEND_NONE;
+        pmc_pm_data.cpu_good_time = prop;
+
+        if (of_property_read_u32(np, "nvidia,cpu-pwr-off-time", &prop))
+                suspend_mode = TEGRA_SUSPEND_NONE;
+        pmc_pm_data.cpu_off_time = prop;
+
+        if (of_property_read_u32_array(np, "nvidia,core-pwr-good-time",
+                        core_good_time, ARRAY_SIZE(core_good_time)))
+                suspend_mode = TEGRA_SUSPEND_NONE;
+        pmc_pm_data.core_osc_time = core_good_time[0];
+        pmc_pm_data.core_pmu_time = core_good_time[1];
+
+        if (of_property_read_u32(np, "nvidia,core-pwr-off-time",
+                                 &prop))
+                suspend_mode = TEGRA_SUSPEND_NONE;
+        pmc_pm_data.core_off_time = prop;
+
+        pmc_pm_data.corereq_high = of_property_read_bool(np,
+                                "nvidia,core-power-req-active-high");
+
+        pmc_pm_data.sysclkreq_high = of_property_read_bool(np,
+                                "nvidia,sys-clock-req-active-high");
+
+        pmc_pm_data.combined_req = of_property_read_bool(np,
+                                "nvidia,combined-power-req");
+
+        pmc_pm_data.cpu_pwr_good_en = of_property_read_bool(np,
+                                "nvidia,cpu-pwr-good-en");
+
+        if (of_property_read_u32_array(np, "nvidia,lp0-vec", lp0_vec,
+                                       ARRAY_SIZE(lp0_vec)))
+                if (suspend_mode == TEGRA_SUSPEND_LP0)
+                        suspend_mode = TEGRA_SUSPEND_LP1;
+
+        pmc_pm_data.lp0_vec_phy_addr = lp0_vec[0];
+        pmc_pm_data.lp0_vec_size = lp0_vec[1];
+
+        pmc_pm_data.suspend_mode = suspend_mode;
+}
+
+void __init tegra_pmc_init(void)
+{
+        u32 val;
+
+        tegra_pmc_parse_dt();
 
         val = tegra_pmc_readl(PMC_CTRL);
-        if (invert_interrupt)
+        if (tegra_pmc_invert_interrupt)
                 val |= PMC_CTRL_INTR_LOW;
         else
                 val &= ~PMC_CTRL_INTR_LOW;
diff --git a/arch/arm/mach-tegra/pmc.h b/arch/arm/mach-tegra/pmc.h
index 8995ee4a8768..e1c2df272f7d 100644
--- a/arch/arm/mach-tegra/pmc.h
+++ b/arch/arm/mach-tegra/pmc.h
@@ -18,6 +18,24 @@
 #ifndef __MACH_TEGRA_PMC_H
 #define __MACH_TEGRA_PMC_H
 
+enum tegra_suspend_mode {
+        TEGRA_SUSPEND_NONE = 0,
+        TEGRA_SUSPEND_LP2,      /* CPU voltage off */
+        TEGRA_SUSPEND_LP1,      /* CPU voltage off, DRAM self-refresh */
+        TEGRA_SUSPEND_LP0,      /* CPU + core voltage off, DRAM self-refresh */
+        TEGRA_MAX_SUSPEND_MODE,
+};
+
+#ifdef CONFIG_PM_SLEEP
+enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void);
+void tegra_pmc_pm_set(enum tegra_suspend_mode mode);
+void tegra_pmc_suspend_init(void);
+#endif
+
+bool tegra_pmc_cpu_is_powered(int cpuid);
+int tegra_pmc_cpu_power_on(int cpuid);
+int tegra_pmc_cpu_remove_clamping(int cpuid);
+
 void tegra_pmc_init(void);
 
 #endif
diff --git a/arch/arm/mach-tegra/reset-handler.S b/arch/arm/mach-tegra/reset-handler.S
index 54382ceade4a..1676aba5e7b8 100644
--- a/arch/arm/mach-tegra/reset-handler.S
+++ b/arch/arm/mach-tegra/reset-handler.S
@@ -41,9 +41,6 @@
  */
 ENTRY(tegra_resume)
         bl      v7_invalidate_l1
-        /* Enable coresight */
-        mov32   r0, 0xC5ACCE55
-        mcr     p14, 0, r0, c7, c12, 6
 
         cpu_id  r0
         cmp     r0, #0                          @ CPU0?
@@ -99,6 +96,8 @@ ENTRY(__tegra_cpu_reset_handler_start)
  *
  * Register usage within the reset handler:
  *
+ *      Others: scratch
+ *      R6  = SoC ID << 8
  *      R7  = CPU present (to the OS) mask
  *      R8  = CPU in LP1 state mask
  *      R9  = CPU in LP2 state mask
@@ -114,6 +113,40 @@ ENTRY(__tegra_cpu_reset_handler_start)
 ENTRY(__tegra_cpu_reset_handler)
 
         cpsid   aif, 0x13                       @ SVC mode, interrupts disabled
+
+        mov32   r6, TEGRA_APB_MISC_BASE
+        ldr     r6, [r6, #APB_MISC_GP_HIDREV]
+        and     r6, r6, #0xff00
+#ifdef CONFIG_ARCH_TEGRA_2x_SOC
+t20_check:
+        cmp     r6, #(0x20 << 8)
+        bne     after_t20_check
+t20_errata:
+        # Tegra20 is a Cortex-A9 r1p1
+        mrc     p15, 0, r0, c1, c0, 0   @ read system control register
+        orr     r0, r0, #1 << 14        @ erratum 716044
+        mcr     p15, 0, r0, c1, c0, 0   @ write system control register
+        mrc     p15, 0, r0, c15, c0, 1  @ read diagnostic register
+        orr     r0, r0, #1 << 4         @ erratum 742230
+        orr     r0, r0, #1 << 11        @ erratum 751472
+        mcr     p15, 0, r0, c15, c0, 1  @ write diagnostic register
+        b       after_errata
+after_t20_check:
+#endif
+#ifdef CONFIG_ARCH_TEGRA_3x_SOC
+t30_check:
+        cmp     r6, #(0x30 << 8)
+        bne     after_t30_check
+t30_errata:
+        # Tegra30 is a Cortex-A9 r2p9
+        mrc     p15, 0, r0, c15, c0, 1  @ read diagnostic register
+        orr     r0, r0, #1 << 6         @ erratum 743622
+        orr     r0, r0, #1 << 11        @ erratum 751472
+        mcr     p15, 0, r0, c15, c0, 1  @ write diagnostic register
+        b       after_errata
+after_t30_check:
+#endif
+after_errata:
         mrc     p15, 0, r10, c0, c0, 5          @ MPIDR
         and     r10, r10, #0x3                  @ R10 = CPU number
         mov     r11, #1
@@ -129,16 +162,13 @@ ENTRY(__tegra_cpu_reset_handler)
 
 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
         /* Are we on Tegra20? */
-        mov32   r6, TEGRA_APB_MISC_BASE
-        ldr     r0, [r6, #APB_MISC_GP_HIDREV]
-        and     r0, r0, #0xff00
-        cmp     r0, #(0x20 << 8)
+        cmp     r6, #(0x20 << 8)
         bne     1f
         /* If not CPU0, don't let CPU0 reset CPU1 now that CPU1 is coming up. */
-        mov32   r6, TEGRA_PMC_BASE
+        mov32   r5, TEGRA_PMC_BASE
         mov     r0, #0
         cmp     r10, #0
-        strne   r0, [r6, #PMC_SCRATCH41]
+        strne   r0, [r5, #PMC_SCRATCH41]
 1:
 #endif
 
diff --git a/arch/arm/mach-tegra/sleep.h b/arch/arm/mach-tegra/sleep.h
index 4ffae541726e..970ebd5138b9 100644
--- a/arch/arm/mach-tegra/sleep.h
+++ b/arch/arm/mach-tegra/sleep.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010-2012, NVIDIA Corporation. All rights reserved.
+ * Copyright (c) 2010-2013, NVIDIA Corporation. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -124,11 +124,11 @@ int tegra_sleep_cpu_finish(unsigned long);
 void tegra_disable_clean_inv_dcache(void);
 
 #ifdef CONFIG_HOTPLUG_CPU
-void tegra20_hotplug_init(void);
-void tegra30_hotplug_init(void);
+void tegra20_hotplug_shutdown(void);
+void tegra30_hotplug_shutdown(void);
+void tegra_hotplug_init(void);
 #else
-static inline void tegra20_hotplug_init(void) {}
-static inline void tegra30_hotplug_init(void) {}
+static inline void tegra_hotplug_init(void) {}
 #endif
 
 void tegra20_cpu_shutdown(int cpu);
diff --git a/arch/arm/mach-tegra/board-dt-tegra20.c b/arch/arm/mach-tegra/tegra.c
index a0edf2510280..61749e2d8111 100644
--- a/arch/arm/mach-tegra/board-dt-tegra20.c
+++ b/arch/arm/mach-tegra/tegra.c
@@ -1,6 +1,7 @@
 /*
- * nVidia Tegra device tree board support
+ * NVIDIA Tegra SoC device tree board support
  *
+ * Copyright (C) 2011, 2013, NVIDIA Corporation
  * Copyright (C) 2010 Secret Lab Technologies, Ltd.
  * Copyright (C) 2010 Google, Inc.
  *
@@ -32,7 +33,10 @@
 #include <linux/io.h>
 #include <linux/i2c.h>
 #include <linux/i2c-tegra.h>
+#include <linux/slab.h>
+#include <linux/sys_soc.h>
 #include <linux/usb/tegra_usb_phy.h>
+#include <linux/clk/tegra.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -41,6 +45,7 @@
 
 #include "board.h"
 #include "common.h"
+#include "fuse.h"
 #include "iomap.h"
 
 static struct tegra_ehci_platform_data tegra_ehci1_pdata = {
@@ -79,12 +84,38 @@ static struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = {
 
 static void __init tegra_dt_init(void)
 {
+        struct soc_device_attribute *soc_dev_attr;
+        struct soc_device *soc_dev;
+        struct device *parent = NULL;
+
+        tegra_clocks_apply_init_table();
+
+        soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
+        if (!soc_dev_attr)
+                goto out;
+
+        soc_dev_attr->family = kasprintf(GFP_KERNEL, "Tegra");
+        soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%d", tegra_revision);
+        soc_dev_attr->soc_id = kasprintf(GFP_KERNEL, "%d", tegra_chip_id);
+
+        soc_dev = soc_device_register(soc_dev_attr);
+        if (IS_ERR(soc_dev)) {
+                kfree(soc_dev_attr->family);
+                kfree(soc_dev_attr->revision);
+                kfree(soc_dev_attr->soc_id);
+                kfree(soc_dev_attr);
+                goto out;
+        }
+
+        parent = soc_device_to_device(soc_dev);
+
         /*
          * Finished with the static registrations now; fill in the missing
          * devices
          */
+out:
         of_platform_populate(NULL, of_default_bus_match_table,
-                                tegra20_auxdata_lookup, NULL);
+                                tegra20_auxdata_lookup, parent);
 }
 
 static void __init trimslice_init(void)
@@ -111,7 +142,8 @@ static void __init harmony_init(void)
 
 static void __init paz00_init(void)
 {
-        tegra_paz00_wifikill_init();
+        if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC))
+                tegra_paz00_wifikill_init();
 }
 
 static struct {
@@ -137,19 +169,21 @@ static void __init tegra_dt_init_late(void)
         }
 }
 
-static const char *tegra20_dt_board_compat[] = {
+static const char * const tegra_dt_board_compat[] = {
+        "nvidia,tegra114",
+        "nvidia,tegra30",
         "nvidia,tegra20",
         NULL
 };
 
-DT_MACHINE_START(TEGRA_DT, "nVidia Tegra20 (Flattened Device Tree)")
+DT_MACHINE_START(TEGRA_DT, "NVIDIA Tegra SoC (Flattened Device Tree)")
         .map_io         = tegra_map_common_io,
         .smp            = smp_ops(tegra_smp_ops),
-        .init_early     = tegra20_init_early,
+        .init_early     = tegra_init_early,
         .init_irq       = tegra_dt_init_irq,
         .init_time      = clocksource_of_init,
         .init_machine   = tegra_dt_init,
         .init_late      = tegra_dt_init_late,
         .restart        = tegra_assert_system_reset,
-        .dt_compat      = tegra20_dt_board_compat,
+        .dt_compat      = tegra_dt_board_compat,
 MACHINE_END
diff --git a/arch/arm/mach-tegra/tegra114_speedo.c b/arch/arm/mach-tegra/tegra114_speedo.c
new file mode 100644
index 000000000000..5218d4853cd3
--- /dev/null
+++ b/arch/arm/mach-tegra/tegra114_speedo.c
@@ -0,0 +1,104 @@
+/*
+ * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/kernel.h>
+#include <linux/bug.h>
+
+#include "fuse.h"
+
+#define CORE_PROCESS_CORNERS_NUM        2
+#define CPU_PROCESS_CORNERS_NUM         2
+
+enum {
+        THRESHOLD_INDEX_0,
+        THRESHOLD_INDEX_1,
+        THRESHOLD_INDEX_COUNT,
+};
+
+static const u32 core_process_speedos[][CORE_PROCESS_CORNERS_NUM] = {
+        {1123,     UINT_MAX},
+        {0,        UINT_MAX},
+};
+
+static const u32 cpu_process_speedos[][CPU_PROCESS_CORNERS_NUM] = {
+        {1695,     UINT_MAX},
+        {0,        UINT_MAX},
+};
+
+static void rev_sku_to_speedo_ids(int rev, int sku, int *threshold)
+{
+        u32 tmp;
+
+        switch (sku) {
+        case 0x00:
+        case 0x10:
+        case 0x05:
+        case 0x06:
+                tegra_cpu_speedo_id = 1;
+                tegra_soc_speedo_id = 0;
+                *threshold = THRESHOLD_INDEX_0;
+                break;
+
+        case 0x03:
+        case 0x04:
+                tegra_cpu_speedo_id = 2;
+                tegra_soc_speedo_id = 1;
+                *threshold = THRESHOLD_INDEX_1;
+                break;
+
+        default:
+                pr_err("Tegra114 Unknown SKU %d\n", sku);
+                tegra_cpu_speedo_id = 0;
+                tegra_soc_speedo_id = 0;
+                *threshold = THRESHOLD_INDEX_0;
+                break;
+        }
+
+        if (rev == TEGRA_REVISION_A01) {
+                tmp = tegra_fuse_readl(0x270) << 1;
+                tmp |= tegra_fuse_readl(0x26c);
+                if (!tmp)
+                        tegra_cpu_speedo_id = 0;
+        }
+}
+
+void tegra114_init_speedo_data(void)
+{
+        u32 cpu_speedo_val;
+        u32 core_speedo_val;
+        int threshold;
+        int i;
+
+        BUILD_BUG_ON(ARRAY_SIZE(cpu_process_speedos) !=
+                        THRESHOLD_INDEX_COUNT);
+        BUILD_BUG_ON(ARRAY_SIZE(core_process_speedos) !=
+                        THRESHOLD_INDEX_COUNT);
+
+        rev_sku_to_speedo_ids(tegra_revision, tegra_sku_id, &threshold);
+
+        cpu_speedo_val = tegra_fuse_readl(0x12c) + 1024;
+        core_speedo_val = tegra_fuse_readl(0x134);
+
+        for (i = 0; i < CPU_PROCESS_CORNERS_NUM; i++)
+                if (cpu_speedo_val < cpu_process_speedos[threshold][i])
+                        break;
+        tegra_cpu_process_id = i;
+
+        for (i = 0; i < CORE_PROCESS_CORNERS_NUM; i++)
+                if (core_speedo_val < core_process_speedos[threshold][i])
+                        break;
+        tegra_core_process_id = i;
+}
diff --git a/arch/arm/mach-tegra/tegra2_emc.c b/arch/arm/mach-tegra/tegra2_emc.c
index ce7ce42a1ac9..9e8bdfa2b369 100644
--- a/arch/arm/mach-tegra/tegra2_emc.c
+++ b/arch/arm/mach-tegra/tegra2_emc.c
@@ -276,7 +276,7 @@ static struct tegra_emc_pdata *tegra_emc_fill_pdata(struct platform_device *pdev
         int i;
 
         WARN_ON(pdev->dev.platform_data);
-        BUG_ON(IS_ERR_OR_NULL(c));
+        BUG_ON(IS_ERR(c));
 
         pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
         pdata->tables = devm_kzalloc(&pdev->dev, sizeof(*pdata->tables),
diff --git a/arch/arm/mach-ux500/board-mop500-pins.c b/arch/arm/mach-ux500/board-mop500-pins.c
index 0a3f30df1eb8..152ae38cd18c 100644
--- a/arch/arm/mach-ux500/board-mop500-pins.c
+++ b/arch/arm/mach-ux500/board-mop500-pins.c
@@ -48,8 +48,12 @@ BIAS(slpm_in_nopull_wkup, PIN_SLEEPMODE_ENABLED|
         PIN_SLPM_DIR_INPUT|PIN_SLPM_PULL_NONE|PIN_SLPM_WAKEUP_ENABLE);
 BIAS(slpm_in_wkup_pdis, PIN_SLEEPMODE_ENABLED|
         PIN_SLPM_DIR_INPUT|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
+BIAS(slpm_in_wkup_pdis_en, PIN_SLEEPMODE_ENABLED|
+        PIN_SLPM_DIR_INPUT|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_ENABLED);
 BIAS(slpm_wkup_pdis, PIN_SLEEPMODE_ENABLED|
         PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
+BIAS(slpm_wkup_pdis_en, PIN_SLEEPMODE_ENABLED|
+        PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_ENABLED);
 BIAS(slpm_out_lo_pdis, PIN_SLEEPMODE_ENABLED|
         PIN_SLPM_OUTPUT_LOW|PIN_SLPM_WAKEUP_DISABLE|PIN_SLPM_PDIS_DISABLED);
 BIAS(slpm_out_lo_wkup, PIN_SLEEPMODE_ENABLED|
@@ -78,9 +82,6 @@ BIAS(out_wkup_pdis, PIN_SLPM_DIR_OUTPUT|PIN_SLPM_WAKEUP_ENABLE|
         PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-db8500", group, func)
 #define DB8500_PIN_HOG(pin,conf) \
         PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-db8500", pin, conf)
-#define DB8500_PIN_SLEEP(pin, conf, dev) \
-        PIN_MAP_CONFIGS_PIN(dev, PINCTRL_STATE_SLEEP, "pinctrl-db8500", \
-                            pin, conf)
 
 /* These are default states associated with device and changed runtime */
 #define DB8500_MUX(group,func,dev) \
@@ -309,8 +310,23 @@ static struct pinctrl_map __initdata mop500_family_pinmap[] = {
         DB8500_PIN_SLEEP("GPIO207_AJ23", slpm_in_wkup_pdis, "sdi4"), /* DAT4 */
 
         /* Mux in USB pins, drive STP high */
-        DB8500_MUX("usb_a_1", "usb", "musb-ux500.0"),
-        DB8500_PIN("GPIO257_AE29", out_hi, "musb-ux500.0"), /* STP */
+        /* USB default state */
+        DB8500_MUX("usb_a_1", "usb", "ab8500-usb.0"),
+        DB8500_PIN("GPIO257_AE29", out_hi, "ab8500-usb.0"), /* STP */
+        /* USB sleep state */
+        DB8500_PIN_SLEEP("GPIO256_AF28", slpm_wkup_pdis_en, "ab8500-usb.0"), /* NXT */
+        DB8500_PIN_SLEEP("GPIO257_AE29", slpm_out_hi_wkup_pdis, "ab8500-usb.0"), /* STP */
+        DB8500_PIN_SLEEP("GPIO258_AD29", slpm_wkup_pdis_en, "ab8500-usb.0"), /* XCLK */
+        DB8500_PIN_SLEEP("GPIO259_AC29", slpm_wkup_pdis_en, "ab8500-usb.0"), /* DIR */
+        DB8500_PIN_SLEEP("GPIO260_AD28", slpm_in_wkup_pdis_en, "ab8500-usb.0"), /* DAT7 */
+        DB8500_PIN_SLEEP("GPIO261_AD26", slpm_in_wkup_pdis_en, "ab8500-usb.0"), /* DAT6 */
+        DB8500_PIN_SLEEP("GPIO262_AE26", slpm_in_wkup_pdis_en, "ab8500-usb.0"), /* DAT5 */
+        DB8500_PIN_SLEEP("GPIO263_AG29", slpm_in_wkup_pdis_en, "ab8500-usb.0"), /* DAT4 */
+        DB8500_PIN_SLEEP("GPIO264_AE27", slpm_in_wkup_pdis_en, "ab8500-usb.0"), /* DAT3 */
+        DB8500_PIN_SLEEP("GPIO265_AD27", slpm_in_wkup_pdis_en, "ab8500-usb.0"), /* DAT2 */
+        DB8500_PIN_SLEEP("GPIO266_AC28", slpm_in_wkup_pdis_en, "ab8500-usb.0"), /* DAT1 */
+        DB8500_PIN_SLEEP("GPIO267_AC27", slpm_in_wkup_pdis_en, "ab8500-usb.0"), /* DAT0 */
+
         /* Mux in SPI2 pins on the "other C1" altfunction */
         DB8500_MUX("spi2_oc1_2", "spi2", "spi2"),
         DB8500_PIN("GPIO216_AG12", gpio_out_hi, "spi2"), /* FRM */
@@ -318,9 +334,9 @@ static struct pinctrl_map __initdata mop500_family_pinmap[] = {
         DB8500_PIN("GPIO215_AH13", out_lo, "spi2"), /* TXD */
         DB8500_PIN("GPIO217_AH12", out_lo, "spi2"), /* CLK */
         /* SPI2 idle state */
-        DB8500_PIN_SLEEP("GPIO218_AH11", slpm_in_wkup_pdis, "spi2"), /* RXD */
-        DB8500_PIN_SLEEP("GPIO215_AH13", slpm_out_lo_wkup_pdis, "spi2"), /* TXD */
-        DB8500_PIN_SLEEP("GPIO217_AH12", slpm_wkup_pdis, "spi2"), /* CLK */
+        DB8500_PIN_IDLE("GPIO218_AH11", slpm_in_wkup_pdis, "spi2"), /* RXD */
+        DB8500_PIN_IDLE("GPIO215_AH13", slpm_out_lo_wkup_pdis, "spi2"), /* TXD */
+        DB8500_PIN_IDLE("GPIO217_AH12", slpm_wkup_pdis, "spi2"), /* CLK */
         /* SPI2 sleep state */
         DB8500_PIN_SLEEP("GPIO216_AG12", slpm_in_wkup_pdis, "spi2"), /* FRM */
         DB8500_PIN_SLEEP("GPIO218_AH11", slpm_in_wkup_pdis, "spi2"), /* RXD */
@@ -747,6 +763,8 @@ static struct pinctrl_map __initdata snowball_pinmap[] = {
         DB8500_PIN_HOG("GPIO21_AB3", out_hi),
         /* Mux in "SM" which is used for the SMSC911x Ethernet adapter */
         DB8500_MUX_HOG("sm_b_1", "sm"),
+        /* User LED */
+        DB8500_PIN_HOG("GPIO142_C11", gpio_out_hi),
         /* Drive RSTn_LAN high */
         DB8500_PIN_HOG("GPIO141_C12", gpio_out_hi),
         /*  Accelerometer/Magnetometer */
diff --git a/arch/arm/mach-ux500/cpu.c b/arch/arm/mach-ux500/cpu.c
index 537870d3fea8..002da9a369d5 100644
--- a/arch/arm/mach-ux500/cpu.c
+++ b/arch/arm/mach-ux500/cpu.c
@@ -140,14 +140,13 @@ struct device * __init ux500_soc_device_init(const char *soc_id)
         soc_info_populate(soc_dev_attr, soc_id);
 
         soc_dev = soc_device_register(soc_dev_attr);
-        if (IS_ERR_OR_NULL(soc_dev)) {
+        if (IS_ERR(soc_dev)) {
                 kfree(soc_dev_attr);
                 return NULL;
         }
 
         parent = soc_device_to_device(soc_dev);
-        if (!IS_ERR_OR_NULL(parent))
-                device_create_file(parent, &ux500_soc_attr);
+        device_create_file(parent, &ux500_soc_attr);
 
         return parent;
 }
diff --git a/arch/arm/mach-ux500/timer.c b/arch/arm/mach-ux500/timer.c
index a6af0b8732ba..d07bbe7f04a6 100644
--- a/arch/arm/mach-ux500/timer.c
+++ b/arch/arm/mach-ux500/timer.c
@@ -7,6 +7,7 @@
 #include <linux/io.h>
 #include <linux/errno.h>
 #include <linux/clksrc-dbx500-prcmu.h>
+#include <linux/clocksource.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
 #include <linux/platform_data/clocksource-nomadik-mtu.h>
@@ -32,7 +33,7 @@ static void __init ux500_twd_init(void)
         twd_local_timer = &u8500_twd_local_timer;
 
         if (of_have_populated_dt())
-                twd_local_timer_of_register();
+                clocksource_of_init();
         else {
                 err = twd_local_timer_register(twd_local_timer);
                 if (err)
diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c
index 25160aeaa3b7..54bb80b012ac 100644
--- a/arch/arm/mach-versatile/core.c
+++ b/arch/arm/mach-versatile/core.c
@@ -749,12 +749,25 @@ void versatile_restart(char mode, const char *cmd)
 /* Early initializations */
 void __init versatile_init_early(void)
 {
+        u32 val;
         void __iomem *sys = __io_address(VERSATILE_SYS_BASE);
 
         osc4_clk.vcoreg = sys + VERSATILE_SYS_OSCCLCD_OFFSET;
         clkdev_add_table(lookups, ARRAY_SIZE(lookups));
 
         versatile_sched_clock_init(sys + VERSATILE_SYS_24MHz_OFFSET, 24000000);
+
+        /*
+         * set clock frequency:
+         *      VERSATILE_REFCLK is 32KHz
+         *      VERSATILE_TIMCLK is 1MHz
+         */
+        val = readl(__io_address(VERSATILE_SCTL_BASE));
+        writel((VERSATILE_TIMCLK << VERSATILE_TIMER1_EnSel) |
+               (VERSATILE_TIMCLK << VERSATILE_TIMER2_EnSel) |
+               (VERSATILE_TIMCLK << VERSATILE_TIMER3_EnSel) |
+               (VERSATILE_TIMCLK << VERSATILE_TIMER4_EnSel) | val,
+               __io_address(VERSATILE_SCTL_BASE));
 }
 
 void __init versatile_init(void)
@@ -785,19 +798,6 @@ void __init versatile_init(void)
  */
 void __init versatile_timer_init(void)
 {
-        u32 val;
-
-        /* 
-         * set clock frequency: 
-         *      VERSATILE_REFCLK is 32KHz
-         *      VERSATILE_TIMCLK is 1MHz
-         */
-        val = readl(__io_address(VERSATILE_SCTL_BASE));
-        writel((VERSATILE_TIMCLK << VERSATILE_TIMER1_EnSel) |
-               (VERSATILE_TIMCLK << VERSATILE_TIMER2_EnSel) | 
-               (VERSATILE_TIMCLK << VERSATILE_TIMER3_EnSel) |
-               (VERSATILE_TIMCLK << VERSATILE_TIMER4_EnSel) | val,
-               __io_address(VERSATILE_SCTL_BASE));
 
         /*
          * Initialise to a known state (all timers off)
diff --git a/arch/arm/mach-versatile/versatile_dt.c b/arch/arm/mach-versatile/versatile_dt.c
index 2558f2e957c3..3621b000a0f6 100644
--- a/arch/arm/mach-versatile/versatile_dt.c
+++ b/arch/arm/mach-versatile/versatile_dt.c
@@ -45,7 +45,6 @@ DT_MACHINE_START(VERSATILE_PB, "ARM-Versatile (Device Tree Support)")
         .map_io         = versatile_map_io,
         .init_early     = versatile_init_early,
         .init_irq       = versatile_init_irq,
-        .init_time      = versatile_timer_init,
         .init_machine   = versatile_dt_init,
         .dt_compat      = versatile_dt_match,
         .restart        = versatile_restart,
diff --git a/arch/arm/mach-vexpress/v2m.c b/arch/arm/mach-vexpress/v2m.c
index 915683cb67d6..09e571ddc984 100644
--- a/arch/arm/mach-vexpress/v2m.c
+++ b/arch/arm/mach-vexpress/v2m.c
@@ -1,10 +1,12 @@
 /*
  * Versatile Express V2M Motherboard Support
  */
+#include <linux/clocksource.h>
 #include <linux/device.h>
 #include <linux/amba/bus.h>
 #include <linux/amba/mmci.h>
 #include <linux/io.h>
+#include <linux/clocksource.h>
 #include <linux/smp.h>
 #include <linux/init.h>
 #include <linux/irqchip.h>
@@ -22,10 +24,8 @@
 #include <linux/regulator/machine.h>
 #include <linux/vexpress.h>
 
-#include <asm/arch_timer.h>
 #include <asm/mach-types.h>
 #include <asm/sizes.h>
-#include <asm/smp_twd.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
@@ -61,9 +61,6 @@ static void __init v2m_sp804_init(void __iomem *base, unsigned int irq)
         if (WARN_ON(!base || irq == NO_IRQ))
                 return;
 
-        writel(0, base + TIMER_1_BASE + TIMER_CTRL);
-        writel(0, base + TIMER_2_BASE + TIMER_CTRL);
-
         sp804_clocksource_init(base + TIMER_2_BASE, "v2m-timer1");
         sp804_clockevents_init(base + TIMER_1_BASE, irq, "v2m-timer0");
 }
@@ -431,25 +428,11 @@ void __init v2m_dt_init_early(void)
 
 static void __init v2m_dt_timer_init(void)
 {
-        struct device_node *node = NULL;
-
         vexpress_clk_of_init();
 
-        do {
-                node = of_find_compatible_node(node, NULL, "arm,sp804");
-        } while (node && vexpress_get_site_by_node(node) != VEXPRESS_SITE_MB);
-        if (node) {
-                pr_info("Using SP804 '%s' as a clock & events source\n",
-                                node->full_name);
-                v2m_sp804_init(of_iomap(node, 0),
-                                irq_of_parse_and_map(node, 0));
-        }
-
-        if (arch_timer_of_register() != 0)
-                twd_local_timer_of_register();
+        clocksource_of_init();
 
-        if (arch_timer_sched_clock_init() != 0)
-                versatile_sched_clock_init(vexpress_get_24mhz_clock_base(),
+        versatile_sched_clock_init(vexpress_get_24mhz_clock_base(),
                                 24000000);
 }
 
diff --git a/arch/arm/mach-virt/virt.c b/arch/arm/mach-virt/virt.c
index 31666f6b4373..adc0945255ae 100644
--- a/arch/arm/mach-virt/virt.c
+++ b/arch/arm/mach-virt/virt.c
@@ -23,21 +23,13 @@
 #include <linux/of_platform.h>
 #include <linux/smp.h>
 
-#include <asm/arch_timer.h>
 #include <asm/mach/arch.h>
-#include <asm/mach/time.h>
 
 static void __init virt_init(void)
 {
         of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
 
-static void __init virt_timer_init(void)
-{
-        WARN_ON(arch_timer_of_register() != 0);
-        WARN_ON(arch_timer_sched_clock_init() != 0);
-}
-
 static const char *virt_dt_match[] = {
         "linux,dummy-virt",
         NULL
@@ -47,7 +39,6 @@ extern struct smp_operations virt_smp_ops;
 
 DT_MACHINE_START(VIRT, "Dummy Virtual Machine")
         .init_irq       = irqchip_init,
-        .init_time      = virt_timer_init,
         .init_machine   = virt_init,
         .smp            = smp_ops(virt_smp_ops),
         .dt_compat      = virt_dt_match,
diff --git a/arch/arm/mach-vt8500/Kconfig b/arch/arm/mach-vt8500/Kconfig
index e3e94b2fa145..9b252934b206 100644
--- a/arch/arm/mach-vt8500/Kconfig
+++ b/arch/arm/mach-vt8500/Kconfig
@@ -7,6 +7,7 @@ config ARCH_VT8500
         select GENERIC_CLOCKEVENTS
         select HAVE_CLK
         select VT8500_TIMER
+        select PINCTRL
         help
           Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
 
diff --git a/arch/arm/mach-zynq/Kconfig b/arch/arm/mach-zynq/Kconfig
index adb6c0ea0e53..d70651e8b705 100644
--- a/arch/arm/mach-zynq/Kconfig
+++ b/arch/arm/mach-zynq/Kconfig
@@ -9,5 +9,6 @@ config ARCH_ZYNQ
         select MIGHT_HAVE_CACHE_L2X0
         select USE_OF
         select SPARSE_IRQ
+        select CADENCE_TTC_TIMER
         help
           Support for Xilinx Zynq ARM Cortex A9 Platform
diff --git a/arch/arm/mach-zynq/Makefile b/arch/arm/mach-zynq/Makefile
index 397268c1b250..320faedeb484 100644
--- a/arch/arm/mach-zynq/Makefile
+++ b/arch/arm/mach-zynq/Makefile
@@ -3,4 +3,4 @@
 #
 
 # Common support
-obj-y                           := common.o timer.o
+obj-y                           := common.o
diff --git a/arch/arm/mach-zynq/common.c b/arch/arm/mach-zynq/common.c
index 5c8983218183..68e0907de5d0 100644
--- a/arch/arm/mach-zynq/common.c
+++ b/arch/arm/mach-zynq/common.c
@@ -20,6 +20,7 @@
 #include <linux/platform_device.h>
 #include <linux/clk.h>
 #include <linux/clk/zynq.h>
+#include <linux/clocksource.h>
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
@@ -77,7 +78,7 @@ static void __init xilinx_zynq_timer_init(void)
 
         xilinx_zynq_clocks_init(slcr);
 
-        xttcps_timer_init();
+        clocksource_of_init();
 }
 
 /**
diff --git a/arch/arm/mach-zynq/common.h b/arch/arm/mach-zynq/common.h
index 8b4dbbaa01cf..5050bb10bb12 100644
--- a/arch/arm/mach-zynq/common.h
+++ b/arch/arm/mach-zynq/common.h
@@ -17,6 +17,4 @@
 #ifndef __MACH_ZYNQ_COMMON_H__
 #define __MACH_ZYNQ_COMMON_H__
 
-void __init xttcps_timer_init(void);
-
 #endif
diff --git a/arch/arm/mach-zynq/timer.c b/arch/arm/mach-zynq/timer.c
deleted file mode 100644
index f9fbc9c1e7a6..000000000000
--- a/arch/arm/mach-zynq/timer.c
+++ /dev/null
@@ -1,324 +0,0 @@
-/*
- * This file contains driver for the Xilinx PS Timer Counter IP.
- *
- *  Copyright (C) 2011 Xilinx
- *
- * based on arch/mips/kernel/time.c timer driver
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <linux/interrupt.h>
-#include <linux/clockchips.h>
-#include <linux/of_address.h>
-#include <linux/of_irq.h>
-#include <linux/slab.h>
-#include <linux/clk-provider.h>
-#include "common.h"
-
-/*
- * Timer Register Offset Definitions of Timer 1, Increment base address by 4
- * and use same offsets for Timer 2
- */
-#define XTTCPS_CLK_CNTRL_OFFSET         0x00 /* Clock Control Reg, RW */
-#define XTTCPS_CNT_CNTRL_OFFSET         0x0C /* Counter Control Reg, RW */
-#define XTTCPS_COUNT_VAL_OFFSET         0x18 /* Counter Value Reg, RO */
-#define XTTCPS_INTR_VAL_OFFSET          0x24 /* Interval Count Reg, RW */
-#define XTTCPS_ISR_OFFSET               0x54 /* Interrupt Status Reg, RO */
-#define XTTCPS_IER_OFFSET               0x60 /* Interrupt Enable Reg, RW */
-
-#define XTTCPS_CNT_CNTRL_DISABLE_MASK   0x1
-
-/*
- * Setup the timers to use pre-scaling, using a fixed value for now that will
- * work across most input frequency, but it may need to be more dynamic
- */
-#define PRESCALE_EXPONENT       11      /* 2 ^ PRESCALE_EXPONENT = PRESCALE */
-#define PRESCALE                2048    /* The exponent must match this */
-#define CLK_CNTRL_PRESCALE      ((PRESCALE_EXPONENT - 1) << 1)
-#define CLK_CNTRL_PRESCALE_EN   1
-#define CNT_CNTRL_RESET         (1<<4)
-
-/**
- * struct xttcps_timer - This definition defines local timer structure
- *
- * @base_addr:  Base address of timer
- **/
-struct xttcps_timer {
-        void __iomem    *base_addr;
-};
-
-struct xttcps_timer_clocksource {
-        struct xttcps_timer     xttc;
-        struct clocksource      cs;
-};
-
-#define to_xttcps_timer_clksrc(x) \
-                container_of(x, struct xttcps_timer_clocksource, cs)
-
-struct xttcps_timer_clockevent {
-        struct xttcps_timer             xttc;
-        struct clock_event_device       ce;
-        struct clk                      *clk;
-};
-
-#define to_xttcps_timer_clkevent(x) \
-                container_of(x, struct xttcps_timer_clockevent, ce)
-
-/**
- * xttcps_set_interval - Set the timer interval value
- *
- * @timer:      Pointer to the timer instance
- * @cycles:     Timer interval ticks
- **/
-static void xttcps_set_interval(struct xttcps_timer *timer,
-                                        unsigned long cycles)
-{
-        u32 ctrl_reg;
-
-        /* Disable the counter, set the counter value  and re-enable counter */
-        ctrl_reg = __raw_readl(timer->base_addr + XTTCPS_CNT_CNTRL_OFFSET);
-        ctrl_reg |= XTTCPS_CNT_CNTRL_DISABLE_MASK;
-        __raw_writel(ctrl_reg, timer->base_addr + XTTCPS_CNT_CNTRL_OFFSET);
-
-        __raw_writel(cycles, timer->base_addr + XTTCPS_INTR_VAL_OFFSET);
-
-        /*
-         * Reset the counter (0x10) so that it starts from 0, one-shot
-         * mode makes this needed for timing to be right.
-         */
-        ctrl_reg |= CNT_CNTRL_RESET;
-        ctrl_reg &= ~XTTCPS_CNT_CNTRL_DISABLE_MASK;
-        __raw_writel(ctrl_reg, timer->base_addr + XTTCPS_CNT_CNTRL_OFFSET);
-}
-
-/**
- * xttcps_clock_event_interrupt - Clock event timer interrupt handler
- *
- * @irq:        IRQ number of the Timer
- * @dev_id:     void pointer to the xttcps_timer instance
- *
- * returns: Always IRQ_HANDLED - success
- **/
-static irqreturn_t xttcps_clock_event_interrupt(int irq, void *dev_id)
-{
-        struct xttcps_timer_clockevent *xttce = dev_id;
-        struct xttcps_timer *timer = &xttce->xttc;
-
-        /* Acknowledge the interrupt and call event handler */
-        __raw_readl(timer->base_addr + XTTCPS_ISR_OFFSET);
-
-        xttce->ce.event_handler(&xttce->ce);
-
-        return IRQ_HANDLED;
-}
-
-/**
- * __xttc_clocksource_read - Reads the timer counter register
- *
- * returns: Current timer counter register value
- **/
-static cycle_t __xttc_clocksource_read(struct clocksource *cs)
-{
-        struct xttcps_timer *timer = &to_xttcps_timer_clksrc(cs)->xttc;
-
-        return (cycle_t)__raw_readl(timer->base_addr +
-                                XTTCPS_COUNT_VAL_OFFSET);
-}
-
-/**
- * xttcps_set_next_event - Sets the time interval for next event
- *
- * @cycles:     Timer interval ticks
- * @evt:        Address of clock event instance
- *
- * returns: Always 0 - success
- **/
-static int xttcps_set_next_event(unsigned long cycles,
-                                        struct clock_event_device *evt)
-{
-        struct xttcps_timer_clockevent *xttce = to_xttcps_timer_clkevent(evt);
-        struct xttcps_timer *timer = &xttce->xttc;
-
-        xttcps_set_interval(timer, cycles);
-        return 0;
-}
-
-/**
- * xttcps_set_mode - Sets the mode of timer
- *
- * @mode:       Mode to be set
- * @evt:        Address of clock event instance
- **/
-static void xttcps_set_mode(enum clock_event_mode mode,
-                                        struct clock_event_device *evt)
-{
-        struct xttcps_timer_clockevent *xttce = to_xttcps_timer_clkevent(evt);
-        struct xttcps_timer *timer = &xttce->xttc;
-        u32 ctrl_reg;
-
-        switch (mode) {
-        case CLOCK_EVT_MODE_PERIODIC:
-                xttcps_set_interval(timer,
-                                     DIV_ROUND_CLOSEST(clk_get_rate(xttce->clk),
-                                                       PRESCALE * HZ));
-                break;
-        case CLOCK_EVT_MODE_ONESHOT:
-        case CLOCK_EVT_MODE_UNUSED:
-        case CLOCK_EVT_MODE_SHUTDOWN:
-                ctrl_reg = __raw_readl(timer->base_addr +
-                                        XTTCPS_CNT_CNTRL_OFFSET);
-                ctrl_reg |= XTTCPS_CNT_CNTRL_DISABLE_MASK;
-                __raw_writel(ctrl_reg,
-                                timer->base_addr + XTTCPS_CNT_CNTRL_OFFSET);
-                break;
-        case CLOCK_EVT_MODE_RESUME:
-                ctrl_reg = __raw_readl(timer->base_addr +
-                                        XTTCPS_CNT_CNTRL_OFFSET);
-                ctrl_reg &= ~XTTCPS_CNT_CNTRL_DISABLE_MASK;
-                __raw_writel(ctrl_reg,
-                                timer->base_addr + XTTCPS_CNT_CNTRL_OFFSET);
-                break;
-        }
-}
-
-static void __init zynq_ttc_setup_clocksource(struct device_node *np,
-                                             void __iomem *base)
-{
-        struct xttcps_timer_clocksource *ttccs;
-        struct clk *clk;
-        int err;
-        u32 reg;
-
-        ttccs = kzalloc(sizeof(*ttccs), GFP_KERNEL);
-        if (WARN_ON(!ttccs))
-                return;
-
-        err = of_property_read_u32(np, "reg", &reg);
-        if (WARN_ON(err))
-                return;
-
-        clk = of_clk_get_by_name(np, "cpu_1x");
-        if (WARN_ON(IS_ERR(clk)))
-                return;
-
-        err = clk_prepare_enable(clk);
-        if (WARN_ON(err))
-                return;
-
-        ttccs->xttc.base_addr = base + reg * 4;
-
-        ttccs->cs.name = np->name;
-        ttccs->cs.rating = 200;
-        ttccs->cs.read = __xttc_clocksource_read;
-        ttccs->cs.mask = CLOCKSOURCE_MASK(16);
-        ttccs->cs.flags = CLOCK_SOURCE_IS_CONTINUOUS;
-
-        __raw_writel(0x0,  ttccs->xttc.base_addr + XTTCPS_IER_OFFSET);
-        __raw_writel(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN,
-                     ttccs->xttc.base_addr + XTTCPS_CLK_CNTRL_OFFSET);
-        __raw_writel(CNT_CNTRL_RESET,
-                     ttccs->xttc.base_addr + XTTCPS_CNT_CNTRL_OFFSET);
-
-        err = clocksource_register_hz(&ttccs->cs, clk_get_rate(clk) / PRESCALE);
-        if (WARN_ON(err))
-                return;
-}
-
-static void __init zynq_ttc_setup_clockevent(struct device_node *np,
-                                            void __iomem *base)
-{
-        struct xttcps_timer_clockevent *ttcce;
-        int err, irq;
-        u32 reg;
-
-        ttcce = kzalloc(sizeof(*ttcce), GFP_KERNEL);
-        if (WARN_ON(!ttcce))
-                return;
-
-        err = of_property_read_u32(np, "reg", &reg);
-        if (WARN_ON(err))
-                return;
-
-        ttcce->xttc.base_addr = base + reg * 4;
-
-        ttcce->clk = of_clk_get_by_name(np, "cpu_1x");
-        if (WARN_ON(IS_ERR(ttcce->clk)))
-                return;
-
-        err = clk_prepare_enable(ttcce->clk);
-        if (WARN_ON(err))
-                return;
-
-        irq = irq_of_parse_and_map(np, 0);
-        if (WARN_ON(!irq))
-                return;
-
-        ttcce->ce.name = np->name;
-        ttcce->ce.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
-        ttcce->ce.set_next_event = xttcps_set_next_event;
-        ttcce->ce.set_mode = xttcps_set_mode;
-        ttcce->ce.rating = 200;
-        ttcce->ce.irq = irq;
-        ttcce->ce.cpumask = cpu_possible_mask;
-
-        __raw_writel(0x23, ttcce->xttc.base_addr + XTTCPS_CNT_CNTRL_OFFSET);
-        __raw_writel(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN,
-                     ttcce->xttc.base_addr + XTTCPS_CLK_CNTRL_OFFSET);
-        __raw_writel(0x1,  ttcce->xttc.base_addr + XTTCPS_IER_OFFSET);
-
-        err = request_irq(irq, xttcps_clock_event_interrupt, IRQF_TIMER,
-                          np->name, ttcce);
-        if (WARN_ON(err))
-                return;
-
-        clockevents_config_and_register(&ttcce->ce,
-                                        clk_get_rate(ttcce->clk) / PRESCALE,
-                                        1, 0xfffe);
-}
-
-static const __initconst struct of_device_id zynq_ttc_match[] = {
-        { .compatible = "xlnx,ttc-counter-clocksource",
-                .data = zynq_ttc_setup_clocksource, },
-        { .compatible = "xlnx,ttc-counter-clockevent",
-                .data = zynq_ttc_setup_clockevent, },
-        {}
-};
-
-/**
- * xttcps_timer_init - Initialize the timer
- *
- * Initializes the timer hardware and register the clock source and clock event
- * timers with Linux kernal timer framework
- **/
-void __init xttcps_timer_init(void)
-{
-        struct device_node *np;
-
-        for_each_compatible_node(np, NULL, "xlnx,ttc") {
-                struct device_node *np_chld;
-                void __iomem *base;
-
-                base = of_iomap(np, 0);
-                if (WARN_ON(!base))
-                        return;
-
-                for_each_available_child_of_node(np, np_chld) {
-                        int (*cb)(struct device_node *np, void __iomem *base);
-                        const struct of_device_id *match;
-
-                        match = of_match_node(zynq_ttc_match, np_chld);
-                        if (match) {
-                                cb = match->data;
-                                cb(np_chld, base);
-                        }
-                }
-        }
-}
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
index a0daa2fb5de6..e6dbc8dbe6a6 100644
--- a/arch/arm/plat-omap/dmtimer.c
+++ b/arch/arm/plat-omap/dmtimer.c
@@ -140,8 +140,7 @@ static int omap_dm_timer_prepare(struct omap_dm_timer *timer)
          */
         if (!(timer->capability & OMAP_TIMER_NEEDS_RESET)) {
                 timer->fclk = clk_get(&timer->pdev->dev, "fck");
-                if (WARN_ON_ONCE(IS_ERR_OR_NULL(timer->fclk))) {
-                        timer->fclk = NULL;
+                if (WARN_ON_ONCE(IS_ERR(timer->fclk))) {
                         dev_err(&timer->pdev->dev, ": No fclk handle.\n");
                         return -EINVAL;
                 }
@@ -373,7 +372,7 @@ EXPORT_SYMBOL_GPL(omap_dm_timer_modify_idlect_mask);
 
 struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer)
 {
-        if (timer)
+        if (timer && !IS_ERR(timer->fclk))
                 return timer->fclk;
         return NULL;
 }
@@ -482,7 +481,7 @@ int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source)
         if (pdata && pdata->set_timer_src)
                 return pdata->set_timer_src(timer->pdev, source);
 
-        if (!timer->fclk)
+        if (IS_ERR(timer->fclk))
                 return -EINVAL;
 
         switch (source) {
@@ -500,13 +499,13 @@ int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source)
         }
 
         parent = clk_get(&timer->pdev->dev, parent_name);
-        if (IS_ERR_OR_NULL(parent)) {
+        if (IS_ERR(parent)) {
                 pr_err("%s: %s not found\n", __func__, parent_name);
                 return -EINVAL;
         }
 
         ret = clk_set_parent(timer->fclk, parent);
-        if (IS_ERR_VALUE(ret))
+        if (ret < 0)
                 pr_err("%s: failed to set %s as parent\n", __func__,
                         parent_name);
 
@@ -808,6 +807,7 @@ static int omap_dm_timer_probe(struct platform_device *pdev)
                 return  -ENOMEM;
         }
 
+        timer->fclk = ERR_PTR(-ENODEV);
         timer->io_base = devm_ioremap_resource(dev, mem);
         if (IS_ERR(timer->io_base))
                 return PTR_ERR(timer->io_base);
diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig
index a9d52167e16e..b708b3e56d27 100644
--- a/arch/arm/plat-samsung/Kconfig
+++ b/arch/arm/plat-samsung/Kconfig
@@ -70,7 +70,7 @@ config S3C_LOWLEVEL_UART_PORT
 
 # timer options
 
-config S5P_HRT
+config SAMSUNG_HRT
         bool
         select SAMSUNG_DEV_PWM
         help
diff --git a/arch/arm/plat-samsung/Makefile b/arch/arm/plat-samsung/Makefile
index 3a7c64d1814a..a23c460299a1 100644
--- a/arch/arm/plat-samsung/Makefile
+++ b/arch/arm/plat-samsung/Makefile
@@ -12,8 +12,7 @@ obj-				:=
 # Objects we always build independent of SoC choice
 
 obj-y                           += init.o cpu.o
-obj-$(CONFIG_ARCH_USES_GETTIMEOFFSET)   += time.o
-obj-$(CONFIG_S5P_HRT)           += s5p-time.o
+obj-$(CONFIG_SAMSUNG_HRT)       += samsung-time.o
 
 obj-$(CONFIG_SAMSUNG_CLOCK)     += clock.o
 obj-$(CONFIG_SAMSUNG_CLOCK)     += pwm-clock.o
diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h
index 37703ef6dfc7..989fefe18be6 100644
--- a/arch/arm/plat-samsung/include/plat/cpu.h
+++ b/arch/arm/plat-samsung/include/plat/cpu.h
@@ -23,6 +23,9 @@ extern unsigned long samsung_cpu_id;
 #define S3C24XX_CPU_ID          0x32400000
 #define S3C24XX_CPU_MASK        0xFFF00000
 
+#define S3C2412_CPU_ID          0x32412000
+#define S3C2412_CPU_MASK        0xFFFFF000
+
 #define S3C6400_CPU_ID          0x36400000
 #define S3C6410_CPU_ID          0x36410000
 #define S3C64XX_CPU_MASK        0xFFFFF000
@@ -53,6 +56,7 @@ static inline int is_samsung_##name(void)	\
 }
 
 IS_SAMSUNG_CPU(s3c24xx, S3C24XX_CPU_ID, S3C24XX_CPU_MASK)
+IS_SAMSUNG_CPU(s3c2412, S3C2412_CPU_ID, S3C2412_CPU_MASK)
 IS_SAMSUNG_CPU(s3c6400, S3C6400_CPU_ID, S3C64XX_CPU_MASK)
 IS_SAMSUNG_CPU(s3c6410, S3C6410_CPU_ID, S3C64XX_CPU_MASK)
 IS_SAMSUNG_CPU(s5p6440, S5P6440_CPU_ID, S5P64XX_CPU_MASK)
@@ -74,6 +78,12 @@ IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK)
 # define soc_is_s3c24xx()       0
 #endif
 
+#if defined(CONFIG_CPU_S3C2412)
+# define soc_is_s3c2412()       is_samsung_s3c2412()
+#else
+# define soc_is_s3c2412()       0
+#endif
+
 #if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
 # define soc_is_s3c64xx()       (is_samsung_s3c6400() || is_samsung_s3c6410())
 #else
@@ -173,7 +183,6 @@ extern void s3c_init_cpu(unsigned long idcode,
 
 /* core initialisation functions */
 
-extern void s3c24xx_init_irq(void);
 extern void s5p_init_irq(u32 *vic, u32 num_vic);
 
 extern void s3c24xx_init_io(struct map_desc *mach_desc, int size);
@@ -192,10 +201,6 @@ extern void s3c24xx_init_uartdevs(char *name,
                                   struct s3c24xx_uart_resources *res,
                                   struct s3c2410_uartcfg *cfg, int no);
 
-/* timer for 2410/2440 */
-
-extern void s3c24xx_timer_init(void);
-
 extern struct syscore_ops s3c2410_pm_syscore_ops;
 extern struct syscore_ops s3c2412_pm_syscore_ops;
 extern struct syscore_ops s3c2416_pm_syscore_ops;
diff --git a/arch/arm/plat-samsung/include/plat/irq.h b/arch/arm/plat-samsung/include/plat/irq.h
deleted file mode 100644
index e21a89bc26c9..000000000000
--- a/arch/arm/plat-samsung/include/plat/irq.h
+++ /dev/null
@@ -1,116 +0,0 @@
-/* linux/arch/arm/plat-samsung/include/plat/irq.h
- *
- * Copyright (c) 2004-2005 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * Header file for S3C24XX CPU IRQ support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/io.h>
-
-#include <mach/hardware.h>
-#include <mach/regs-irq.h>
-#include <mach/regs-gpio.h>
-
-#define irqdbf(x...)
-#define irqdbf2(x...)
-
-#define EXTINT_OFF (IRQ_EINT4 - 4)
-
-/* these are exported for arch/arm/mach-* usage */
-extern struct irq_chip s3c_irq_level_chip;
-extern struct irq_chip s3c_irq_chip;
-
-static inline void s3c_irqsub_mask(unsigned int irqno,
-                                   unsigned int parentbit,
-                                   int subcheck)
-{
-        unsigned long mask;
-        unsigned long submask;
-
-        submask = __raw_readl(S3C2410_INTSUBMSK);
-        mask = __raw_readl(S3C2410_INTMSK);
-
-        submask |= (1UL << (irqno - IRQ_S3CUART_RX0));
-
-        /* check to see if we need to mask the parent IRQ */
-
-        if ((submask  & subcheck) == subcheck)
-                __raw_writel(mask | parentbit, S3C2410_INTMSK);
-
-        /* write back masks */
-        __raw_writel(submask, S3C2410_INTSUBMSK);
-
-}
-
-static inline void s3c_irqsub_unmask(unsigned int irqno,
-                                     unsigned int parentbit)
-{
-        unsigned long mask;
-        unsigned long submask;
-
-        submask = __raw_readl(S3C2410_INTSUBMSK);
-        mask = __raw_readl(S3C2410_INTMSK);
-
-        submask &= ~(1UL << (irqno - IRQ_S3CUART_RX0));
-        mask &= ~parentbit;
-
-        /* write back masks */
-        __raw_writel(submask, S3C2410_INTSUBMSK);
-        __raw_writel(mask, S3C2410_INTMSK);
-}
-
-
-static inline void s3c_irqsub_maskack(unsigned int irqno,
-                                      unsigned int parentmask,
-                                      unsigned int group)
-{
-        unsigned int bit = 1UL << (irqno - IRQ_S3CUART_RX0);
-
-        s3c_irqsub_mask(irqno, parentmask, group);
-
-        __raw_writel(bit, S3C2410_SUBSRCPND);
-
-        /* only ack parent if we've got all the irqs (seems we must
-         * ack, all and hope that the irq system retriggers ok when
-         * the interrupt goes off again)
-         */
-
-        if (1) {
-                __raw_writel(parentmask, S3C2410_SRCPND);
-                __raw_writel(parentmask, S3C2410_INTPND);
-        }
-}
-
-static inline void s3c_irqsub_ack(unsigned int irqno,
-                                  unsigned int parentmask,
-                                  unsigned int group)
-{
-        unsigned int bit = 1UL << (irqno - IRQ_S3CUART_RX0);
-
-        __raw_writel(bit, S3C2410_SUBSRCPND);
-
-        /* only ack parent if we've got all the irqs (seems we must
-         * ack, all and hope that the irq system retriggers ok when
-         * the interrupt goes off again)
-         */
-
-        if (1) {
-                __raw_writel(parentmask, S3C2410_SRCPND);
-                __raw_writel(parentmask, S3C2410_INTPND);
-        }
-}
-
-/* exported for use in arch/arm/mach-s3c2410 */
-
-#ifdef CONFIG_PM
-extern int s3c_irq_wake(struct irq_data *data, unsigned int state);
-#else
-#define s3c_irq_wake NULL
-#endif
-
-extern int s3c_irqext_type(struct irq_data *d, unsigned int type);
diff --git a/arch/arm/plat-samsung/include/plat/s3c2410.h b/arch/arm/plat-samsung/include/plat/s3c2410.h
deleted file mode 100644
index 55b0e5f51e97..000000000000
--- a/arch/arm/plat-samsung/include/plat/s3c2410.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/* linux/arch/arm/plat-samsung/include/plat/s3c2410.h
- *
- * Copyright (c) 2004 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * Header file for s3c2410 machine directory
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
-*/
-
-#ifdef CONFIG_CPU_S3C2410
-
-extern  int s3c2410_init(void);
-extern  int s3c2410a_init(void);
-
-extern void s3c2410_map_io(void);
-
-extern void s3c2410_init_uarts(struct s3c2410_uartcfg *cfg, int no);
-
-extern void s3c2410_init_clocks(int xtal);
-
-#else
-#define s3c2410_init_clocks NULL
-#define s3c2410_init_uarts NULL
-#define s3c2410_map_io NULL
-#define s3c2410_init NULL
-#define s3c2410a_init NULL
-#endif
diff --git a/arch/arm/plat-samsung/include/plat/s3c2412.h b/arch/arm/plat-samsung/include/plat/s3c2412.h
deleted file mode 100644
index cbae50ddacc8..000000000000
--- a/arch/arm/plat-samsung/include/plat/s3c2412.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/* linux/arch/arm/plat-samsung/include/plat/s3c2412.h
- *
- * Copyright (c) 2006 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * Header file for s3c2412 cpu support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifdef CONFIG_CPU_S3C2412
-
-extern  int s3c2412_init(void);
-
-extern void s3c2412_map_io(void);
-
-extern void s3c2412_init_uarts(struct s3c2410_uartcfg *cfg, int no);
-
-extern void s3c2412_init_clocks(int xtal);
-
-extern  int s3c2412_baseclk_add(void);
-
-extern void s3c2412_restart(char mode, const char *cmd);
-#else
-#define s3c2412_init_clocks NULL
-#define s3c2412_init_uarts NULL
-#define s3c2412_map_io NULL
-#define s3c2412_init NULL
-#define s3c2412_restart NULL
-#endif
diff --git a/arch/arm/plat-samsung/include/plat/s3c2416.h b/arch/arm/plat-samsung/include/plat/s3c2416.h
deleted file mode 100644
index f27399a3c68d..000000000000
--- a/arch/arm/plat-samsung/include/plat/s3c2416.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/* linux/arch/arm/plat-samsung/include/plat/s3c2416.h
- *
- * Copyright (c) 2009 Yauhen Kharuzhy <jekhor@gmail.com>
- *
- * Header file for s3c2416 cpu support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifdef CONFIG_CPU_S3C2416
-
-struct s3c2410_uartcfg;
-
-extern  int s3c2416_init(void);
-
-extern void s3c2416_map_io(void);
-
-extern void s3c2416_init_uarts(struct s3c2410_uartcfg *cfg, int no);
-
-extern void s3c2416_init_clocks(int xtal);
-
-extern  int s3c2416_baseclk_add(void);
-
-extern void s3c2416_restart(char mode, const char *cmd);
-
-extern void s3c2416_init_irq(void);
-extern struct syscore_ops s3c2416_irq_syscore_ops;
-
-#else
-#define s3c2416_init_clocks NULL
-#define s3c2416_init_uarts NULL
-#define s3c2416_map_io NULL
-#define s3c2416_init NULL
-#define s3c2416_restart NULL
-#endif
diff --git a/arch/arm/plat-samsung/include/plat/s3c2443.h b/arch/arm/plat-samsung/include/plat/s3c2443.h
deleted file mode 100644
index 71b88ec48956..000000000000
--- a/arch/arm/plat-samsung/include/plat/s3c2443.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/* linux/arch/arm/plat-samsung/include/plat/s3c2443.h
- *
- * Copyright (c) 2004-2005 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * Header file for s3c2443 cpu support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifdef CONFIG_CPU_S3C2443
-
-struct s3c2410_uartcfg;
-
-extern  int s3c2443_init(void);
-
-extern void s3c2443_map_io(void);
-
-extern void s3c2443_init_uarts(struct s3c2410_uartcfg *cfg, int no);
-
-extern void s3c2443_init_clocks(int xtal);
-
-extern  int s3c2443_baseclk_add(void);
-
-extern void s3c2443_restart(char mode, const char *cmd);
-
-extern void s3c2443_init_irq(void);
-#else
-#define s3c2443_init_clocks NULL
-#define s3c2443_init_uarts NULL
-#define s3c2443_map_io NULL
-#define s3c2443_init NULL
-#define s3c2443_restart NULL
-#endif
diff --git a/arch/arm/plat-samsung/include/plat/s3c244x.h b/arch/arm/plat-samsung/include/plat/s3c244x.h
deleted file mode 100644
index ea0c961b7603..000000000000
--- a/arch/arm/plat-samsung/include/plat/s3c244x.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/* linux/arch/arm/plat-samsung/include/plat/s3c244x.h
- *
- * Copyright (c) 2004-2005 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * Header file for S3C2440 and S3C2442 cpu support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442)
-
-extern void s3c244x_map_io(void);
-
-extern void s3c244x_init_uarts(struct s3c2410_uartcfg *cfg, int no);
-
-extern void s3c244x_init_clocks(int xtal);
-
-#else
-#define s3c244x_init_clocks NULL
-#define s3c244x_init_uarts NULL
-#endif
-
-#ifdef CONFIG_CPU_S3C2440
-extern  int s3c2440_init(void);
-
-extern void s3c2440_map_io(void);
-#else
-#define s3c2440_init NULL
-#define s3c2440_map_io NULL
-#endif
-
-#ifdef CONFIG_CPU_S3C2442
-extern  int s3c2442_init(void);
-
-extern void s3c2442_map_io(void);
-#else
-#define s3c2442_init NULL
-#define s3c2442_map_io NULL
-#endif
diff --git a/arch/arm/plat-samsung/include/plat/s5p-time.h b/arch/arm/plat-samsung/include/plat/s5p-time.h
deleted file mode 100644
index 9c96f3586ce0..000000000000
--- a/arch/arm/plat-samsung/include/plat/s5p-time.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/* linux/arch/arm/plat-samsung/include/plat/s5p-time.h
- *
- * Copyright 2011 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
- *
- * Header file for s5p time support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_PLAT_S5P_TIME_H
-#define __ASM_PLAT_S5P_TIME_H __FILE__
-
-/* S5P HR-Timer Clock mode */
-enum s5p_timer_mode {
-        S5P_PWM0,
-        S5P_PWM1,
-        S5P_PWM2,
-        S5P_PWM3,
-        S5P_PWM4,
-};
-
-struct s5p_timer_source {
-        unsigned int event_id;
-        unsigned int source_id;
-};
-
-/* Be able to sleep for atleast 4 seconds (usually more) */
-#define S5PTIMER_MIN_RANGE      4
-
-#define TCNT_MAX                0xffffffff
-#define NON_PERIODIC            0
-#define PERIODIC                1
-
-extern void __init s5p_set_timer_source(enum s5p_timer_mode event,
-                                        enum s5p_timer_mode source);
-extern  void s5p_timer_init(void);
-#endif /* __ASM_PLAT_S5P_TIME_H */
diff --git a/arch/arm/plat-samsung/include/plat/samsung-time.h b/arch/arm/plat-samsung/include/plat/samsung-time.h
new file mode 100644
index 000000000000..4cc99bb1f176
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/samsung-time.h
@@ -0,0 +1,53 @@
+/* linux/arch/arm/plat-samsung/include/plat/samsung-time.h
+ *
+ * Copyright 2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com/
+ *
+ * Header file for samsung s3c and s5p time support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_PLAT_SAMSUNG_TIME_H
+#define __ASM_PLAT_SAMSUNG_TIME_H __FILE__
+
+/* SAMSUNG HR-Timer Clock mode */
+enum samsung_timer_mode {
+        SAMSUNG_PWM0,
+        SAMSUNG_PWM1,
+        SAMSUNG_PWM2,
+        SAMSUNG_PWM3,
+        SAMSUNG_PWM4,
+};
+
+struct samsung_timer_source {
+        unsigned int event_id;
+        unsigned int source_id;
+};
+
+/* Be able to sleep for atleast 4 seconds (usually more) */
+#define SAMSUNG_TIMER_MIN_RANGE 4
+
+#if defined(CONFIG_ARCH_S3C24XX) || defined(CONFIG_ARCH_S5PC100)
+#define TCNT_MAX                0xffff
+#define TSCALER_DIV             25
+#define TDIV                    50
+#define TSIZE                   16
+#else
+#define TCNT_MAX                0xffffffff
+#define TSCALER_DIV             2
+#define TDIV                    2
+#define TSIZE                   32
+#endif
+
+#define NON_PERIODIC            0
+#define PERIODIC                1
+
+extern void __init samsung_set_timer_source(enum samsung_timer_mode event,
+                                        enum samsung_timer_mode source);
+
+extern void __init samsung_timer_init(void);
+
+#endif /* __ASM_PLAT_SAMSUNG_TIME_H */
diff --git a/arch/arm/plat-samsung/s5p-time.c b/arch/arm/plat-samsung/samsung-time.c
index e92510cf82ee..f899cbc9b288 100644
--- a/arch/arm/plat-samsung/s5p-time.c
+++ b/arch/arm/plat-samsung/samsung-time.c
@@ -2,7 +2,7 @@
  * Copyright (c) 2011 Samsung Electronics Co., Ltd.
  *              http://www.samsung.com/
  *
- * S5P - Common hr-timer support
+ * samsung - Common hr-timer support (s3c and s5p)
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -25,41 +25,41 @@
 #include <mach/map.h>
 #include <plat/devs.h>
 #include <plat/regs-timer.h>
-#include <plat/s5p-time.h>
+#include <plat/samsung-time.h>
 
 static struct clk *tin_event;
 static struct clk *tin_source;
 static struct clk *tdiv_event;
 static struct clk *tdiv_source;
 static struct clk *timerclk;
-static struct s5p_timer_source timer_source;
+static struct samsung_timer_source timer_source;
 static unsigned long clock_count_per_tick;
-static void s5p_timer_resume(void);
+static void samsung_timer_resume(void);
 
-static void s5p_time_stop(enum s5p_timer_mode mode)
+static void samsung_time_stop(enum samsung_timer_mode mode)
 {
         unsigned long tcon;
 
         tcon = __raw_readl(S3C2410_TCON);
 
         switch (mode) {
-        case S5P_PWM0:
+        case SAMSUNG_PWM0:
                 tcon &= ~S3C2410_TCON_T0START;
                 break;
 
-        case S5P_PWM1:
+        case SAMSUNG_PWM1:
                 tcon &= ~S3C2410_TCON_T1START;
                 break;
 
-        case S5P_PWM2:
+        case SAMSUNG_PWM2:
                 tcon &= ~S3C2410_TCON_T2START;
                 break;
 
-        case S5P_PWM3:
+        case SAMSUNG_PWM3:
                 tcon &= ~S3C2410_TCON_T3START;
                 break;
 
-        case S5P_PWM4:
+        case SAMSUNG_PWM4:
                 tcon &= ~S3C2410_TCON_T4START;
                 break;
 
@@ -70,7 +70,7 @@ static void s5p_time_stop(enum s5p_timer_mode mode)
         __raw_writel(tcon, S3C2410_TCON);
 }
 
-static void s5p_time_setup(enum s5p_timer_mode mode, unsigned long tcnt)
+static void samsung_time_setup(enum samsung_timer_mode mode, unsigned long tcnt)
 {
         unsigned long tcon;
 
@@ -79,27 +79,27 @@ static void s5p_time_setup(enum s5p_timer_mode mode, unsigned long tcnt)
         tcnt--;
 
         switch (mode) {
-        case S5P_PWM0:
+        case SAMSUNG_PWM0:
                 tcon &= ~(0x0f << 0);
                 tcon |= S3C2410_TCON_T0MANUALUPD;
                 break;
 
-        case S5P_PWM1:
+        case SAMSUNG_PWM1:
                 tcon &= ~(0x0f << 8);
                 tcon |= S3C2410_TCON_T1MANUALUPD;
                 break;
 
-        case S5P_PWM2:
+        case SAMSUNG_PWM2:
                 tcon &= ~(0x0f << 12);
                 tcon |= S3C2410_TCON_T2MANUALUPD;
                 break;
 
-        case S5P_PWM3:
+        case SAMSUNG_PWM3:
                 tcon &= ~(0x0f << 16);
                 tcon |= S3C2410_TCON_T3MANUALUPD;
                 break;
 
-        case S5P_PWM4:
+        case SAMSUNG_PWM4:
                 tcon &= ~(0x07 << 20);
                 tcon |= S3C2410_TCON_T4MANUALUPD;
                 break;
@@ -114,14 +114,14 @@ static void s5p_time_setup(enum s5p_timer_mode mode, unsigned long tcnt)
         __raw_writel(tcon, S3C2410_TCON);
 }
 
-static void s5p_time_start(enum s5p_timer_mode mode, bool periodic)
+static void samsung_time_start(enum samsung_timer_mode mode, bool periodic)
 {
         unsigned long tcon;
 
         tcon  = __raw_readl(S3C2410_TCON);
 
         switch (mode) {
-        case S5P_PWM0:
+        case SAMSUNG_PWM0:
                 tcon |= S3C2410_TCON_T0START;
                 tcon &= ~S3C2410_TCON_T0MANUALUPD;
 
@@ -131,7 +131,7 @@ static void s5p_time_start(enum s5p_timer_mode mode, bool periodic)
                         tcon &= ~S3C2410_TCON_T0RELOAD;
                 break;
 
-        case S5P_PWM1:
+        case SAMSUNG_PWM1:
                 tcon |= S3C2410_TCON_T1START;
                 tcon &= ~S3C2410_TCON_T1MANUALUPD;
 
@@ -141,7 +141,7 @@ static void s5p_time_start(enum s5p_timer_mode mode, bool periodic)
                         tcon &= ~S3C2410_TCON_T1RELOAD;
                 break;
 
-        case S5P_PWM2:
+        case SAMSUNG_PWM2:
                 tcon |= S3C2410_TCON_T2START;
                 tcon &= ~S3C2410_TCON_T2MANUALUPD;
 
@@ -151,7 +151,7 @@ static void s5p_time_start(enum s5p_timer_mode mode, bool periodic)
                         tcon &= ~S3C2410_TCON_T2RELOAD;
                 break;
 
-        case S5P_PWM3:
+        case SAMSUNG_PWM3:
                 tcon |= S3C2410_TCON_T3START;
                 tcon &= ~S3C2410_TCON_T3MANUALUPD;
 
@@ -161,7 +161,7 @@ static void s5p_time_start(enum s5p_timer_mode mode, bool periodic)
                         tcon &= ~S3C2410_TCON_T3RELOAD;
                 break;
 
-        case S5P_PWM4:
+        case SAMSUNG_PWM4:
                 tcon |= S3C2410_TCON_T4START;
                 tcon &= ~S3C2410_TCON_T4MANUALUPD;
 
@@ -178,24 +178,24 @@ static void s5p_time_start(enum s5p_timer_mode mode, bool periodic)
         __raw_writel(tcon, S3C2410_TCON);
 }
 
-static int s5p_set_next_event(unsigned long cycles,
+static int samsung_set_next_event(unsigned long cycles,
                                 struct clock_event_device *evt)
 {
-        s5p_time_setup(timer_source.event_id, cycles);
-        s5p_time_start(timer_source.event_id, NON_PERIODIC);
+        samsung_time_setup(timer_source.event_id, cycles);
+        samsung_time_start(timer_source.event_id, NON_PERIODIC);
 
         return 0;
 }
 
-static void s5p_set_mode(enum clock_event_mode mode,
+static void samsung_set_mode(enum clock_event_mode mode,
                                 struct clock_event_device *evt)
 {
-        s5p_time_stop(timer_source.event_id);
+        samsung_time_stop(timer_source.event_id);
 
         switch (mode) {
         case CLOCK_EVT_MODE_PERIODIC:
-                s5p_time_setup(timer_source.event_id, clock_count_per_tick);
-                s5p_time_start(timer_source.event_id, PERIODIC);
+                samsung_time_setup(timer_source.event_id, clock_count_per_tick);
+                samsung_time_start(timer_source.event_id, PERIODIC);
                 break;
 
         case CLOCK_EVT_MODE_ONESHOT:
@@ -206,24 +206,24 @@ static void s5p_set_mode(enum clock_event_mode mode,
                 break;
 
         case CLOCK_EVT_MODE_RESUME:
-                s5p_timer_resume();
+                samsung_timer_resume();
                 break;
         }
 }
 
-static void s5p_timer_resume(void)
+static void samsung_timer_resume(void)
 {
         /* event timer restart */
-        s5p_time_setup(timer_source.event_id, clock_count_per_tick);
-        s5p_time_start(timer_source.event_id, PERIODIC);
+        samsung_time_setup(timer_source.event_id, clock_count_per_tick);
+        samsung_time_start(timer_source.event_id, PERIODIC);
 
         /* source timer restart */
-        s5p_time_setup(timer_source.source_id, TCNT_MAX);
-        s5p_time_start(timer_source.source_id, PERIODIC);
+        samsung_time_setup(timer_source.source_id, TCNT_MAX);
+        samsung_time_start(timer_source.source_id, PERIODIC);
 }
 
-void __init s5p_set_timer_source(enum s5p_timer_mode event,
-                                 enum s5p_timer_mode source)
+void __init samsung_set_timer_source(enum samsung_timer_mode event,
+                                 enum samsung_timer_mode source)
 {
         s3c_device_timer[event].dev.bus = &platform_bus_type;
         s3c_device_timer[source].dev.bus = &platform_bus_type;
@@ -233,14 +233,14 @@ void __init s5p_set_timer_source(enum s5p_timer_mode event,
 }
 
 static struct clock_event_device time_event_device = {
-        .name           = "s5p_event_timer",
+        .name           = "samsung_event_timer",
         .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
         .rating         = 200,
-        .set_next_event = s5p_set_next_event,
-        .set_mode       = s5p_set_mode,
+        .set_next_event = samsung_set_next_event,
+        .set_mode       = samsung_set_mode,
 };
 
-static irqreturn_t s5p_clock_event_isr(int irq, void *dev_id)
+static irqreturn_t samsung_clock_event_isr(int irq, void *dev_id)
 {
         struct clock_event_device *evt = dev_id;
 
@@ -249,14 +249,14 @@ static irqreturn_t s5p_clock_event_isr(int irq, void *dev_id)
         return IRQ_HANDLED;
 }
 
-static struct irqaction s5p_clock_event_irq = {
-        .name           = "s5p_time_irq",
+static struct irqaction samsung_clock_event_irq = {
+        .name           = "samsung_time_irq",
         .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
-        .handler        = s5p_clock_event_isr,
+        .handler        = samsung_clock_event_isr,
         .dev_id         = &time_event_device,
 };
 
-static void __init s5p_clockevent_init(void)
+static void __init samsung_clockevent_init(void)
 {
         unsigned long pclk;
         unsigned long clock_rate;
@@ -267,8 +267,8 @@ static void __init s5p_clockevent_init(void)
 
         tscaler = clk_get_parent(tdiv_event);
 
-        clk_set_rate(tscaler, pclk / 2);
-        clk_set_rate(tdiv_event, pclk / 2);
+        clk_set_rate(tscaler, pclk / TSCALER_DIV);
+        clk_set_rate(tdiv_event, pclk / TDIV);
         clk_set_parent(tin_event, tdiv_event);
 
         clock_rate = clk_get_rate(tin_event);
@@ -278,22 +278,22 @@ static void __init s5p_clockevent_init(void)
         clockevents_config_and_register(&time_event_device, clock_rate, 1, -1);
 
         irq_number = timer_source.event_id + IRQ_TIMER0;
-        setup_irq(irq_number, &s5p_clock_event_irq);
+        setup_irq(irq_number, &samsung_clock_event_irq);
 }
 
-static void __iomem *s5p_timer_reg(void)
+static void __iomem *samsung_timer_reg(void)
 {
         unsigned long offset = 0;
 
         switch (timer_source.source_id) {
-        case S5P_PWM0:
-        case S5P_PWM1:
-        case S5P_PWM2:
-        case S5P_PWM3:
+        case SAMSUNG_PWM0:
+        case SAMSUNG_PWM1:
+        case SAMSUNG_PWM2:
+        case SAMSUNG_PWM3:
                 offset = (timer_source.source_id * 0x0c) + 0x14;
                 break;
 
-        case S5P_PWM4:
+        case SAMSUNG_PWM4:
                 offset = 0x40;
                 break;
 
@@ -312,9 +312,9 @@ static void __iomem *s5p_timer_reg(void)
  * this wraps around for now, since it is just a relative time
  * stamp. (Inspired by U300 implementation.)
  */
-static u32 notrace s5p_read_sched_clock(void)
+static u32 notrace samsung_read_sched_clock(void)
 {
-        void __iomem *reg = s5p_timer_reg();
+        void __iomem *reg = samsung_timer_reg();
 
         if (!reg)
                 return 0;
@@ -322,29 +322,29 @@ static u32 notrace s5p_read_sched_clock(void)
         return ~__raw_readl(reg);
 }
 
-static void __init s5p_clocksource_init(void)
+static void __init samsung_clocksource_init(void)
 {
         unsigned long pclk;
         unsigned long clock_rate;
 
         pclk = clk_get_rate(timerclk);
 
-        clk_set_rate(tdiv_source, pclk / 2);
+        clk_set_rate(tdiv_source, pclk / TDIV);
         clk_set_parent(tin_source, tdiv_source);
 
         clock_rate = clk_get_rate(tin_source);
 
-        s5p_time_setup(timer_source.source_id, TCNT_MAX);
-        s5p_time_start(timer_source.source_id, PERIODIC);
+        samsung_time_setup(timer_source.source_id, TCNT_MAX);
+        samsung_time_start(timer_source.source_id, PERIODIC);
 
-        setup_sched_clock(s5p_read_sched_clock, 32, clock_rate);
+        setup_sched_clock(samsung_read_sched_clock, TSIZE, clock_rate);
 
-        if (clocksource_mmio_init(s5p_timer_reg(), "s5p_clocksource_timer",
-                        clock_rate, 250, 32, clocksource_mmio_readl_down))
-                panic("s5p_clocksource_timer: can't register clocksource\n");
+        if (clocksource_mmio_init(samsung_timer_reg(), "samsung_clocksource_timer",
+                        clock_rate, 250, TSIZE, clocksource_mmio_readl_down))
+                panic("samsung_clocksource_timer: can't register clocksource\n");
 }
 
-static void __init s5p_timer_resources(void)
+static void __init samsung_timer_resources(void)
 {
 
         unsigned long event_id = timer_source.event_id;
@@ -386,9 +386,9 @@ static void __init s5p_timer_resources(void)
         clk_enable(tin_source);
 }
 
-void __init s5p_timer_init(void)
+void __init samsung_timer_init(void)
 {
-        s5p_timer_resources();
-        s5p_clockevent_init();
-        s5p_clocksource_init();
+        samsung_timer_resources();
+        samsung_clockevent_init();
+        samsung_clocksource_init();
 }
diff --git a/arch/arm/plat-samsung/time.c b/arch/arm/plat-samsung/time.c
deleted file mode 100644
index 73defd00c3e4..000000000000
--- a/arch/arm/plat-samsung/time.c
+++ /dev/null
@@ -1,287 +0,0 @@
-/* linux/arch/arm/plat-samsung/time.c
- *
- * Copyright (C) 2003-2005 Simtec Electronics
- *      Ben Dooks, <ben@simtec.co.uk>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#include <linux/kernel.h>
-#include <linux/sched.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/err.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/platform_device.h>
-#include <linux/syscore_ops.h>
-
-#include <asm/mach-types.h>
-
-#include <asm/irq.h>
-#include <mach/map.h>
-#include <plat/regs-timer.h>
-#include <mach/regs-irq.h>
-#include <asm/mach/time.h>
-#include <mach/tick.h>
-
-#include <plat/clock.h>
-#include <plat/cpu.h>
-
-static unsigned long timer_startval;
-static unsigned long timer_usec_ticks;
-
-#ifndef TICK_MAX
-#define TICK_MAX (0xffff)
-#endif
-
-#define TIMER_USEC_SHIFT 16
-
-/* we use the shifted arithmetic to work out the ratio of timer ticks
- * to usecs, as often the peripheral clock is not a nice even multiple
- * of 1MHz.
- *
- * shift of 14 and 15 are too low for the 12MHz, 16 seems to be ok
- * for the current HZ value of 200 without producing overflows.
- *
- * Original patch by Dimitry Andric, updated by Ben Dooks
-*/
-
-
-/* timer_mask_usec_ticks
- *
- * given a clock and divisor, make the value to pass into timer_ticks_to_usec
- * to scale the ticks into usecs
-*/
-
-static inline unsigned long
-timer_mask_usec_ticks(unsigned long scaler, unsigned long pclk)
-{
-        unsigned long den = pclk / 1000;
-
-        return ((1000 << TIMER_USEC_SHIFT) * scaler + (den >> 1)) / den;
-}
-
-/* timer_ticks_to_usec
- *
- * convert timer ticks to usec.
-*/
-
-static inline unsigned long timer_ticks_to_usec(unsigned long ticks)
-{
-        unsigned long res;
-
-        res = ticks * timer_usec_ticks;
-        res += 1 << (TIMER_USEC_SHIFT - 4);     /* round up slightly */
-
-        return res >> TIMER_USEC_SHIFT;
-}
-
-/***
- * Returns microsecond  since last clock interrupt.  Note that interrupts
- * will have been disabled by do_gettimeoffset()
- * IRQs are disabled before entering here from do_gettimeofday()
- */
-
-static u32 s3c2410_gettimeoffset(void)
-{
-        unsigned long tdone;
-        unsigned long tval;
-
-        /* work out how many ticks have gone since last timer interrupt */
-
-        tval =  __raw_readl(S3C2410_TCNTO(4));
-        tdone = timer_startval - tval;
-
-        /* check to see if there is an interrupt pending */
-
-        if (s3c24xx_ostimer_pending()) {
-                /* re-read the timer, and try and fix up for the missed
-                 * interrupt. Note, the interrupt may go off before the
-                 * timer has re-loaded from wrapping.
-                 */
-
-                tval =  __raw_readl(S3C2410_TCNTO(4));
-                tdone = timer_startval - tval;
-
-                if (tval != 0)
-                        tdone += timer_startval;
-        }
-
-        return timer_ticks_to_usec(tdone) * 1000;
-}
-
-
-/*
- * IRQ handler for the timer
- */
-static irqreturn_t
-s3c2410_timer_interrupt(int irq, void *dev_id)
-{
-        timer_tick();
-        return IRQ_HANDLED;
-}
-
-static struct irqaction s3c2410_timer_irq = {
-        .name           = "S3C2410 Timer Tick",
-        .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
-        .handler        = s3c2410_timer_interrupt,
-};
-
-#define use_tclk1_12() ( \
-        machine_is_bast()       || \
-        machine_is_vr1000()     || \
-        machine_is_anubis()     || \
-        machine_is_osiris())
-
-static struct clk *tin;
-static struct clk *tdiv;
-static struct clk *timerclk;
-
-/*
- * Set up timer interrupt, and return the current time in seconds.
- *
- * Currently we only use timer4, as it is the only timer which has no
- * other function that can be exploited externally
- */
-static void s3c2410_timer_setup (void)
-{
-        unsigned long tcon;
-        unsigned long tcnt;
-        unsigned long tcfg1;
-        unsigned long tcfg0;
-
-        tcnt = TICK_MAX;  /* default value for tcnt */
-
-        /* configure the system for whichever machine is in use */
-
-        if (use_tclk1_12()) {
-                /* timer is at 12MHz, scaler is 1 */
-                timer_usec_ticks = timer_mask_usec_ticks(1, 12000000);
-                tcnt = 12000000 / HZ;
-
-                tcfg1 = __raw_readl(S3C2410_TCFG1);
-                tcfg1 &= ~S3C2410_TCFG1_MUX4_MASK;
-                tcfg1 |= S3C2410_TCFG1_MUX4_TCLK1;
-                __raw_writel(tcfg1, S3C2410_TCFG1);
-        } else {
-                unsigned long pclk;
-                struct clk *tscaler;
-
-                /* for the h1940 (and others), we use the pclk from the core
-                 * to generate the timer values. since values around 50 to
-                 * 70MHz are not values we can directly generate the timer
-                 * value from, we need to pre-scale and divide before using it.
-                 *
-                 * for instance, using 50.7MHz and dividing by 6 gives 8.45MHz
-                 * (8.45 ticks per usec)
-                 */
-
-                pclk = clk_get_rate(timerclk);
-
-                /* configure clock tick */
-
-                timer_usec_ticks = timer_mask_usec_ticks(6, pclk);
-
-                tscaler = clk_get_parent(tdiv);
-
-                clk_set_rate(tscaler, pclk / 3);
-                clk_set_rate(tdiv, pclk / 6);
-                clk_set_parent(tin, tdiv);
-
-                tcnt = clk_get_rate(tin) / HZ;
-        }
-
-        tcon = __raw_readl(S3C2410_TCON);
-        tcfg0 = __raw_readl(S3C2410_TCFG0);
-        tcfg1 = __raw_readl(S3C2410_TCFG1);
-
-        /* timers reload after counting zero, so reduce the count by 1 */
-
-        tcnt--;
-
-        printk(KERN_DEBUG "timer tcon=%08lx, tcnt %04lx, tcfg %08lx,%08lx, usec %08lx\n",
-               tcon, tcnt, tcfg0, tcfg1, timer_usec_ticks);
-
-        /* check to see if timer is within 16bit range... */
-        if (tcnt > TICK_MAX) {
-                panic("setup_timer: HZ is too small, cannot configure timer!");
-                return;
-        }
-
-        __raw_writel(tcfg1, S3C2410_TCFG1);
-        __raw_writel(tcfg0, S3C2410_TCFG0);
-
-        timer_startval = tcnt;
-        __raw_writel(tcnt, S3C2410_TCNTB(4));
-
-        /* ensure timer is stopped... */
-
-        tcon &= ~(7<<20);
-        tcon |= S3C2410_TCON_T4RELOAD;
-        tcon |= S3C2410_TCON_T4MANUALUPD;
-
-        __raw_writel(tcon, S3C2410_TCON);
-        __raw_writel(tcnt, S3C2410_TCNTB(4));
-        __raw_writel(tcnt, S3C2410_TCMPB(4));
-
-        /* start the timer running */
-        tcon |= S3C2410_TCON_T4START;
-        tcon &= ~S3C2410_TCON_T4MANUALUPD;
-        __raw_writel(tcon, S3C2410_TCON);
-}
-
-static void __init s3c2410_timer_resources(void)
-{
-        struct platform_device tmpdev;
-
-        tmpdev.dev.bus = &platform_bus_type;
-        tmpdev.id = 4;
-
-        timerclk = clk_get(NULL, "timers");
-        if (IS_ERR(timerclk))
-                panic("failed to get clock for system timer");
-
-        clk_enable(timerclk);
-
-        if (!use_tclk1_12()) {
-                tmpdev.id = 4;
-                tmpdev.dev.init_name = "s3c24xx-pwm.4";
-                tin = clk_get(&tmpdev.dev, "pwm-tin");
-                if (IS_ERR(tin))
-                        panic("failed to get pwm-tin clock for system timer");
-
-                tdiv = clk_get(&tmpdev.dev, "pwm-tdiv");
-                if (IS_ERR(tdiv))
-                        panic("failed to get pwm-tdiv clock for system timer");
-        }
-
-        clk_enable(tin);
-}
-
-static struct syscore_ops s3c24xx_syscore_ops = {
-        .resume         = s3c2410_timer_setup,
-};
-
-void __init s3c24xx_timer_init(void)
-{
-        arch_gettimeoffset = s3c2410_gettimeoffset;
-
-        s3c2410_timer_resources();
-        s3c2410_timer_setup();
-        setup_irq(IRQ_TIMER4, &s3c2410_timer_irq);
-        register_syscore_ops(&s3c24xx_syscore_ops);
-}