5 files changed, 135 insertions, 43 deletions

diff --git a/arch/arm/boot/dts/imx6dl-sabresd.dts b/arch/arm/boot/dts/imx6dl-sabresd.dts
index 1e45f2f9d0b6..38f50fca94f2 100644
--- a/arch/arm/boot/dts/imx6dl-sabresd.dts
+++ b/arch/arm/boot/dts/imx6dl-sabresd.dts
@@ -15,3 +15,16 @@
         model = "Freescale i.MX6 DualLite SABRE Smart Device Board";
         compatible = "fsl,imx6dl-sabresd", "fsl,imx6dl";
 };
+
+&ldb {
+        ipu_id = <0>;
+        sec_ipu_id = <0>;
+};
+
+&mxcfb1 {
+        status = "okay";
+};
+
+&mxcfb2 {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6q-sabresd.dts b/arch/arm/boot/dts/imx6q-sabresd.dts
index 5e62c2427b07..f1a4a69caf6d 100644
--- a/arch/arm/boot/dts/imx6q-sabresd.dts
+++ b/arch/arm/boot/dts/imx6q-sabresd.dts
@@ -19,3 +19,19 @@
         model = "Freescale i.MX6 Quad SABRE Smart Device Board";
         compatible = "fsl,imx6q-sabresd", "fsl,imx6q";
 };
+
+&mxcfb1 {
+        status = "okay";
+};
+
+&mxcfb2 {
+        status = "okay";
+};
+
+&mxcfb3 {
+        status = "okay";
+};
+
+&mxcfb4 {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index 453cd771fafc..70c5990191d0 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -12,6 +12,10 @@
 #include "imx6qdl.dtsi"
 
 / {
+        aliases {
+                ipu1 = &ipu2;
+        };
+
         cpus {
                 #address-cells = <1>;
                 #size-cells = <0>;
@@ -123,30 +127,17 @@
                 };
 
                 ipu2: ipu@02800000 {
-                        #crtc-cells = <1>;
                         compatible = "fsl,imx6q-ipu";
                         reg = <0x02800000 0x400000>;
                         interrupts = <0 8 0x4 0 7 0x4>;
-                        clocks = <&clks 133>, <&clks 134>, <&clks 137>;
-                        clock-names = "bus", "di0", "di1";
+                        clocks = <&clks 133>, <&clks 134>, <&clks 137>,
+                                 <&clks 41>, <&clks 42>,
+                                 <&clks 135>, <&clks 136>;
+                        clock-names = "bus", "di0", "di1",
+                                      "di0_sel", "di1_sel",
+                                      "ldb_di0", "ldb_di1";
                         resets = <&src 4>;
+                        bypass_reset = <0>;
                 };
         };
 };
-
-&ldb {
-        clocks = <&clks 33>, <&clks 34>,
-                 <&clks 39>, <&clks 40>, <&clks 41>, <&clks 42>,
-                 <&clks 135>, <&clks 136>;
-        clock-names = "di0_pll", "di1_pll",
-                      "di0_sel", "di1_sel", "di2_sel", "di3_sel",
-                      "di0", "di1";
-
-        lvds-channel@0 {
-                crtcs = <&ipu1 0>, <&ipu1 1>, <&ipu2 0>, <&ipu2 1>;
-        };
-
-        lvds-channel@1 {
-                crtcs = <&ipu1 0>, <&ipu1 1>, <&ipu2 0>, <&ipu2 1>;
-        };
-};
diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
index f39bfcffdcf9..43388f4d78cd 100644
--- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
@@ -11,6 +11,13 @@
  */
 
 / {
+        aliases {
+                mxcfb0 = &mxcfb1;
+                mxcfb1 = &mxcfb2;
+                mxcfb2 = &mxcfb3;
+                mxcfb3 = &mxcfb4;
+        };
+
         memory {
                 reg = <0x10000000 0x40000000>;
         };
@@ -69,6 +76,61 @@
                 mux-int-port = <2>;
                 mux-ext-port = <3>;
         };
+
+        mxcfb1: fb@0 {
+                compatible = "fsl,mxc_sdc_fb";
+                disp_dev = "ldb";
+                interface_pix_fmt = "RGB666";
+                mode_str ="LDB-XGA";
+                default_bpp = <16>;
+                int_clk = <0>;
+                late_init = <0>;
+                status = "disabled";
+        };
+
+        mxcfb2: fb@1 {
+                compatible = "fsl,mxc_sdc_fb";
+                disp_dev = "ldb";
+                interface_pix_fmt = "RGB666";
+                mode_str ="LDB-XGA";
+                default_bpp = <16>;
+                int_clk = <0>;
+                late_init = <0>;
+                status = "disabled";
+        };
+
+        mxcfb3: fb@2 {
+                compatible = "fsl,mxc_sdc_fb";
+                disp_dev = "lcd";
+                interface_pix_fmt = "RGB565";
+                mode_str ="CLAA-WVGA";
+                default_bpp = <16>;
+                int_clk = <0>;
+                late_init = <0>;
+                status = "disabled";
+        };
+
+        mxcfb4: fb@3 {
+                compatible = "fsl,mxc_sdc_fb";
+                disp_dev = "ldb";
+                interface_pix_fmt = "RGB666";
+                mode_str ="LDB-XGA";
+                default_bpp = <16>;
+                int_clk = <0>;
+                late_init = <0>;
+                status = "disabled";
+        };
+
+        lcd@0 {
+                compatible = "fsl,lcd";
+                ipu_id = <0>;
+                disp_id = <0>;
+                default_ifmt = "RGB565";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_ipu1_1>;
+                status = "okay";
+        };
+
 };
 
 &audmux {
@@ -132,6 +194,16 @@
         };
 };
 
+&ldb {
+        ipu_id = <1>;
+        disp_id = <1>;
+        ext_ref = <1>;
+        mode = "sep1";
+        sec_ipu_id = <1>;
+        sec_disp_id = <0>;
+        status = "okay";
+};
+
 &ssi2 {
         fsl,mode = "i2s-slave";
         status = "okay";
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index 39180df78170..59bd248789ea 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -15,11 +15,6 @@
 
 / {
         aliases {
-                serial0 = &uart1;
-                serial1 = &uart2;
-                serial2 = &uart3;
-                serial3 = &uart4;
-                serial4 = &uart5;
                 gpio0 = &gpio1;
                 gpio1 = &gpio2;
                 gpio2 = &gpio3;
@@ -27,6 +22,12 @@
                 gpio4 = &gpio5;
                 gpio5 = &gpio6;
                 gpio6 = &gpio7;
+                ipu0 = &ipu1;
+                serial0 = &uart1;
+                serial1 = &uart2;
+                serial2 = &uart3;
+                serial3 = &uart4;
+                serial4 = &uart5;
         };
 
         intc: interrupt-controller@00a01000 {
@@ -1231,23 +1232,15 @@
                         };
 
                         ldb: ldb@020e0008 {
-                                #address-cells = <1>;
-                                #size-cells = <0>;
                                 compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb";
-                                gpr = <&gpr>;
+                                reg = <0x020e0000 0x4000>;
+                                clocks = <&clks 135>, <&clks 136>,
+                                         <&clks 39>, <&clks 40>,
+                                         <&clks 41>, <&clks 42>;
+                                clock-names = "ldb_di0", "ldb_di1",
+                                              "ipu1_di0_sel", "ipu1_di1_sel",
+                                              "ipu2_di0_sel", "ipu2_di1_sel";
                                 status = "disabled";
-
-                                lvds-channel@0 {
-                                        reg = <0>;
-                                        crtcs = <&ipu1 0>;
-                                        status = "disabled";
-                                };
-
-                                lvds-channel@1 {
-                                        reg = <1>;
-                                        crtcs = <&ipu1 1>;
-                                        status = "disabled";
-                                };
                         };
 
                         dcic1: dcic@020e4000 {
@@ -1469,8 +1462,11 @@
                         };
 
                         vdoa@021e4000 {
+                                compatible = "fsl,imx6q-vdoa";
                                 reg = <0x021e4000 0x4000>;
                                 interrupts = <0 18 0x04>;
+                                clocks = <&clks 202>;
+                                iram = <&ocram>;
                         };
 
                         uart2: serial@021e8000 {
@@ -1519,13 +1515,17 @@
                 };
 
                 ipu1: ipu@02400000 {
-                        #crtc-cells = <1>;
                         compatible = "fsl,imx6q-ipu";
                         reg = <0x02400000 0x400000>;
                         interrupts = <0 6 0x4 0 5 0x4>;
-                        clocks = <&clks 130>, <&clks 131>, <&clks 132>;
-                        clock-names = "bus", "di0", "di1";
+                        clocks = <&clks 130>, <&clks 131>, <&clks 132>,
+                                 <&clks 39>, <&clks 40>,
+                                 <&clks 135>, <&clks 136>;
+                        clock-names = "bus", "di0", "di1",
+                                      "di0_sel", "di1_sel",
+                                      "ldb_di0", "ldb_di1";
                         resets = <&src 2>;
+                        bypass_reset = <0>;
                 };
         };
 };