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diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h
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1/*
2 * OMAP clock: data structure definitions, function prototypes, shared macros
3 *
4 * Copyright (C) 2004-2005, 2008-2010 Nokia Corporation
5 * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
6 * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#ifndef __ARCH_ARM_OMAP_CLOCK_H
14#define __ARCH_ARM_OMAP_CLOCK_H
15
16#include <linux/list.h>
17
18struct module;
19struct clk;
20struct clockdomain;
21
22/* Temporary, needed during the common clock framework conversion */
23#define __clk_get_name(clk) (clk->name)
24#define __clk_get_parent(clk) (clk->parent)
25#define __clk_get_rate(clk) (clk->rate)
26
27/**
28 * struct clkops - some clock function pointers
29 * @enable: fn ptr that enables the current clock in hardware
30 * @disable: fn ptr that enables the current clock in hardware
31 * @find_idlest: function returning the IDLEST register for the clock's IP blk
32 * @find_companion: function returning the "companion" clk reg for the clock
33 * @allow_idle: fn ptr that enables autoidle for the current clock in hardware
34 * @deny_idle: fn ptr that disables autoidle for the current clock in hardware
35 *
36 * A "companion" clk is an accompanying clock to the one being queried
37 * that must be enabled for the IP module connected to the clock to
38 * become accessible by the hardware. Neither @find_idlest nor
39 * @find_companion should be needed; that information is IP
40 * block-specific; the hwmod code has been created to handle this, but
41 * until hwmod data is ready and drivers have been converted to use PM
42 * runtime calls in place of clk_enable()/clk_disable(), @find_idlest and
43 * @find_companion must, unfortunately, remain.
44 */
45struct clkops {
46 int (*enable)(struct clk *);
47 void (*disable)(struct clk *);
48 void (*find_idlest)(struct clk *, void __iomem **,
49 u8 *, u8 *);
50 void (*find_companion)(struct clk *, void __iomem **,
51 u8 *);
52 void (*allow_idle)(struct clk *);
53 void (*deny_idle)(struct clk *);
54};
55
56#ifdef CONFIG_ARCH_OMAP2PLUS
57
58/* struct clksel_rate.flags possibilities */
59#define RATE_IN_242X (1 << 0)
60#define RATE_IN_243X (1 << 1)
61#define RATE_IN_3430ES1 (1 << 2) /* 3430ES1 rates only */
62#define RATE_IN_3430ES2PLUS (1 << 3) /* 3430 ES >= 2 rates only */
63#define RATE_IN_36XX (1 << 4)
64#define RATE_IN_4430 (1 << 5)
65#define RATE_IN_TI816X (1 << 6)
66#define RATE_IN_4460 (1 << 7)
67#define RATE_IN_AM33XX (1 << 8)
68#define RATE_IN_TI814X (1 << 9)
69
70#define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X)
71#define RATE_IN_34XX (RATE_IN_3430ES1 | RATE_IN_3430ES2PLUS)
72#define RATE_IN_3XXX (RATE_IN_34XX | RATE_IN_36XX)
73#define RATE_IN_44XX (RATE_IN_4430 | RATE_IN_4460)
74
75/* RATE_IN_3430ES2PLUS_36XX includes 34xx/35xx with ES >=2, and all 36xx/37xx */
76#define RATE_IN_3430ES2PLUS_36XX (RATE_IN_3430ES2PLUS | RATE_IN_36XX)
77
78
79/**
80 * struct clksel_rate - register bitfield values corresponding to clk divisors
81 * @val: register bitfield value (shifted to bit 0)
82 * @div: clock divisor corresponding to @val
83 * @flags: (see "struct clksel_rate.flags possibilities" above)
84 *
85 * @val should match the value of a read from struct clk.clksel_reg
86 * AND'ed with struct clk.clksel_mask, shifted right to bit 0.
87 *
88 * @div is the divisor that should be applied to the parent clock's rate
89 * to produce the current clock's rate.
90 */
91struct clksel_rate {
92 u32 val;
93 u8 div;
94 u16 flags;
95};
96
97/**
98 * struct clksel - available parent clocks, and a pointer to their divisors
99 * @parent: struct clk * to a possible parent clock
100 * @rates: available divisors for this parent clock
101 *
102 * A struct clksel is always associated with one or more struct clks
103 * and one or more struct clksel_rates.
104 */
105struct clksel {
106 struct clk *parent;
107 const struct clksel_rate *rates;
108};
109
110/**
111 * struct dpll_data - DPLL registers and integration data
112 * @mult_div1_reg: register containing the DPLL M and N bitfields
113 * @mult_mask: mask of the DPLL M bitfield in @mult_div1_reg
114 * @div1_mask: mask of the DPLL N bitfield in @mult_div1_reg
115 * @clk_bypass: struct clk pointer to the clock's bypass clock input
116 * @clk_ref: struct clk pointer to the clock's reference clock input
117 * @control_reg: register containing the DPLL mode bitfield
118 * @enable_mask: mask of the DPLL mode bitfield in @control_reg
119 * @last_rounded_rate: cache of the last rate result of omap2_dpll_round_rate()
120 * @last_rounded_m: cache of the last M result of omap2_dpll_round_rate()
121 * @max_multiplier: maximum valid non-bypass multiplier value (actual)
122 * @last_rounded_n: cache of the last N result of omap2_dpll_round_rate()
123 * @min_divider: minimum valid non-bypass divider value (actual)
124 * @max_divider: maximum valid non-bypass divider value (actual)
125 * @modes: possible values of @enable_mask
126 * @autoidle_reg: register containing the DPLL autoidle mode bitfield
127 * @idlest_reg: register containing the DPLL idle status bitfield
128 * @autoidle_mask: mask of the DPLL autoidle mode bitfield in @autoidle_reg
129 * @freqsel_mask: mask of the DPLL jitter correction bitfield in @control_reg
130 * @idlest_mask: mask of the DPLL idle status bitfield in @idlest_reg
131 * @auto_recal_bit: bitshift of the driftguard enable bit in @control_reg
132 * @recal_en_bit: bitshift of the PRM_IRQENABLE_* bit for recalibration IRQs
133 * @recal_st_bit: bitshift of the PRM_IRQSTATUS_* bit for recalibration IRQs
134 * @flags: DPLL type/features (see below)
135 *
136 * Possible values for @flags:
137 * DPLL_J_TYPE: "J-type DPLL" (only some 36xx, 4xxx DPLLs)
138 *
139 * @freqsel_mask is only used on the OMAP34xx family and AM35xx.
140 *
141 * XXX Some DPLLs have multiple bypass inputs, so it's not technically
142 * correct to only have one @clk_bypass pointer.
143 *
144 * XXX The runtime-variable fields (@last_rounded_rate, @last_rounded_m,
145 * @last_rounded_n) should be separated from the runtime-fixed fields
146 * and placed into a different structure, so that the runtime-fixed data
147 * can be placed into read-only space.
148 */
149struct dpll_data {
150 void __iomem *mult_div1_reg;
151 u32 mult_mask;
152 u32 div1_mask;
153 struct clk *clk_bypass;
154 struct clk *clk_ref;
155 void __iomem *control_reg;
156 u32 enable_mask;
157 unsigned long last_rounded_rate;
158 u16 last_rounded_m;
159 u16 max_multiplier;
160 u8 last_rounded_n;
161 u8 min_divider;
162 u16 max_divider;
163 u8 modes;
164 void __iomem *autoidle_reg;
165 void __iomem *idlest_reg;
166 u32 autoidle_mask;
167 u32 freqsel_mask;
168 u32 idlest_mask;
169 u32 dco_mask;
170 u32 sddiv_mask;
171 u8 auto_recal_bit;
172 u8 recal_en_bit;
173 u8 recal_st_bit;
174 u8 flags;
175};
176
177#endif
178
179/*
180 * struct clk.flags possibilities
181 *
182 * XXX document the rest of the clock flags here
183 *
184 * CLOCK_CLKOUTX2: (OMAP4 only) DPLL CLKOUT and CLKOUTX2 GATE_CTRL
185 * bits share the same register. This flag allows the
186 * omap4_dpllmx*() code to determine which GATE_CTRL bit field
187 * should be used. This is a temporary solution - a better approach
188 * would be to associate clock type-specific data with the clock,
189 * similar to the struct dpll_data approach.
190 */
191#define ENABLE_REG_32BIT (1 << 0) /* Use 32-bit access */
192#define CLOCK_IDLE_CONTROL (1 << 1)
193#define CLOCK_NO_IDLE_PARENT (1 << 2)
194#define ENABLE_ON_INIT (1 << 3) /* Enable upon framework init */
195#define INVERT_ENABLE (1 << 4) /* 0 enables, 1 disables */
196#define CLOCK_CLKOUTX2 (1 << 5)
197
198/**
199 * struct clk - OMAP struct clk
200 * @node: list_head connecting this clock into the full clock list
201 * @ops: struct clkops * for this clock
202 * @name: the name of the clock in the hardware (used in hwmod data and debug)
203 * @parent: pointer to this clock's parent struct clk
204 * @children: list_head connecting to the child clks' @sibling list_heads
205 * @sibling: list_head connecting this clk to its parent clk's @children
206 * @rate: current clock rate
207 * @enable_reg: register to write to enable the clock (see @enable_bit)
208 * @recalc: fn ptr that returns the clock's current rate
209 * @set_rate: fn ptr that can change the clock's current rate
210 * @round_rate: fn ptr that can round the clock's current rate
211 * @init: fn ptr to do clock-specific initialization
212 * @enable_bit: bitshift to write to enable/disable the clock (see @enable_reg)
213 * @usecount: number of users that have requested this clock to be enabled
214 * @fixed_div: when > 0, this clock's rate is its parent's rate / @fixed_div
215 * @flags: see "struct clk.flags possibilities" above
216 * @clksel_reg: for clksel clks, register va containing src/divisor select
217 * @clksel_mask: bitmask in @clksel_reg for the src/divisor selector
218 * @clksel: for clksel clks, pointer to struct clksel for this clock
219 * @dpll_data: for DPLLs, pointer to struct dpll_data for this clock
220 * @clkdm_name: clockdomain name that this clock is contained in
221 * @clkdm: pointer to struct clockdomain, resolved from @clkdm_name at runtime
222 * @rate_offset: bitshift for rate selection bitfield (OMAP1 only)
223 * @src_offset: bitshift for source selection bitfield (OMAP1 only)
224 *
225 * XXX @rate_offset, @src_offset should probably be removed and OMAP1
226 * clock code converted to use clksel.
227 *
228 * XXX @usecount is poorly named. It should be "enable_count" or
229 * something similar. "users" in the description refers to kernel
230 * code (core code or drivers) that have called clk_enable() and not
231 * yet called clk_disable(); the usecount of parent clocks is also
232 * incremented by the clock code when clk_enable() is called on child
233 * clocks and decremented by the clock code when clk_disable() is
234 * called on child clocks.
235 *
236 * XXX @clkdm, @usecount, @children, @sibling should be marked for
237 * internal use only.
238 *
239 * @children and @sibling are used to optimize parent-to-child clock
240 * tree traversals. (child-to-parent traversals use @parent.)
241 *
242 * XXX The notion of the clock's current rate probably needs to be
243 * separated from the clock's target rate.
244 */
245struct clk {
246 struct list_head node;
247 const struct clkops *ops;
248 const char *name;
249 struct clk *parent;
250 struct list_head children;
251 struct list_head sibling; /* node for children */
252 unsigned long rate;
253 void __iomem *enable_reg;
254 unsigned long (*recalc)(struct clk *);
255 int (*set_rate)(struct clk *, unsigned long);
256 long (*round_rate)(struct clk *, unsigned long);
257 void (*init)(struct clk *);
258 u8 enable_bit;
259 s8 usecount;
260 u8 fixed_div;
261 u8 flags;
262#ifdef CONFIG_ARCH_OMAP2PLUS
263 void __iomem *clksel_reg;
264 u32 clksel_mask;
265 const struct clksel *clksel;
266 struct dpll_data *dpll_data;
267 const char *clkdm_name;
268 struct clockdomain *clkdm;
269#else
270 u8 rate_offset;
271 u8 src_offset;
272#endif
273#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
274 struct dentry *dent; /* For visible tree hierarchy */
275#endif
276};
277
278struct clk_functions {
279 int (*clk_enable)(struct clk *clk);
280 void (*clk_disable)(struct clk *clk);
281 long (*clk_round_rate)(struct clk *clk, unsigned long rate);
282 int (*clk_set_rate)(struct clk *clk, unsigned long rate);
283 int (*clk_set_parent)(struct clk *clk, struct clk *parent);
284 void (*clk_allow_idle)(struct clk *clk);
285 void (*clk_deny_idle)(struct clk *clk);
286 void (*clk_disable_unused)(struct clk *clk);
287};
288
289extern int mpurate;
290
291extern int clk_init(struct clk_functions *custom_clocks);
292extern void clk_preinit(struct clk *clk);
293extern int clk_register(struct clk *clk);
294extern void clk_reparent(struct clk *child, struct clk *parent);
295extern void clk_unregister(struct clk *clk);
296extern void propagate_rate(struct clk *clk);
297extern void recalculate_root_clocks(void);
298extern unsigned long followparent_recalc(struct clk *clk);
299extern void clk_enable_init_clocks(void);
300unsigned long omap_fixed_divisor_recalc(struct clk *clk);
301extern struct clk *omap_clk_get_by_name(const char *name);
302extern int omap_clk_enable_autoidle_all(void);
303extern int omap_clk_disable_autoidle_all(void);
304
305extern const struct clkops clkops_null;
306
307extern struct clk dummy_ck;
308
309#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-30 21:57:39 -0500