diff options
Diffstat (limited to 'arch/arm/plat-mxc/include/mach/mx27.h')
-rw-r--r-- | arch/arm/plat-mxc/include/mach/mx27.h | 127 |
1 files changed, 64 insertions, 63 deletions
diff --git a/arch/arm/plat-mxc/include/mach/mx27.h b/arch/arm/plat-mxc/include/mach/mx27.h index 6265357284d7..e074616d54ca 100644 --- a/arch/arm/plat-mxc/include/mach/mx27.h +++ b/arch/arm/plat-mxc/include/mach/mx27.h | |||
@@ -128,69 +128,70 @@ | |||
128 | #define MX27_IO_ADDRESS(x) IOMEM(MX27_IO_P2V(x)) | 128 | #define MX27_IO_ADDRESS(x) IOMEM(MX27_IO_P2V(x)) |
129 | 129 | ||
130 | /* fixed interrupt numbers */ | 130 | /* fixed interrupt numbers */ |
131 | #define MX27_INT_I2C2 1 | 131 | #include <asm/irq.h> |
132 | #define MX27_INT_GPT6 2 | 132 | #define MX27_INT_I2C2 (NR_IRQS_LEGACY + 1) |
133 | #define MX27_INT_GPT5 3 | 133 | #define MX27_INT_GPT6 (NR_IRQS_LEGACY + 2) |
134 | #define MX27_INT_GPT4 4 | 134 | #define MX27_INT_GPT5 (NR_IRQS_LEGACY + 3) |
135 | #define MX27_INT_RTIC 5 | 135 | #define MX27_INT_GPT4 (NR_IRQS_LEGACY + 4) |
136 | #define MX27_INT_CSPI3 6 | 136 | #define MX27_INT_RTIC (NR_IRQS_LEGACY + 5) |
137 | #define MX27_INT_SDHC 7 | 137 | #define MX27_INT_CSPI3 (NR_IRQS_LEGACY + 6) |
138 | #define MX27_INT_GPIO 8 | 138 | #define MX27_INT_SDHC (NR_IRQS_LEGACY + 7) |
139 | #define MX27_INT_SDHC3 9 | 139 | #define MX27_INT_GPIO (NR_IRQS_LEGACY + 8) |
140 | #define MX27_INT_SDHC2 10 | 140 | #define MX27_INT_SDHC3 (NR_IRQS_LEGACY + 9) |
141 | #define MX27_INT_SDHC1 11 | 141 | #define MX27_INT_SDHC2 (NR_IRQS_LEGACY + 10) |
142 | #define MX27_INT_I2C1 12 | 142 | #define MX27_INT_SDHC1 (NR_IRQS_LEGACY + 11) |
143 | #define MX27_INT_SSI2 13 | 143 | #define MX27_INT_I2C1 (NR_IRQS_LEGACY + 12) |
144 | #define MX27_INT_SSI1 14 | 144 | #define MX27_INT_SSI2 (NR_IRQS_LEGACY + 13) |
145 | #define MX27_INT_CSPI2 15 | 145 | #define MX27_INT_SSI1 (NR_IRQS_LEGACY + 14) |
146 | #define MX27_INT_CSPI1 16 | 146 | #define MX27_INT_CSPI2 (NR_IRQS_LEGACY + 15) |
147 | #define MX27_INT_UART4 17 | 147 | #define MX27_INT_CSPI1 (NR_IRQS_LEGACY + 16) |
148 | #define MX27_INT_UART3 18 | 148 | #define MX27_INT_UART4 (NR_IRQS_LEGACY + 17) |
149 | #define MX27_INT_UART2 19 | 149 | #define MX27_INT_UART3 (NR_IRQS_LEGACY + 18) |
150 | #define MX27_INT_UART1 20 | 150 | #define MX27_INT_UART2 (NR_IRQS_LEGACY + 19) |
151 | #define MX27_INT_KPP 21 | 151 | #define MX27_INT_UART1 (NR_IRQS_LEGACY + 20) |
152 | #define MX27_INT_RTC 22 | 152 | #define MX27_INT_KPP (NR_IRQS_LEGACY + 21) |
153 | #define MX27_INT_PWM 23 | 153 | #define MX27_INT_RTC (NR_IRQS_LEGACY + 22) |
154 | #define MX27_INT_GPT3 24 | 154 | #define MX27_INT_PWM (NR_IRQS_LEGACY + 23) |
155 | #define MX27_INT_GPT2 25 | 155 | #define MX27_INT_GPT3 (NR_IRQS_LEGACY + 24) |
156 | #define MX27_INT_GPT1 26 | 156 | #define MX27_INT_GPT2 (NR_IRQS_LEGACY + 25) |
157 | #define MX27_INT_WDOG 27 | 157 | #define MX27_INT_GPT1 (NR_IRQS_LEGACY + 26) |
158 | #define MX27_INT_PCMCIA 28 | 158 | #define MX27_INT_WDOG (NR_IRQS_LEGACY + 27) |
159 | #define MX27_INT_NFC 29 | 159 | #define MX27_INT_PCMCIA (NR_IRQS_LEGACY + 28) |
160 | #define MX27_INT_ATA 30 | 160 | #define MX27_INT_NFC (NR_IRQS_LEGACY + 29) |
161 | #define MX27_INT_CSI 31 | 161 | #define MX27_INT_ATA (NR_IRQS_LEGACY + 30) |
162 | #define MX27_INT_DMACH0 32 | 162 | #define MX27_INT_CSI (NR_IRQS_LEGACY + 31) |
163 | #define MX27_INT_DMACH1 33 | 163 | #define MX27_INT_DMACH0 (NR_IRQS_LEGACY + 32) |
164 | #define MX27_INT_DMACH2 34 | 164 | #define MX27_INT_DMACH1 (NR_IRQS_LEGACY + 33) |
165 | #define MX27_INT_DMACH3 35 | 165 | #define MX27_INT_DMACH2 (NR_IRQS_LEGACY + 34) |
166 | #define MX27_INT_DMACH4 36 | 166 | #define MX27_INT_DMACH3 (NR_IRQS_LEGACY + 35) |
167 | #define MX27_INT_DMACH5 37 | 167 | #define MX27_INT_DMACH4 (NR_IRQS_LEGACY + 36) |
168 | #define MX27_INT_DMACH6 38 | 168 | #define MX27_INT_DMACH5 (NR_IRQS_LEGACY + 37) |
169 | #define MX27_INT_DMACH7 39 | 169 | #define MX27_INT_DMACH6 (NR_IRQS_LEGACY + 38) |
170 | #define MX27_INT_DMACH8 40 | 170 | #define MX27_INT_DMACH7 (NR_IRQS_LEGACY + 39) |
171 | #define MX27_INT_DMACH9 41 | 171 | #define MX27_INT_DMACH8 (NR_IRQS_LEGACY + 40) |
172 | #define MX27_INT_DMACH10 42 | 172 | #define MX27_INT_DMACH9 (NR_IRQS_LEGACY + 41) |
173 | #define MX27_INT_DMACH11 43 | 173 | #define MX27_INT_DMACH10 (NR_IRQS_LEGACY + 42) |
174 | #define MX27_INT_DMACH12 44 | 174 | #define MX27_INT_DMACH11 (NR_IRQS_LEGACY + 43) |
175 | #define MX27_INT_DMACH13 45 | 175 | #define MX27_INT_DMACH12 (NR_IRQS_LEGACY + 44) |
176 | #define MX27_INT_DMACH14 46 | 176 | #define MX27_INT_DMACH13 (NR_IRQS_LEGACY + 45) |
177 | #define MX27_INT_DMACH15 47 | 177 | #define MX27_INT_DMACH14 (NR_IRQS_LEGACY + 46) |
178 | #define MX27_INT_UART6 48 | 178 | #define MX27_INT_DMACH15 (NR_IRQS_LEGACY + 47) |
179 | #define MX27_INT_UART5 49 | 179 | #define MX27_INT_UART6 (NR_IRQS_LEGACY + 48) |
180 | #define MX27_INT_FEC 50 | 180 | #define MX27_INT_UART5 (NR_IRQS_LEGACY + 49) |
181 | #define MX27_INT_EMMAPRP 51 | 181 | #define MX27_INT_FEC (NR_IRQS_LEGACY + 50) |
182 | #define MX27_INT_EMMAPP 52 | 182 | #define MX27_INT_EMMAPRP (NR_IRQS_LEGACY + 51) |
183 | #define MX27_INT_VPU 53 | 183 | #define MX27_INT_EMMAPP (NR_IRQS_LEGACY + 52) |
184 | #define MX27_INT_USB_HS1 54 | 184 | #define MX27_INT_VPU (NR_IRQS_LEGACY + 53) |
185 | #define MX27_INT_USB_HS2 55 | 185 | #define MX27_INT_USB_HS1 (NR_IRQS_LEGACY + 54) |
186 | #define MX27_INT_USB_OTG 56 | 186 | #define MX27_INT_USB_HS2 (NR_IRQS_LEGACY + 55) |
187 | #define MX27_INT_SCC_SMN 57 | 187 | #define MX27_INT_USB_OTG (NR_IRQS_LEGACY + 56) |
188 | #define MX27_INT_SCC_SCM 58 | 188 | #define MX27_INT_SCC_SMN (NR_IRQS_LEGACY + 57) |
189 | #define MX27_INT_SAHARA 59 | 189 | #define MX27_INT_SCC_SCM (NR_IRQS_LEGACY + 58) |
190 | #define MX27_INT_SLCDC 60 | 190 | #define MX27_INT_SAHARA (NR_IRQS_LEGACY + 59) |
191 | #define MX27_INT_LCDC 61 | 191 | #define MX27_INT_SLCDC (NR_IRQS_LEGACY + 60) |
192 | #define MX27_INT_IIM 62 | 192 | #define MX27_INT_LCDC (NR_IRQS_LEGACY + 61) |
193 | #define MX27_INT_CCM 63 | 193 | #define MX27_INT_IIM (NR_IRQS_LEGACY + 62) |
194 | #define MX27_INT_CCM (NR_IRQS_LEGACY + 63) | ||
194 | 195 | ||
195 | /* fixed DMA request numbers */ | 196 | /* fixed DMA request numbers */ |
196 | #define MX27_DMA_REQ_CSPI3_RX 1 | 197 | #define MX27_DMA_REQ_CSPI3_RX 1 |