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-rw-r--r--arch/arm/mach-versatile/core.c18
1 files changed, 8 insertions, 10 deletions
diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c
index 6bbd74e950ab..cf4687ee2a7b 100644
--- a/arch/arm/mach-versatile/core.c
+++ b/arch/arm/mach-versatile/core.c
@@ -66,12 +66,6 @@
66#define VA_VIC_BASE __io_address(VERSATILE_VIC_BASE) 66#define VA_VIC_BASE __io_address(VERSATILE_VIC_BASE)
67#define VA_SIC_BASE __io_address(VERSATILE_SIC_BASE) 67#define VA_SIC_BASE __io_address(VERSATILE_SIC_BASE)
68 68
69static struct fpga_irq_data sic_irq = {
70 .base = VA_SIC_BASE,
71 .irq_start = IRQ_SIC_START,
72 .chip.name = "SIC",
73};
74
75#if 1 69#if 1
76#define IRQ_MMCI0A IRQ_VICSOURCE22 70#define IRQ_MMCI0A IRQ_VICSOURCE22
77#define IRQ_AACI IRQ_VICSOURCE24 71#define IRQ_AACI IRQ_VICSOURCE24
@@ -105,8 +99,11 @@ void __init versatile_init_irq(void)
105 99
106 writel(~0, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR); 100 writel(~0, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR);
107 101
108 fpga_irq_init(IRQ_VICSOURCE31, ~PIC_MASK, &sic_irq); 102 np = of_find_matching_node_by_address(NULL, sic_of_match,
109 irq_domain_generate_simple(sic_of_match, VERSATILE_SIC_BASE, IRQ_SIC_START); 103 VERSATILE_SIC_BASE);
104
105 fpga_irq_init(VA_SIC_BASE, "SIC", IRQ_SIC_START,
106 IRQ_VICSOURCE31, ~PIC_MASK, np);
110 107
111 /* 108 /*
112 * Interrupts on secondary controller from 0 to 8 are routed to 109 * Interrupts on secondary controller from 0 to 8 are routed to
@@ -666,17 +663,18 @@ static struct amba_device *amba_devs[] __initdata = {
666 * having a specific name. 663 * having a specific name.
667 */ 664 */
668struct of_dev_auxdata versatile_auxdata_lookup[] __initdata = { 665struct of_dev_auxdata versatile_auxdata_lookup[] __initdata = {
669 OF_DEV_AUXDATA("arm,primecell", VERSATILE_MMCI0_BASE, "fpga:05", NULL), 666 OF_DEV_AUXDATA("arm,primecell", VERSATILE_MMCI0_BASE, "fpga:05", &mmc0_plat_data),
670 OF_DEV_AUXDATA("arm,primecell", VERSATILE_KMI0_BASE, "fpga:06", NULL), 667 OF_DEV_AUXDATA("arm,primecell", VERSATILE_KMI0_BASE, "fpga:06", NULL),
671 OF_DEV_AUXDATA("arm,primecell", VERSATILE_KMI1_BASE, "fpga:07", NULL), 668 OF_DEV_AUXDATA("arm,primecell", VERSATILE_KMI1_BASE, "fpga:07", NULL),
672 OF_DEV_AUXDATA("arm,primecell", VERSATILE_UART3_BASE, "fpga:09", NULL), 669 OF_DEV_AUXDATA("arm,primecell", VERSATILE_UART3_BASE, "fpga:09", NULL),
670 /* FIXME: this is buggy, the platform data is needed for this MMC instance too */
673 OF_DEV_AUXDATA("arm,primecell", VERSATILE_MMCI1_BASE, "fpga:0b", NULL), 671 OF_DEV_AUXDATA("arm,primecell", VERSATILE_MMCI1_BASE, "fpga:0b", NULL),
674 672
675 OF_DEV_AUXDATA("arm,primecell", VERSATILE_CLCD_BASE, "dev:20", &clcd_plat_data), 673 OF_DEV_AUXDATA("arm,primecell", VERSATILE_CLCD_BASE, "dev:20", &clcd_plat_data),
676 OF_DEV_AUXDATA("arm,primecell", VERSATILE_UART0_BASE, "dev:f1", NULL), 674 OF_DEV_AUXDATA("arm,primecell", VERSATILE_UART0_BASE, "dev:f1", NULL),
677 OF_DEV_AUXDATA("arm,primecell", VERSATILE_UART1_BASE, "dev:f2", NULL), 675 OF_DEV_AUXDATA("arm,primecell", VERSATILE_UART1_BASE, "dev:f2", NULL),
678 OF_DEV_AUXDATA("arm,primecell", VERSATILE_UART2_BASE, "dev:f3", NULL), 676 OF_DEV_AUXDATA("arm,primecell", VERSATILE_UART2_BASE, "dev:f3", NULL),
679 OF_DEV_AUXDATA("arm,primecell", VERSATILE_SSP_BASE, "dev:f4", NULL), 677 OF_DEV_AUXDATA("arm,primecell", VERSATILE_SSP_BASE, "dev:f4", &ssp0_plat_data),
680 678
681#if 0 679#if 0
682 /* 680 /*