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-rw-r--r--arch/arm/mach-ux500/include/mach/db5500-regs.h143
-rw-r--r--arch/arm/mach-ux500/include/mach/debug-macro.S4
-rw-r--r--arch/arm/mach-ux500/include/mach/devices.h1
-rw-r--r--arch/arm/mach-ux500/include/mach/hardware.h1
-rw-r--r--arch/arm/mach-ux500/include/mach/irqs-board-u5500.h21
-rw-r--r--arch/arm/mach-ux500/include/mach/irqs-db5500.h113
-rw-r--r--arch/arm/mach-ux500/include/mach/irqs.h5
-rw-r--r--arch/arm/mach-ux500/include/mach/mbox-db5500.h88
-rw-r--r--arch/arm/mach-ux500/include/mach/setup.h6
-rw-r--r--arch/arm/mach-ux500/include/mach/uncompress.h7
10 files changed, 2 insertions, 387 deletions
diff --git a/arch/arm/mach-ux500/include/mach/db5500-regs.h b/arch/arm/mach-ux500/include/mach/db5500-regs.h
deleted file mode 100644
index 8e714bcb099f..000000000000
--- a/arch/arm/mach-ux500/include/mach/db5500-regs.h
+++ /dev/null
@@ -1,143 +0,0 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * License terms: GNU General Public License (GPL) version 2
5 */
6
7#ifndef __MACH_DB5500_REGS_H
8#define __MACH_DB5500_REGS_H
9
10#define U5500_PER1_BASE 0xA0020000
11#define U5500_PER2_BASE 0xA0010000
12#define U5500_PER3_BASE 0x80140000
13#define U5500_PER4_BASE 0x80150000
14#define U5500_PER5_BASE 0x80100000
15#define U5500_PER6_BASE 0x80120000
16
17#define U5500_GIC_DIST_BASE 0xA0411000
18#define U5500_GIC_CPU_BASE 0xA0410100
19#define U5500_DMA_BASE 0x90030000
20#define U5500_STM_BASE 0x90020000
21#define U5500_STM_REG_BASE (U5500_STM_BASE + 0xF000)
22#define U5500_MCDE_BASE 0xA0400000
23#define U5500_MODEM_BASE 0xB0000000
24#define U5500_L2CC_BASE 0xA0412000
25#define U5500_SCU_BASE 0xA0410000
26#define U5500_DSI1_BASE 0xA0401000
27#define U5500_DSI2_BASE 0xA0402000
28#define U5500_SIA_BASE 0xA0100000
29#define U5500_SVA_BASE 0x80200000
30#define U5500_HSEM_BASE 0xA0000000
31#define U5500_NAND0_BASE 0x60000000
32#define U5500_NAND1_BASE 0x70000000
33#define U5500_TWD_BASE 0xa0410600
34#define U5500_ICN_BASE 0xA0040000
35#define U5500_B2R2_BASE 0xa0200000
36#define U5500_BOOT_ROM_BASE 0x90000000
37
38#define U5500_FSMC_BASE (U5500_PER1_BASE + 0x0000)
39#define U5500_SDI0_BASE (U5500_PER1_BASE + 0x1000)
40#define U5500_SDI2_BASE (U5500_PER1_BASE + 0x2000)
41#define U5500_UART0_BASE (U5500_PER1_BASE + 0x3000)
42#define U5500_I2C1_BASE (U5500_PER1_BASE + 0x4000)
43#define U5500_MSP0_BASE (U5500_PER1_BASE + 0x5000)
44#define U5500_GPIO0_BASE (U5500_PER1_BASE + 0xE000)
45#define U5500_CLKRST1_BASE (U5500_PER1_BASE + 0xF000)
46
47#define U5500_USBOTG_BASE (U5500_PER2_BASE + 0x0000)
48#define U5500_GPIO1_BASE (U5500_PER2_BASE + 0xE000)
49#define U5500_CLKRST2_BASE (U5500_PER2_BASE + 0xF000)
50
51#define U5500_KEYPAD_BASE (U5500_PER3_BASE + 0x0000)
52#define U5500_PWM_BASE (U5500_PER3_BASE + 0x1000)
53#define U5500_GPIO3_BASE (U5500_PER3_BASE + 0xE000)
54#define U5500_CLKRST3_BASE (U5500_PER3_BASE + 0xF000)
55
56#define U5500_BACKUPRAM0_BASE (U5500_PER4_BASE + 0x0000)
57#define U5500_BACKUPRAM1_BASE (U5500_PER4_BASE + 0x1000)
58#define U5500_RTT0_BASE (U5500_PER4_BASE + 0x2000)
59#define U5500_RTT1_BASE (U5500_PER4_BASE + 0x3000)
60#define U5500_RTC_BASE (U5500_PER4_BASE + 0x4000)
61#define U5500_SCR_BASE (U5500_PER4_BASE + 0x5000)
62#define U5500_DMC_BASE (U5500_PER4_BASE + 0x6000)
63#define U5500_PRCMU_BASE (U5500_PER4_BASE + 0x7000)
64#define U5500_PRCMU_TIMER_3_BASE (U5500_PER4_BASE + 0x07338)
65#define U5500_PRCMU_TIMER_4_BASE (U5500_PER4_BASE + 0x07450)
66#define U5500_MSP1_BASE (U5500_PER4_BASE + 0x9000)
67#define U5500_GPIO2_BASE (U5500_PER4_BASE + 0xA000)
68#define U5500_MTIMER_BASE (U5500_PER4_BASE + 0xC000)
69#define U5500_CDETECT_BASE (U5500_PER4_BASE + 0xF000)
70#define U5500_PRCMU_TCDM_BASE (U5500_PER4_BASE + 0x18000)
71#define U5500_PRCMU_TCPM_BASE (U5500_PER4_BASE + 0x10000)
72#define U5500_TPIU_BASE (U5500_PER4_BASE + 0x50000)
73
74#define U5500_SPI0_BASE (U5500_PER5_BASE + 0x0000)
75#define U5500_SPI1_BASE (U5500_PER5_BASE + 0x1000)
76#define U5500_SPI2_BASE (U5500_PER5_BASE + 0x2000)
77#define U5500_SPI3_BASE (U5500_PER5_BASE + 0x3000)
78#define U5500_UART1_BASE (U5500_PER5_BASE + 0x4000)
79#define U5500_UART2_BASE (U5500_PER5_BASE + 0x5000)
80#define U5500_UART3_BASE (U5500_PER5_BASE + 0x6000)
81#define U5500_SDI1_BASE (U5500_PER5_BASE + 0x7000)
82#define U5500_SDI3_BASE (U5500_PER5_BASE + 0x8000)
83#define U5500_SDI4_BASE (U5500_PER5_BASE + 0x9000)
84#define U5500_I2C2_BASE (U5500_PER5_BASE + 0xA000)
85#define U5500_I2C3_BASE (U5500_PER5_BASE + 0xB000)
86#define U5500_MSP2_BASE (U5500_PER5_BASE + 0xC000)
87#define U5500_IRDA_BASE (U5500_PER5_BASE + 0xD000)
88#define U5500_IRRC_BASE (U5500_PER5_BASE + 0x10000)
89#define U5500_GPIO4_BASE (U5500_PER5_BASE + 0x1E000)
90#define U5500_CLKRST5_BASE (U5500_PER5_BASE + 0x1F000)
91
92#define U5500_RNG_BASE (U5500_PER6_BASE + 0x0000)
93#define U5500_HASH0_BASE (U5500_PER6_BASE + 0x1000)
94#define U5500_HASH1_BASE (U5500_PER6_BASE + 0x2000)
95#define U5500_PKA_BASE (U5500_PER6_BASE + 0x4000)
96#define U5500_PKAM_BASE (U5500_PER6_BASE + 0x5100)
97#define U5500_MTU0_BASE (U5500_PER6_BASE + 0x6000)
98#define U5500_MTU1_BASE (U5500_PER6_BASE + 0x7000)
99#define U5500_CR_BASE (U5500_PER6_BASE + 0x8000)
100#define U5500_CRYP0_BASE (U5500_PER6_BASE + 0xA000)
101#define U5500_CRYP1_BASE (U5500_PER6_BASE + 0xB000)
102#define U5500_CLKRST6_BASE (U5500_PER6_BASE + 0xF000)
103
104#define U5500_GPIOBANK0_BASE U5500_GPIO0_BASE
105#define U5500_GPIOBANK1_BASE (U5500_GPIO0_BASE + 0x80)
106#define U5500_GPIOBANK2_BASE U5500_GPIO1_BASE
107#define U5500_GPIOBANK3_BASE U5500_GPIO2_BASE
108#define U5500_GPIOBANK4_BASE U5500_GPIO3_BASE
109#define U5500_GPIOBANK5_BASE U5500_GPIO4_BASE
110#define U5500_GPIOBANK6_BASE (U5500_GPIO4_BASE + 0x80)
111#define U5500_GPIOBANK7_BASE (U5500_GPIO4_BASE + 0x100)
112
113#define U5500_MBOX_BASE (U5500_MODEM_BASE + 0xFFD1000)
114#define U5500_MBOX0_PEER_START (U5500_MBOX_BASE + 0x40)
115#define U5500_MBOX0_PEER_END (U5500_MBOX_BASE + 0x5F)
116#define U5500_MBOX0_LOCAL_START (U5500_MBOX_BASE + 0x60)
117#define U5500_MBOX0_LOCAL_END (U5500_MBOX_BASE + 0x7F)
118#define U5500_MBOX1_PEER_START (U5500_MBOX_BASE + 0x80)
119#define U5500_MBOX1_PEER_END (U5500_MBOX_BASE + 0x9F)
120#define U5500_MBOX1_LOCAL_START (U5500_MBOX_BASE + 0xA0)
121#define U5500_MBOX1_LOCAL_END (U5500_MBOX_BASE + 0xBF)
122#define U5500_MBOX2_PEER_START (U5500_MBOX_BASE + 0x00)
123#define U5500_MBOX2_PEER_END (U5500_MBOX_BASE + 0x1F)
124#define U5500_MBOX2_LOCAL_START (U5500_MBOX_BASE + 0x20)
125#define U5500_MBOX2_LOCAL_END (U5500_MBOX_BASE + 0x3F)
126
127#define U5500_ACCCON_BASE_SEC (0xBFFF0000)
128#define U5500_ACCCON_BASE (0xBFFF1000)
129#define U5500_ACCCON_CPUVEC_RESET_ADDR_OFFSET (0x00000020)
130#define U5500_ACCCON_ACC_CPU_CTRL_OFFSET (0x000000BC)
131#define U5500_INTCON_MBOX1_INT_RESET_ADDR (0xBFFD31A4)
132
133#define U5500_ESRAM_BASE 0x40000000
134#define U5500_ESRAM_DMA_LCPA_OFFSET 0x10000
135#define U5500_DMA_LCPA_BASE (U5500_ESRAM_BASE + U5500_ESRAM_DMA_LCPA_OFFSET)
136
137#define U5500_MCDE_SIZE 0x1000
138#define U5500_DSI_LINK_SIZE 0x1000
139#define U5500_DSI_LINK_COUNT 0x2
140#define U5500_DSI_LINK1_BASE (U5500_MCDE_BASE + U5500_MCDE_SIZE)
141#define U5500_DSI_LINK2_BASE (U5500_DSI_LINK1_BASE + U5500_DSI_LINK_SIZE)
142
143#endif
diff --git a/arch/arm/mach-ux500/include/mach/debug-macro.S b/arch/arm/mach-ux500/include/mach/debug-macro.S
index 8d74d927d4e2..67035223334a 100644
--- a/arch/arm/mach-ux500/include/mach/debug-macro.S
+++ b/arch/arm/mach-ux500/include/mach/debug-macro.S
@@ -20,10 +20,6 @@
20 * built, so that there's some hint during the build that something is wrong. 20 * built, so that there's some hint during the build that something is wrong.
21 */ 21 */
22 22
23#ifdef CONFIG_UX500_SOC_DB5500
24#define __UX500_UART(n) U5500_UART##n##_BASE
25#endif
26
27#ifdef CONFIG_UX500_SOC_DB8500 23#ifdef CONFIG_UX500_SOC_DB8500
28#define __UX500_UART(n) U8500_UART##n##_BASE 24#define __UX500_UART(n) U8500_UART##n##_BASE
29#endif 25#endif
diff --git a/arch/arm/mach-ux500/include/mach/devices.h b/arch/arm/mach-ux500/include/mach/devices.h
index 5f6cb71fc62d..9b5eb69a0154 100644
--- a/arch/arm/mach-ux500/include/mach/devices.h
+++ b/arch/arm/mach-ux500/include/mach/devices.h
@@ -10,7 +10,6 @@
10struct platform_device; 10struct platform_device;
11struct amba_device; 11struct amba_device;
12 12
13extern struct platform_device u5500_gpio_devs[];
14extern struct platform_device u8500_gpio_devs[]; 13extern struct platform_device u8500_gpio_devs[];
15 14
16extern struct amba_device ux500_pl031_device; 15extern struct amba_device ux500_pl031_device;
diff --git a/arch/arm/mach-ux500/include/mach/hardware.h b/arch/arm/mach-ux500/include/mach/hardware.h
index f84698936d36..cf6fac3d1eeb 100644
--- a/arch/arm/mach-ux500/include/mach/hardware.h
+++ b/arch/arm/mach-ux500/include/mach/hardware.h
@@ -28,7 +28,6 @@
28#define io_p2v(n) __io_address(n) 28#define io_p2v(n) __io_address(n)
29 29
30#include <mach/db8500-regs.h> 30#include <mach/db8500-regs.h>
31#include <mach/db5500-regs.h>
32 31
33#define MSP_TX_RX_REG_OFFSET 0 32#define MSP_TX_RX_REG_OFFSET 0
34 33
diff --git a/arch/arm/mach-ux500/include/mach/irqs-board-u5500.h b/arch/arm/mach-ux500/include/mach/irqs-board-u5500.h
deleted file mode 100644
index 29d972c7717b..000000000000
--- a/arch/arm/mach-ux500/include/mach/irqs-board-u5500.h
+++ /dev/null
@@ -1,21 +0,0 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * License terms: GNU General Public License (GPL) version 2
5 */
6
7#ifndef __MACH_IRQS_BOARD_U5500_H
8#define __MACH_IRQS_BOARD_U5500_H
9
10#define AB5500_NR_IRQS 5
11#define IRQ_AB5500_BASE IRQ_BOARD_START
12#define IRQ_AB5500_END (IRQ_AB5500_BASE + AB5500_NR_IRQS)
13
14#define U5500_IRQ_END IRQ_AB5500_END
15
16#if IRQ_BOARD_END < U5500_IRQ_END
17#undef IRQ_BOARD_END
18#define IRQ_BOARD_END U5500_IRQ_END
19#endif
20
21#endif
diff --git a/arch/arm/mach-ux500/include/mach/irqs-db5500.h b/arch/arm/mach-ux500/include/mach/irqs-db5500.h
deleted file mode 100644
index 77239776a6f2..000000000000
--- a/arch/arm/mach-ux500/include/mach/irqs-db5500.h
+++ /dev/null
@@ -1,113 +0,0 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * Author: Rabin Vincent <rabin.vincent@stericsson.com>
5 * License terms: GNU General Public License (GPL) version 2
6 */
7
8#ifndef __MACH_IRQS_DB5500_H
9#define __MACH_IRQS_DB5500_H
10
11#define IRQ_DB5500_MTU0 (IRQ_SHPI_START + 4)
12#define IRQ_DB5500_SPI2 (IRQ_SHPI_START + 6)
13#define IRQ_DB5500_PMU0 (IRQ_SHPI_START + 7)
14#define IRQ_DB5500_SPI0 (IRQ_SHPI_START + 8)
15#define IRQ_DB5500_RTT (IRQ_SHPI_START + 9)
16#define IRQ_DB5500_PKA (IRQ_SHPI_START + 10)
17#define IRQ_DB5500_UART0 (IRQ_SHPI_START + 11)
18#define IRQ_DB5500_I2C3 (IRQ_SHPI_START + 12)
19#define IRQ_DB5500_L2CC (IRQ_SHPI_START + 13)
20#define IRQ_DB5500_MSP0 (IRQ_SHPI_START + 14)
21#define IRQ_DB5500_CRYP1 (IRQ_SHPI_START + 15)
22#define IRQ_DB5500_PMU1 (IRQ_SHPI_START + 16)
23#define IRQ_DB5500_MTU1 (IRQ_SHPI_START + 17)
24#define IRQ_DB5500_RTC (IRQ_SHPI_START + 18)
25#define IRQ_DB5500_UART1 (IRQ_SHPI_START + 19)
26#define IRQ_DB5500_USB_WAKEUP (IRQ_SHPI_START + 20)
27#define IRQ_DB5500_I2C0 (IRQ_SHPI_START + 21)
28#define IRQ_DB5500_I2C1 (IRQ_SHPI_START + 22)
29#define IRQ_DB5500_USBOTG (IRQ_SHPI_START + 23)
30#define IRQ_DB5500_DMA_SECURE (IRQ_SHPI_START + 24)
31#define IRQ_DB5500_DMA (IRQ_SHPI_START + 25)
32#define IRQ_DB5500_UART2 (IRQ_SHPI_START + 26)
33#define IRQ_DB5500_ICN_PMU1 (IRQ_SHPI_START + 27)
34#define IRQ_DB5500_ICN_PMU2 (IRQ_SHPI_START + 28)
35#define IRQ_DB5500_UART3 (IRQ_SHPI_START + 29)
36#define IRQ_DB5500_SPI3 (IRQ_SHPI_START + 30)
37#define IRQ_DB5500_SDMMC4 (IRQ_SHPI_START + 31)
38#define IRQ_DB5500_IRRC (IRQ_SHPI_START + 33)
39#define IRQ_DB5500_IRDA_FT (IRQ_SHPI_START + 34)
40#define IRQ_DB5500_IRDA_SD (IRQ_SHPI_START + 35)
41#define IRQ_DB5500_IRDA_FI (IRQ_SHPI_START + 36)
42#define IRQ_DB5500_IRDA_FD (IRQ_SHPI_START + 37)
43#define IRQ_DB5500_FSMC_CODEREADY (IRQ_SHPI_START + 38)
44#define IRQ_DB5500_FSMC_NANDWAIT (IRQ_SHPI_START + 39)
45#define IRQ_DB5500_AB5500 (IRQ_SHPI_START + 40)
46#define IRQ_DB5500_SDMMC2 (IRQ_SHPI_START + 41)
47#define IRQ_DB5500_SIA (IRQ_SHPI_START + 42)
48#define IRQ_DB5500_SIA2 (IRQ_SHPI_START + 43)
49#define IRQ_DB5500_HVA (IRQ_SHPI_START + 44)
50#define IRQ_DB5500_HVA2 (IRQ_SHPI_START + 45)
51#define IRQ_DB5500_PRCMU0 (IRQ_SHPI_START + 46)
52#define IRQ_DB5500_PRCMU1 (IRQ_SHPI_START + 47)
53#define IRQ_DB5500_DISP (IRQ_SHPI_START + 48)
54#define IRQ_DB5500_SDMMC1 (IRQ_SHPI_START + 50)
55#define IRQ_DB5500_MSP1 (IRQ_SHPI_START + 52)
56#define IRQ_DB5500_KBD (IRQ_SHPI_START + 53)
57#define IRQ_DB5500_I2C2 (IRQ_SHPI_START + 55)
58#define IRQ_DB5500_B2R2 (IRQ_SHPI_START + 56)
59#define IRQ_DB5500_CRYP0 (IRQ_SHPI_START + 57)
60#define IRQ_DB5500_SDMMC3 (IRQ_SHPI_START + 59)
61#define IRQ_DB5500_SDMMC0 (IRQ_SHPI_START + 60)
62#define IRQ_DB5500_HSEM (IRQ_SHPI_START + 61)
63#define IRQ_DB5500_SBAG (IRQ_SHPI_START + 63)
64#define IRQ_DB5500_MODEM (IRQ_SHPI_START + 65)
65#define IRQ_DB5500_SPI1 (IRQ_SHPI_START + 96)
66#define IRQ_DB5500_MSP2 (IRQ_SHPI_START + 98)
67#define IRQ_DB5500_SRPTIMER (IRQ_SHPI_START + 101)
68#define IRQ_DB5500_CTI0 (IRQ_SHPI_START + 108)
69#define IRQ_DB5500_CTI1 (IRQ_SHPI_START + 109)
70#define IRQ_DB5500_ICN_ERR (IRQ_SHPI_START + 110)
71#define IRQ_DB5500_MALI_PPMMU (IRQ_SHPI_START + 112)
72#define IRQ_DB5500_MALI_PP (IRQ_SHPI_START + 113)
73#define IRQ_DB5500_MALI_GPMMU (IRQ_SHPI_START + 114)
74#define IRQ_DB5500_MALI_GP (IRQ_SHPI_START + 115)
75#define IRQ_DB5500_MALI (IRQ_SHPI_START + 116)
76#define IRQ_DB5500_PRCMU_SEM (IRQ_SHPI_START + 118)
77#define IRQ_DB5500_GPIO0 (IRQ_SHPI_START + 119)
78#define IRQ_DB5500_GPIO1 (IRQ_SHPI_START + 120)
79#define IRQ_DB5500_GPIO2 (IRQ_SHPI_START + 121)
80#define IRQ_DB5500_GPIO3 (IRQ_SHPI_START + 122)
81#define IRQ_DB5500_GPIO4 (IRQ_SHPI_START + 123)
82#define IRQ_DB5500_GPIO5 (IRQ_SHPI_START + 124)
83#define IRQ_DB5500_GPIO6 (IRQ_SHPI_START + 125)
84#define IRQ_DB5500_GPIO7 (IRQ_SHPI_START + 126)
85
86#ifdef CONFIG_UX500_SOC_DB5500
87
88/*
89 * After the GPIO ones we reserve a range of IRQ:s in which virtual
90 * IRQ:s representing modem IRQ:s can be allocated
91 */
92#define IRQ_MODEM_EVENTS_BASE IRQ_SOC_START
93#define IRQ_MODEM_EVENTS_NBR 72
94#define IRQ_MODEM_EVENTS_END (IRQ_MODEM_EVENTS_BASE + IRQ_MODEM_EVENTS_NBR)
95
96/* List of virtual IRQ:s that are allocated from the range above */
97#define MBOX_PAIR0_VIRT_IRQ (IRQ_MODEM_EVENTS_BASE + 43)
98#define MBOX_PAIR1_VIRT_IRQ (IRQ_MODEM_EVENTS_BASE + 45)
99#define MBOX_PAIR2_VIRT_IRQ (IRQ_MODEM_EVENTS_BASE + 41)
100
101/*
102 * We may have several SoCs, but only one will run at a
103 * time, so the one with most IRQs will bump this ahead,
104 * but the IRQ_SOC_START remains the same for either SoC.
105 */
106#if IRQ_SOC_END < IRQ_MODEM_EVENTS_END
107#undef IRQ_SOC_END
108#define IRQ_SOC_END IRQ_MODEM_EVENTS_END
109#endif
110
111#endif /* CONFIG_UX500_SOC_DB5500 */
112
113#endif
diff --git a/arch/arm/mach-ux500/include/mach/irqs.h b/arch/arm/mach-ux500/include/mach/irqs.h
index c23a6b5f0c4e..d06dcf6208fa 100644
--- a/arch/arm/mach-ux500/include/mach/irqs.h
+++ b/arch/arm/mach-ux500/include/mach/irqs.h
@@ -36,7 +36,6 @@
36/* This will be overridden by SoC-specific irq headers */ 36/* This will be overridden by SoC-specific irq headers */
37#define IRQ_SOC_END IRQ_SOC_START 37#define IRQ_SOC_END IRQ_SOC_START
38 38
39#include <mach/irqs-db5500.h>
40#include <mach/irqs-db8500.h> 39#include <mach/irqs-db8500.h>
41 40
42#define IRQ_BOARD_START IRQ_SOC_END 41#define IRQ_BOARD_START IRQ_SOC_END
@@ -47,10 +46,6 @@
47#include <mach/irqs-board-mop500.h> 46#include <mach/irqs-board-mop500.h>
48#endif 47#endif
49 48
50#ifdef CONFIG_MACH_U5500
51#include <mach/irqs-board-u5500.h>
52#endif
53
54#define NR_IRQS IRQ_BOARD_END 49#define NR_IRQS IRQ_BOARD_END
55 50
56#endif /* ASM_ARCH_IRQS_H */ 51#endif /* ASM_ARCH_IRQS_H */
diff --git a/arch/arm/mach-ux500/include/mach/mbox-db5500.h b/arch/arm/mach-ux500/include/mach/mbox-db5500.h
deleted file mode 100644
index 7f9da4d2fbda..000000000000
--- a/arch/arm/mach-ux500/include/mach/mbox-db5500.h
+++ /dev/null
@@ -1,88 +0,0 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 * Author: Stefan Nilsson <stefan.xk.nilsson@stericsson.com> for ST-Ericsson.
4 * Author: Martin Persson <martin.persson@stericsson.com> for ST-Ericsson.
5 * License terms: GNU General Public License (GPL), version 2.
6 */
7
8#ifndef __INC_STE_MBOX_H
9#define __INC_STE_MBOX_H
10
11#define MBOX_BUF_SIZE 16
12#define MBOX_NAME_SIZE 8
13
14/**
15 * mbox_recv_cb_t - Definition of the mailbox callback.
16 * @mbox_msg: The mailbox message.
17 * @priv: The clients private data as specified in the call to mbox_setup.
18 *
19 * This function will be called upon reception of new mailbox messages.
20 */
21typedef void mbox_recv_cb_t (u32 mbox_msg, void *priv);
22
23/**
24 * struct mbox - Mailbox instance struct
25 * @list: Linked list head.
26 * @pdev: Pointer to device struct.
27 * @cb: Callback function. Will be called
28 * when new data is received.
29 * @client_data: Clients private data. Will be sent back
30 * in the callback function.
31 * @virtbase_peer: Virtual address for outgoing mailbox.
32 * @virtbase_local: Virtual address for incoming mailbox.
33 * @buffer: Then internal queue for outgoing messages.
34 * @name: Name of this mailbox.
35 * @buffer_available: Completion variable to achieve "blocking send".
36 * This variable will be signaled when there is
37 * internal buffer space available.
38 * @client_blocked: To keep track if any client is currently
39 * blocked.
40 * @lock: Spinlock to protect this mailbox instance.
41 * @write_index: Index in internal buffer to write to.
42 * @read_index: Index in internal buffer to read from.
43 * @allocated: Indicates whether this particular mailbox
44 * id has been allocated by someone.
45 */
46struct mbox {
47 struct list_head list;
48 struct platform_device *pdev;
49 mbox_recv_cb_t *cb;
50 void *client_data;
51 void __iomem *virtbase_peer;
52 void __iomem *virtbase_local;
53 u32 buffer[MBOX_BUF_SIZE];
54 char name[MBOX_NAME_SIZE];
55 struct completion buffer_available;
56 u8 client_blocked;
57 spinlock_t lock;
58 u8 write_index;
59 u8 read_index;
60 bool allocated;
61};
62
63/**
64 * mbox_setup - Set up a mailbox and return its instance.
65 * @mbox_id: The ID number of the mailbox. 0 or 1 for modem CPU,
66 * 2 for modem DSP.
67 * @mbox_cb: Pointer to the callback function to be called when a new message
68 * is received.
69 * @priv: Client user data which will be returned in the callback.
70 *
71 * Returns a mailbox instance to be specified in subsequent calls to mbox_send.
72 */
73struct mbox *mbox_setup(u8 mbox_id, mbox_recv_cb_t *mbox_cb, void *priv);
74
75/**
76 * mbox_send - Send a mailbox message.
77 * @mbox: Mailbox instance (returned by mbox_setup)
78 * @mbox_msg: The mailbox message to send.
79 * @block: Specifies whether this call will block until send is possible,
80 * or return an error if the mailbox buffer is full.
81 *
82 * Returns 0 on success or a negative error code on error. -ENOMEM indicates
83 * that the internal buffer is full and you have to try again later (or
84 * specify "block" in order to block until send is possible).
85 */
86int mbox_send(struct mbox *mbox, u32 mbox_msg, bool block);
87
88#endif /*INC_STE_MBOX_H*/
diff --git a/arch/arm/mach-ux500/include/mach/setup.h b/arch/arm/mach-ux500/include/mach/setup.h
index 3dc00ffa7bfa..4e369f1645ec 100644
--- a/arch/arm/mach-ux500/include/mach/setup.h
+++ b/arch/arm/mach-ux500/include/mach/setup.h
@@ -15,18 +15,12 @@
15#include <linux/init.h> 15#include <linux/init.h>
16 16
17void __init ux500_map_io(void); 17void __init ux500_map_io(void);
18extern void __init u5500_map_io(void);
19extern void __init u8500_map_io(void); 18extern void __init u8500_map_io(void);
20 19
21extern struct device * __init u5500_init_devices(void);
22extern struct device * __init u8500_init_devices(void); 20extern struct device * __init u8500_init_devices(void);
23 21
24extern void __init ux500_init_irq(void); 22extern void __init ux500_init_irq(void);
25 23
26extern void __init u5500_sdi_init(struct device *parent);
27
28extern void __init db5500_dma_init(struct device *parent);
29
30extern struct device *ux500_soc_device_init(const char *soc_id); 24extern struct device *ux500_soc_device_init(const char *soc_id);
31 25
32struct amba_device; 26struct amba_device;
diff --git a/arch/arm/mach-ux500/include/mach/uncompress.h b/arch/arm/mach-ux500/include/mach/uncompress.h
index 6fb3c4b0105d..34775baadaea 100644
--- a/arch/arm/mach-ux500/include/mach/uncompress.h
+++ b/arch/arm/mach-ux500/include/mach/uncompress.h
@@ -50,11 +50,8 @@ static void flush(void)
50 50
51static inline void arch_decomp_setup(void) 51static inline void arch_decomp_setup(void)
52{ 52{
53 /* Check in run time if we run on an U8500 or U5500 */ 53 /* Use machine_is_foo() macro if you need to switch base someday */
54 if (machine_is_u5500()) 54 ux500_uart_base = U8500_UART2_BASE;
55 ux500_uart_base = U5500_UART0_BASE;
56 else
57 ux500_uart_base = U8500_UART2_BASE;
58} 55}
59 56
60#define arch_decomp_wdog() /* nothing to do here */ 57#define arch_decomp_wdog() /* nothing to do here */
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-28 18:04:13 -0500