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-rw-r--r--arch/arm/mach-ux500/include/mach/db5500-regs.h4
-rw-r--r--arch/arm/mach-ux500/include/mach/db8500-regs.h3
-rw-r--r--arch/arm/mach-ux500/include/mach/devices.h17
-rw-r--r--arch/arm/mach-ux500/include/mach/entry-macro.S68
-rw-r--r--arch/arm/mach-ux500/include/mach/gpio.h38
-rw-r--r--arch/arm/mach-ux500/include/mach/hardware.h2
-rw-r--r--arch/arm/mach-ux500/include/mach/irqs-board-mop500.h28
-rw-r--r--arch/arm/mach-ux500/include/mach/irqs.h44
-rw-r--r--arch/arm/mach-ux500/include/mach/mbox-db5500.h (renamed from arch/arm/mach-ux500/include/mach/mbox.h)0
-rw-r--r--arch/arm/mach-ux500/include/mach/prcmu-defs.h30
-rw-r--r--arch/arm/mach-ux500/include/mach/prcmu-regs.h15
-rw-r--r--arch/arm/mach-ux500/include/mach/prcmu.h15
-rw-r--r--arch/arm/mach-ux500/include/mach/setup.h7
-rw-r--r--arch/arm/mach-ux500/include/mach/smp.h5
-rw-r--r--arch/arm/mach-ux500/include/mach/uncompress.h23
15 files changed, 112 insertions, 187 deletions
diff --git a/arch/arm/mach-ux500/include/mach/db5500-regs.h b/arch/arm/mach-ux500/include/mach/db5500-regs.h
index 3eafc0e24ba5..bd88c1e74060 100644
--- a/arch/arm/mach-ux500/include/mach/db5500-regs.h
+++ b/arch/arm/mach-ux500/include/mach/db5500-regs.h
@@ -114,4 +114,8 @@
114#define U5500_MBOX2_LOCAL_START (U5500_MBOX_BASE + 0x20) 114#define U5500_MBOX2_LOCAL_START (U5500_MBOX_BASE + 0x20)
115#define U5500_MBOX2_LOCAL_END (U5500_MBOX_BASE + 0x3F) 115#define U5500_MBOX2_LOCAL_END (U5500_MBOX_BASE + 0x3F)
116 116
117#define U5500_ESRAM_BASE 0x40000000
118#define U5500_ESRAM_DMA_LCPA_OFFSET 0x10000
119#define U5500_DMA_LCPA_BASE (U5500_ESRAM_BASE + U5500_ESRAM_DMA_LCPA_OFFSET)
120
117#endif 121#endif
diff --git a/arch/arm/mach-ux500/include/mach/db8500-regs.h b/arch/arm/mach-ux500/include/mach/db8500-regs.h
index f07d0986409d..0fefb34c11e4 100644
--- a/arch/arm/mach-ux500/include/mach/db8500-regs.h
+++ b/arch/arm/mach-ux500/include/mach/db8500-regs.h
@@ -92,7 +92,8 @@
92#define U8500_SCR_BASE (U8500_PER4_BASE + 0x05000) 92#define U8500_SCR_BASE (U8500_PER4_BASE + 0x05000)
93#define U8500_DMC_BASE (U8500_PER4_BASE + 0x06000) 93#define U8500_DMC_BASE (U8500_PER4_BASE + 0x06000)
94#define U8500_PRCMU_BASE (U8500_PER4_BASE + 0x07000) 94#define U8500_PRCMU_BASE (U8500_PER4_BASE + 0x07000)
95#define U8500_PRCMU_TCDM_BASE (U8500_PER4_BASE + 0x0f000) 95#define U8500_PRCMU_TCDM_BASE_V1 (U8500_PER4_BASE + 0x0f000)
96#define U8500_PRCMU_TCDM_BASE (U8500_PER4_BASE + 0x68000)
96 97
97/* per3 base addresses */ 98/* per3 base addresses */
98#define U8500_FSMC_BASE (U8500_PER3_BASE + 0x0000) 99#define U8500_FSMC_BASE (U8500_PER3_BASE + 0x0000)
diff --git a/arch/arm/mach-ux500/include/mach/devices.h b/arch/arm/mach-ux500/include/mach/devices.h
index b91a4d1211a2..020b6369a30a 100644
--- a/arch/arm/mach-ux500/include/mach/devices.h
+++ b/arch/arm/mach-ux500/include/mach/devices.h
@@ -14,27 +14,10 @@ extern struct platform_device u5500_gpio_devs[];
14extern struct platform_device u8500_gpio_devs[]; 14extern struct platform_device u8500_gpio_devs[];
15 15
16extern struct amba_device ux500_pl031_device; 16extern struct amba_device ux500_pl031_device;
17extern struct amba_device u8500_ssp0_device;
18extern struct amba_device ux500_uart0_device;
19extern struct amba_device ux500_uart1_device;
20extern struct amba_device ux500_uart2_device;
21 17
22extern struct platform_device ux500_i2c1_device;
23extern struct platform_device ux500_i2c2_device;
24extern struct platform_device ux500_i2c3_device;
25
26extern struct platform_device u8500_i2c0_device;
27extern struct platform_device u8500_i2c4_device;
28extern struct platform_device u8500_dma40_device; 18extern struct platform_device u8500_dma40_device;
29extern struct platform_device ux500_ske_keypad_device; 19extern struct platform_device ux500_ske_keypad_device;
30 20
31extern struct amba_device u8500_sdi0_device;
32extern struct amba_device u8500_sdi1_device;
33extern struct amba_device u8500_sdi2_device;
34extern struct amba_device u8500_sdi3_device;
35extern struct amba_device u8500_sdi4_device;
36extern struct amba_device u8500_sdi5_device;
37
38void dma40_u8500ed_fixup(void); 21void dma40_u8500ed_fixup(void);
39 22
40#endif 23#endif
diff --git a/arch/arm/mach-ux500/include/mach/entry-macro.S b/arch/arm/mach-ux500/include/mach/entry-macro.S
index 60ea88db8283..a37f585a3ecb 100644
--- a/arch/arm/mach-ux500/include/mach/entry-macro.S
+++ b/arch/arm/mach-ux500/include/mach/entry-macro.S
@@ -11,7 +11,8 @@
11 * warranty of any kind, whether express or implied. 11 * warranty of any kind, whether express or implied.
12 */ 12 */
13#include <mach/hardware.h> 13#include <mach/hardware.h>
14#include <asm/hardware/gic.h> 14#define HAVE_GET_IRQNR_PREAMBLE
15#include <asm/hardware/entry-macro-gic.S>
15 16
16 .macro disable_fiq 17 .macro disable_fiq
17 .endm 18 .endm
@@ -22,68 +23,3 @@
22 23
23 .macro arch_ret_to_user, tmp1, tmp2 24 .macro arch_ret_to_user, tmp1, tmp2
24 .endm 25 .endm
25
26 /*
27 * The interrupt numbering scheme is defined in the
28 * interrupt controller spec. To wit:
29 *
30 * Interrupts 0-15 are IPI
31 * 16-28 are reserved
32 * 29-31 are local. We allow 30 to be used for the watchdog.
33 * 32-1020 are global
34 * 1021-1022 are reserved
35 * 1023 is "spurious" (no interrupt)
36 *
37 * For now, we ignore all local interrupts so only return an
38 * interrupt if it's between 30 and 1020. The test_for_ipi
39 * routine below will pick up on IPIs.
40 *
41 * A simple read from the controller will tell us the number
42 * of the highest priority enabled interrupt. We then just
43 * need to check whether it is in the valid range for an
44 * IRQ (30-1020 inclusive).
45 */
46
47 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
48
49 /* bits 12-10 = src CPU, 9-0 = int # */
50 ldr \irqstat, [\base, #GIC_CPU_INTACK]
51
52 ldr \tmp, =1021
53
54 bic \irqnr, \irqstat, #0x1c00
55
56 cmp \irqnr, #29
57 cmpcc \irqnr, \irqnr
58 cmpne \irqnr, \tmp
59 cmpcs \irqnr, \irqnr
60
61 .endm
62
63 /* We assume that irqstat (the raw value of the IRQ
64 * acknowledge register) is preserved from the macro above.
65 * If there is an IPI, we immediately signal end of
66 * interrupt on the controller, since this requires the
67 * original irqstat value which we won't easily be able
68 * to recreate later.
69 */
70
71 .macro test_for_ipi, irqnr, irqstat, base, tmp
72 bic \irqnr, \irqstat, #0x1c00
73 cmp \irqnr, #16
74 strcc \irqstat, [\base, #GIC_CPU_EOI]
75 cmpcs \irqnr, \irqnr
76 .endm
77
78 /* As above, this assumes that irqstat and base
79 * are preserved..
80 */
81
82 .macro test_for_ltirq, irqnr, irqstat, base, tmp
83 bic \irqnr, \irqstat, #0x1c00
84 mov \tmp, #0
85 cmp \irqnr, #29
86 moveq \tmp, #1
87 streq \irqstat, [\base, #GIC_CPU_EOI]
88 cmp \tmp, #0
89 .endm
diff --git a/arch/arm/mach-ux500/include/mach/gpio.h b/arch/arm/mach-ux500/include/mach/gpio.h
index d548a622e7d2..3c4cd31ad9f7 100644
--- a/arch/arm/mach-ux500/include/mach/gpio.h
+++ b/arch/arm/mach-ux500/include/mach/gpio.h
@@ -9,42 +9,4 @@
9 9
10#include <plat/gpio.h> 10#include <plat/gpio.h>
11 11
12#define __GPIO_RESOURCE(soc, block) \
13 { \
14 .start = soc##_GPIOBANK##block##_BASE, \
15 .end = soc##_GPIOBANK##block##_BASE + 127, \
16 .flags = IORESOURCE_MEM, \
17 }, \
18 { \
19 .start = IRQ_GPIO##block, \
20 .end = IRQ_GPIO##block, \
21 .flags = IORESOURCE_IRQ, \
22 }
23
24#define __GPIO_DEVICE(soc, block) \
25 { \
26 .name = "gpio", \
27 .id = block, \
28 .num_resources = 2, \
29 .resource = &soc##_gpio_resources[block * 2], \
30 .dev = { \
31 .platform_data = &soc##_gpio_data[block], \
32 }, \
33 }
34
35#define GPIO_DATA(_name, first) \
36 { \
37 .name = _name, \
38 .first_gpio = first, \
39 .first_irq = NOMADIK_GPIO_TO_IRQ(first), \
40 }
41
42#ifdef CONFIG_UX500_SOC_DB8500
43#define GPIO_RESOURCE(block) __GPIO_RESOURCE(U8500, block)
44#define GPIO_DEVICE(block) __GPIO_DEVICE(u8500, block)
45#elif defined(CONFIG_UX500_SOC_DB5500)
46#define GPIO_RESOURCE(block) __GPIO_RESOURCE(U5500, block)
47#define GPIO_DEVICE(block) __GPIO_DEVICE(u5500, block)
48#endif
49
50#endif /* __ASM_ARCH_GPIO_H */ 12#endif /* __ASM_ARCH_GPIO_H */
diff --git a/arch/arm/mach-ux500/include/mach/hardware.h b/arch/arm/mach-ux500/include/mach/hardware.h
index 32e883a8f2a2..6295cc581355 100644
--- a/arch/arm/mach-ux500/include/mach/hardware.h
+++ b/arch/arm/mach-ux500/include/mach/hardware.h
@@ -142,6 +142,8 @@ static inline bool cpu_is_u5500(void)
142#endif 142#endif
143} 143}
144 144
145#define ARRAY_AND_SIZE(x) (x), ARRAY_SIZE(x)
146
145#endif 147#endif
146 148
147#endif /* __MACH_HARDWARE_H */ 149#endif /* __MACH_HARDWARE_H */
diff --git a/arch/arm/mach-ux500/include/mach/irqs-board-mop500.h b/arch/arm/mach-ux500/include/mach/irqs-board-mop500.h
index cca4f705601e..7cdeb2af0ebb 100644
--- a/arch/arm/mach-ux500/include/mach/irqs-board-mop500.h
+++ b/arch/arm/mach-ux500/include/mach/irqs-board-mop500.h
@@ -8,12 +8,36 @@
8#ifndef __MACH_IRQS_BOARD_MOP500_H 8#ifndef __MACH_IRQS_BOARD_MOP500_H
9#define __MACH_IRQS_BOARD_MOP500_H 9#define __MACH_IRQS_BOARD_MOP500_H
10 10
11#define AB8500_NR_IRQS 104 11/* Number of AB8500 irqs is taken from header file */
12#include <linux/mfd/ab8500.h>
12 13
13#define MOP500_AB8500_IRQ_BASE IRQ_BOARD_START 14#define MOP500_AB8500_IRQ_BASE IRQ_BOARD_START
14#define MOP500_AB8500_IRQ_END (MOP500_AB8500_IRQ_BASE \ 15#define MOP500_AB8500_IRQ_END (MOP500_AB8500_IRQ_BASE \
15 + AB8500_NR_IRQS) 16 + AB8500_NR_IRQS)
16#define MOP500_IRQ_END MOP500_AB8500_IRQ_END 17
18/* TC35892 */
19#define TC35892_NR_INTERNAL_IRQS 8
20#define TC35892_INT_GPIO(x) (TC35892_NR_INTERNAL_IRQS + (x))
21#define TC35892_NR_GPIOS 24
22#define TC35892_NR_IRQS TC35892_INT_GPIO(TC35892_NR_GPIOS)
23
24#define MOP500_EGPIO_NR_IRQS TC35892_NR_IRQS
25
26#define MOP500_EGPIO_IRQ_BASE MOP500_AB8500_IRQ_END
27#define MOP500_EGPIO_IRQ_END (MOP500_EGPIO_IRQ_BASE \
28 + MOP500_EGPIO_NR_IRQS)
29/* STMPE1601 irqs */
30#define STMPE_NR_INTERNAL_IRQS 9
31#define STMPE_INT_GPIO(x) (STMPE_NR_INTERNAL_IRQS + (x))
32#define STMPE_NR_GPIOS 24
33#define STMPE_NR_IRQS STMPE_INT_GPIO(STMPE_NR_GPIOS)
34
35#define MOP500_STMPE1601_IRQBASE MOP500_EGPIO_IRQ_END
36#define MOP500_STMPE1601_IRQ(x) (MOP500_STMPE1601_IRQBASE + (x))
37
38#define MOP500_NR_IRQS MOP500_STMPE1601_IRQ(STMPE_NR_INTERNAL_IRQS)
39
40#define MOP500_IRQ_END MOP500_NR_IRQS
17 41
18#if MOP500_IRQ_END > IRQ_BOARD_END 42#if MOP500_IRQ_END > IRQ_BOARD_END
19#undef IRQ_BOARD_END 43#undef IRQ_BOARD_END
diff --git a/arch/arm/mach-ux500/include/mach/irqs.h b/arch/arm/mach-ux500/include/mach/irqs.h
index 693aa57de88d..880ae45bc235 100644
--- a/arch/arm/mach-ux500/include/mach/irqs.h
+++ b/arch/arm/mach-ux500/include/mach/irqs.h
@@ -21,50 +21,6 @@
21 21
22/* Interrupt numbers generic for shared peripheral */ 22/* Interrupt numbers generic for shared peripheral */
23#define IRQ_MTU0 (IRQ_SHPI_START + 4) 23#define IRQ_MTU0 (IRQ_SHPI_START + 4)
24#define IRQ_SPI2 (IRQ_SHPI_START + 6)
25#define IRQ_SPI0 (IRQ_SHPI_START + 8)
26#define IRQ_UART0 (IRQ_SHPI_START + 11)
27#define IRQ_I2C3 (IRQ_SHPI_START + 12)
28#define IRQ_SSP0 (IRQ_SHPI_START + 14)
29#define IRQ_MTU1 (IRQ_SHPI_START + 17)
30#define IRQ_RTC_RTT (IRQ_SHPI_START + 18)
31#define IRQ_UART1 (IRQ_SHPI_START + 19)
32#define IRQ_I2C0 (IRQ_SHPI_START + 21)
33#define IRQ_I2C1 (IRQ_SHPI_START + 22)
34#define IRQ_USBOTG (IRQ_SHPI_START + 23)
35#define IRQ_DMA (IRQ_SHPI_START + 25)
36#define IRQ_UART2 (IRQ_SHPI_START + 26)
37#define IRQ_HSIR_EXCEP (IRQ_SHPI_START + 29)
38#define IRQ_MSP0 (IRQ_SHPI_START + 31)
39#define IRQ_HSIR_CH0_OVRRUN (IRQ_SHPI_START + 32)
40#define IRQ_HSIR_CH1_OVRRUN (IRQ_SHPI_START + 33)
41#define IRQ_HSIR_CH2_OVRRUN (IRQ_SHPI_START + 34)
42#define IRQ_HSIR_CH3_OVRRUN (IRQ_SHPI_START + 35)
43#define IRQ_AB8500 (IRQ_SHPI_START + 40)
44#define IRQ_PRCMU (IRQ_SHPI_START + 47)
45#define IRQ_DISP (IRQ_SHPI_START + 48)
46#define IRQ_SiPI3 (IRQ_SHPI_START + 49)
47#define IRQ_I2C4 (IRQ_SHPI_START + 51)
48#define IRQ_SSP1 (IRQ_SHPI_START + 52)
49#define IRQ_I2C2 (IRQ_SHPI_START + 55)
50#define IRQ_SDMMC0 (IRQ_SHPI_START + 60)
51#define IRQ_MSP1 (IRQ_SHPI_START + 62)
52#define IRQ_SPI1 (IRQ_SHPI_START + 96)
53#define IRQ_MSP2 (IRQ_SHPI_START + 98)
54#define IRQ_SDMMC4 (IRQ_SHPI_START + 99)
55#define IRQ_HSIRD0 (IRQ_SHPI_START + 104)
56#define IRQ_HSIRD1 (IRQ_SHPI_START + 105)
57#define IRQ_HSITD0 (IRQ_SHPI_START + 106)
58#define IRQ_HSITD1 (IRQ_SHPI_START + 107)
59#define IRQ_GPIO0 (IRQ_SHPI_START + 119)
60#define IRQ_GPIO1 (IRQ_SHPI_START + 120)
61#define IRQ_GPIO2 (IRQ_SHPI_START + 121)
62#define IRQ_GPIO3 (IRQ_SHPI_START + 122)
63#define IRQ_GPIO4 (IRQ_SHPI_START + 123)
64#define IRQ_GPIO5 (IRQ_SHPI_START + 124)
65#define IRQ_GPIO6 (IRQ_SHPI_START + 125)
66#define IRQ_GPIO7 (IRQ_SHPI_START + 126)
67#define IRQ_GPIO8 (IRQ_SHPI_START + 127)
68 24
69/* There are 128 shared peripheral interrupts assigned to 25/* There are 128 shared peripheral interrupts assigned to
70 * INTID[160:32]. The first 32 interrupts are reserved. 26 * INTID[160:32]. The first 32 interrupts are reserved.
diff --git a/arch/arm/mach-ux500/include/mach/mbox.h b/arch/arm/mach-ux500/include/mach/mbox-db5500.h
index 7f9da4d2fbda..7f9da4d2fbda 100644
--- a/arch/arm/mach-ux500/include/mach/mbox.h
+++ b/arch/arm/mach-ux500/include/mach/mbox-db5500.h
diff --git a/arch/arm/mach-ux500/include/mach/prcmu-defs.h b/arch/arm/mach-ux500/include/mach/prcmu-defs.h
new file mode 100644
index 000000000000..848ba64b561f
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/prcmu-defs.h
@@ -0,0 +1,30 @@
1/*
2 * Copyright (C) STMicroelectronics 2009
3 * Copyright (C) ST-Ericsson SA 2010
4 *
5 * Author: Sundar Iyer <sundar.iyer@stericsson.com>
6 * Author: Martin Persson <martin.persson@stericsson.com>
7 *
8 * License Terms: GNU General Public License v2
9 *
10 * PRCM Unit definitions
11 */
12
13#ifndef __MACH_PRCMU_DEFS_H
14#define __MACH_PRCMU_DEFS_H
15
16enum prcmu_cpu_opp {
17 CPU_OPP_INIT = 0x00,
18 CPU_OPP_NO_CHANGE = 0x01,
19 CPU_OPP_100 = 0x02,
20 CPU_OPP_50 = 0x03,
21 CPU_OPP_MAX = 0x04,
22 CPU_OPP_EXT_CLK = 0x07
23};
24enum prcmu_ape_opp {
25 APE_OPP_NO_CHANGE = 0x00,
26 APE_OPP_100 = 0x02,
27 APE_OPP_50 = 0x03,
28};
29
30#endif /* __MACH_PRCMU_DEFS_H */
diff --git a/arch/arm/mach-ux500/include/mach/prcmu-regs.h b/arch/arm/mach-ux500/include/mach/prcmu-regs.h
index 8885f39a6421..455467e88791 100644
--- a/arch/arm/mach-ux500/include/mach/prcmu-regs.h
+++ b/arch/arm/mach-ux500/include/mach/prcmu-regs.h
@@ -1,10 +1,15 @@
1/* 1/*
2 * Copyright (c) 2009 ST-Ericsson SA 2 * Copyright (C) STMicroelectronics 2009
3 * Copyright (C) ST-Ericsson SA 2010
3 * 4 *
4 * This program is free software; you can redistribute it and/or modify 5 * Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com>
5 * it under the terms of the GNU General Public License version 2 6 * Author: Sundar Iyer <sundar.iyer@stericsson.com>
6 * as published by the Free Software Foundation. 7 *
8 * License Terms: GNU General Public License v2
9 *
10 * PRCM Unit registers
7 */ 11 */
12
8#ifndef __MACH_PRCMU_REGS_H 13#ifndef __MACH_PRCMU_REGS_H
9#define __MACH_PRCMU_REGS_H 14#define __MACH_PRCMU_REGS_H
10 15
@@ -88,4 +93,4 @@
88/* Miscellaneous unit registers */ 93/* Miscellaneous unit registers */
89#define PRCM_DSI_SW_RESET (_PRCMU_BASE + 0x324) 94#define PRCM_DSI_SW_RESET (_PRCMU_BASE + 0x324)
90 95
91#endif /* __MACH_PRCMU__REGS_H */ 96#endif /* __MACH_PRCMU_REGS_H */
diff --git a/arch/arm/mach-ux500/include/mach/prcmu.h b/arch/arm/mach-ux500/include/mach/prcmu.h
index 549843ff6dbe..c49e456162ef 100644
--- a/arch/arm/mach-ux500/include/mach/prcmu.h
+++ b/arch/arm/mach-ux500/include/mach/prcmu.h
@@ -2,14 +2,27 @@
2 * Copyright (C) STMicroelectronics 2009 2 * Copyright (C) STMicroelectronics 2009
3 * Copyright (C) ST-Ericsson SA 2010 3 * Copyright (C) ST-Ericsson SA 2010
4 * 4 *
5 * Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com>
6 * Author: Sundar Iyer <sundar.iyer@stericsson.com>
7 * Author: Mattias Nilsson <mattias.i.nilsson@stericsson.com>
8 *
5 * License Terms: GNU General Public License v2 9 * License Terms: GNU General Public License v2
6 * 10 *
7 * PRCMU f/w APIs 11 * PRCM Unit f/w API
8 */ 12 */
9#ifndef __MACH_PRCMU_H 13#ifndef __MACH_PRCMU_H
10#define __MACH_PRCMU_H 14#define __MACH_PRCMU_H
15#include <mach/prcmu-defs.h>
11 16
17void __init prcmu_early_init(void);
12int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size); 18int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size);
13int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size); 19int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size);
20int prcmu_set_ape_opp(enum prcmu_ape_opp opp);
21int prcmu_set_cpu_opp(enum prcmu_cpu_opp opp);
22int prcmu_set_ape_cpu_opps(enum prcmu_ape_opp ape_opp,
23 enum prcmu_cpu_opp cpu_opp);
24int prcmu_get_ape_opp(void);
25int prcmu_get_cpu_opp(void);
26bool prcmu_has_arm_maxopp(void);
14 27
15#endif /* __MACH_PRCMU_H */ 28#endif /* __MACH_PRCMU_H */
diff --git a/arch/arm/mach-ux500/include/mach/setup.h b/arch/arm/mach-ux500/include/mach/setup.h
index 54bbe648bf58..469877e0de90 100644
--- a/arch/arm/mach-ux500/include/mach/setup.h
+++ b/arch/arm/mach-ux500/include/mach/setup.h
@@ -18,14 +18,19 @@ extern void __init ux500_map_io(void);
18extern void __init u5500_map_io(void); 18extern void __init u5500_map_io(void);
19extern void __init u8500_map_io(void); 19extern void __init u8500_map_io(void);
20 20
21extern void __init ux500_init_devices(void);
22extern void __init u5500_init_devices(void); 21extern void __init u5500_init_devices(void);
23extern void __init u8500_init_devices(void); 22extern void __init u8500_init_devices(void);
24 23
25extern void __init ux500_init_irq(void); 24extern void __init ux500_init_irq(void);
25
26extern void __init u5500_sdi_init(void);
27
28extern void __init db5500_dma_init(void);
29
26/* We re-use nomadik_timer for this platform */ 30/* We re-use nomadik_timer for this platform */
27extern void nmdk_timer_init(void); 31extern void nmdk_timer_init(void);
28 32
33struct amba_device;
29extern void __init amba_add_devices(struct amba_device *devs[], int num); 34extern void __init amba_add_devices(struct amba_device *devs[], int num);
30 35
31struct sys_timer; 36struct sys_timer;
diff --git a/arch/arm/mach-ux500/include/mach/smp.h b/arch/arm/mach-ux500/include/mach/smp.h
index 197e8417375e..ca2b15b1b3b1 100644
--- a/arch/arm/mach-ux500/include/mach/smp.h
+++ b/arch/arm/mach-ux500/include/mach/smp.h
@@ -10,7 +10,6 @@
10#define ASMARM_ARCH_SMP_H 10#define ASMARM_ARCH_SMP_H
11 11
12#include <asm/hardware/gic.h> 12#include <asm/hardware/gic.h>
13#include <asm/smp_mpidr.h>
14 13
15/* This is required to wakeup the secondary core */ 14/* This is required to wakeup the secondary core */
16extern void u8500_secondary_startup(void); 15extern void u8500_secondary_startup(void);
@@ -18,8 +17,8 @@ extern void u8500_secondary_startup(void);
18/* 17/*
19 * We use IRQ1 as the IPI 18 * We use IRQ1 as the IPI
20 */ 19 */
21static inline void smp_cross_call(const struct cpumask *mask) 20static inline void smp_cross_call(const struct cpumask *mask, int ipi)
22{ 21{
23 gic_raise_softirq(mask, 1); 22 gic_raise_softirq(mask, ipi);
24} 23}
25#endif 24#endif
diff --git a/arch/arm/mach-ux500/include/mach/uncompress.h b/arch/arm/mach-ux500/include/mach/uncompress.h
index 0271ca0a83df..9a6614c6808e 100644
--- a/arch/arm/mach-ux500/include/mach/uncompress.h
+++ b/arch/arm/mach-ux500/include/mach/uncompress.h
@@ -19,38 +19,43 @@
19#define __ASM_ARCH_UNCOMPRESS_H 19#define __ASM_ARCH_UNCOMPRESS_H
20 20
21#include <asm/setup.h> 21#include <asm/setup.h>
22#include <asm/mach-types.h>
22#include <linux/io.h> 23#include <linux/io.h>
24#include <linux/amba/serial.h>
23#include <mach/hardware.h> 25#include <mach/hardware.h>
24 26
25#define U8500_UART_DR 0x80007000 27static u32 ux500_uart_base;
26#define U8500_UART_LCRH 0x8000702c
27#define U8500_UART_CR 0x80007030
28#define U8500_UART_FR 0x80007018
29 28
30static void putc(const char c) 29static void putc(const char c)
31{ 30{
32 /* Do nothing if the UART is not enabled. */ 31 /* Do nothing if the UART is not enabled. */
33 if (!(__raw_readb(U8500_UART_CR) & 0x1)) 32 if (!(__raw_readb(ux500_uart_base + UART011_CR) & 0x1))
34 return; 33 return;
35 34
36 if (c == '\n') 35 if (c == '\n')
37 putc('\r'); 36 putc('\r');
38 37
39 while (__raw_readb(U8500_UART_FR) & (1 << 5)) 38 while (__raw_readb(ux500_uart_base + UART01x_FR) & (1 << 5))
40 barrier(); 39 barrier();
41 __raw_writeb(c, U8500_UART_DR); 40 __raw_writeb(c, ux500_uart_base + UART01x_DR);
42} 41}
43 42
44static void flush(void) 43static void flush(void)
45{ 44{
46 if (!(__raw_readb(U8500_UART_CR) & 0x1)) 45 if (!(__raw_readb(ux500_uart_base + UART011_CR) & 0x1))
47 return; 46 return;
48 while (__raw_readb(U8500_UART_FR) & (1 << 3)) 47 while (__raw_readb(ux500_uart_base + UART01x_FR) & (1 << 3))
49 barrier(); 48 barrier();
50} 49}
51 50
52static inline void arch_decomp_setup(void) 51static inline void arch_decomp_setup(void)
53{ 52{
53 if (machine_is_u8500())
54 ux500_uart_base = U8500_UART2_BASE;
55 else if (machine_is_u5500())
56 ux500_uart_base = U5500_UART0_BASE;
57 else /* not much can be done to help here */
58 ux500_uart_base = U8500_UART2_BASE;
54} 59}
55 60
56#define arch_decomp_wdog() /* nothing to do here */ 61#define arch_decomp_wdog() /* nothing to do here */