diff options
Diffstat (limited to 'arch/arm/mach-tegra/common.c')
-rw-r--r-- | arch/arm/mach-tegra/common.c | 69 |
1 files changed, 19 insertions, 50 deletions
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c index 8f0ffe97ffee..5449a3f2977b 100644 --- a/arch/arm/mach-tegra/common.c +++ b/arch/arm/mach-tegra/common.c | |||
@@ -1,6 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * arch/arm/mach-tegra/common.c | 2 | * arch/arm/mach-tegra/common.c |
3 | * | 3 | * |
4 | * Copyright (c) 2013 NVIDIA Corporation. All rights reserved. | ||
4 | * Copyright (C) 2010 Google, Inc. | 5 | * Copyright (C) 2010 Google, Inc. |
5 | * | 6 | * |
6 | * Author: | 7 | * Author: |
@@ -22,13 +23,13 @@ | |||
22 | #include <linux/clk.h> | 23 | #include <linux/clk.h> |
23 | #include <linux/delay.h> | 24 | #include <linux/delay.h> |
24 | #include <linux/irqchip.h> | 25 | #include <linux/irqchip.h> |
26 | #include <linux/clk/tegra.h> | ||
25 | 27 | ||
26 | #include <asm/hardware/cache-l2x0.h> | 28 | #include <asm/hardware/cache-l2x0.h> |
27 | 29 | ||
28 | #include <mach/powergate.h> | 30 | #include <mach/powergate.h> |
29 | 31 | ||
30 | #include "board.h" | 32 | #include "board.h" |
31 | #include "clock.h" | ||
32 | #include "common.h" | 33 | #include "common.h" |
33 | #include "fuse.h" | 34 | #include "fuse.h" |
34 | #include "iomap.h" | 35 | #include "iomap.h" |
@@ -59,6 +60,7 @@ u32 tegra_uart_config[4] = { | |||
59 | #ifdef CONFIG_OF | 60 | #ifdef CONFIG_OF |
60 | void __init tegra_dt_init_irq(void) | 61 | void __init tegra_dt_init_irq(void) |
61 | { | 62 | { |
63 | tegra_clocks_init(); | ||
62 | tegra_init_irq(); | 64 | tegra_init_irq(); |
63 | irqchip_init(); | 65 | irqchip_init(); |
64 | } | 66 | } |
@@ -74,43 +76,6 @@ void tegra_assert_system_reset(char mode, const char *cmd) | |||
74 | writel_relaxed(reg, reset); | 76 | writel_relaxed(reg, reset); |
75 | } | 77 | } |
76 | 78 | ||
77 | #ifdef CONFIG_ARCH_TEGRA_2x_SOC | ||
78 | static __initdata struct tegra_clk_init_table tegra20_clk_init_table[] = { | ||
79 | /* name parent rate enabled */ | ||
80 | { "clk_m", NULL, 0, true }, | ||
81 | { "pll_p", "clk_m", 216000000, true }, | ||
82 | { "pll_p_out1", "pll_p", 28800000, true }, | ||
83 | { "pll_p_out2", "pll_p", 48000000, true }, | ||
84 | { "pll_p_out3", "pll_p", 72000000, true }, | ||
85 | { "pll_p_out4", "pll_p", 24000000, true }, | ||
86 | { "pll_c", "clk_m", 600000000, true }, | ||
87 | { "pll_c_out1", "pll_c", 120000000, true }, | ||
88 | { "sclk", "pll_c_out1", 120000000, true }, | ||
89 | { "hclk", "sclk", 120000000, true }, | ||
90 | { "pclk", "hclk", 60000000, true }, | ||
91 | { "csite", NULL, 0, true }, | ||
92 | { "emc", NULL, 0, true }, | ||
93 | { "cpu", NULL, 0, true }, | ||
94 | { NULL, NULL, 0, 0}, | ||
95 | }; | ||
96 | #endif | ||
97 | |||
98 | #ifdef CONFIG_ARCH_TEGRA_3x_SOC | ||
99 | static __initdata struct tegra_clk_init_table tegra30_clk_init_table[] = { | ||
100 | /* name parent rate enabled */ | ||
101 | { "clk_m", NULL, 0, true }, | ||
102 | { "pll_p", "pll_ref", 408000000, true }, | ||
103 | { "pll_p_out1", "pll_p", 9600000, true }, | ||
104 | { "pll_p_out4", "pll_p", 102000000, true }, | ||
105 | { "sclk", "pll_p_out4", 102000000, true }, | ||
106 | { "hclk", "sclk", 102000000, true }, | ||
107 | { "pclk", "hclk", 51000000, true }, | ||
108 | { "csite", NULL, 0, true }, | ||
109 | { NULL, NULL, 0, 0}, | ||
110 | }; | ||
111 | #endif | ||
112 | |||
113 | |||
114 | static void __init tegra_init_cache(void) | 79 | static void __init tegra_init_cache(void) |
115 | { | 80 | { |
116 | #ifdef CONFIG_CACHE_L2X0 | 81 | #ifdef CONFIG_CACHE_L2X0 |
@@ -129,35 +94,39 @@ static void __init tegra_init_cache(void) | |||
129 | 94 | ||
130 | } | 95 | } |
131 | 96 | ||
132 | #ifdef CONFIG_ARCH_TEGRA_2x_SOC | 97 | static void __init tegra_init_early(void) |
133 | void __init tegra20_init_early(void) | ||
134 | { | 98 | { |
135 | tegra_cpu_reset_handler_init(); | 99 | tegra_cpu_reset_handler_init(); |
136 | tegra_apb_io_init(); | 100 | tegra_apb_io_init(); |
137 | tegra_init_fuse(); | 101 | tegra_init_fuse(); |
138 | tegra2_init_clocks(); | ||
139 | tegra_clk_init_from_table(tegra20_clk_init_table); | ||
140 | tegra_init_cache(); | 102 | tegra_init_cache(); |
141 | tegra_pmc_init(); | 103 | tegra_pmc_init(); |
142 | tegra_powergate_init(); | 104 | tegra_powergate_init(); |
105 | } | ||
106 | |||
107 | #ifdef CONFIG_ARCH_TEGRA_2x_SOC | ||
108 | void __init tegra20_init_early(void) | ||
109 | { | ||
110 | tegra_init_early(); | ||
143 | tegra20_hotplug_init(); | 111 | tegra20_hotplug_init(); |
144 | } | 112 | } |
145 | #endif | 113 | #endif |
114 | |||
146 | #ifdef CONFIG_ARCH_TEGRA_3x_SOC | 115 | #ifdef CONFIG_ARCH_TEGRA_3x_SOC |
147 | void __init tegra30_init_early(void) | 116 | void __init tegra30_init_early(void) |
148 | { | 117 | { |
149 | tegra_cpu_reset_handler_init(); | 118 | tegra_init_early(); |
150 | tegra_apb_io_init(); | ||
151 | tegra_init_fuse(); | ||
152 | tegra30_init_clocks(); | ||
153 | tegra_clk_init_from_table(tegra30_clk_init_table); | ||
154 | tegra_init_cache(); | ||
155 | tegra_pmc_init(); | ||
156 | tegra_powergate_init(); | ||
157 | tegra30_hotplug_init(); | 119 | tegra30_hotplug_init(); |
158 | } | 120 | } |
159 | #endif | 121 | #endif |
160 | 122 | ||
123 | #ifdef CONFIG_ARCH_TEGRA_114_SOC | ||
124 | void __init tegra114_init_early(void) | ||
125 | { | ||
126 | tegra_init_early(); | ||
127 | } | ||
128 | #endif | ||
129 | |||
161 | void __init tegra_init_late(void) | 130 | void __init tegra_init_late(void) |
162 | { | 131 | { |
163 | tegra_powergate_debugfs_init(); | 132 | tegra_powergate_debugfs_init(); |