1 files changed, 98 insertions, 0 deletions

diff --git a/arch/arm/mach-spear3xx/clock.c b/arch/arm/mach-spear3xx/clock.c
index eeafe38eab25..cd6c11099083 100644
--- a/arch/arm/mach-spear3xx/clock.c
+++ b/arch/arm/mach-spear3xx/clock.c
@@ -19,6 +19,104 @@
 #include <asm/mach-types.h>
 #include <plat/clock.h>
 #include <mach/misc_regs.h>
+#include <mach/spear.h>
+
+#define PLL1_CTR                (MISC_BASE + 0x008)
+#define PLL1_FRQ                (MISC_BASE + 0x00C)
+#define PLL1_MOD                (MISC_BASE + 0x010)
+#define PLL2_CTR                (MISC_BASE + 0x014)
+/* PLL_CTR register masks */
+#define PLL_ENABLE              2
+#define PLL_MODE_SHIFT          4
+#define PLL_MODE_MASK           0x3
+#define PLL_MODE_NORMAL         0
+#define PLL_MODE_FRACTION       1
+#define PLL_MODE_DITH_DSB       2
+#define PLL_MODE_DITH_SSB       3
+
+#define PLL2_FRQ                (MISC_BASE + 0x018)
+/* PLL FRQ register masks */
+#define PLL_DIV_N_SHIFT         0
+#define PLL_DIV_N_MASK          0xFF
+#define PLL_DIV_P_SHIFT         8
+#define PLL_DIV_P_MASK          0x7
+#define PLL_NORM_FDBK_M_SHIFT   24
+#define PLL_NORM_FDBK_M_MASK    0xFF
+#define PLL_DITH_FDBK_M_SHIFT   16
+#define PLL_DITH_FDBK_M_MASK    0xFFFF
+
+#define PLL2_MOD                (MISC_BASE + 0x01C)
+#define PLL_CLK_CFG             (MISC_BASE + 0x020)
+#define CORE_CLK_CFG            (MISC_BASE + 0x024)
+/* CORE CLK CFG register masks */
+#define PLL_HCLK_RATIO_SHIFT    10
+#define PLL_HCLK_RATIO_MASK     0x3
+#define HCLK_PCLK_RATIO_SHIFT   8
+#define HCLK_PCLK_RATIO_MASK    0x3
+
+#define PERIP_CLK_CFG           (MISC_BASE + 0x028)
+/* PERIP_CLK_CFG register masks */
+#define UART_CLK_SHIFT          4
+#define UART_CLK_MASK           0x1
+#define FIRDA_CLK_SHIFT         5
+#define FIRDA_CLK_MASK          0x3
+#define GPT0_CLK_SHIFT          8
+#define GPT1_CLK_SHIFT          11
+#define GPT2_CLK_SHIFT          12
+#define GPT_CLK_MASK            0x1
+#define AUX_CLK_PLL3_VAL        0
+#define AUX_CLK_PLL1_VAL        1
+
+#define PERIP1_CLK_ENB          (MISC_BASE + 0x02C)
+/* PERIP1_CLK_ENB register masks */
+#define UART_CLK_ENB            3
+#define SSP_CLK_ENB             5
+#define I2C_CLK_ENB             7
+#define JPEG_CLK_ENB            8
+#define FIRDA_CLK_ENB           10
+#define GPT1_CLK_ENB            11
+#define GPT2_CLK_ENB            12
+#define ADC_CLK_ENB             15
+#define RTC_CLK_ENB             17
+#define GPIO_CLK_ENB            18
+#define DMA_CLK_ENB             19
+#define SMI_CLK_ENB             21
+#define GMAC_CLK_ENB            23
+#define USBD_CLK_ENB            24
+#define USBH_CLK_ENB            25
+#define C3_CLK_ENB              31
+
+#define RAS_CLK_ENB             (MISC_BASE + 0x034)
+
+#define PRSC1_CLK_CFG           (MISC_BASE + 0x044)
+#define PRSC2_CLK_CFG           (MISC_BASE + 0x048)
+#define PRSC3_CLK_CFG           (MISC_BASE + 0x04C)
+/* gpt synthesizer register masks */
+#define GPT_MSCALE_SHIFT        0
+#define GPT_MSCALE_MASK         0xFFF
+#define GPT_NSCALE_SHIFT        12
+#define GPT_NSCALE_MASK         0xF
+
+#define AMEM_CLK_CFG            (MISC_BASE + 0x050)
+#define EXPI_CLK_CFG            (MISC_BASE + 0x054)
+#define CLCD_CLK_SYNT           (MISC_BASE + 0x05C)
+#define FIRDA_CLK_SYNT          (MISC_BASE + 0x060)
+#define UART_CLK_SYNT           (MISC_BASE + 0x064)
+#define GMAC_CLK_SYNT           (MISC_BASE + 0x068)
+#define RAS1_CLK_SYNT           (MISC_BASE + 0x06C)
+#define RAS2_CLK_SYNT           (MISC_BASE + 0x070)
+#define RAS3_CLK_SYNT           (MISC_BASE + 0x074)
+#define RAS4_CLK_SYNT           (MISC_BASE + 0x078)
+/* aux clk synthesiser register masks for irda to ras4 */
+#define AUX_SYNT_ENB            31
+#define AUX_EQ_SEL_SHIFT        30
+#define AUX_EQ_SEL_MASK         1
+#define AUX_EQ1_SEL             0
+#define AUX_EQ2_SEL             1
+#define AUX_XSCALE_SHIFT        16
+#define AUX_XSCALE_MASK         0xFFF
+#define AUX_YSCALE_SHIFT        0
+#define AUX_YSCALE_MASK         0xFFF
 
 /* root clks */
 /* 32 KHz oscillator clock */