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-rw-r--r--arch/arm/mach-shmobile/pfc-sh73a0.c193
1 files changed, 80 insertions, 113 deletions
diff --git a/arch/arm/mach-shmobile/pfc-sh73a0.c b/arch/arm/mach-shmobile/pfc-sh73a0.c
index 5abe02fbd6b9..e05634ce2e0d 100644
--- a/arch/arm/mach-shmobile/pfc-sh73a0.c
+++ b/arch/arm/mach-shmobile/pfc-sh73a0.c
@@ -24,83 +24,71 @@
24#include <mach/sh73a0.h> 24#include <mach/sh73a0.h>
25#include <mach/irqs.h> 25#include <mach/irqs.h>
26 26
27#define _1(fn, pfx, sfx) fn(pfx, sfx) 27#define CPU_ALL_PORT(fn, pfx, sfx) \
28 28 PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \
29#define _10(fn, pfx, sfx) \ 29 PORT_10(fn, pfx##2, sfx), PORT_10(fn, pfx##3, sfx), \
30 _1(fn, pfx##0, sfx), _1(fn, pfx##1, sfx), \ 30 PORT_10(fn, pfx##4, sfx), PORT_10(fn, pfx##5, sfx), \
31 _1(fn, pfx##2, sfx), _1(fn, pfx##3, sfx), \ 31 PORT_10(fn, pfx##6, sfx), PORT_10(fn, pfx##7, sfx), \
32 _1(fn, pfx##4, sfx), _1(fn, pfx##5, sfx), \ 32 PORT_10(fn, pfx##8, sfx), PORT_10(fn, pfx##9, sfx), \
33 _1(fn, pfx##6, sfx), _1(fn, pfx##7, sfx), \ 33 PORT_10(fn, pfx##10, sfx), \
34 _1(fn, pfx##8, sfx), _1(fn, pfx##9, sfx) 34 PORT_1(fn, pfx##110, sfx), PORT_1(fn, pfx##111, sfx), \
35 35 PORT_1(fn, pfx##112, sfx), PORT_1(fn, pfx##113, sfx), \
36#define _310(fn, pfx, sfx) \ 36 PORT_1(fn, pfx##114, sfx), PORT_1(fn, pfx##115, sfx), \
37 _10(fn, pfx, sfx), _10(fn, pfx##1, sfx), \ 37 PORT_1(fn, pfx##116, sfx), PORT_1(fn, pfx##117, sfx), \
38 _10(fn, pfx##2, sfx), _10(fn, pfx##3, sfx), \ 38 PORT_1(fn, pfx##118, sfx), \
39 _10(fn, pfx##4, sfx), _10(fn, pfx##5, sfx), \ 39 PORT_1(fn, pfx##128, sfx), PORT_1(fn, pfx##129, sfx), \
40 _10(fn, pfx##6, sfx), _10(fn, pfx##7, sfx), \ 40 PORT_10(fn, pfx##13, sfx), PORT_10(fn, pfx##14, sfx), \
41 _10(fn, pfx##8, sfx), _10(fn, pfx##9, sfx), \ 41 PORT_10(fn, pfx##15, sfx), \
42 _10(fn, pfx##10, sfx), \ 42 PORT_1(fn, pfx##160, sfx), PORT_1(fn, pfx##161, sfx), \
43 _1(fn, pfx##110, sfx), _1(fn, pfx##111, sfx), \ 43 PORT_1(fn, pfx##162, sfx), PORT_1(fn, pfx##163, sfx), \
44 _1(fn, pfx##112, sfx), _1(fn, pfx##113, sfx), \ 44 PORT_1(fn, pfx##164, sfx), \
45 _1(fn, pfx##114, sfx), _1(fn, pfx##115, sfx), \ 45 PORT_1(fn, pfx##192, sfx), PORT_1(fn, pfx##193, sfx), \
46 _1(fn, pfx##116, sfx), _1(fn, pfx##117, sfx), \ 46 PORT_1(fn, pfx##194, sfx), PORT_1(fn, pfx##195, sfx), \
47 _1(fn, pfx##118, sfx), \ 47 PORT_1(fn, pfx##196, sfx), PORT_1(fn, pfx##197, sfx), \
48 _1(fn, pfx##128, sfx), _1(fn, pfx##129, sfx), \ 48 PORT_1(fn, pfx##198, sfx), PORT_1(fn, pfx##199, sfx), \
49 _10(fn, pfx##13, sfx), _10(fn, pfx##14, sfx), \ 49 PORT_10(fn, pfx##20, sfx), PORT_10(fn, pfx##21, sfx), \
50 _10(fn, pfx##15, sfx), \ 50 PORT_10(fn, pfx##22, sfx), PORT_10(fn, pfx##23, sfx), \
51 _1(fn, pfx##160, sfx), _1(fn, pfx##161, sfx), \ 51 PORT_10(fn, pfx##24, sfx), PORT_10(fn, pfx##25, sfx), \
52 _1(fn, pfx##162, sfx), _1(fn, pfx##163, sfx), \ 52 PORT_10(fn, pfx##26, sfx), PORT_10(fn, pfx##27, sfx), \
53 _1(fn, pfx##164, sfx), \ 53 PORT_1(fn, pfx##280, sfx), PORT_1(fn, pfx##281, sfx), \
54 _1(fn, pfx##192, sfx), _1(fn, pfx##193, sfx), \ 54 PORT_1(fn, pfx##282, sfx), \
55 _1(fn, pfx##194, sfx), _1(fn, pfx##195, sfx), \ 55 PORT_1(fn, pfx##288, sfx), PORT_1(fn, pfx##289, sfx), \
56 _1(fn, pfx##196, sfx), _1(fn, pfx##197, sfx), \ 56 PORT_10(fn, pfx##29, sfx), PORT_10(fn, pfx##30, sfx)
57 _1(fn, pfx##198, sfx), _1(fn, pfx##199, sfx), \
58 _10(fn, pfx##20, sfx), _10(fn, pfx##21, sfx), \
59 _10(fn, pfx##22, sfx), _10(fn, pfx##23, sfx), \
60 _10(fn, pfx##24, sfx), _10(fn, pfx##25, sfx), \
61 _10(fn, pfx##26, sfx), _10(fn, pfx##27, sfx), \
62 _1(fn, pfx##280, sfx), _1(fn, pfx##281, sfx), \
63 _1(fn, pfx##282, sfx), \
64 _1(fn, pfx##288, sfx), _1(fn, pfx##289, sfx), \
65 _10(fn, pfx##29, sfx), _10(fn, pfx##30, sfx)
66
67#define _PORT(pfx, sfx) pfx##_##sfx
68#define PORT_310(str) _310(_PORT, PORT, str)
69 57
70enum { 58enum {
71 PINMUX_RESERVED = 0, 59 PINMUX_RESERVED = 0,
72 60
73 PINMUX_DATA_BEGIN, 61 PINMUX_DATA_BEGIN,
74 PORT_310(DATA), /* PORT0_DATA -> PORT309_DATA */ 62 PORT_ALL(DATA), /* PORT0_DATA -> PORT309_DATA */
75 PINMUX_DATA_END, 63 PINMUX_DATA_END,
76 64
77 PINMUX_INPUT_BEGIN, 65 PINMUX_INPUT_BEGIN,
78 PORT_310(IN), /* PORT0_IN -> PORT309_IN */ 66 PORT_ALL(IN), /* PORT0_IN -> PORT309_IN */
79 PINMUX_INPUT_END, 67 PINMUX_INPUT_END,
80 68
81 PINMUX_INPUT_PULLUP_BEGIN, 69 PINMUX_INPUT_PULLUP_BEGIN,
82 PORT_310(IN_PU), /* PORT0_IN_PU -> PORT309_IN_PU */ 70 PORT_ALL(IN_PU), /* PORT0_IN_PU -> PORT309_IN_PU */
83 PINMUX_INPUT_PULLUP_END, 71 PINMUX_INPUT_PULLUP_END,
84 72
85 PINMUX_INPUT_PULLDOWN_BEGIN, 73 PINMUX_INPUT_PULLDOWN_BEGIN,
86 PORT_310(IN_PD), /* PORT0_IN_PD -> PORT309_IN_PD */ 74 PORT_ALL(IN_PD), /* PORT0_IN_PD -> PORT309_IN_PD */
87 PINMUX_INPUT_PULLDOWN_END, 75 PINMUX_INPUT_PULLDOWN_END,
88 76
89 PINMUX_OUTPUT_BEGIN, 77 PINMUX_OUTPUT_BEGIN,
90 PORT_310(OUT), /* PORT0_OUT -> PORT309_OUT */ 78 PORT_ALL(OUT), /* PORT0_OUT -> PORT309_OUT */
91 PINMUX_OUTPUT_END, 79 PINMUX_OUTPUT_END,
92 80
93 PINMUX_FUNCTION_BEGIN, 81 PINMUX_FUNCTION_BEGIN,
94 PORT_310(FN_IN), /* PORT0_FN_IN -> PORT309_FN_IN */ 82 PORT_ALL(FN_IN), /* PORT0_FN_IN -> PORT309_FN_IN */
95 PORT_310(FN_OUT), /* PORT0_FN_OUT -> PORT309_FN_OUT */ 83 PORT_ALL(FN_OUT), /* PORT0_FN_OUT -> PORT309_FN_OUT */
96 PORT_310(FN0), /* PORT0_FN0 -> PORT309_FN0 */ 84 PORT_ALL(FN0), /* PORT0_FN0 -> PORT309_FN0 */
97 PORT_310(FN1), /* PORT0_FN1 -> PORT309_FN1 */ 85 PORT_ALL(FN1), /* PORT0_FN1 -> PORT309_FN1 */
98 PORT_310(FN2), /* PORT0_FN2 -> PORT309_FN2 */ 86 PORT_ALL(FN2), /* PORT0_FN2 -> PORT309_FN2 */
99 PORT_310(FN3), /* PORT0_FN3 -> PORT309_FN3 */ 87 PORT_ALL(FN3), /* PORT0_FN3 -> PORT309_FN3 */
100 PORT_310(FN4), /* PORT0_FN4 -> PORT309_FN4 */ 88 PORT_ALL(FN4), /* PORT0_FN4 -> PORT309_FN4 */
101 PORT_310(FN5), /* PORT0_FN5 -> PORT309_FN5 */ 89 PORT_ALL(FN5), /* PORT0_FN5 -> PORT309_FN5 */
102 PORT_310(FN6), /* PORT0_FN6 -> PORT309_FN6 */ 90 PORT_ALL(FN6), /* PORT0_FN6 -> PORT309_FN6 */
103 PORT_310(FN7), /* PORT0_FN7 -> PORT309_FN7 */ 91 PORT_ALL(FN7), /* PORT0_FN7 -> PORT309_FN7 */
104 92
105 MSEL2CR_MSEL19_0, MSEL2CR_MSEL19_1, 93 MSEL2CR_MSEL19_0, MSEL2CR_MSEL19_1,
106 MSEL2CR_MSEL18_0, MSEL2CR_MSEL18_1, 94 MSEL2CR_MSEL18_0, MSEL2CR_MSEL18_1,
@@ -508,6 +496,14 @@ enum {
508 SDHICMD2_PU_MARK, 496 SDHICMD2_PU_MARK,
509 MMCCMD0_PU_MARK, 497 MMCCMD0_PU_MARK,
510 MMCCMD1_PU_MARK, 498 MMCCMD1_PU_MARK,
499 MMCD0_0_PU_MARK,
500 MMCD0_1_PU_MARK,
501 MMCD0_2_PU_MARK,
502 MMCD0_3_PU_MARK,
503 MMCD0_4_PU_MARK,
504 MMCD0_5_PU_MARK,
505 MMCD0_6_PU_MARK,
506 MMCD0_7_PU_MARK,
511 FSIBISLD_PU_MARK, 507 FSIBISLD_PU_MARK,
512 FSIACK_PU_MARK, 508 FSIACK_PU_MARK,
513 FSIAILR_PU_MARK, 509 FSIAILR_PU_MARK,
@@ -517,45 +513,6 @@ enum {
517 PINMUX_MARK_END, 513 PINMUX_MARK_END,
518}; 514};
519 515
520#define PORT_DATA_I(nr) \
521 PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_IN)
522
523#define PORT_DATA_I_PD(nr) \
524 PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
525 PORT##nr##_IN, PORT##nr##_IN_PD)
526
527#define PORT_DATA_I_PU(nr) \
528 PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
529 PORT##nr##_IN, PORT##nr##_IN_PU)
530
531#define PORT_DATA_I_PU_PD(nr) \
532 PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
533 PORT##nr##_IN, PORT##nr##_IN_PD, \
534 PORT##nr##_IN_PU)
535
536#define PORT_DATA_O(nr) \
537 PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
538 PORT##nr##_OUT)
539
540#define PORT_DATA_IO(nr) \
541 PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
542 PORT##nr##_OUT, PORT##nr##_IN)
543
544#define PORT_DATA_IO_PD(nr) \
545 PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
546 PORT##nr##_OUT, PORT##nr##_IN, \
547 PORT##nr##_IN_PD)
548
549#define PORT_DATA_IO_PU(nr) \
550 PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
551 PORT##nr##_OUT, PORT##nr##_IN, \
552 PORT##nr##_IN_PU)
553
554#define PORT_DATA_IO_PU_PD(nr) \
555 PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
556 PORT##nr##_OUT, PORT##nr##_IN, \
557 PORT##nr##_IN_PD, PORT##nr##_IN_PU)
558
559static pinmux_enum_t pinmux_data[] = { 516static pinmux_enum_t pinmux_data[] = {
560 /* specify valid pin states for each pin in GPIO mode */ 517 /* specify valid pin states for each pin in GPIO mode */
561 518
@@ -1561,6 +1518,24 @@ static pinmux_enum_t pinmux_data[] = {
1561 MSEL4CR_MSEL15_0), 1518 MSEL4CR_MSEL15_0),
1562 PINMUX_DATA(MMCCMD1_PU_MARK, PORT297_FN2, PORT297_IN_PU, 1519 PINMUX_DATA(MMCCMD1_PU_MARK, PORT297_FN2, PORT297_IN_PU,
1563 MSEL4CR_MSEL15_1), 1520 MSEL4CR_MSEL15_1),
1521
1522 PINMUX_DATA(MMCD0_0_PU_MARK,
1523 PORT271_FN1, PORT271_IN_PU, MSEL4CR_MSEL15_0),
1524 PINMUX_DATA(MMCD0_1_PU_MARK,
1525 PORT272_FN1, PORT272_IN_PU, MSEL4CR_MSEL15_0),
1526 PINMUX_DATA(MMCD0_2_PU_MARK,
1527 PORT273_FN1, PORT273_IN_PU, MSEL4CR_MSEL15_0),
1528 PINMUX_DATA(MMCD0_3_PU_MARK,
1529 PORT274_FN1, PORT274_IN_PU, MSEL4CR_MSEL15_0),
1530 PINMUX_DATA(MMCD0_4_PU_MARK,
1531 PORT275_FN1, PORT275_IN_PU, MSEL4CR_MSEL15_0),
1532 PINMUX_DATA(MMCD0_5_PU_MARK,
1533 PORT276_FN1, PORT276_IN_PU, MSEL4CR_MSEL15_0),
1534 PINMUX_DATA(MMCD0_6_PU_MARK,
1535 PORT277_FN1, PORT277_IN_PU, MSEL4CR_MSEL15_0),
1536 PINMUX_DATA(MMCD0_7_PU_MARK,
1537 PORT278_FN1, PORT278_IN_PU, MSEL4CR_MSEL15_0),
1538
1564 PINMUX_DATA(FSIBISLD_PU_MARK, PORT39_FN1, PORT39_IN_PU), 1539 PINMUX_DATA(FSIBISLD_PU_MARK, PORT39_FN1, PORT39_IN_PU),
1565 PINMUX_DATA(FSIACK_PU_MARK, PORT49_FN1, PORT49_IN_PU), 1540 PINMUX_DATA(FSIACK_PU_MARK, PORT49_FN1, PORT49_IN_PU),
1566 PINMUX_DATA(FSIAILR_PU_MARK, PORT50_FN5, PORT50_IN_PU), 1541 PINMUX_DATA(FSIAILR_PU_MARK, PORT50_FN5, PORT50_IN_PU),
@@ -1568,12 +1543,8 @@ static pinmux_enum_t pinmux_data[] = {
1568 PINMUX_DATA(FSIAISLD_PU_MARK, PORT55_FN1, PORT55_IN_PU), 1543 PINMUX_DATA(FSIAISLD_PU_MARK, PORT55_FN1, PORT55_IN_PU),
1569}; 1544};
1570 1545
1571#define _GPIO_PORT(pfx, sfx) PINMUX_GPIO(GPIO_PORT##pfx, PORT##pfx##_DATA)
1572#define GPIO_PORT_310() _310(_GPIO_PORT, , unused)
1573#define GPIO_FN(str) PINMUX_GPIO(GPIO_FN_##str, str##_MARK)
1574
1575static struct pinmux_gpio pinmux_gpios[] = { 1546static struct pinmux_gpio pinmux_gpios[] = {
1576 GPIO_PORT_310(), 1547 GPIO_PORT_ALL(),
1577 1548
1578 /* Table 25-1 (Functions 0-7) */ 1549 /* Table 25-1 (Functions 0-7) */
1579 GPIO_FN(VBUS_0), 1550 GPIO_FN(VBUS_0),
@@ -2236,24 +2207,20 @@ static struct pinmux_gpio pinmux_gpios[] = {
2236 GPIO_FN(SDHICMD2_PU), 2207 GPIO_FN(SDHICMD2_PU),
2237 GPIO_FN(MMCCMD0_PU), 2208 GPIO_FN(MMCCMD0_PU),
2238 GPIO_FN(MMCCMD1_PU), 2209 GPIO_FN(MMCCMD1_PU),
2210 GPIO_FN(MMCD0_0_PU),
2211 GPIO_FN(MMCD0_1_PU),
2212 GPIO_FN(MMCD0_2_PU),
2213 GPIO_FN(MMCD0_3_PU),
2214 GPIO_FN(MMCD0_4_PU),
2215 GPIO_FN(MMCD0_5_PU),
2216 GPIO_FN(MMCD0_6_PU),
2217 GPIO_FN(MMCD0_7_PU),
2239 GPIO_FN(FSIACK_PU), 2218 GPIO_FN(FSIACK_PU),
2240 GPIO_FN(FSIAILR_PU), 2219 GPIO_FN(FSIAILR_PU),
2241 GPIO_FN(FSIAIBT_PU), 2220 GPIO_FN(FSIAIBT_PU),
2242 GPIO_FN(FSIAISLD_PU), 2221 GPIO_FN(FSIAISLD_PU),
2243}; 2222};
2244 2223
2245#define PORTCR(nr, reg) \
2246 { PINMUX_CFG_REG("PORT" nr "CR", reg, 8, 4) { \
2247 0, \
2248 /*0001*/ PORT##nr##_OUT , \
2249 /*0010*/ PORT##nr##_IN , 0, 0, 0, 0, 0, 0, 0, \
2250 /*1010*/ PORT##nr##_IN_PD, 0, 0, 0, \
2251 /*1110*/ PORT##nr##_IN_PU, 0, \
2252 PORT##nr##_FN0, PORT##nr##_FN1, PORT##nr##_FN2, \
2253 PORT##nr##_FN3, PORT##nr##_FN4, PORT##nr##_FN5, \
2254 PORT##nr##_FN6, PORT##nr##_FN7, 0, 0, 0, 0, 0, 0, 0, 0 } \
2255 }
2256
2257static struct pinmux_cfg_reg pinmux_config_regs[] = { 2224static struct pinmux_cfg_reg pinmux_config_regs[] = {
2258 PORTCR(0, 0xe6050000), /* PORT0CR */ 2225 PORTCR(0, 0xe6050000), /* PORT0CR */
2259 PORTCR(1, 0xe6050001), /* PORT1CR */ 2226 PORTCR(1, 0xe6050001), /* PORT1CR */
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-07 12:56:51 -0500