diff options
Diffstat (limited to 'arch/arm/mach-s5p64x0/clock-s5p6440.c')
-rw-r--r-- | arch/arm/mach-s5p64x0/clock-s5p6440.c | 32 |
1 files changed, 23 insertions, 9 deletions
diff --git a/arch/arm/mach-s5p64x0/clock-s5p6440.c b/arch/arm/mach-s5p64x0/clock-s5p6440.c index eb4ffe331e1a..4c797ab3b3fd 100644 --- a/arch/arm/mach-s5p64x0/clock-s5p6440.c +++ b/arch/arm/mach-s5p64x0/clock-s5p6440.c | |||
@@ -422,15 +422,6 @@ static struct clksrc_clk clksrcs[] = { | |||
422 | .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 }, | 422 | .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 }, |
423 | }, { | 423 | }, { |
424 | .clk = { | 424 | .clk = { |
425 | .name = "uclk1", | ||
426 | .ctrlbit = (1 << 5), | ||
427 | .enable = s5p64x0_sclk_ctrl, | ||
428 | }, | ||
429 | .sources = &clkset_uart, | ||
430 | .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 13, .size = 1 }, | ||
431 | .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 16, .size = 4 }, | ||
432 | }, { | ||
433 | .clk = { | ||
434 | .name = "sclk_spi", | 425 | .name = "sclk_spi", |
435 | .devname = "s3c64xx-spi.0", | 426 | .devname = "s3c64xx-spi.0", |
436 | .ctrlbit = (1 << 20), | 427 | .ctrlbit = (1 << 20), |
@@ -488,6 +479,17 @@ static struct clksrc_clk clksrcs[] = { | |||
488 | }, | 479 | }, |
489 | }; | 480 | }; |
490 | 481 | ||
482 | static struct clksrc_clk clk_sclk_uclk = { | ||
483 | .clk = { | ||
484 | .name = "uclk1", | ||
485 | .ctrlbit = (1 << 5), | ||
486 | .enable = s5p64x0_sclk_ctrl, | ||
487 | }, | ||
488 | .sources = &clkset_uart, | ||
489 | .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 13, .size = 1 }, | ||
490 | .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 16, .size = 4 }, | ||
491 | }; | ||
492 | |||
491 | /* Clock initialization code */ | 493 | /* Clock initialization code */ |
492 | static struct clksrc_clk *sysclks[] = { | 494 | static struct clksrc_clk *sysclks[] = { |
493 | &clk_mout_apll, | 495 | &clk_mout_apll, |
@@ -506,6 +508,15 @@ static struct clk dummy_apb_pclk = { | |||
506 | .id = -1, | 508 | .id = -1, |
507 | }; | 509 | }; |
508 | 510 | ||
511 | static struct clksrc_clk *clksrc_cdev[] = { | ||
512 | &clk_sclk_uclk, | ||
513 | }; | ||
514 | |||
515 | static struct clk_lookup s5p6440_clk_lookup[] = { | ||
516 | CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_pclk_low.clk), | ||
517 | CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uclk.clk), | ||
518 | }; | ||
519 | |||
509 | void __init_or_cpufreq s5p6440_setup_clocks(void) | 520 | void __init_or_cpufreq s5p6440_setup_clocks(void) |
510 | { | 521 | { |
511 | struct clk *xtal_clk; | 522 | struct clk *xtal_clk; |
@@ -584,9 +595,12 @@ void __init s5p6440_register_clocks(void) | |||
584 | 595 | ||
585 | s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs)); | 596 | s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs)); |
586 | s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks)); | 597 | s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks)); |
598 | for (ptr = 0; ptr < ARRAY_SIZE(clksrc_cdev); ptr++) | ||
599 | s3c_register_clksrc(clksrc_cdev[ptr], 1); | ||
587 | 600 | ||
588 | s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); | 601 | s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); |
589 | s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); | 602 | s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); |
603 | clkdev_add_table(s5p6440_clk_lookup, ARRAY_SIZE(s5p6440_clk_lookup)); | ||
590 | 604 | ||
591 | s3c24xx_register_clock(&dummy_apb_pclk); | 605 | s3c24xx_register_clock(&dummy_apb_pclk); |
592 | 606 | ||