3 files changed, 29 insertions, 3 deletions

diff --git a/arch/arm/mach-s3c64xx/include/mach/irqs.h b/arch/arm/mach-s3c64xx/include/mach/irqs.h
index ddb63a1863ab..c026f67a80de 100644
--- a/arch/arm/mach-s3c64xx/include/mach/irqs.h
+++ b/arch/arm/mach-s3c64xx/include/mach/irqs.h
@@ -217,6 +217,7 @@
 /* Compatibility */
 
 #define IRQ_ONENAND     IRQ_ONENAND0
+#define IRQ_I2S0        IRQ_S3C6410_IIS
 
 #endif /* __ASM_MACH_S3C64XX_IRQS_H */
 
diff --git a/arch/arm/mach-s3c64xx/include/mach/pm-core.h b/arch/arm/mach-s3c64xx/include/mach/pm-core.h
index 1e9f20f0bb7b..38659bebe4b1 100644
--- a/arch/arm/mach-s3c64xx/include/mach/pm-core.h
+++ b/arch/arm/mach-s3c64xx/include/mach/pm-core.h
@@ -53,7 +53,7 @@ static inline void s3c_pm_arch_show_resume_irqs(void)
  * the IRQ wake controls depending on the CPU we are running on */
 
 #define s3c_irqwake_eintallow   ((1 << 28) - 1)
-#define s3c_irqwake_intallow    (0)
+#define s3c_irqwake_intallow    (~0)
 
 static inline void s3c_pm_arch_update_uart(void __iomem *regs,
                                            struct pm_uart_save *save)
@@ -96,3 +96,20 @@ static inline void s3c_pm_arch_update_uart(void __iomem *regs,
                 save->ucon = new_ucon;
         }
 }
+
+static inline void s3c_pm_restored_gpios(void)
+{
+        /* ensure sleep mode has been cleared from the system */
+
+        __raw_writel(0, S3C64XX_SLPEN);
+}
+
+static inline void s3c_pm_saved_gpios(void)
+{
+        /* turn on the sleep mode and keep it there, as it seems that during
+         * suspend the xCON registers get re-set and thus you can end up with
+         * problems between going to sleep and resuming.
+         */
+
+        __raw_writel(S3C64XX_SLPEN_USE_xSLP, S3C64XX_SLPEN);
+}
diff --git a/arch/arm/mach-s3c64xx/irq.c b/arch/arm/mach-s3c64xx/irq.c
index 97660c8141ae..75d9a0e49193 100644
--- a/arch/arm/mach-s3c64xx/irq.c
+++ b/arch/arm/mach-s3c64xx/irq.c
@@ -48,14 +48,22 @@ static struct s3c_uart_irq uart_irqs[] = {
         },
 };
 
+/* setup the sources the vic should advertise resume for, even though it
+ * is not doing the wake (set_irq_wake needs to be valid) */
+#define IRQ_VIC0_RESUME (1 << (IRQ_RTC_TIC - IRQ_VIC0_BASE))
+#define IRQ_VIC1_RESUME (1 << (IRQ_RTC_ALARM - IRQ_VIC1_BASE) | \
+                         1 << (IRQ_PENDN - IRQ_VIC1_BASE) |     \
+                         1 << (IRQ_HSMMC0 - IRQ_VIC1_BASE) |    \
+                         1 << (IRQ_HSMMC1 - IRQ_VIC1_BASE) |    \
+                         1 << (IRQ_HSMMC2 - IRQ_VIC1_BASE))
 
 void __init s3c64xx_init_irq(u32 vic0_valid, u32 vic1_valid)
 {
         printk(KERN_DEBUG "%s: initialising interrupts\n", __func__);
 
         /* initialise the pair of VICs */
-        vic_init(VA_VIC0, IRQ_VIC0_BASE, vic0_valid, 0);
-        vic_init(VA_VIC1, IRQ_VIC1_BASE, vic1_valid, 0);
+        vic_init(VA_VIC0, IRQ_VIC0_BASE, vic0_valid, IRQ_VIC0_RESUME);
+        vic_init(VA_VIC1, IRQ_VIC1_BASE, vic1_valid, IRQ_VIC1_RESUME);
 
         /* add the timer sub-irqs */
         s3c_init_vic_timer_irq(5, IRQ_TIMER0);