aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/mach-pxa/include/mach
diff options
context:
space:
mode:
Diffstat (limited to 'arch/arm/mach-pxa/include/mach')
-rw-r--r--arch/arm/mach-pxa/include/mach/addr-map.h48
-rw-r--r--arch/arm/mach-pxa/include/mach/balloon3.h6
-rw-r--r--arch/arm/mach-pxa/include/mach/colibri.h14
-rw-r--r--arch/arm/mach-pxa/include/mach/hardware.h47
-rw-r--r--arch/arm/mach-pxa/include/mach/irqs.h48
-rw-r--r--arch/arm/mach-pxa/include/mach/pxa2xx-regs.h66
-rw-r--r--arch/arm/mach-pxa/include/mach/pxa3xx-regs.h9
-rw-r--r--arch/arm/mach-pxa/include/mach/regs-intc.h4
-rw-r--r--arch/arm/mach-pxa/include/mach/smemc.h74
9 files changed, 184 insertions, 132 deletions
diff --git a/arch/arm/mach-pxa/include/mach/addr-map.h b/arch/arm/mach-pxa/include/mach/addr-map.h
new file mode 100644
index 000000000000..f4c03659168c
--- /dev/null
+++ b/arch/arm/mach-pxa/include/mach/addr-map.h
@@ -0,0 +1,48 @@
1#ifndef __ASM_MACH_ADDR_MAP_H
2#define __ASM_MACH_ADDR_MAP_H
3
4/*
5 * Chip Selects
6 */
7#define PXA_CS0_PHYS 0x00000000
8#define PXA_CS1_PHYS 0x04000000
9#define PXA_CS2_PHYS 0x08000000
10#define PXA_CS3_PHYS 0x0C000000
11#define PXA_CS4_PHYS 0x10000000
12#define PXA_CS5_PHYS 0x14000000
13
14#define PXA300_CS0_PHYS 0x00000000 /* PXA300/PXA310 _only_ */
15#define PXA300_CS1_PHYS 0x30000000 /* PXA300/PXA310 _only_ */
16#define PXA3xx_CS2_PHYS 0x10000000
17#define PXA3xx_CS3_PHYS 0x14000000
18
19/*
20 * Peripheral Bus
21 */
22#define PERIPH_PHYS 0x40000000
23#define PERIPH_VIRT 0xf2000000
24#define PERIPH_SIZE 0x02000000
25
26/*
27 * Static Memory Controller (w/ SDRAM controls on PXA25x/PXA27x)
28 */
29#define PXA2XX_SMEMC_PHYS 0x48000000
30#define PXA3XX_SMEMC_PHYS 0x4a000000
31#define SMEMC_VIRT 0xf6000000
32#define SMEMC_SIZE 0x00100000
33
34/*
35 * Dynamic Memory Controller (only on PXA3xx)
36 */
37#define DMEMC_PHYS 0x48100000
38#define DMEMC_VIRT 0xf6100000
39#define DMEMC_SIZE 0x00100000
40
41/*
42 * Internal Memory Controller (PXA27x and later)
43 */
44#define IMEMC_PHYS 0x58000000
45#define IMEMC_VIRT 0xfe000000
46#define IMEMC_SIZE 0x00100000
47
48#endif /* __ASM_MACH_ADDR_MAP_H */
diff --git a/arch/arm/mach-pxa/include/mach/balloon3.h b/arch/arm/mach-pxa/include/mach/balloon3.h
index 561562b4360b..7074e76146c9 100644
--- a/arch/arm/mach-pxa/include/mach/balloon3.h
+++ b/arch/arm/mach-pxa/include/mach/balloon3.h
@@ -26,6 +26,8 @@ enum balloon3_features {
26#define BALLOON3_FPGA_VIRT (0xf1000000) /* as per balloon2 */ 26#define BALLOON3_FPGA_VIRT (0xf1000000) /* as per balloon2 */
27#define BALLOON3_FPGA_LENGTH 0x01000000 27#define BALLOON3_FPGA_LENGTH 0x01000000
28 28
29#define BALLOON3_FPGA_SETnCLR (0x1000)
30
29/* FPGA / CPLD registers for CF socket */ 31/* FPGA / CPLD registers for CF socket */
30#define BALLOON3_CF_STATUS_REG (BALLOON3_FPGA_VIRT + 0x00e00008) 32#define BALLOON3_CF_STATUS_REG (BALLOON3_FPGA_VIRT + 0x00e00008)
31#define BALLOON3_CF_CONTROL_REG (BALLOON3_FPGA_VIRT + 0x00e00008) 33#define BALLOON3_CF_CONTROL_REG (BALLOON3_FPGA_VIRT + 0x00e00008)
@@ -35,7 +37,7 @@ enum balloon3_features {
35#define BALLOON3_NAND_BASE (PXA_CS4_PHYS + 0x00e00000) 37#define BALLOON3_NAND_BASE (PXA_CS4_PHYS + 0x00e00000)
36#define BALLOON3_NAND_IO_REG (BALLOON3_FPGA_VIRT + 0x00e00000) 38#define BALLOON3_NAND_IO_REG (BALLOON3_FPGA_VIRT + 0x00e00000)
37#define BALLOON3_NAND_CONTROL2_REG (BALLOON3_FPGA_VIRT + 0x00e00010) 39#define BALLOON3_NAND_CONTROL2_REG (BALLOON3_FPGA_VIRT + 0x00e00010)
38#define BALLOON3_NAND_STAT_REG (BALLOON3_FPGA_VIRT + 0x00e00010) 40#define BALLOON3_NAND_STAT_REG (BALLOON3_FPGA_VIRT + 0x00e00014)
39#define BALLOON3_NAND_CONTROL_REG (BALLOON3_FPGA_VIRT + 0x00e00014) 41#define BALLOON3_NAND_CONTROL_REG (BALLOON3_FPGA_VIRT + 0x00e00014)
40 42
41/* fpga/cpld interrupt control register */ 43/* fpga/cpld interrupt control register */
@@ -174,7 +176,7 @@ enum balloon3_features {
174#define BALLOON3_CODEC_IRQ IRQ_GPIO(BALLOON3_GPIO_CODEC_IRQ) 176#define BALLOON3_CODEC_IRQ IRQ_GPIO(BALLOON3_GPIO_CODEC_IRQ)
175#define BALLOON3_S0_CD_IRQ IRQ_GPIO(BALLOON3_GPIO_S0_CD) 177#define BALLOON3_S0_CD_IRQ IRQ_GPIO(BALLOON3_GPIO_S0_CD)
176 178
177#define BALLOON3_NR_IRQS (IRQ_BOARD_START + 4) 179#define BALLOON3_NR_IRQS (IRQ_BOARD_START + 16)
178 180
179extern int balloon3_has(enum balloon3_features feature); 181extern int balloon3_has(enum balloon3_features feature);
180 182
diff --git a/arch/arm/mach-pxa/include/mach/colibri.h b/arch/arm/mach-pxa/include/mach/colibri.h
index 58dada11054f..388a96f1ef93 100644
--- a/arch/arm/mach-pxa/include/mach/colibri.h
+++ b/arch/arm/mach-pxa/include/mach/colibri.h
@@ -9,14 +9,14 @@
9 */ 9 */
10 10
11enum { 11enum {
12 COLIBRI_PXA270_EVALBOARD = 0, 12 COLIBRI_EVALBOARD = 0,
13 COLIBRI_PXA270_INCOME, 13 COLIBRI_PXA270_INCOME,
14}; 14};
15 15
16#if defined(CONFIG_MACH_COLIBRI_PXA270_EVALBOARD) 16#if defined(CONFIG_MACH_COLIBRI_EVALBOARD)
17extern void colibri_pxa270_evalboard_init(void); 17extern void colibri_evalboard_init(void);
18#else 18#else
19static inline void colibri_pxa270_evalboard_init(void) {} 19static inline void colibri_evalboard_init(void) {}
20#endif 20#endif
21 21
22#if defined(CONFIG_MACH_COLIBRI_PXA270_INCOME) 22#if defined(CONFIG_MACH_COLIBRI_PXA270_INCOME)
@@ -59,5 +59,11 @@ static inline void colibri_pxa3xx_init_nand(void) {}
59#define GPIO0_COLIBRI_PXA270_SD_DETECT 0 59#define GPIO0_COLIBRI_PXA270_SD_DETECT 0
60#define GPIO113_COLIBRI_PXA270_TS_IRQ 113 60#define GPIO113_COLIBRI_PXA270_TS_IRQ 113
61 61
62/* GPIO definitions for Colibri PXA300/310 */
63#define GPIO39_COLIBRI_PXA300_SD_DETECT 39
64
65/* GPIO definitions for Colibri PXA320 */
66#define GPIO28_COLIBRI_PXA320_SD_DETECT 28
67
62#endif /* _COLIBRI_H_ */ 68#endif /* _COLIBRI_H_ */
63 69
diff --git a/arch/arm/mach-pxa/include/mach/hardware.h b/arch/arm/mach-pxa/include/mach/hardware.h
index 814f1458a06a..6957ba56025b 100644
--- a/arch/arm/mach-pxa/include/mach/hardware.h
+++ b/arch/arm/mach-pxa/include/mach/hardware.h
@@ -13,6 +13,8 @@
13#ifndef __ASM_ARCH_HARDWARE_H 13#ifndef __ASM_ARCH_HARDWARE_H
14#define __ASM_ARCH_HARDWARE_H 14#define __ASM_ARCH_HARDWARE_H
15 15
16#include <mach/addr-map.h>
17
16/* 18/*
17 * Workarounds for at least 2 errata so far require this. 19 * Workarounds for at least 2 errata so far require this.
18 * The mapping is set in mach-pxa/generic.c. 20 * The mapping is set in mach-pxa/generic.c.
@@ -193,14 +195,15 @@
193#define __cpu_is_pxa935(id) (0) 195#define __cpu_is_pxa935(id) (0)
194#endif 196#endif
195 197
196#ifdef CONFIG_CPU_PXA950 198#ifdef CONFIG_CPU_PXA955
197#define __cpu_is_pxa950(id) \ 199#define __cpu_is_pxa955(id) \
198 ({ \ 200 ({ \
199 unsigned int _id = (id) >> 4 & 0xfff; \ 201 unsigned int _id = (id) >> 4 & 0xfff; \
200 _id == 0x697; \ 202 _id == 0x581 || _id == 0xc08 \
201 }) 203 || _id == 0xb76; \
204 })
202#else 205#else
203#define __cpu_is_pxa950(id) (0) 206#define __cpu_is_pxa955(id) (0)
204#endif 207#endif
205 208
206#define cpu_is_pxa210() \ 209#define cpu_is_pxa210() \
@@ -253,16 +256,15 @@
253 __cpu_is_pxa935(read_cpuid_id()); \ 256 __cpu_is_pxa935(read_cpuid_id()); \
254 }) 257 })
255 258
256#define cpu_is_pxa950() \ 259#define cpu_is_pxa955() \
257 ({ \ 260 ({ \
258 __cpu_is_pxa950(read_cpuid_id()); \ 261 __cpu_is_pxa955(read_cpuid_id()); \
259 }) 262 })
260 263
261 264
262/* 265/*
263 * CPUID Core Generation Bit 266 * CPUID Core Generation Bit
264 * <= 0x2 for pxa21x/pxa25x/pxa26x/pxa27x 267 * <= 0x2 for pxa21x/pxa25x/pxa26x/pxa27x
265 * == 0x3 for pxa300/pxa310/pxa320
266 */ 268 */
267#if defined(CONFIG_PXA25x) || defined(CONFIG_PXA27x) 269#if defined(CONFIG_PXA25x) || defined(CONFIG_PXA27x)
268#define __cpu_is_pxa2xx(id) \ 270#define __cpu_is_pxa2xx(id) \
@@ -277,8 +279,10 @@
277#ifdef CONFIG_PXA3xx 279#ifdef CONFIG_PXA3xx
278#define __cpu_is_pxa3xx(id) \ 280#define __cpu_is_pxa3xx(id) \
279 ({ \ 281 ({ \
280 unsigned int _id = (id) >> 13 & 0x7; \ 282 __cpu_is_pxa300(id) \
281 _id == 0x3; \ 283 || __cpu_is_pxa310(id) \
284 || __cpu_is_pxa320(id) \
285 || __cpu_is_pxa93x(id); \
282 }) 286 })
283#else 287#else
284#define __cpu_is_pxa3xx(id) (0) 288#define __cpu_is_pxa3xx(id) (0)
@@ -287,13 +291,22 @@
287#if defined(CONFIG_CPU_PXA930) || defined(CONFIG_CPU_PXA935) 291#if defined(CONFIG_CPU_PXA930) || defined(CONFIG_CPU_PXA935)
288#define __cpu_is_pxa93x(id) \ 292#define __cpu_is_pxa93x(id) \
289 ({ \ 293 ({ \
290 unsigned int _id = (id) >> 4 & 0xfff; \ 294 __cpu_is_pxa930(id) \
291 _id == 0x683 || _id == 0x693; \ 295 || __cpu_is_pxa935(id); \
292 }) 296 })
293#else 297#else
294#define __cpu_is_pxa93x(id) (0) 298#define __cpu_is_pxa93x(id) (0)
295#endif 299#endif
296 300
301#ifdef CONFIG_PXA95x
302#define __cpu_is_pxa95x(id) \
303 ({ \
304 __cpu_is_pxa955(id); \
305 })
306#else
307#define __cpu_is_pxa95x(id) (0)
308#endif
309
297#define cpu_is_pxa2xx() \ 310#define cpu_is_pxa2xx() \
298 ({ \ 311 ({ \
299 __cpu_is_pxa2xx(read_cpuid_id()); \ 312 __cpu_is_pxa2xx(read_cpuid_id()); \
@@ -308,6 +321,12 @@
308 ({ \ 321 ({ \
309 __cpu_is_pxa93x(read_cpuid_id()); \ 322 __cpu_is_pxa93x(read_cpuid_id()); \
310 }) 323 })
324
325#define cpu_is_pxa95x() \
326 ({ \
327 __cpu_is_pxa95x(read_cpuid_id()); \
328 })
329
311/* 330/*
312 * return current memory and LCD clock frequency in units of 10kHz 331 * return current memory and LCD clock frequency in units of 10kHz
313 */ 332 */
diff --git a/arch/arm/mach-pxa/include/mach/irqs.h b/arch/arm/mach-pxa/include/mach/irqs.h
index d372caa75dc7..a4285fc00878 100644
--- a/arch/arm/mach-pxa/include/mach/irqs.h
+++ b/arch/arm/mach-pxa/include/mach/irqs.h
@@ -21,16 +21,14 @@
21 21
22#define PXA_IRQ(x) (PXA_ISA_IRQ_NUM + (x)) 22#define PXA_IRQ(x) (PXA_ISA_IRQ_NUM + (x))
23 23
24#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
25#define IRQ_SSP3 PXA_IRQ(0) /* SSP3 service request */ 24#define IRQ_SSP3 PXA_IRQ(0) /* SSP3 service request */
26#define IRQ_MSL PXA_IRQ(1) /* MSL Interface interrupt */ 25#define IRQ_MSL PXA_IRQ(1) /* MSL Interface interrupt */
27#define IRQ_USBH2 PXA_IRQ(2) /* USB Host interrupt 1 (OHCI) */ 26#define IRQ_USBH2 PXA_IRQ(2) /* USB Host interrupt 1 (OHCI,PXA27x) */
28#define IRQ_USBH1 PXA_IRQ(3) /* USB Host interrupt 2 (non-OHCI) */ 27#define IRQ_USBH1 PXA_IRQ(3) /* USB Host interrupt 2 (non-OHCI,PXA27x) */
29#define IRQ_KEYPAD PXA_IRQ(4) /* Key pad controller */ 28#define IRQ_KEYPAD PXA_IRQ(4) /* Key pad controller */
30#define IRQ_MEMSTK PXA_IRQ(5) /* Memory Stick interrupt */ 29#define IRQ_MEMSTK PXA_IRQ(5) /* Memory Stick interrupt (PXA27x) */
30#define IRQ_ACIPC0 PXA_IRQ(5) /* AP-CP Communication (PXA930) */
31#define IRQ_PWRI2C PXA_IRQ(6) /* Power I2C interrupt */ 31#define IRQ_PWRI2C PXA_IRQ(6) /* Power I2C interrupt */
32#endif
33
34#define IRQ_HWUART PXA_IRQ(7) /* HWUART Transmit/Receive/Error (PXA26x) */ 32#define IRQ_HWUART PXA_IRQ(7) /* HWUART Transmit/Receive/Error (PXA26x) */
35#define IRQ_OST_4_11 PXA_IRQ(7) /* OS timer 4-11 matches (PXA27x) */ 33#define IRQ_OST_4_11 PXA_IRQ(7) /* OS timer 4-11 matches (PXA27x) */
36#define IRQ_GPIO0 PXA_IRQ(8) /* GPIO0 Edge Detect */ 34#define IRQ_GPIO0 PXA_IRQ(8) /* GPIO0 Edge Detect */
@@ -38,7 +36,8 @@
38#define IRQ_GPIO_2_x PXA_IRQ(10) /* GPIO[2-x] Edge Detect */ 36#define IRQ_GPIO_2_x PXA_IRQ(10) /* GPIO[2-x] Edge Detect */
39#define IRQ_USB PXA_IRQ(11) /* USB Service */ 37#define IRQ_USB PXA_IRQ(11) /* USB Service */
40#define IRQ_PMU PXA_IRQ(12) /* Performance Monitoring Unit */ 38#define IRQ_PMU PXA_IRQ(12) /* Performance Monitoring Unit */
41#define IRQ_I2S PXA_IRQ(13) /* I2S Interrupt */ 39#define IRQ_I2S PXA_IRQ(13) /* I2S Interrupt (PXA27x) */
40#define IRQ_SSP4 PXA_IRQ(13) /* SSP4 service request (PXA3xx) */
42#define IRQ_AC97 PXA_IRQ(14) /* AC97 Interrupt */ 41#define IRQ_AC97 PXA_IRQ(14) /* AC97 Interrupt */
43#define IRQ_ASSP PXA_IRQ(15) /* Audio SSP Service Request (PXA25x) */ 42#define IRQ_ASSP PXA_IRQ(15) /* Audio SSP Service Request (PXA25x) */
44#define IRQ_USIM PXA_IRQ(15) /* Smart Card interface interrupt (PXA27x) */ 43#define IRQ_USIM PXA_IRQ(15) /* Smart Card interface interrupt (PXA27x) */
@@ -47,6 +46,7 @@
47#define IRQ_LCD PXA_IRQ(17) /* LCD Controller Service Request */ 46#define IRQ_LCD PXA_IRQ(17) /* LCD Controller Service Request */
48#define IRQ_I2C PXA_IRQ(18) /* I2C Service Request */ 47#define IRQ_I2C PXA_IRQ(18) /* I2C Service Request */
49#define IRQ_ICP PXA_IRQ(19) /* ICP Transmit/Receive/Error */ 48#define IRQ_ICP PXA_IRQ(19) /* ICP Transmit/Receive/Error */
49#define IRQ_ACIPC2 PXA_IRQ(19) /* AP-CP Communication (PXA930) */
50#define IRQ_STUART PXA_IRQ(20) /* STUART Transmit/Receive/Error */ 50#define IRQ_STUART PXA_IRQ(20) /* STUART Transmit/Receive/Error */
51#define IRQ_BTUART PXA_IRQ(21) /* BTUART Transmit/Receive/Error */ 51#define IRQ_BTUART PXA_IRQ(21) /* BTUART Transmit/Receive/Error */
52#define IRQ_FFUART PXA_IRQ(22) /* FFUART Transmit/Receive/Error*/ 52#define IRQ_FFUART PXA_IRQ(22) /* FFUART Transmit/Receive/Error*/
@@ -60,19 +60,17 @@
60#define IRQ_RTC1Hz PXA_IRQ(30) /* RTC HZ Clock Tick */ 60#define IRQ_RTC1Hz PXA_IRQ(30) /* RTC HZ Clock Tick */
61#define IRQ_RTCAlrm PXA_IRQ(31) /* RTC Alarm */ 61#define IRQ_RTCAlrm PXA_IRQ(31) /* RTC Alarm */
62 62
63#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
64#define IRQ_TPM PXA_IRQ(32) /* TPM interrupt */ 63#define IRQ_TPM PXA_IRQ(32) /* TPM interrupt */
65#define IRQ_CAMERA PXA_IRQ(33) /* Camera Interface */ 64#define IRQ_CAMERA PXA_IRQ(33) /* Camera Interface */
66#endif
67
68#ifdef CONFIG_PXA3xx
69#define IRQ_SSP4 PXA_IRQ(13) /* SSP4 service request */
70#define IRQ_CIR PXA_IRQ(34) /* Consumer IR */ 65#define IRQ_CIR PXA_IRQ(34) /* Consumer IR */
71#define IRQ_COMM_WDT PXA_IRQ(35) /* Comm WDT interrupt */ 66#define IRQ_COMM_WDT PXA_IRQ(35) /* Comm WDT interrupt */
72#define IRQ_TSI PXA_IRQ(36) /* Touch Screen Interface (PXA320) */ 67#define IRQ_TSI PXA_IRQ(36) /* Touch Screen Interface (PXA320) */
68#define IRQ_ENHROT PXA_IRQ(37) /* Enhanced Rotary (PXA930) */
73#define IRQ_USIM2 PXA_IRQ(38) /* USIM2 Controller */ 69#define IRQ_USIM2 PXA_IRQ(38) /* USIM2 Controller */
74#define IRQ_GCU PXA_IRQ(39) /* Graphics Controller */ 70#define IRQ_GCU PXA_IRQ(39) /* Graphics Controller (PXA3xx) */
71#define IRQ_ACIPC1 PXA_IRQ(40) /* AP-CP Communication (PXA930) */
75#define IRQ_MMC2 PXA_IRQ(41) /* MMC2 Controller */ 72#define IRQ_MMC2 PXA_IRQ(41) /* MMC2 Controller */
73#define IRQ_TRKBALL PXA_IRQ(43) /* Track Ball (PXA930) */
76#define IRQ_1WIRE PXA_IRQ(44) /* 1-Wire Controller */ 74#define IRQ_1WIRE PXA_IRQ(44) /* 1-Wire Controller */
77#define IRQ_NAND PXA_IRQ(45) /* NAND Controller */ 75#define IRQ_NAND PXA_IRQ(45) /* NAND Controller */
78#define IRQ_USB2 PXA_IRQ(46) /* USB 2.0 Device Controller */ 76#define IRQ_USB2 PXA_IRQ(46) /* USB 2.0 Device Controller */
@@ -80,30 +78,14 @@
80#define IRQ_WAKEUP1 PXA_IRQ(50) /* EXT_WAKEUP1 */ 78#define IRQ_WAKEUP1 PXA_IRQ(50) /* EXT_WAKEUP1 */
81#define IRQ_DMEMC PXA_IRQ(51) /* Dynamic Memory Controller */ 79#define IRQ_DMEMC PXA_IRQ(51) /* Dynamic Memory Controller */
82#define IRQ_MMC3 PXA_IRQ(55) /* MMC3 Controller (PXA310) */ 80#define IRQ_MMC3 PXA_IRQ(55) /* MMC3 Controller (PXA310) */
83#endif
84 81
85#ifdef CONFIG_CPU_PXA935
86#define IRQ_U2O PXA_IRQ(64) /* USB OTG 2.0 Controller (PXA935) */ 82#define IRQ_U2O PXA_IRQ(64) /* USB OTG 2.0 Controller (PXA935) */
87#define IRQ_U2H PXA_IRQ(65) /* USB Host 2.0 Controller (PXA935) */ 83#define IRQ_U2H PXA_IRQ(65) /* USB Host 2.0 Controller (PXA935) */
88 84#define IRQ_PXA935_MMC0 PXA_IRQ(72) /* MMC0 Controller (PXA935) */
89#define IRQ_MMC3_PXA935 PXA_IRQ(72) /* MMC3 Controller (PXA935) */ 85#define IRQ_PXA935_MMC1 PXA_IRQ(73) /* MMC1 Controller (PXA935) */
90#define IRQ_MMC4_PXA935 PXA_IRQ(73) /* MMC4 Controller (PXA935) */ 86#define IRQ_PXA935_MMC2 PXA_IRQ(74) /* MMC2 Controller (PXA935) */
91#define IRQ_MMC5_PXA935 PXA_IRQ(74) /* MMC5 Controller (PXA935) */ 87#define IRQ_PXA955_MMC3 PXA_IRQ(75) /* MMC3 Controller (PXA955) */
92
93#define IRQ_U2P PXA_IRQ(93) /* USB PHY D+/D- Lines (PXA935) */ 88#define IRQ_U2P PXA_IRQ(93) /* USB PHY D+/D- Lines (PXA935) */
94#endif
95
96#ifdef CONFIG_CPU_PXA930
97#define IRQ_ENHROT PXA_IRQ(37) /* Enhanced Rotary (PXA930) */
98#define IRQ_ACIPC0 PXA_IRQ(5)
99#define IRQ_ACIPC1 PXA_IRQ(40)
100#define IRQ_ACIPC2 PXA_IRQ(19)
101#define IRQ_TRKBALL PXA_IRQ(43) /* Track Ball */
102#endif
103
104#ifdef CONFIG_CPU_PXA950
105#define IRQ_GC500 PXA_IRQ(70) /* Graphics Controller (PXA950) */
106#endif
107 89
108#define PXA_GPIO_IRQ_BASE PXA_IRQ(96) 90#define PXA_GPIO_IRQ_BASE PXA_IRQ(96)
109#define PXA_GPIO_IRQ_NUM (192) 91#define PXA_GPIO_IRQ_NUM (192)
diff --git a/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h b/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h
index 4fcddd9cab76..ee6ced1cea7f 100644
--- a/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h
+++ b/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h
@@ -17,72 +17,6 @@
17#include <mach/hardware.h> 17#include <mach/hardware.h>
18 18
19/* 19/*
20 * PXA Chip selects
21 */
22
23#define PXA_CS0_PHYS 0x00000000
24#define PXA_CS1_PHYS 0x04000000
25#define PXA_CS2_PHYS 0x08000000
26#define PXA_CS3_PHYS 0x0C000000
27#define PXA_CS4_PHYS 0x10000000
28#define PXA_CS5_PHYS 0x14000000
29
30/*
31 * Memory controller
32 */
33
34#define MDCNFG __REG(0x48000000) /* SDRAM Configuration Register 0 */
35#define MDREFR __REG(0x48000004) /* SDRAM Refresh Control Register */
36#define MSC0 __REG(0x48000008) /* Static Memory Control Register 0 */
37#define MSC1 __REG(0x4800000C) /* Static Memory Control Register 1 */
38#define MSC2 __REG(0x48000010) /* Static Memory Control Register 2 */
39#define MECR __REG(0x48000014) /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */
40#define SXLCR __REG(0x48000018) /* LCR value to be written to SDRAM-Timing Synchronous Flash */
41#define SXCNFG __REG(0x4800001C) /* Synchronous Static Memory Control Register */
42#define SXMRS __REG(0x48000024) /* MRS value to be written to Synchronous Flash or SMROM */
43#define MCMEM0 __REG(0x48000028) /* Card interface Common Memory Space Socket 0 Timing */
44#define MCMEM1 __REG(0x4800002C) /* Card interface Common Memory Space Socket 1 Timing */
45#define MCATT0 __REG(0x48000030) /* Card interface Attribute Space Socket 0 Timing Configuration */
46#define MCATT1 __REG(0x48000034) /* Card interface Attribute Space Socket 1 Timing Configuration */
47#define MCIO0 __REG(0x48000038) /* Card interface I/O Space Socket 0 Timing Configuration */
48#define MCIO1 __REG(0x4800003C) /* Card interface I/O Space Socket 1 Timing Configuration */
49#define MDMRS __REG(0x48000040) /* MRS value to be written to SDRAM */
50#define BOOT_DEF __REG(0x48000044) /* Read-Only Boot-Time Register. Contains BOOT_SEL and PKG_SEL */
51
52/*
53 * More handy macros for PCMCIA
54 *
55 * Arg is socket number
56 */
57#define MCMEM(s) __REG2(0x48000028, (s)<<2 ) /* Card interface Common Memory Space Socket s Timing */
58#define MCATT(s) __REG2(0x48000030, (s)<<2 ) /* Card interface Attribute Space Socket s Timing Configuration */
59#define MCIO(s) __REG2(0x48000038, (s)<<2 ) /* Card interface I/O Space Socket s Timing Configuration */
60
61/* MECR register defines */
62#define MECR_NOS (1 << 0) /* Number Of Sockets: 0 -> 1 sock, 1 -> 2 sock */
63#define MECR_CIT (1 << 1) /* Card Is There: 0 -> no card, 1 -> card inserted */
64
65#define MDCNFG_DE0 (1 << 0) /* SDRAM Bank 0 Enable */
66#define MDCNFG_DE1 (1 << 1) /* SDRAM Bank 1 Enable */
67#define MDCNFG_DE2 (1 << 16) /* SDRAM Bank 2 Enable */
68#define MDCNFG_DE3 (1 << 17) /* SDRAM Bank 3 Enable */
69
70#define MDREFR_K0DB4 (1 << 29) /* SDCLK0 Divide by 4 Control/Status */
71#define MDREFR_K2FREE (1 << 25) /* SDRAM Free-Running Control */
72#define MDREFR_K1FREE (1 << 24) /* SDRAM Free-Running Control */
73#define MDREFR_K0FREE (1 << 23) /* SDRAM Free-Running Control */
74#define MDREFR_SLFRSH (1 << 22) /* SDRAM Self-Refresh Control/Status */
75#define MDREFR_APD (1 << 20) /* SDRAM/SSRAM Auto-Power-Down Enable */
76#define MDREFR_K2DB2 (1 << 19) /* SDCLK2 Divide by 2 Control/Status */
77#define MDREFR_K2RUN (1 << 18) /* SDCLK2 Run Control/Status */
78#define MDREFR_K1DB2 (1 << 17) /* SDCLK1 Divide by 2 Control/Status */
79#define MDREFR_K1RUN (1 << 16) /* SDCLK1 Run Control/Status */
80#define MDREFR_E1PIN (1 << 15) /* SDCKE1 Level Control/Status */
81#define MDREFR_K0DB2 (1 << 14) /* SDCLK0 Divide by 2 Control/Status */
82#define MDREFR_K0RUN (1 << 13) /* SDCLK0 Run Control/Status */
83#define MDREFR_E0PIN (1 << 12) /* SDCKE0 Level Control/Status */
84
85/*
86 * Power Manager 20 * Power Manager
87 */ 21 */
88 22
diff --git a/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h b/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h
index e91d63cfe811..e4fb4668c26e 100644
--- a/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h
+++ b/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h
@@ -16,15 +16,6 @@
16#include <mach/hardware.h> 16#include <mach/hardware.h>
17 17
18/* 18/*
19 * Static Chip Selects
20 */
21
22#define PXA300_CS0_PHYS (0x00000000) /* PXA300/PXA310 _only_ */
23#define PXA300_CS1_PHYS (0x30000000) /* PXA300/PXA310 _only_ */
24#define PXA3xx_CS2_PHYS (0x10000000)
25#define PXA3xx_CS3_PHYS (0x14000000)
26
27/*
28 * Oscillator Configuration Register (OSCC) 19 * Oscillator Configuration Register (OSCC)
29 */ 20 */
30#define OSCC __REG(0x41350000) /* Oscillator Configuration Register */ 21#define OSCC __REG(0x41350000) /* Oscillator Configuration Register */
diff --git a/arch/arm/mach-pxa/include/mach/regs-intc.h b/arch/arm/mach-pxa/include/mach/regs-intc.h
index 68464ce1c1ea..662288eb6f95 100644
--- a/arch/arm/mach-pxa/include/mach/regs-intc.h
+++ b/arch/arm/mach-pxa/include/mach/regs-intc.h
@@ -27,8 +27,4 @@
27#define ICFP3 __REG(0x40D0013C) /* Interrupt Controller FIQ Pending Register 3 */ 27#define ICFP3 __REG(0x40D0013C) /* Interrupt Controller FIQ Pending Register 3 */
28#define ICPR3 __REG(0x40D00140) /* Interrupt Controller Pending Register 3 */ 28#define ICPR3 __REG(0x40D00140) /* Interrupt Controller Pending Register 3 */
29 29
30#define IPR(x) __REG(0x40D0001C + (x < 32 ? (x << 2) \
31 : (x < 64 ? (0x94 + ((x - 32) << 2)) \
32 : (0x128 + ((x - 64) << 2)))))
33
34#endif /* __ASM_MACH_REGS_INTC_H */ 30#endif /* __ASM_MACH_REGS_INTC_H */
diff --git a/arch/arm/mach-pxa/include/mach/smemc.h b/arch/arm/mach-pxa/include/mach/smemc.h
new file mode 100644
index 000000000000..654adc90c9a0
--- /dev/null
+++ b/arch/arm/mach-pxa/include/mach/smemc.h
@@ -0,0 +1,74 @@
1/*
2 * Static memory controller register definitions for PXA CPUs
3 *
4 * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __SMEMC_REGS_H
12#define __SMEMC_REGS_H
13
14#define PXA2XX_SMEMC_BASE 0x48000000
15#define PXA3XX_SMEMC_BASE 0x4a000000
16#define SMEMC_VIRT 0xf6000000
17
18#define MDCNFG (SMEMC_VIRT + 0x00) /* SDRAM Configuration Register 0 */
19#define MDREFR (SMEMC_VIRT + 0x04) /* SDRAM Refresh Control Register */
20#define MSC0 (SMEMC_VIRT + 0x08) /* Static Memory Control Register 0 */
21#define MSC1 (SMEMC_VIRT + 0x0C) /* Static Memory Control Register 1 */
22#define MSC2 (SMEMC_VIRT + 0x10) /* Static Memory Control Register 2 */
23#define MECR (SMEMC_VIRT + 0x14) /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */
24#define SXLCR (SMEMC_VIRT + 0x18) /* LCR value to be written to SDRAM-Timing Synchronous Flash */
25#define SXCNFG (SMEMC_VIRT + 0x1C) /* Synchronous Static Memory Control Register */
26#define SXMRS (SMEMC_VIRT + 0x24) /* MRS value to be written to Synchronous Flash or SMROM */
27#define MCMEM0 (SMEMC_VIRT + 0x28) /* Card interface Common Memory Space Socket 0 Timing */
28#define MCMEM1 (SMEMC_VIRT + 0x2C) /* Card interface Common Memory Space Socket 1 Timing */
29#define MCATT0 (SMEMC_VIRT + 0x30) /* Card interface Attribute Space Socket 0 Timing Configuration */
30#define MCATT1 (SMEMC_VIRT + 0x34) /* Card interface Attribute Space Socket 1 Timing Configuration */
31#define MCIO0 (SMEMC_VIRT + 0x38) /* Card interface I/O Space Socket 0 Timing Configuration */
32#define MCIO1 (SMEMC_VIRT + 0x3C) /* Card interface I/O Space Socket 1 Timing Configuration */
33#define MDMRS (SMEMC_VIRT + 0x40) /* MRS value to be written to SDRAM */
34#define BOOT_DEF (SMEMC_VIRT + 0x44) /* Read-Only Boot-Time Register. Contains BOOT_SEL and PKG_SEL */
35#define MEMCLKCFG (SMEMC_VIRT + 0x68) /* Clock Configuration */
36#define CSADRCFG0 (SMEMC_VIRT + 0x80) /* Address Configuration Register for CS0 */
37#define CSADRCFG1 (SMEMC_VIRT + 0x84) /* Address Configuration Register for CS1 */
38#define CSADRCFG2 (SMEMC_VIRT + 0x88) /* Address Configuration Register for CS2 */
39#define CSADRCFG3 (SMEMC_VIRT + 0x8C) /* Address Configuration Register for CS3 */
40
41/*
42 * More handy macros for PCMCIA
43 *
44 * Arg is socket number
45 */
46#define MCMEM(s) (SMEMC_VIRT + 0x28 + ((s)<<2)) /* Card interface Common Memory Space Socket s Timing */
47#define MCATT(s) (SMEMC_VIRT + 0x30 + ((s)<<2)) /* Card interface Attribute Space Socket s Timing Configuration */
48#define MCIO(s) (SMEMC_VIRT + 0x38 + ((s)<<2)) /* Card interface I/O Space Socket s Timing Configuration */
49
50/* MECR register defines */
51#define MECR_NOS (1 << 0) /* Number Of Sockets: 0 -> 1 sock, 1 -> 2 sock */
52#define MECR_CIT (1 << 1) /* Card Is There: 0 -> no card, 1 -> card inserted */
53
54#define MDCNFG_DE0 (1 << 0) /* SDRAM Bank 0 Enable */
55#define MDCNFG_DE1 (1 << 1) /* SDRAM Bank 1 Enable */
56#define MDCNFG_DE2 (1 << 16) /* SDRAM Bank 2 Enable */
57#define MDCNFG_DE3 (1 << 17) /* SDRAM Bank 3 Enable */
58
59#define MDREFR_K0DB4 (1 << 29) /* SDCLK0 Divide by 4 Control/Status */
60#define MDREFR_K2FREE (1 << 25) /* SDRAM Free-Running Control */
61#define MDREFR_K1FREE (1 << 24) /* SDRAM Free-Running Control */
62#define MDREFR_K0FREE (1 << 23) /* SDRAM Free-Running Control */
63#define MDREFR_SLFRSH (1 << 22) /* SDRAM Self-Refresh Control/Status */
64#define MDREFR_APD (1 << 20) /* SDRAM/SSRAM Auto-Power-Down Enable */
65#define MDREFR_K2DB2 (1 << 19) /* SDCLK2 Divide by 2 Control/Status */
66#define MDREFR_K2RUN (1 << 18) /* SDCLK2 Run Control/Status */
67#define MDREFR_K1DB2 (1 << 17) /* SDCLK1 Divide by 2 Control/Status */
68#define MDREFR_K1RUN (1 << 16) /* SDCLK1 Run Control/Status */
69#define MDREFR_E1PIN (1 << 15) /* SDCKE1 Level Control/Status */
70#define MDREFR_K0DB2 (1 << 14) /* SDCLK0 Divide by 2 Control/Status */
71#define MDREFR_K0RUN (1 << 13) /* SDCLK0 Run Control/Status */
72#define MDREFR_E0PIN (1 << 12) /* SDCKE0 Level Control/Status */
73
74#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-16 12:51:24 -0500