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-rw-r--r--arch/arm/mach-omap2/prm.h352
1 files changed, 4 insertions, 348 deletions
diff --git a/arch/arm/mach-omap2/prm.h b/arch/arm/mach-omap2/prm.h
index 10a24ca3f400..39d562169d18 100644
--- a/arch/arm/mach-omap2/prm.h
+++ b/arch/arm/mach-omap2/prm.h
@@ -1,304 +1,20 @@
1#ifndef __ARCH_ARM_MACH_OMAP2_PRM_H
2#define __ARCH_ARM_MACH_OMAP2_PRM_H
3
4/* 1/*
5 * OMAP2/3 Power/Reset Management (PRM) register definitions 2 * OMAP2/3/4 Power/Reset Management (PRM) bitfield definitions
6 * 3 *
7 * Copyright (C) 2007-2009 Texas Instruments, Inc. 4 * Copyright (C) 2007-2009 Texas Instruments, Inc.
8 * Copyright (C) 2010 Nokia Corporation 5 * Copyright (C) 2010 Nokia Corporation
9 * 6 *
10 * Written by Paul Walmsley 7 * Paul Walmsley
11 * 8 *
12 * This program is free software; you can redistribute it and/or modify 9 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as 10 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation. 11 * published by the Free Software Foundation.
15 */ 12 */
13#ifndef __ARCH_ARM_MACH_OMAP2_PRM_H
14#define __ARCH_ARM_MACH_OMAP2_PRM_H
16 15
17#include "prcm-common.h" 16#include "prcm-common.h"
18 17
19#define OMAP2420_PRM_REGADDR(module, reg) \
20 OMAP2_L4_IO_ADDRESS(OMAP2420_PRM_BASE + (module) + (reg))
21#define OMAP2430_PRM_REGADDR(module, reg) \
22 OMAP2_L4_IO_ADDRESS(OMAP2430_PRM_BASE + (module) + (reg))
23#define OMAP34XX_PRM_REGADDR(module, reg) \
24 OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE + (module) + (reg))
25
26/*
27 * Architecture-specific global PRM registers
28 * Use __raw_{read,write}l() with these registers.
29 *
30 * With a few exceptions, these are the register names beginning with
31 * PRCM_* on 24xx, and PRM_* on 34xx. (The exceptions are the
32 * IRQSTATUS and IRQENABLE bits.)
33 *
34 */
35
36#define OMAP2_PRCM_REVISION_OFFSET 0x0000
37#define OMAP2420_PRCM_REVISION OMAP2420_PRM_REGADDR(OCP_MOD, 0x0000)
38#define OMAP2_PRCM_SYSCONFIG_OFFSET 0x0010
39#define OMAP2420_PRCM_SYSCONFIG OMAP2420_PRM_REGADDR(OCP_MOD, 0x0010)
40
41#define OMAP2_PRCM_IRQSTATUS_MPU_OFFSET 0x0018
42#define OMAP2420_PRCM_IRQSTATUS_MPU OMAP2420_PRM_REGADDR(OCP_MOD, 0x0018)
43#define OMAP2_PRCM_IRQENABLE_MPU_OFFSET 0x001c
44#define OMAP2420_PRCM_IRQENABLE_MPU OMAP2420_PRM_REGADDR(OCP_MOD, 0x001c)
45
46#define OMAP2_PRCM_VOLTCTRL_OFFSET 0x0050
47#define OMAP2420_PRCM_VOLTCTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0050)
48#define OMAP2_PRCM_VOLTST_OFFSET 0x0054
49#define OMAP2420_PRCM_VOLTST OMAP2420_PRM_REGADDR(OCP_MOD, 0x0054)
50#define OMAP2_PRCM_CLKSRC_CTRL_OFFSET 0x0060
51#define OMAP2420_PRCM_CLKSRC_CTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0060)
52#define OMAP2_PRCM_CLKOUT_CTRL_OFFSET 0x0070
53#define OMAP2420_PRCM_CLKOUT_CTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0070)
54#define OMAP2_PRCM_CLKEMUL_CTRL_OFFSET 0x0078
55#define OMAP2420_PRCM_CLKEMUL_CTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0078)
56#define OMAP2_PRCM_CLKCFG_CTRL_OFFSET 0x0080
57#define OMAP2420_PRCM_CLKCFG_CTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0080)
58#define OMAP2_PRCM_CLKCFG_STATUS_OFFSET 0x0084
59#define OMAP2420_PRCM_CLKCFG_STATUS OMAP2420_PRM_REGADDR(OCP_MOD, 0x0084)
60#define OMAP2_PRCM_VOLTSETUP_OFFSET 0x0090
61#define OMAP2420_PRCM_VOLTSETUP OMAP2420_PRM_REGADDR(OCP_MOD, 0x0090)
62#define OMAP2_PRCM_CLKSSETUP_OFFSET 0x0094
63#define OMAP2420_PRCM_CLKSSETUP OMAP2420_PRM_REGADDR(OCP_MOD, 0x0094)
64#define OMAP2_PRCM_POLCTRL_OFFSET 0x0098
65#define OMAP2420_PRCM_POLCTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0098)
66
67#define OMAP2430_PRCM_REVISION OMAP2430_PRM_REGADDR(OCP_MOD, 0x0000)
68#define OMAP2430_PRCM_SYSCONFIG OMAP2430_PRM_REGADDR(OCP_MOD, 0x0010)
69
70#define OMAP2430_PRCM_IRQSTATUS_MPU OMAP2430_PRM_REGADDR(OCP_MOD, 0x0018)
71#define OMAP2430_PRCM_IRQENABLE_MPU OMAP2430_PRM_REGADDR(OCP_MOD, 0x001c)
72
73#define OMAP2430_PRCM_VOLTCTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0050)
74#define OMAP2430_PRCM_VOLTST OMAP2430_PRM_REGADDR(OCP_MOD, 0x0054)
75#define OMAP2430_PRCM_CLKSRC_CTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0060)
76#define OMAP2430_PRCM_CLKOUT_CTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0070)
77#define OMAP2430_PRCM_CLKEMUL_CTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0078)
78#define OMAP2430_PRCM_CLKCFG_CTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0080)
79#define OMAP2430_PRCM_CLKCFG_STATUS OMAP2430_PRM_REGADDR(OCP_MOD, 0x0084)
80#define OMAP2430_PRCM_VOLTSETUP OMAP2430_PRM_REGADDR(OCP_MOD, 0x0090)
81#define OMAP2430_PRCM_CLKSSETUP OMAP2430_PRM_REGADDR(OCP_MOD, 0x0094)
82#define OMAP2430_PRCM_POLCTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0098)
83
84#define OMAP3_PRM_REVISION_OFFSET 0x0004
85#define OMAP3430_PRM_REVISION OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0004)
86#define OMAP3_PRM_SYSCONFIG_OFFSET 0x0014
87#define OMAP3430_PRM_SYSCONFIG OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0014)
88
89#define OMAP3_PRM_IRQSTATUS_MPU_OFFSET 0x0018
90#define OMAP3430_PRM_IRQSTATUS_MPU OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0018)
91#define OMAP3_PRM_IRQENABLE_MPU_OFFSET 0x001c
92#define OMAP3430_PRM_IRQENABLE_MPU OMAP34XX_PRM_REGADDR(OCP_MOD, 0x001c)
93
94
95#define OMAP3_PRM_VC_SMPS_SA_OFFSET 0x0020
96#define OMAP3430_PRM_VC_SMPS_SA OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0020)
97#define OMAP3_PRM_VC_SMPS_VOL_RA_OFFSET 0x0024
98#define OMAP3430_PRM_VC_SMPS_VOL_RA OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0024)
99#define OMAP3_PRM_VC_SMPS_CMD_RA_OFFSET 0x0028
100#define OMAP3430_PRM_VC_SMPS_CMD_RA OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0028)
101#define OMAP3_PRM_VC_CMD_VAL_0_OFFSET 0x002c
102#define OMAP3430_PRM_VC_CMD_VAL_0 OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x002c)
103#define OMAP3_PRM_VC_CMD_VAL_1_OFFSET 0x0030
104#define OMAP3430_PRM_VC_CMD_VAL_1 OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0030)
105#define OMAP3_PRM_VC_CH_CONF_OFFSET 0x0034
106#define OMAP3430_PRM_VC_CH_CONF OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0034)
107#define OMAP3_PRM_VC_I2C_CFG_OFFSET 0x0038
108#define OMAP3430_PRM_VC_I2C_CFG OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0038)
109#define OMAP3_PRM_VC_BYPASS_VAL_OFFSET 0x003c
110#define OMAP3430_PRM_VC_BYPASS_VAL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x003c)
111#define OMAP3_PRM_RSTCTRL_OFFSET 0x0050
112#define OMAP3430_PRM_RSTCTRL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0050)
113#define OMAP3_PRM_RSTTIME_OFFSET 0x0054
114#define OMAP3430_PRM_RSTTIME OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0054)
115#define OMAP3_PRM_RSTST_OFFSET 0x0058
116#define OMAP3430_PRM_RSTST OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0058)
117#define OMAP3_PRM_VOLTCTRL_OFFSET 0x0060
118#define OMAP3430_PRM_VOLTCTRL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0060)
119#define OMAP3_PRM_SRAM_PCHARGE_OFFSET 0x0064
120#define OMAP3430_PRM_SRAM_PCHARGE OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0064)
121#define OMAP3_PRM_CLKSRC_CTRL_OFFSET 0x0070
122#define OMAP3430_PRM_CLKSRC_CTRL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0070)
123#define OMAP3_PRM_VOLTSETUP1_OFFSET 0x0090
124#define OMAP3430_PRM_VOLTSETUP1 OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0090)
125#define OMAP3_PRM_VOLTOFFSET_OFFSET 0x0094
126#define OMAP3430_PRM_VOLTOFFSET OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0094)
127#define OMAP3_PRM_CLKSETUP_OFFSET 0x0098
128#define OMAP3430_PRM_CLKSETUP OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0098)
129#define OMAP3_PRM_POLCTRL_OFFSET 0x009c
130#define OMAP3430_PRM_POLCTRL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x009c)
131#define OMAP3_PRM_VOLTSETUP2_OFFSET 0x00a0
132#define OMAP3430_PRM_VOLTSETUP2 OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00a0)
133#define OMAP3_PRM_VP1_CONFIG_OFFSET 0x00b0
134#define OMAP3430_PRM_VP1_CONFIG OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b0)
135#define OMAP3_PRM_VP1_VSTEPMIN_OFFSET 0x00b4
136#define OMAP3430_PRM_VP1_VSTEPMIN OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b4)
137#define OMAP3_PRM_VP1_VSTEPMAX_OFFSET 0x00b8
138#define OMAP3430_PRM_VP1_VSTEPMAX OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b8)
139#define OMAP3_PRM_VP1_VLIMITTO_OFFSET 0x00bc
140#define OMAP3430_PRM_VP1_VLIMITTO OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00bc)
141#define OMAP3_PRM_VP1_VOLTAGE_OFFSET 0x00c0
142#define OMAP3430_PRM_VP1_VOLTAGE OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c0)
143#define OMAP3_PRM_VP1_STATUS_OFFSET 0x00c4
144#define OMAP3430_PRM_VP1_STATUS OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c4)
145#define OMAP3_PRM_VP2_CONFIG_OFFSET 0x00d0
146#define OMAP3430_PRM_VP2_CONFIG OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d0)
147#define OMAP3_PRM_VP2_VSTEPMIN_OFFSET 0x00d4
148#define OMAP3430_PRM_VP2_VSTEPMIN OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d4)
149#define OMAP3_PRM_VP2_VSTEPMAX_OFFSET 0x00d8
150#define OMAP3430_PRM_VP2_VSTEPMAX OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d8)
151#define OMAP3_PRM_VP2_VLIMITTO_OFFSET 0x00dc
152#define OMAP3430_PRM_VP2_VLIMITTO OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00dc)
153#define OMAP3_PRM_VP2_VOLTAGE_OFFSET 0x00e0
154#define OMAP3430_PRM_VP2_VOLTAGE OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e0)
155#define OMAP3_PRM_VP2_STATUS_OFFSET 0x00e4
156#define OMAP3430_PRM_VP2_STATUS OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e4)
157
158#define OMAP3_PRM_CLKSEL_OFFSET 0x0040
159#define OMAP3430_PRM_CLKSEL OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0040)
160#define OMAP3_PRM_CLKOUT_CTRL_OFFSET 0x0070
161#define OMAP3430_PRM_CLKOUT_CTRL OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0070)
162
163/*
164 * Module specific PRM registers from PRM_BASE + domain offset
165 *
166 * Use prm_{read,write}_mod_reg() with these registers.
167 *
168 * With a few exceptions, these are the register names beginning with
169 * {PM,RM}_* on both architectures. (The exceptions are the IRQSTATUS
170 * and IRQENABLE bits.)
171 *
172 */
173
174/* Registers appearing on both 24xx and 34xx */
175
176#define OMAP2_RM_RSTCTRL 0x0050
177#define OMAP2_RM_RSTTIME 0x0054
178#define OMAP2_RM_RSTST 0x0058
179#define OMAP2_PM_PWSTCTRL 0x00e0
180#define OMAP2_PM_PWSTST 0x00e4
181
182#define PM_WKEN 0x00a0
183#define PM_WKEN1 PM_WKEN
184#define PM_WKST 0x00b0
185#define PM_WKST1 PM_WKST
186#define PM_WKDEP 0x00c8
187#define PM_EVGENCTRL 0x00d4
188#define PM_EVGENONTIM 0x00d8
189#define PM_EVGENOFFTIM 0x00dc
190
191/* Omap2 specific registers */
192#define OMAP24XX_PM_WKEN2 0x00a4
193#define OMAP24XX_PM_WKST2 0x00b4
194
195#define OMAP24XX_PRCM_IRQSTATUS_DSP 0x00f0 /* IVA mod */
196#define OMAP24XX_PRCM_IRQENABLE_DSP 0x00f4 /* IVA mod */
197#define OMAP24XX_PRCM_IRQSTATUS_IVA 0x00f8
198#define OMAP24XX_PRCM_IRQENABLE_IVA 0x00fc
199
200/* Omap3 specific registers */
201#define OMAP3430ES2_PM_WKEN3 0x00f0
202#define OMAP3430ES2_PM_WKST3 0x00b8
203
204#define OMAP3430_PM_MPUGRPSEL 0x00a4
205#define OMAP3430_PM_MPUGRPSEL1 OMAP3430_PM_MPUGRPSEL
206#define OMAP3430ES2_PM_MPUGRPSEL3 0x00f8
207
208#define OMAP3430_PM_IVAGRPSEL 0x00a8
209#define OMAP3430_PM_IVAGRPSEL1 OMAP3430_PM_IVAGRPSEL
210#define OMAP3430ES2_PM_IVAGRPSEL3 0x00f4
211
212#define OMAP3430_PM_PREPWSTST 0x00e8
213
214#define OMAP3430_PRM_IRQSTATUS_IVA2 0x00f8
215#define OMAP3430_PRM_IRQENABLE_IVA2 0x00fc
216
217
218#ifndef __ASSEMBLER__
219
220/* Power/reset management domain register get/set */
221extern u32 prm_read_mod_reg(s16 module, u16 idx);
222extern void prm_write_mod_reg(u32 val, s16 module, u16 idx);
223extern u32 prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx);
224
225/* Read-modify-write bits in a PRM register (by domain) */
226static inline u32 prm_set_mod_reg_bits(u32 bits, s16 module, s16 idx)
227{
228 return prm_rmw_mod_reg_bits(bits, bits, module, idx);
229}
230
231static inline u32 prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
232{
233 return prm_rmw_mod_reg_bits(bits, 0x0, module, idx);
234}
235
236/* These omap2_ PRM functions apply to both OMAP2 and 3 */
237int omap2_prm_is_hardreset_asserted(s16 prm_mod, u8 shift);
238int omap2_prm_assert_hardreset(s16 prm_mod, u8 shift);
239int omap2_prm_deassert_hardreset(s16 prm_mod, u8 shift);
240
241#endif
242
243/*
244 * Bits common to specific registers
245 *
246 * The 3430 register and bit names are generally used,
247 * since they tend to make more sense
248 */
249
250/* PM_EVGENONTIM_MPU */
251/* Named PM_EVEGENONTIM_MPU on the 24XX */
252#define OMAP_ONTIMEVAL_SHIFT 0
253#define OMAP_ONTIMEVAL_MASK (0xffffffff << 0)
254
255/* PM_EVGENOFFTIM_MPU */
256/* Named PM_EVEGENOFFTIM_MPU on the 24XX */
257#define OMAP_OFFTIMEVAL_SHIFT 0
258#define OMAP_OFFTIMEVAL_MASK (0xffffffff << 0)
259
260/* PRM_CLKSETUP and PRCM_VOLTSETUP */
261/* Named PRCM_CLKSSETUP on the 24XX */
262#define OMAP_SETUP_TIME_SHIFT 0
263#define OMAP_SETUP_TIME_MASK (0xffff << 0)
264
265/* PRM_CLKSRC_CTRL */
266/* Named PRCM_CLKSRC_CTRL on the 24XX */
267#define OMAP_SYSCLKDIV_SHIFT 6
268#define OMAP_SYSCLKDIV_MASK (0x3 << 6)
269#define OMAP_AUTOEXTCLKMODE_SHIFT 3
270#define OMAP_AUTOEXTCLKMODE_MASK (0x3 << 3)
271#define OMAP_SYSCLKSEL_SHIFT 0
272#define OMAP_SYSCLKSEL_MASK (0x3 << 0)
273
274/* PM_EVGENCTRL_MPU */
275#define OMAP_OFFLOADMODE_SHIFT 3
276#define OMAP_OFFLOADMODE_MASK (0x3 << 3)
277#define OMAP_ONLOADMODE_SHIFT 1
278#define OMAP_ONLOADMODE_MASK (0x3 << 1)
279#define OMAP_ENABLE_MASK (1 << 0)
280
281/* PRM_RSTTIME */
282/* Named RM_RSTTIME_WKUP on the 24xx */
283#define OMAP_RSTTIME2_SHIFT 8
284#define OMAP_RSTTIME2_MASK (0x1f << 8)
285#define OMAP_RSTTIME1_SHIFT 0
286#define OMAP_RSTTIME1_MASK (0xff << 0)
287
288/* PRM_RSTCTRL */
289/* Named RM_RSTCTRL_WKUP on the 24xx */
290/* 2420 calls RST_DPLL3 'RST_DPLL' */
291#define OMAP_RST_DPLL3_MASK (1 << 2)
292#define OMAP_RST_GS_MASK (1 << 1)
293
294
295/*
296 * Bits common to module-shared registers
297 *
298 * Not all registers of a particular type support all of these bits -
299 * check TRM if you are unsure
300 */
301
302/* 18/*
303 * 24XX: PM_PWSTST_CORE, PM_PWSTST_GFX, PM_PWSTST_MPU, PM_PWSTST_DSP 19 * 24XX: PM_PWSTST_CORE, PM_PWSTST_GFX, PM_PWSTST_MPU, PM_PWSTST_DSP
304 * 20 *
@@ -324,59 +40,6 @@ int omap2_prm_deassert_hardreset(s16 prm_mod, u8 shift);
324#define OMAP_POWERSTATEST_MASK (0x3 << 0) 40#define OMAP_POWERSTATEST_MASK (0x3 << 0)
325 41
326/* 42/*
327 * 24XX: RM_RSTST_MPU and RM_RSTST_DSP - on 24XX, 'COREDOMAINWKUP_RST' is
328 * called 'COREWKUP_RST'
329 *
330 * 3430: RM_RSTST_IVA2, RM_RSTST_MPU, RM_RSTST_GFX, RM_RSTST_DSS,
331 * RM_RSTST_CAM, RM_RSTST_PER, RM_RSTST_NEON
332 */
333#define OMAP_COREDOMAINWKUP_RST_MASK (1 << 3)
334
335/*
336 * 24XX: RM_RSTST_MPU, RM_RSTST_GFX, RM_RSTST_DSP
337 *
338 * 2430: RM_RSTST_MDM
339 *
340 * 3430: RM_RSTST_CORE, RM_RSTST_EMU
341 */
342#define OMAP_DOMAINWKUP_RST_MASK (1 << 2)
343
344/*
345 * 24XX: RM_RSTST_MPU, RM_RSTST_WKUP, RM_RSTST_DSP
346 * On 24XX, 'GLOBALWARM_RST' is called 'GLOBALWMPU_RST'.
347 *
348 * 2430: RM_RSTST_MDM
349 *
350 * 3430: RM_RSTST_CORE, RM_RSTST_EMU
351 */
352#define OMAP_GLOBALWARM_RST_MASK (1 << 1)
353#define OMAP_GLOBALCOLD_RST_MASK (1 << 0)
354
355/*
356 * 24XX: PM_WKDEP_GFX, PM_WKDEP_MPU, PM_WKDEP_CORE, PM_WKDEP_DSP
357 * 2420 TRM sometimes uses "EN_WAKEUP" instead of "EN_WKUP"
358 *
359 * 2430: PM_WKDEP_MDM
360 *
361 * 3430: PM_WKDEP_IVA2, PM_WKDEP_GFX, PM_WKDEP_DSS, PM_WKDEP_CAM,
362 * PM_WKDEP_PER
363 */
364#define OMAP_EN_WKUP_SHIFT 4
365#define OMAP_EN_WKUP_MASK (1 << 4)
366
367/*
368 * 24XX: PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX,
369 * PM_PWSTCTRL_DSP
370 *
371 * 2430: PM_PWSTCTRL_MDM
372 *
373 * 3430: PM_PWSTCTRL_IVA2, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX,
374 * PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM, PM_PWSTCTRL_PER,
375 * PM_PWSTCTRL_NEON
376 */
377#define OMAP_LOGICRETSTATE_MASK (1 << 2)
378
379/*
380 * 24XX: PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX, 43 * 24XX: PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX,
381 * PM_PWSTCTRL_DSP, PM_PWSTST_MPU 44 * PM_PWSTCTRL_DSP, PM_PWSTST_MPU
382 * 45 *
@@ -390,11 +53,4 @@ int omap2_prm_deassert_hardreset(s16 prm_mod, u8 shift);
390#define OMAP_POWERSTATE_MASK (0x3 << 0) 53#define OMAP_POWERSTATE_MASK (0x3 << 0)
391 54
392 55
393/*
394 * MAX_MODULE_HARDRESET_WAIT: Maximum microseconds to wait for an OMAP
395 * submodule to exit hardreset
396 */
397#define MAX_MODULE_HARDRESET_WAIT 10000
398
399
400#endif 56#endif
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