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-rw-r--r--arch/arm/mach-omap2/prcm-common.h75
1 files changed, 74 insertions, 1 deletions
diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h
index 0363dcb0ef93..0f69d8fc5628 100644
--- a/arch/arm/mach-omap2/prcm-common.h
+++ b/arch/arm/mach-omap2/prcm-common.h
@@ -4,7 +4,7 @@
4/* 4/*
5 * OMAP2/3 PRCM base and module definitions 5 * OMAP2/3 PRCM base and module definitions
6 * 6 *
7 * Copyright (C) 2007-2009 Texas Instruments, Inc. 7 * Copyright (C) 2007-2009, 2011 Texas Instruments, Inc.
8 * Copyright (C) 2007-2009 Nokia Corporation 8 * Copyright (C) 2007-2009 Nokia Corporation
9 * 9 *
10 * Written by Paul Walmsley 10 * Written by Paul Walmsley
@@ -408,6 +408,79 @@
408extern void __iomem *prm_base; 408extern void __iomem *prm_base;
409extern void __iomem *cm_base; 409extern void __iomem *cm_base;
410extern void __iomem *cm2_base; 410extern void __iomem *cm2_base;
411
412/**
413 * struct omap_prcm_irq - describes a PRCM interrupt bit
414 * @name: a short name describing the interrupt type, e.g. "wkup" or "io"
415 * @offset: the bit shift of the interrupt inside the IRQ{ENABLE,STATUS} regs
416 * @priority: should this interrupt be handled before @priority=false IRQs?
417 *
418 * Describes interrupt bits inside the PRM_IRQ{ENABLE,STATUS}_MPU* registers.
419 * On systems with multiple PRM MPU IRQ registers, the bitfields read from
420 * the registers are concatenated, so @offset could be > 31 on these systems -
421 * see omap_prm_irq_handler() for more details. I/O ring interrupts should
422 * have @priority set to true.
423 */
424struct omap_prcm_irq {
425 const char *name;
426 unsigned int offset;
427 bool priority;
428};
429
430/**
431 * struct omap_prcm_irq_setup - PRCM interrupt controller details
432 * @ack: PRM register offset for the first PRM_IRQSTATUS_MPU register
433 * @mask: PRM register offset for the first PRM_IRQENABLE_MPU register
434 * @nr_regs: number of PRM_IRQ{STATUS,ENABLE}_MPU* registers
435 * @nr_irqs: number of entries in the @irqs array
436 * @irqs: ptr to an array of PRCM interrupt bits (see @nr_irqs)
437 * @irq: MPU IRQ asserted when a PRCM interrupt arrives
438 * @read_pending_irqs: fn ptr to determine if any PRCM IRQs are pending
439 * @ocp_barrier: fn ptr to force buffered PRM writes to complete
440 * @save_and_clear_irqen: fn ptr to save and clear IRQENABLE regs
441 * @restore_irqen: fn ptr to save and clear IRQENABLE regs
442 * @saved_mask: IRQENABLE regs are saved here during suspend
443 * @priority_mask: 1 bit per IRQ, set to 1 if omap_prcm_irq.priority = true
444 * @base_irq: base dynamic IRQ number, returned from irq_alloc_descs() in init
445 * @suspended: set to true after Linux suspend code has called our ->prepare()
446 * @suspend_save_flag: set to true after IRQ masks have been saved and disabled
447 *
448 * @saved_mask, @priority_mask, @base_irq, @suspended, and
449 * @suspend_save_flag are populated dynamically, and are not to be
450 * specified in static initializers.
451 */
452struct omap_prcm_irq_setup {
453 u16 ack;
454 u16 mask;
455 u8 nr_regs;
456 u8 nr_irqs;
457 const struct omap_prcm_irq *irqs;
458 int irq;
459 void (*read_pending_irqs)(unsigned long *events);
460 void (*ocp_barrier)(void);
461 void (*save_and_clear_irqen)(u32 *saved_mask);
462 void (*restore_irqen)(u32 *saved_mask);
463 u32 *saved_mask;
464 u32 *priority_mask;
465 int base_irq;
466 bool suspended;
467 bool suspend_save_flag;
468};
469
470/* OMAP_PRCM_IRQ: convenience macro for creating struct omap_prcm_irq records */
471#define OMAP_PRCM_IRQ(_name, _offset, _priority) { \
472 .name = _name, \
473 .offset = _offset, \
474 .priority = _priority \
475 }
476
477extern void omap_prcm_irq_cleanup(void);
478extern int omap_prcm_register_chain_handler(
479 struct omap_prcm_irq_setup *irq_setup);
480extern int omap_prcm_event_to_irq(const char *event);
481extern void omap_prcm_irq_prepare(void);
482extern void omap_prcm_irq_complete(void);
483
411# endif 484# endif
412 485
413#endif 486#endif