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-rw-r--r--arch/arm/mach-omap2/omap_hwmod_3xxx_data.c654
1 files changed, 131 insertions, 523 deletions
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index 909a84de6682..1a52716e48bf 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips 2 * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips
3 * 3 *
4 * Copyright (C) 2009-2010 Nokia Corporation 4 * Copyright (C) 2009-2011 Nokia Corporation
5 * Paul Walmsley 5 * Paul Walmsley
6 * 6 *
7 * This program is free software; you can redistribute it and/or modify 7 * This program is free software; you can redistribute it and/or modify
@@ -103,6 +103,7 @@ static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = {
103static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs[] = { 103static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs[] = {
104 { .irq = INT_34XX_L3_DBG_IRQ }, 104 { .irq = INT_34XX_L3_DBG_IRQ },
105 { .irq = INT_34XX_L3_APP_IRQ }, 105 { .irq = INT_34XX_L3_APP_IRQ },
106 { .irq = -1 }
106}; 107};
107 108
108static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = { 109static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = {
@@ -111,6 +112,7 @@ static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = {
111 .pa_end = 0x6800ffff, 112 .pa_end = 0x6800ffff,
112 .flags = ADDR_TYPE_RT, 113 .flags = ADDR_TYPE_RT,
113 }, 114 },
115 { }
114}; 116};
115 117
116/* MPU -> L3 interface */ 118/* MPU -> L3 interface */
@@ -118,7 +120,6 @@ static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
118 .master = &omap3xxx_mpu_hwmod, 120 .master = &omap3xxx_mpu_hwmod,
119 .slave = &omap3xxx_l3_main_hwmod, 121 .slave = &omap3xxx_l3_main_hwmod,
120 .addr = omap3xxx_l3_main_addrs, 122 .addr = omap3xxx_l3_main_addrs,
121 .addr_cnt = ARRAY_SIZE(omap3xxx_l3_main_addrs),
122 .user = OCP_USER_MPU, 123 .user = OCP_USER_MPU,
123}; 124};
124 125
@@ -150,8 +151,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_l3_main_masters[] = {
150static struct omap_hwmod omap3xxx_l3_main_hwmod = { 151static struct omap_hwmod omap3xxx_l3_main_hwmod = {
151 .name = "l3_main", 152 .name = "l3_main",
152 .class = &l3_hwmod_class, 153 .class = &l3_hwmod_class,
153 .mpu_irqs = omap3xxx_l3_main_irqs, 154 .mpu_irqs = omap3xxx_l3_main_irqs,
154 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_l3_main_irqs),
155 .masters = omap3xxx_l3_main_masters, 155 .masters = omap3xxx_l3_main_masters,
156 .masters_cnt = ARRAY_SIZE(omap3xxx_l3_main_masters), 156 .masters_cnt = ARRAY_SIZE(omap3xxx_l3_main_masters),
157 .slaves = omap3xxx_l3_main_slaves, 157 .slaves = omap3xxx_l3_main_slaves,
@@ -190,39 +190,21 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
190}; 190};
191 191
192/* L4 CORE -> MMC1 interface */ 192/* L4 CORE -> MMC1 interface */
193static struct omap_hwmod_addr_space omap3xxx_mmc1_addr_space[] = {
194 {
195 .pa_start = 0x4809c000,
196 .pa_end = 0x4809c1ff,
197 .flags = ADDR_TYPE_RT,
198 },
199};
200
201static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc1 = { 193static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc1 = {
202 .master = &omap3xxx_l4_core_hwmod, 194 .master = &omap3xxx_l4_core_hwmod,
203 .slave = &omap3xxx_mmc1_hwmod, 195 .slave = &omap3xxx_mmc1_hwmod,
204 .clk = "mmchs1_ick", 196 .clk = "mmchs1_ick",
205 .addr = omap3xxx_mmc1_addr_space, 197 .addr = omap2430_mmc1_addr_space,
206 .addr_cnt = ARRAY_SIZE(omap3xxx_mmc1_addr_space),
207 .user = OCP_USER_MPU | OCP_USER_SDMA, 198 .user = OCP_USER_MPU | OCP_USER_SDMA,
208 .flags = OMAP_FIREWALL_L4 199 .flags = OMAP_FIREWALL_L4
209}; 200};
210 201
211/* L4 CORE -> MMC2 interface */ 202/* L4 CORE -> MMC2 interface */
212static struct omap_hwmod_addr_space omap3xxx_mmc2_addr_space[] = {
213 {
214 .pa_start = 0x480b4000,
215 .pa_end = 0x480b41ff,
216 .flags = ADDR_TYPE_RT,
217 },
218};
219
220static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc2 = { 203static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc2 = {
221 .master = &omap3xxx_l4_core_hwmod, 204 .master = &omap3xxx_l4_core_hwmod,
222 .slave = &omap3xxx_mmc2_hwmod, 205 .slave = &omap3xxx_mmc2_hwmod,
223 .clk = "mmchs2_ick", 206 .clk = "mmchs2_ick",
224 .addr = omap3xxx_mmc2_addr_space, 207 .addr = omap2430_mmc2_addr_space,
225 .addr_cnt = ARRAY_SIZE(omap3xxx_mmc2_addr_space),
226 .user = OCP_USER_MPU | OCP_USER_SDMA, 208 .user = OCP_USER_MPU | OCP_USER_SDMA,
227 .flags = OMAP_FIREWALL_L4 209 .flags = OMAP_FIREWALL_L4
228}; 210};
@@ -234,6 +216,7 @@ static struct omap_hwmod_addr_space omap3xxx_mmc3_addr_space[] = {
234 .pa_end = 0x480ad1ff, 216 .pa_end = 0x480ad1ff,
235 .flags = ADDR_TYPE_RT, 217 .flags = ADDR_TYPE_RT,
236 }, 218 },
219 { }
237}; 220};
238 221
239static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = { 222static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = {
@@ -241,7 +224,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = {
241 .slave = &omap3xxx_mmc3_hwmod, 224 .slave = &omap3xxx_mmc3_hwmod,
242 .clk = "mmchs3_ick", 225 .clk = "mmchs3_ick",
243 .addr = omap3xxx_mmc3_addr_space, 226 .addr = omap3xxx_mmc3_addr_space,
244 .addr_cnt = ARRAY_SIZE(omap3xxx_mmc3_addr_space),
245 .user = OCP_USER_MPU | OCP_USER_SDMA, 227 .user = OCP_USER_MPU | OCP_USER_SDMA,
246 .flags = OMAP_FIREWALL_L4 228 .flags = OMAP_FIREWALL_L4
247}; 229};
@@ -253,6 +235,7 @@ static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = {
253 .pa_end = OMAP3_UART1_BASE + SZ_8K - 1, 235 .pa_end = OMAP3_UART1_BASE + SZ_8K - 1,
254 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, 236 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
255 }, 237 },
238 { }
256}; 239};
257 240
258static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = { 241static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
@@ -260,7 +243,6 @@ static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
260 .slave = &omap3xxx_uart1_hwmod, 243 .slave = &omap3xxx_uart1_hwmod,
261 .clk = "uart1_ick", 244 .clk = "uart1_ick",
262 .addr = omap3xxx_uart1_addr_space, 245 .addr = omap3xxx_uart1_addr_space,
263 .addr_cnt = ARRAY_SIZE(omap3xxx_uart1_addr_space),
264 .user = OCP_USER_MPU | OCP_USER_SDMA, 246 .user = OCP_USER_MPU | OCP_USER_SDMA,
265}; 247};
266 248
@@ -271,6 +253,7 @@ static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = {
271 .pa_end = OMAP3_UART2_BASE + SZ_1K - 1, 253 .pa_end = OMAP3_UART2_BASE + SZ_1K - 1,
272 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, 254 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
273 }, 255 },
256 { }
274}; 257};
275 258
276static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = { 259static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
@@ -278,7 +261,6 @@ static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
278 .slave = &omap3xxx_uart2_hwmod, 261 .slave = &omap3xxx_uart2_hwmod,
279 .clk = "uart2_ick", 262 .clk = "uart2_ick",
280 .addr = omap3xxx_uart2_addr_space, 263 .addr = omap3xxx_uart2_addr_space,
281 .addr_cnt = ARRAY_SIZE(omap3xxx_uart2_addr_space),
282 .user = OCP_USER_MPU | OCP_USER_SDMA, 264 .user = OCP_USER_MPU | OCP_USER_SDMA,
283}; 265};
284 266
@@ -289,6 +271,7 @@ static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = {
289 .pa_end = OMAP3_UART3_BASE + SZ_1K - 1, 271 .pa_end = OMAP3_UART3_BASE + SZ_1K - 1,
290 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, 272 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
291 }, 273 },
274 { }
292}; 275};
293 276
294static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = { 277static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
@@ -296,7 +279,6 @@ static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
296 .slave = &omap3xxx_uart3_hwmod, 279 .slave = &omap3xxx_uart3_hwmod,
297 .clk = "uart3_ick", 280 .clk = "uart3_ick",
298 .addr = omap3xxx_uart3_addr_space, 281 .addr = omap3xxx_uart3_addr_space,
299 .addr_cnt = ARRAY_SIZE(omap3xxx_uart3_addr_space),
300 .user = OCP_USER_MPU | OCP_USER_SDMA, 282 .user = OCP_USER_MPU | OCP_USER_SDMA,
301}; 283};
302 284
@@ -307,6 +289,7 @@ static struct omap_hwmod_addr_space omap3xxx_uart4_addr_space[] = {
307 .pa_end = OMAP3_UART4_BASE + SZ_1K - 1, 289 .pa_end = OMAP3_UART4_BASE + SZ_1K - 1,
308 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, 290 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
309 }, 291 },
292 { }
310}; 293};
311 294
312static struct omap_hwmod_ocp_if omap3_l4_per__uart4 = { 295static struct omap_hwmod_ocp_if omap3_l4_per__uart4 = {
@@ -314,28 +297,15 @@ static struct omap_hwmod_ocp_if omap3_l4_per__uart4 = {
314 .slave = &omap3xxx_uart4_hwmod, 297 .slave = &omap3xxx_uart4_hwmod,
315 .clk = "uart4_ick", 298 .clk = "uart4_ick",
316 .addr = omap3xxx_uart4_addr_space, 299 .addr = omap3xxx_uart4_addr_space,
317 .addr_cnt = ARRAY_SIZE(omap3xxx_uart4_addr_space),
318 .user = OCP_USER_MPU | OCP_USER_SDMA, 300 .user = OCP_USER_MPU | OCP_USER_SDMA,
319}; 301};
320 302
321/* I2C IP block address space length (in bytes) */
322#define OMAP2_I2C_AS_LEN 128
323
324/* L4 CORE -> I2C1 interface */ 303/* L4 CORE -> I2C1 interface */
325static struct omap_hwmod_addr_space omap3xxx_i2c1_addr_space[] = {
326 {
327 .pa_start = 0x48070000,
328 .pa_end = 0x48070000 + OMAP2_I2C_AS_LEN - 1,
329 .flags = ADDR_TYPE_RT,
330 },
331};
332
333static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = { 304static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
334 .master = &omap3xxx_l4_core_hwmod, 305 .master = &omap3xxx_l4_core_hwmod,
335 .slave = &omap3xxx_i2c1_hwmod, 306 .slave = &omap3xxx_i2c1_hwmod,
336 .clk = "i2c1_ick", 307 .clk = "i2c1_ick",
337 .addr = omap3xxx_i2c1_addr_space, 308 .addr = omap2_i2c1_addr_space,
338 .addr_cnt = ARRAY_SIZE(omap3xxx_i2c1_addr_space),
339 .fw = { 309 .fw = {
340 .omap2 = { 310 .omap2 = {
341 .l4_fw_region = OMAP3_L4_CORE_FW_I2C1_REGION, 311 .l4_fw_region = OMAP3_L4_CORE_FW_I2C1_REGION,
@@ -347,20 +317,11 @@ static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
347}; 317};
348 318
349/* L4 CORE -> I2C2 interface */ 319/* L4 CORE -> I2C2 interface */
350static struct omap_hwmod_addr_space omap3xxx_i2c2_addr_space[] = {
351 {
352 .pa_start = 0x48072000,
353 .pa_end = 0x48072000 + OMAP2_I2C_AS_LEN - 1,
354 .flags = ADDR_TYPE_RT,
355 },
356};
357
358static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = { 320static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
359 .master = &omap3xxx_l4_core_hwmod, 321 .master = &omap3xxx_l4_core_hwmod,
360 .slave = &omap3xxx_i2c2_hwmod, 322 .slave = &omap3xxx_i2c2_hwmod,
361 .clk = "i2c2_ick", 323 .clk = "i2c2_ick",
362 .addr = omap3xxx_i2c2_addr_space, 324 .addr = omap2_i2c2_addr_space,
363 .addr_cnt = ARRAY_SIZE(omap3xxx_i2c2_addr_space),
364 .fw = { 325 .fw = {
365 .omap2 = { 326 .omap2 = {
366 .l4_fw_region = OMAP3_L4_CORE_FW_I2C2_REGION, 327 .l4_fw_region = OMAP3_L4_CORE_FW_I2C2_REGION,
@@ -375,9 +336,10 @@ static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
375static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = { 336static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = {
376 { 337 {
377 .pa_start = 0x48060000, 338 .pa_start = 0x48060000,
378 .pa_end = 0x48060000 + OMAP2_I2C_AS_LEN - 1, 339 .pa_end = 0x48060000 + SZ_128 - 1,
379 .flags = ADDR_TYPE_RT, 340 .flags = ADDR_TYPE_RT,
380 }, 341 },
342 { }
381}; 343};
382 344
383static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = { 345static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
@@ -385,7 +347,6 @@ static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
385 .slave = &omap3xxx_i2c3_hwmod, 347 .slave = &omap3xxx_i2c3_hwmod,
386 .clk = "i2c3_ick", 348 .clk = "i2c3_ick",
387 .addr = omap3xxx_i2c3_addr_space, 349 .addr = omap3xxx_i2c3_addr_space,
388 .addr_cnt = ARRAY_SIZE(omap3xxx_i2c3_addr_space),
389 .fw = { 350 .fw = {
390 .omap2 = { 351 .omap2 = {
391 .l4_fw_region = OMAP3_L4_CORE_FW_I2C3_REGION, 352 .l4_fw_region = OMAP3_L4_CORE_FW_I2C3_REGION,
@@ -403,6 +364,7 @@ static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = {
403 .pa_end = OMAP34XX_SR1_BASE + SZ_1K - 1, 364 .pa_end = OMAP34XX_SR1_BASE + SZ_1K - 1,
404 .flags = ADDR_TYPE_RT, 365 .flags = ADDR_TYPE_RT,
405 }, 366 },
367 { }
406}; 368};
407 369
408static struct omap_hwmod_ocp_if omap3_l4_core__sr1 = { 370static struct omap_hwmod_ocp_if omap3_l4_core__sr1 = {
@@ -410,7 +372,6 @@ static struct omap_hwmod_ocp_if omap3_l4_core__sr1 = {
410 .slave = &omap34xx_sr1_hwmod, 372 .slave = &omap34xx_sr1_hwmod,
411 .clk = "sr_l4_ick", 373 .clk = "sr_l4_ick",
412 .addr = omap3_sr1_addr_space, 374 .addr = omap3_sr1_addr_space,
413 .addr_cnt = ARRAY_SIZE(omap3_sr1_addr_space),
414 .user = OCP_USER_MPU, 375 .user = OCP_USER_MPU,
415}; 376};
416 377
@@ -421,6 +382,7 @@ static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = {
421 .pa_end = OMAP34XX_SR2_BASE + SZ_1K - 1, 382 .pa_end = OMAP34XX_SR2_BASE + SZ_1K - 1,
422 .flags = ADDR_TYPE_RT, 383 .flags = ADDR_TYPE_RT,
423 }, 384 },
385 { }
424}; 386};
425 387
426static struct omap_hwmod_ocp_if omap3_l4_core__sr2 = { 388static struct omap_hwmod_ocp_if omap3_l4_core__sr2 = {
@@ -428,7 +390,6 @@ static struct omap_hwmod_ocp_if omap3_l4_core__sr2 = {
428 .slave = &omap34xx_sr2_hwmod, 390 .slave = &omap34xx_sr2_hwmod,
429 .clk = "sr_l4_ick", 391 .clk = "sr_l4_ick",
430 .addr = omap3_sr2_addr_space, 392 .addr = omap3_sr2_addr_space,
431 .addr_cnt = ARRAY_SIZE(omap3_sr2_addr_space),
432 .user = OCP_USER_MPU, 393 .user = OCP_USER_MPU,
433}; 394};
434 395
@@ -442,6 +403,7 @@ static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = {
442 .pa_end = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1, 403 .pa_end = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1,
443 .flags = ADDR_TYPE_RT 404 .flags = ADDR_TYPE_RT
444 }, 405 },
406 { }
445}; 407};
446 408
447/* l4_core -> usbhsotg */ 409/* l4_core -> usbhsotg */
@@ -450,7 +412,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = {
450 .slave = &omap3xxx_usbhsotg_hwmod, 412 .slave = &omap3xxx_usbhsotg_hwmod,
451 .clk = "l4_ick", 413 .clk = "l4_ick",
452 .addr = omap3xxx_usbhsotg_addrs, 414 .addr = omap3xxx_usbhsotg_addrs,
453 .addr_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_addrs),
454 .user = OCP_USER_MPU, 415 .user = OCP_USER_MPU,
455}; 416};
456 417
@@ -468,6 +429,7 @@ static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = {
468 .pa_end = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1, 429 .pa_end = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1,
469 .flags = ADDR_TYPE_RT 430 .flags = ADDR_TYPE_RT
470 }, 431 },
432 { }
471}; 433};
472 434
473/* l4_core -> usbhsotg */ 435/* l4_core -> usbhsotg */
@@ -476,7 +438,6 @@ static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = {
476 .slave = &am35xx_usbhsotg_hwmod, 438 .slave = &am35xx_usbhsotg_hwmod,
477 .clk = "l4_ick", 439 .clk = "l4_ick",
478 .addr = am35xx_usbhsotg_addrs, 440 .addr = am35xx_usbhsotg_addrs,
479 .addr_cnt = ARRAY_SIZE(am35xx_usbhsotg_addrs),
480 .user = OCP_USER_MPU, 441 .user = OCP_USER_MPU,
481}; 442};
482 443
@@ -611,9 +572,6 @@ static struct omap_hwmod_class omap3xxx_timer_hwmod_class = {
611 572
612/* timer1 */ 573/* timer1 */
613static struct omap_hwmod omap3xxx_timer1_hwmod; 574static struct omap_hwmod omap3xxx_timer1_hwmod;
614static struct omap_hwmod_irq_info omap3xxx_timer1_mpu_irqs[] = {
615 { .irq = 37, },
616};
617 575
618static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = { 576static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = {
619 { 577 {
@@ -621,6 +579,7 @@ static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = {
621 .pa_end = 0x48318000 + SZ_1K - 1, 579 .pa_end = 0x48318000 + SZ_1K - 1,
622 .flags = ADDR_TYPE_RT 580 .flags = ADDR_TYPE_RT
623 }, 581 },
582 { }
624}; 583};
625 584
626/* l4_wkup -> timer1 */ 585/* l4_wkup -> timer1 */
@@ -629,7 +588,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = {
629 .slave = &omap3xxx_timer1_hwmod, 588 .slave = &omap3xxx_timer1_hwmod,
630 .clk = "gpt1_ick", 589 .clk = "gpt1_ick",
631 .addr = omap3xxx_timer1_addrs, 590 .addr = omap3xxx_timer1_addrs,
632 .addr_cnt = ARRAY_SIZE(omap3xxx_timer1_addrs),
633 .user = OCP_USER_MPU | OCP_USER_SDMA, 591 .user = OCP_USER_MPU | OCP_USER_SDMA,
634}; 592};
635 593
@@ -641,8 +599,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_timer1_slaves[] = {
641/* timer1 hwmod */ 599/* timer1 hwmod */
642static struct omap_hwmod omap3xxx_timer1_hwmod = { 600static struct omap_hwmod omap3xxx_timer1_hwmod = {
643 .name = "timer1", 601 .name = "timer1",
644 .mpu_irqs = omap3xxx_timer1_mpu_irqs, 602 .mpu_irqs = omap2_timer1_mpu_irqs,
645 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer1_mpu_irqs),
646 .main_clk = "gpt1_fck", 603 .main_clk = "gpt1_fck",
647 .prcm = { 604 .prcm = {
648 .omap2 = { 605 .omap2 = {
@@ -661,9 +618,6 @@ static struct omap_hwmod omap3xxx_timer1_hwmod = {
661 618
662/* timer2 */ 619/* timer2 */
663static struct omap_hwmod omap3xxx_timer2_hwmod; 620static struct omap_hwmod omap3xxx_timer2_hwmod;
664static struct omap_hwmod_irq_info omap3xxx_timer2_mpu_irqs[] = {
665 { .irq = 38, },
666};
667 621
668static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = { 622static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = {
669 { 623 {
@@ -671,6 +625,7 @@ static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = {
671 .pa_end = 0x49032000 + SZ_1K - 1, 625 .pa_end = 0x49032000 + SZ_1K - 1,
672 .flags = ADDR_TYPE_RT 626 .flags = ADDR_TYPE_RT
673 }, 627 },
628 { }
674}; 629};
675 630
676/* l4_per -> timer2 */ 631/* l4_per -> timer2 */
@@ -679,7 +634,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = {
679 .slave = &omap3xxx_timer2_hwmod, 634 .slave = &omap3xxx_timer2_hwmod,
680 .clk = "gpt2_ick", 635 .clk = "gpt2_ick",
681 .addr = omap3xxx_timer2_addrs, 636 .addr = omap3xxx_timer2_addrs,
682 .addr_cnt = ARRAY_SIZE(omap3xxx_timer2_addrs),
683 .user = OCP_USER_MPU | OCP_USER_SDMA, 637 .user = OCP_USER_MPU | OCP_USER_SDMA,
684}; 638};
685 639
@@ -691,8 +645,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_timer2_slaves[] = {
691/* timer2 hwmod */ 645/* timer2 hwmod */
692static struct omap_hwmod omap3xxx_timer2_hwmod = { 646static struct omap_hwmod omap3xxx_timer2_hwmod = {
693 .name = "timer2", 647 .name = "timer2",
694 .mpu_irqs = omap3xxx_timer2_mpu_irqs, 648 .mpu_irqs = omap2_timer2_mpu_irqs,
695 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer2_mpu_irqs),
696 .main_clk = "gpt2_fck", 649 .main_clk = "gpt2_fck",
697 .prcm = { 650 .prcm = {
698 .omap2 = { 651 .omap2 = {
@@ -711,9 +664,6 @@ static struct omap_hwmod omap3xxx_timer2_hwmod = {
711 664
712/* timer3 */ 665/* timer3 */
713static struct omap_hwmod omap3xxx_timer3_hwmod; 666static struct omap_hwmod omap3xxx_timer3_hwmod;
714static struct omap_hwmod_irq_info omap3xxx_timer3_mpu_irqs[] = {
715 { .irq = 39, },
716};
717 667
718static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = { 668static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = {
719 { 669 {
@@ -721,6 +671,7 @@ static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = {
721 .pa_end = 0x49034000 + SZ_1K - 1, 671 .pa_end = 0x49034000 + SZ_1K - 1,
722 .flags = ADDR_TYPE_RT 672 .flags = ADDR_TYPE_RT
723 }, 673 },
674 { }
724}; 675};
725 676
726/* l4_per -> timer3 */ 677/* l4_per -> timer3 */
@@ -729,7 +680,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = {
729 .slave = &omap3xxx_timer3_hwmod, 680 .slave = &omap3xxx_timer3_hwmod,
730 .clk = "gpt3_ick", 681 .clk = "gpt3_ick",
731 .addr = omap3xxx_timer3_addrs, 682 .addr = omap3xxx_timer3_addrs,
732 .addr_cnt = ARRAY_SIZE(omap3xxx_timer3_addrs),
733 .user = OCP_USER_MPU | OCP_USER_SDMA, 683 .user = OCP_USER_MPU | OCP_USER_SDMA,
734}; 684};
735 685
@@ -741,8 +691,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_timer3_slaves[] = {
741/* timer3 hwmod */ 691/* timer3 hwmod */
742static struct omap_hwmod omap3xxx_timer3_hwmod = { 692static struct omap_hwmod omap3xxx_timer3_hwmod = {
743 .name = "timer3", 693 .name = "timer3",
744 .mpu_irqs = omap3xxx_timer3_mpu_irqs, 694 .mpu_irqs = omap2_timer3_mpu_irqs,
745 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer3_mpu_irqs),
746 .main_clk = "gpt3_fck", 695 .main_clk = "gpt3_fck",
747 .prcm = { 696 .prcm = {
748 .omap2 = { 697 .omap2 = {
@@ -761,9 +710,6 @@ static struct omap_hwmod omap3xxx_timer3_hwmod = {
761 710
762/* timer4 */ 711/* timer4 */
763static struct omap_hwmod omap3xxx_timer4_hwmod; 712static struct omap_hwmod omap3xxx_timer4_hwmod;
764static struct omap_hwmod_irq_info omap3xxx_timer4_mpu_irqs[] = {
765 { .irq = 40, },
766};
767 713
768static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = { 714static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = {
769 { 715 {
@@ -771,6 +717,7 @@ static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = {
771 .pa_end = 0x49036000 + SZ_1K - 1, 717 .pa_end = 0x49036000 + SZ_1K - 1,
772 .flags = ADDR_TYPE_RT 718 .flags = ADDR_TYPE_RT
773 }, 719 },
720 { }
774}; 721};
775 722
776/* l4_per -> timer4 */ 723/* l4_per -> timer4 */
@@ -779,7 +726,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = {
779 .slave = &omap3xxx_timer4_hwmod, 726 .slave = &omap3xxx_timer4_hwmod,
780 .clk = "gpt4_ick", 727 .clk = "gpt4_ick",
781 .addr = omap3xxx_timer4_addrs, 728 .addr = omap3xxx_timer4_addrs,
782 .addr_cnt = ARRAY_SIZE(omap3xxx_timer4_addrs),
783 .user = OCP_USER_MPU | OCP_USER_SDMA, 729 .user = OCP_USER_MPU | OCP_USER_SDMA,
784}; 730};
785 731
@@ -791,8 +737,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_timer4_slaves[] = {
791/* timer4 hwmod */ 737/* timer4 hwmod */
792static struct omap_hwmod omap3xxx_timer4_hwmod = { 738static struct omap_hwmod omap3xxx_timer4_hwmod = {
793 .name = "timer4", 739 .name = "timer4",
794 .mpu_irqs = omap3xxx_timer4_mpu_irqs, 740 .mpu_irqs = omap2_timer4_mpu_irqs,
795 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer4_mpu_irqs),
796 .main_clk = "gpt4_fck", 741 .main_clk = "gpt4_fck",
797 .prcm = { 742 .prcm = {
798 .omap2 = { 743 .omap2 = {
@@ -811,9 +756,6 @@ static struct omap_hwmod omap3xxx_timer4_hwmod = {
811 756
812/* timer5 */ 757/* timer5 */
813static struct omap_hwmod omap3xxx_timer5_hwmod; 758static struct omap_hwmod omap3xxx_timer5_hwmod;
814static struct omap_hwmod_irq_info omap3xxx_timer5_mpu_irqs[] = {
815 { .irq = 41, },
816};
817 759
818static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = { 760static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = {
819 { 761 {
@@ -821,6 +763,7 @@ static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = {
821 .pa_end = 0x49038000 + SZ_1K - 1, 763 .pa_end = 0x49038000 + SZ_1K - 1,
822 .flags = ADDR_TYPE_RT 764 .flags = ADDR_TYPE_RT
823 }, 765 },
766 { }
824}; 767};
825 768
826/* l4_per -> timer5 */ 769/* l4_per -> timer5 */
@@ -829,7 +772,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = {
829 .slave = &omap3xxx_timer5_hwmod, 772 .slave = &omap3xxx_timer5_hwmod,
830 .clk = "gpt5_ick", 773 .clk = "gpt5_ick",
831 .addr = omap3xxx_timer5_addrs, 774 .addr = omap3xxx_timer5_addrs,
832 .addr_cnt = ARRAY_SIZE(omap3xxx_timer5_addrs),
833 .user = OCP_USER_MPU | OCP_USER_SDMA, 775 .user = OCP_USER_MPU | OCP_USER_SDMA,
834}; 776};
835 777
@@ -841,8 +783,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_timer5_slaves[] = {
841/* timer5 hwmod */ 783/* timer5 hwmod */
842static struct omap_hwmod omap3xxx_timer5_hwmod = { 784static struct omap_hwmod omap3xxx_timer5_hwmod = {
843 .name = "timer5", 785 .name = "timer5",
844 .mpu_irqs = omap3xxx_timer5_mpu_irqs, 786 .mpu_irqs = omap2_timer5_mpu_irqs,
845 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer5_mpu_irqs),
846 .main_clk = "gpt5_fck", 787 .main_clk = "gpt5_fck",
847 .prcm = { 788 .prcm = {
848 .omap2 = { 789 .omap2 = {
@@ -861,9 +802,6 @@ static struct omap_hwmod omap3xxx_timer5_hwmod = {
861 802
862/* timer6 */ 803/* timer6 */
863static struct omap_hwmod omap3xxx_timer6_hwmod; 804static struct omap_hwmod omap3xxx_timer6_hwmod;
864static struct omap_hwmod_irq_info omap3xxx_timer6_mpu_irqs[] = {
865 { .irq = 42, },
866};
867 805
868static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = { 806static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = {
869 { 807 {
@@ -871,6 +809,7 @@ static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = {
871 .pa_end = 0x4903A000 + SZ_1K - 1, 809 .pa_end = 0x4903A000 + SZ_1K - 1,
872 .flags = ADDR_TYPE_RT 810 .flags = ADDR_TYPE_RT
873 }, 811 },
812 { }
874}; 813};
875 814
876/* l4_per -> timer6 */ 815/* l4_per -> timer6 */
@@ -879,7 +818,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = {
879 .slave = &omap3xxx_timer6_hwmod, 818 .slave = &omap3xxx_timer6_hwmod,
880 .clk = "gpt6_ick", 819 .clk = "gpt6_ick",
881 .addr = omap3xxx_timer6_addrs, 820 .addr = omap3xxx_timer6_addrs,
882 .addr_cnt = ARRAY_SIZE(omap3xxx_timer6_addrs),
883 .user = OCP_USER_MPU | OCP_USER_SDMA, 821 .user = OCP_USER_MPU | OCP_USER_SDMA,
884}; 822};
885 823
@@ -891,8 +829,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_timer6_slaves[] = {
891/* timer6 hwmod */ 829/* timer6 hwmod */
892static struct omap_hwmod omap3xxx_timer6_hwmod = { 830static struct omap_hwmod omap3xxx_timer6_hwmod = {
893 .name = "timer6", 831 .name = "timer6",
894 .mpu_irqs = omap3xxx_timer6_mpu_irqs, 832 .mpu_irqs = omap2_timer6_mpu_irqs,
895 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer6_mpu_irqs),
896 .main_clk = "gpt6_fck", 833 .main_clk = "gpt6_fck",
897 .prcm = { 834 .prcm = {
898 .omap2 = { 835 .omap2 = {
@@ -911,9 +848,6 @@ static struct omap_hwmod omap3xxx_timer6_hwmod = {
911 848
912/* timer7 */ 849/* timer7 */
913static struct omap_hwmod omap3xxx_timer7_hwmod; 850static struct omap_hwmod omap3xxx_timer7_hwmod;
914static struct omap_hwmod_irq_info omap3xxx_timer7_mpu_irqs[] = {
915 { .irq = 43, },
916};
917 851
918static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = { 852static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = {
919 { 853 {
@@ -921,6 +855,7 @@ static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = {
921 .pa_end = 0x4903C000 + SZ_1K - 1, 855 .pa_end = 0x4903C000 + SZ_1K - 1,
922 .flags = ADDR_TYPE_RT 856 .flags = ADDR_TYPE_RT
923 }, 857 },
858 { }
924}; 859};
925 860
926/* l4_per -> timer7 */ 861/* l4_per -> timer7 */
@@ -929,7 +864,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = {
929 .slave = &omap3xxx_timer7_hwmod, 864 .slave = &omap3xxx_timer7_hwmod,
930 .clk = "gpt7_ick", 865 .clk = "gpt7_ick",
931 .addr = omap3xxx_timer7_addrs, 866 .addr = omap3xxx_timer7_addrs,
932 .addr_cnt = ARRAY_SIZE(omap3xxx_timer7_addrs),
933 .user = OCP_USER_MPU | OCP_USER_SDMA, 867 .user = OCP_USER_MPU | OCP_USER_SDMA,
934}; 868};
935 869
@@ -941,8 +875,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_timer7_slaves[] = {
941/* timer7 hwmod */ 875/* timer7 hwmod */
942static struct omap_hwmod omap3xxx_timer7_hwmod = { 876static struct omap_hwmod omap3xxx_timer7_hwmod = {
943 .name = "timer7", 877 .name = "timer7",
944 .mpu_irqs = omap3xxx_timer7_mpu_irqs, 878 .mpu_irqs = omap2_timer7_mpu_irqs,
945 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer7_mpu_irqs),
946 .main_clk = "gpt7_fck", 879 .main_clk = "gpt7_fck",
947 .prcm = { 880 .prcm = {
948 .omap2 = { 881 .omap2 = {
@@ -961,9 +894,6 @@ static struct omap_hwmod omap3xxx_timer7_hwmod = {
961 894
962/* timer8 */ 895/* timer8 */
963static struct omap_hwmod omap3xxx_timer8_hwmod; 896static struct omap_hwmod omap3xxx_timer8_hwmod;
964static struct omap_hwmod_irq_info omap3xxx_timer8_mpu_irqs[] = {
965 { .irq = 44, },
966};
967 897
968static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = { 898static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = {
969 { 899 {
@@ -971,6 +901,7 @@ static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = {
971 .pa_end = 0x4903E000 + SZ_1K - 1, 901 .pa_end = 0x4903E000 + SZ_1K - 1,
972 .flags = ADDR_TYPE_RT 902 .flags = ADDR_TYPE_RT
973 }, 903 },
904 { }
974}; 905};
975 906
976/* l4_per -> timer8 */ 907/* l4_per -> timer8 */
@@ -979,7 +910,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = {
979 .slave = &omap3xxx_timer8_hwmod, 910 .slave = &omap3xxx_timer8_hwmod,
980 .clk = "gpt8_ick", 911 .clk = "gpt8_ick",
981 .addr = omap3xxx_timer8_addrs, 912 .addr = omap3xxx_timer8_addrs,
982 .addr_cnt = ARRAY_SIZE(omap3xxx_timer8_addrs),
983 .user = OCP_USER_MPU | OCP_USER_SDMA, 913 .user = OCP_USER_MPU | OCP_USER_SDMA,
984}; 914};
985 915
@@ -991,8 +921,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_timer8_slaves[] = {
991/* timer8 hwmod */ 921/* timer8 hwmod */
992static struct omap_hwmod omap3xxx_timer8_hwmod = { 922static struct omap_hwmod omap3xxx_timer8_hwmod = {
993 .name = "timer8", 923 .name = "timer8",
994 .mpu_irqs = omap3xxx_timer8_mpu_irqs, 924 .mpu_irqs = omap2_timer8_mpu_irqs,
995 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer8_mpu_irqs),
996 .main_clk = "gpt8_fck", 925 .main_clk = "gpt8_fck",
997 .prcm = { 926 .prcm = {
998 .omap2 = { 927 .omap2 = {
@@ -1011,9 +940,6 @@ static struct omap_hwmod omap3xxx_timer8_hwmod = {
1011 940
1012/* timer9 */ 941/* timer9 */
1013static struct omap_hwmod omap3xxx_timer9_hwmod; 942static struct omap_hwmod omap3xxx_timer9_hwmod;
1014static struct omap_hwmod_irq_info omap3xxx_timer9_mpu_irqs[] = {
1015 { .irq = 45, },
1016};
1017 943
1018static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = { 944static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = {
1019 { 945 {
@@ -1021,6 +947,7 @@ static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = {
1021 .pa_end = 0x49040000 + SZ_1K - 1, 947 .pa_end = 0x49040000 + SZ_1K - 1,
1022 .flags = ADDR_TYPE_RT 948 .flags = ADDR_TYPE_RT
1023 }, 949 },
950 { }
1024}; 951};
1025 952
1026/* l4_per -> timer9 */ 953/* l4_per -> timer9 */
@@ -1029,7 +956,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = {
1029 .slave = &omap3xxx_timer9_hwmod, 956 .slave = &omap3xxx_timer9_hwmod,
1030 .clk = "gpt9_ick", 957 .clk = "gpt9_ick",
1031 .addr = omap3xxx_timer9_addrs, 958 .addr = omap3xxx_timer9_addrs,
1032 .addr_cnt = ARRAY_SIZE(omap3xxx_timer9_addrs),
1033 .user = OCP_USER_MPU | OCP_USER_SDMA, 959 .user = OCP_USER_MPU | OCP_USER_SDMA,
1034}; 960};
1035 961
@@ -1041,8 +967,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_timer9_slaves[] = {
1041/* timer9 hwmod */ 967/* timer9 hwmod */
1042static struct omap_hwmod omap3xxx_timer9_hwmod = { 968static struct omap_hwmod omap3xxx_timer9_hwmod = {
1043 .name = "timer9", 969 .name = "timer9",
1044 .mpu_irqs = omap3xxx_timer9_mpu_irqs, 970 .mpu_irqs = omap2_timer9_mpu_irqs,
1045 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer9_mpu_irqs),
1046 .main_clk = "gpt9_fck", 971 .main_clk = "gpt9_fck",
1047 .prcm = { 972 .prcm = {
1048 .omap2 = { 973 .omap2 = {
@@ -1061,25 +986,13 @@ static struct omap_hwmod omap3xxx_timer9_hwmod = {
1061 986
1062/* timer10 */ 987/* timer10 */
1063static struct omap_hwmod omap3xxx_timer10_hwmod; 988static struct omap_hwmod omap3xxx_timer10_hwmod;
1064static struct omap_hwmod_irq_info omap3xxx_timer10_mpu_irqs[] = {
1065 { .irq = 46, },
1066};
1067
1068static struct omap_hwmod_addr_space omap3xxx_timer10_addrs[] = {
1069 {
1070 .pa_start = 0x48086000,
1071 .pa_end = 0x48086000 + SZ_1K - 1,
1072 .flags = ADDR_TYPE_RT
1073 },
1074};
1075 989
1076/* l4_core -> timer10 */ 990/* l4_core -> timer10 */
1077static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = { 991static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = {
1078 .master = &omap3xxx_l4_core_hwmod, 992 .master = &omap3xxx_l4_core_hwmod,
1079 .slave = &omap3xxx_timer10_hwmod, 993 .slave = &omap3xxx_timer10_hwmod,
1080 .clk = "gpt10_ick", 994 .clk = "gpt10_ick",
1081 .addr = omap3xxx_timer10_addrs, 995 .addr = omap2_timer10_addrs,
1082 .addr_cnt = ARRAY_SIZE(omap3xxx_timer10_addrs),
1083 .user = OCP_USER_MPU | OCP_USER_SDMA, 996 .user = OCP_USER_MPU | OCP_USER_SDMA,
1084}; 997};
1085 998
@@ -1091,8 +1004,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_timer10_slaves[] = {
1091/* timer10 hwmod */ 1004/* timer10 hwmod */
1092static struct omap_hwmod omap3xxx_timer10_hwmod = { 1005static struct omap_hwmod omap3xxx_timer10_hwmod = {
1093 .name = "timer10", 1006 .name = "timer10",
1094 .mpu_irqs = omap3xxx_timer10_mpu_irqs, 1007 .mpu_irqs = omap2_timer10_mpu_irqs,
1095 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer10_mpu_irqs),
1096 .main_clk = "gpt10_fck", 1008 .main_clk = "gpt10_fck",
1097 .prcm = { 1009 .prcm = {
1098 .omap2 = { 1010 .omap2 = {
@@ -1111,25 +1023,13 @@ static struct omap_hwmod omap3xxx_timer10_hwmod = {
1111 1023
1112/* timer11 */ 1024/* timer11 */
1113static struct omap_hwmod omap3xxx_timer11_hwmod; 1025static struct omap_hwmod omap3xxx_timer11_hwmod;
1114static struct omap_hwmod_irq_info omap3xxx_timer11_mpu_irqs[] = {
1115 { .irq = 47, },
1116};
1117
1118static struct omap_hwmod_addr_space omap3xxx_timer11_addrs[] = {
1119 {
1120 .pa_start = 0x48088000,
1121 .pa_end = 0x48088000 + SZ_1K - 1,
1122 .flags = ADDR_TYPE_RT
1123 },
1124};
1125 1026
1126/* l4_core -> timer11 */ 1027/* l4_core -> timer11 */
1127static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = { 1028static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = {
1128 .master = &omap3xxx_l4_core_hwmod, 1029 .master = &omap3xxx_l4_core_hwmod,
1129 .slave = &omap3xxx_timer11_hwmod, 1030 .slave = &omap3xxx_timer11_hwmod,
1130 .clk = "gpt11_ick", 1031 .clk = "gpt11_ick",
1131 .addr = omap3xxx_timer11_addrs, 1032 .addr = omap2_timer11_addrs,
1132 .addr_cnt = ARRAY_SIZE(omap3xxx_timer11_addrs),
1133 .user = OCP_USER_MPU | OCP_USER_SDMA, 1033 .user = OCP_USER_MPU | OCP_USER_SDMA,
1134}; 1034};
1135 1035
@@ -1141,8 +1041,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_timer11_slaves[] = {
1141/* timer11 hwmod */ 1041/* timer11 hwmod */
1142static struct omap_hwmod omap3xxx_timer11_hwmod = { 1042static struct omap_hwmod omap3xxx_timer11_hwmod = {
1143 .name = "timer11", 1043 .name = "timer11",
1144 .mpu_irqs = omap3xxx_timer11_mpu_irqs, 1044 .mpu_irqs = omap2_timer11_mpu_irqs,
1145 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer11_mpu_irqs),
1146 .main_clk = "gpt11_fck", 1045 .main_clk = "gpt11_fck",
1147 .prcm = { 1046 .prcm = {
1148 .omap2 = { 1047 .omap2 = {
@@ -1163,6 +1062,7 @@ static struct omap_hwmod omap3xxx_timer11_hwmod = {
1163static struct omap_hwmod omap3xxx_timer12_hwmod; 1062static struct omap_hwmod omap3xxx_timer12_hwmod;
1164static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = { 1063static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = {
1165 { .irq = 95, }, 1064 { .irq = 95, },
1065 { .irq = -1 }
1166}; 1066};
1167 1067
1168static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = { 1068static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = {
@@ -1171,6 +1071,7 @@ static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = {
1171 .pa_end = 0x48304000 + SZ_1K - 1, 1071 .pa_end = 0x48304000 + SZ_1K - 1,
1172 .flags = ADDR_TYPE_RT 1072 .flags = ADDR_TYPE_RT
1173 }, 1073 },
1074 { }
1174}; 1075};
1175 1076
1176/* l4_core -> timer12 */ 1077/* l4_core -> timer12 */
@@ -1179,7 +1080,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer12 = {
1179 .slave = &omap3xxx_timer12_hwmod, 1080 .slave = &omap3xxx_timer12_hwmod,
1180 .clk = "gpt12_ick", 1081 .clk = "gpt12_ick",
1181 .addr = omap3xxx_timer12_addrs, 1082 .addr = omap3xxx_timer12_addrs,
1182 .addr_cnt = ARRAY_SIZE(omap3xxx_timer12_addrs),
1183 .user = OCP_USER_MPU | OCP_USER_SDMA, 1083 .user = OCP_USER_MPU | OCP_USER_SDMA,
1184}; 1084};
1185 1085
@@ -1192,7 +1092,6 @@ static struct omap_hwmod_ocp_if *omap3xxx_timer12_slaves[] = {
1192static struct omap_hwmod omap3xxx_timer12_hwmod = { 1092static struct omap_hwmod omap3xxx_timer12_hwmod = {
1193 .name = "timer12", 1093 .name = "timer12",
1194 .mpu_irqs = omap3xxx_timer12_mpu_irqs, 1094 .mpu_irqs = omap3xxx_timer12_mpu_irqs,
1195 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer12_mpu_irqs),
1196 .main_clk = "gpt12_fck", 1095 .main_clk = "gpt12_fck",
1197 .prcm = { 1096 .prcm = {
1198 .omap2 = { 1097 .omap2 = {
@@ -1216,6 +1115,7 @@ static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = {
1216 .pa_end = 0x4831407f, 1115 .pa_end = 0x4831407f,
1217 .flags = ADDR_TYPE_RT 1116 .flags = ADDR_TYPE_RT
1218 }, 1117 },
1118 { }
1219}; 1119};
1220 1120
1221static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = { 1121static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
@@ -1223,7 +1123,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
1223 .slave = &omap3xxx_wd_timer2_hwmod, 1123 .slave = &omap3xxx_wd_timer2_hwmod,
1224 .clk = "wdt2_ick", 1124 .clk = "wdt2_ick",
1225 .addr = omap3xxx_wd_timer2_addrs, 1125 .addr = omap3xxx_wd_timer2_addrs,
1226 .addr_cnt = ARRAY_SIZE(omap3xxx_wd_timer2_addrs),
1227 .user = OCP_USER_MPU | OCP_USER_SDMA, 1126 .user = OCP_USER_MPU | OCP_USER_SDMA,
1228}; 1127};
1229 1128
@@ -1291,45 +1190,16 @@ static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
1291 .flags = HWMOD_SWSUP_SIDLE, 1190 .flags = HWMOD_SWSUP_SIDLE,
1292}; 1191};
1293 1192
1294/* UART common */
1295
1296static struct omap_hwmod_class_sysconfig uart_sysc = {
1297 .rev_offs = 0x50,
1298 .sysc_offs = 0x54,
1299 .syss_offs = 0x58,
1300 .sysc_flags = (SYSC_HAS_SIDLEMODE |
1301 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1302 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1303 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1304 .sysc_fields = &omap_hwmod_sysc_type1,
1305};
1306
1307static struct omap_hwmod_class uart_class = {
1308 .name = "uart",
1309 .sysc = &uart_sysc,
1310};
1311
1312/* UART1 */ 1193/* UART1 */
1313 1194
1314static struct omap_hwmod_irq_info uart1_mpu_irqs[] = {
1315 { .irq = INT_24XX_UART1_IRQ, },
1316};
1317
1318static struct omap_hwmod_dma_info uart1_sdma_reqs[] = {
1319 { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, },
1320 { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, },
1321};
1322
1323static struct omap_hwmod_ocp_if *omap3xxx_uart1_slaves[] = { 1195static struct omap_hwmod_ocp_if *omap3xxx_uart1_slaves[] = {
1324 &omap3_l4_core__uart1, 1196 &omap3_l4_core__uart1,
1325}; 1197};
1326 1198
1327static struct omap_hwmod omap3xxx_uart1_hwmod = { 1199static struct omap_hwmod omap3xxx_uart1_hwmod = {
1328 .name = "uart1", 1200 .name = "uart1",
1329 .mpu_irqs = uart1_mpu_irqs, 1201 .mpu_irqs = omap2_uart1_mpu_irqs,
1330 .mpu_irqs_cnt = ARRAY_SIZE(uart1_mpu_irqs), 1202 .sdma_reqs = omap2_uart1_sdma_reqs,
1331 .sdma_reqs = uart1_sdma_reqs,
1332 .sdma_reqs_cnt = ARRAY_SIZE(uart1_sdma_reqs),
1333 .main_clk = "uart1_fck", 1203 .main_clk = "uart1_fck",
1334 .prcm = { 1204 .prcm = {
1335 .omap2 = { 1205 .omap2 = {
@@ -1342,31 +1212,20 @@ static struct omap_hwmod omap3xxx_uart1_hwmod = {
1342 }, 1212 },
1343 .slaves = omap3xxx_uart1_slaves, 1213 .slaves = omap3xxx_uart1_slaves,
1344 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart1_slaves), 1214 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart1_slaves),
1345 .class = &uart_class, 1215 .class = &omap2_uart_class,
1346 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), 1216 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1347}; 1217};
1348 1218
1349/* UART2 */ 1219/* UART2 */
1350 1220
1351static struct omap_hwmod_irq_info uart2_mpu_irqs[] = {
1352 { .irq = INT_24XX_UART2_IRQ, },
1353};
1354
1355static struct omap_hwmod_dma_info uart2_sdma_reqs[] = {
1356 { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, },
1357 { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, },
1358};
1359
1360static struct omap_hwmod_ocp_if *omap3xxx_uart2_slaves[] = { 1221static struct omap_hwmod_ocp_if *omap3xxx_uart2_slaves[] = {
1361 &omap3_l4_core__uart2, 1222 &omap3_l4_core__uart2,
1362}; 1223};
1363 1224
1364static struct omap_hwmod omap3xxx_uart2_hwmod = { 1225static struct omap_hwmod omap3xxx_uart2_hwmod = {
1365 .name = "uart2", 1226 .name = "uart2",
1366 .mpu_irqs = uart2_mpu_irqs, 1227 .mpu_irqs = omap2_uart2_mpu_irqs,
1367 .mpu_irqs_cnt = ARRAY_SIZE(uart2_mpu_irqs), 1228 .sdma_reqs = omap2_uart2_sdma_reqs,
1368 .sdma_reqs = uart2_sdma_reqs,
1369 .sdma_reqs_cnt = ARRAY_SIZE(uart2_sdma_reqs),
1370 .main_clk = "uart2_fck", 1229 .main_clk = "uart2_fck",
1371 .prcm = { 1230 .prcm = {
1372 .omap2 = { 1231 .omap2 = {
@@ -1379,31 +1238,20 @@ static struct omap_hwmod omap3xxx_uart2_hwmod = {
1379 }, 1238 },
1380 .slaves = omap3xxx_uart2_slaves, 1239 .slaves = omap3xxx_uart2_slaves,
1381 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart2_slaves), 1240 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart2_slaves),
1382 .class = &uart_class, 1241 .class = &omap2_uart_class,
1383 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), 1242 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1384}; 1243};
1385 1244
1386/* UART3 */ 1245/* UART3 */
1387 1246
1388static struct omap_hwmod_irq_info uart3_mpu_irqs[] = {
1389 { .irq = INT_24XX_UART3_IRQ, },
1390};
1391
1392static struct omap_hwmod_dma_info uart3_sdma_reqs[] = {
1393 { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, },
1394 { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, },
1395};
1396
1397static struct omap_hwmod_ocp_if *omap3xxx_uart3_slaves[] = { 1247static struct omap_hwmod_ocp_if *omap3xxx_uart3_slaves[] = {
1398 &omap3_l4_per__uart3, 1248 &omap3_l4_per__uart3,
1399}; 1249};
1400 1250
1401static struct omap_hwmod omap3xxx_uart3_hwmod = { 1251static struct omap_hwmod omap3xxx_uart3_hwmod = {
1402 .name = "uart3", 1252 .name = "uart3",
1403 .mpu_irqs = uart3_mpu_irqs, 1253 .mpu_irqs = omap2_uart3_mpu_irqs,
1404 .mpu_irqs_cnt = ARRAY_SIZE(uart3_mpu_irqs), 1254 .sdma_reqs = omap2_uart3_sdma_reqs,
1405 .sdma_reqs = uart3_sdma_reqs,
1406 .sdma_reqs_cnt = ARRAY_SIZE(uart3_sdma_reqs),
1407 .main_clk = "uart3_fck", 1255 .main_clk = "uart3_fck",
1408 .prcm = { 1256 .prcm = {
1409 .omap2 = { 1257 .omap2 = {
@@ -1416,7 +1264,7 @@ static struct omap_hwmod omap3xxx_uart3_hwmod = {
1416 }, 1264 },
1417 .slaves = omap3xxx_uart3_slaves, 1265 .slaves = omap3xxx_uart3_slaves,
1418 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart3_slaves), 1266 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart3_slaves),
1419 .class = &uart_class, 1267 .class = &omap2_uart_class,
1420 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), 1268 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1421}; 1269};
1422 1270
@@ -1424,11 +1272,13 @@ static struct omap_hwmod omap3xxx_uart3_hwmod = {
1424 1272
1425static struct omap_hwmod_irq_info uart4_mpu_irqs[] = { 1273static struct omap_hwmod_irq_info uart4_mpu_irqs[] = {
1426 { .irq = INT_36XX_UART4_IRQ, }, 1274 { .irq = INT_36XX_UART4_IRQ, },
1275 { .irq = -1 }
1427}; 1276};
1428 1277
1429static struct omap_hwmod_dma_info uart4_sdma_reqs[] = { 1278static struct omap_hwmod_dma_info uart4_sdma_reqs[] = {
1430 { .name = "rx", .dma_req = OMAP36XX_DMA_UART4_RX, }, 1279 { .name = "rx", .dma_req = OMAP36XX_DMA_UART4_RX, },
1431 { .name = "tx", .dma_req = OMAP36XX_DMA_UART4_TX, }, 1280 { .name = "tx", .dma_req = OMAP36XX_DMA_UART4_TX, },
1281 { .dma_req = -1 }
1432}; 1282};
1433 1283
1434static struct omap_hwmod_ocp_if *omap3xxx_uart4_slaves[] = { 1284static struct omap_hwmod_ocp_if *omap3xxx_uart4_slaves[] = {
@@ -1438,9 +1288,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_uart4_slaves[] = {
1438static struct omap_hwmod omap3xxx_uart4_hwmod = { 1288static struct omap_hwmod omap3xxx_uart4_hwmod = {
1439 .name = "uart4", 1289 .name = "uart4",
1440 .mpu_irqs = uart4_mpu_irqs, 1290 .mpu_irqs = uart4_mpu_irqs,
1441 .mpu_irqs_cnt = ARRAY_SIZE(uart4_mpu_irqs),
1442 .sdma_reqs = uart4_sdma_reqs, 1291 .sdma_reqs = uart4_sdma_reqs,
1443 .sdma_reqs_cnt = ARRAY_SIZE(uart4_sdma_reqs),
1444 .main_clk = "uart4_fck", 1292 .main_clk = "uart4_fck",
1445 .prcm = { 1293 .prcm = {
1446 .omap2 = { 1294 .omap2 = {
@@ -1453,7 +1301,7 @@ static struct omap_hwmod omap3xxx_uart4_hwmod = {
1453 }, 1301 },
1454 .slaves = omap3xxx_uart4_slaves, 1302 .slaves = omap3xxx_uart4_slaves,
1455 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart4_slaves), 1303 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart4_slaves),
1456 .class = &uart_class, 1304 .class = &omap2_uart_class,
1457 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1), 1305 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
1458}; 1306};
1459 1307
@@ -1462,27 +1310,10 @@ static struct omap_hwmod_class i2c_class = {
1462 .sysc = &i2c_sysc, 1310 .sysc = &i2c_sysc,
1463}; 1311};
1464 1312
1465/*
1466 * 'dss' class
1467 * display sub-system
1468 */
1469
1470static struct omap_hwmod_class_sysconfig omap3xxx_dss_sysc = {
1471 .rev_offs = 0x0000,
1472 .sysc_offs = 0x0010,
1473 .syss_offs = 0x0014,
1474 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1475 .sysc_fields = &omap_hwmod_sysc_type1,
1476};
1477
1478static struct omap_hwmod_class omap3xxx_dss_hwmod_class = {
1479 .name = "dss",
1480 .sysc = &omap3xxx_dss_sysc,
1481};
1482
1483static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = { 1313static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = {
1484 { .name = "dispc", .dma_req = 5 }, 1314 { .name = "dispc", .dma_req = 5 },
1485 { .name = "dsi1", .dma_req = 74 }, 1315 { .name = "dsi1", .dma_req = 74 },
1316 { .dma_req = -1 }
1486}; 1317};
1487 1318
1488/* dss */ 1319/* dss */
@@ -1491,21 +1322,12 @@ static struct omap_hwmod_ocp_if *omap3xxx_dss_masters[] = {
1491 &omap3xxx_dss__l3, 1322 &omap3xxx_dss__l3,
1492}; 1323};
1493 1324
1494static struct omap_hwmod_addr_space omap3xxx_dss_addrs[] = {
1495 {
1496 .pa_start = 0x48050000,
1497 .pa_end = 0x480503FF,
1498 .flags = ADDR_TYPE_RT
1499 },
1500};
1501
1502/* l4_core -> dss */ 1325/* l4_core -> dss */
1503static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = { 1326static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = {
1504 .master = &omap3xxx_l4_core_hwmod, 1327 .master = &omap3xxx_l4_core_hwmod,
1505 .slave = &omap3430es1_dss_core_hwmod, 1328 .slave = &omap3430es1_dss_core_hwmod,
1506 .clk = "dss_ick", 1329 .clk = "dss_ick",
1507 .addr = omap3xxx_dss_addrs, 1330 .addr = omap2_dss_addrs,
1508 .addr_cnt = ARRAY_SIZE(omap3xxx_dss_addrs),
1509 .fw = { 1331 .fw = {
1510 .omap2 = { 1332 .omap2 = {
1511 .l4_fw_region = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION, 1333 .l4_fw_region = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION,
@@ -1520,8 +1342,7 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = {
1520 .master = &omap3xxx_l4_core_hwmod, 1342 .master = &omap3xxx_l4_core_hwmod,
1521 .slave = &omap3xxx_dss_core_hwmod, 1343 .slave = &omap3xxx_dss_core_hwmod,
1522 .clk = "dss_ick", 1344 .clk = "dss_ick",
1523 .addr = omap3xxx_dss_addrs, 1345 .addr = omap2_dss_addrs,
1524 .addr_cnt = ARRAY_SIZE(omap3xxx_dss_addrs),
1525 .fw = { 1346 .fw = {
1526 .omap2 = { 1347 .omap2 = {
1527 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_CORE_REGION, 1348 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_CORE_REGION,
@@ -1549,11 +1370,9 @@ static struct omap_hwmod_opt_clk dss_opt_clks[] = {
1549 1370
1550static struct omap_hwmod omap3430es1_dss_core_hwmod = { 1371static struct omap_hwmod omap3430es1_dss_core_hwmod = {
1551 .name = "dss_core", 1372 .name = "dss_core",
1552 .class = &omap3xxx_dss_hwmod_class, 1373 .class = &omap2_dss_hwmod_class,
1553 .main_clk = "dss1_alwon_fck", /* instead of dss_fck */ 1374 .main_clk = "dss1_alwon_fck", /* instead of dss_fck */
1554 .sdma_reqs = omap3xxx_dss_sdma_chs, 1375 .sdma_reqs = omap3xxx_dss_sdma_chs,
1555 .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_dss_sdma_chs),
1556
1557 .prcm = { 1376 .prcm = {
1558 .omap2 = { 1377 .omap2 = {
1559 .prcm_reg_id = 1, 1378 .prcm_reg_id = 1,
@@ -1575,11 +1394,9 @@ static struct omap_hwmod omap3430es1_dss_core_hwmod = {
1575 1394
1576static struct omap_hwmod omap3xxx_dss_core_hwmod = { 1395static struct omap_hwmod omap3xxx_dss_core_hwmod = {
1577 .name = "dss_core", 1396 .name = "dss_core",
1578 .class = &omap3xxx_dss_hwmod_class, 1397 .class = &omap2_dss_hwmod_class,
1579 .main_clk = "dss1_alwon_fck", /* instead of dss_fck */ 1398 .main_clk = "dss1_alwon_fck", /* instead of dss_fck */
1580 .sdma_reqs = omap3xxx_dss_sdma_chs, 1399 .sdma_reqs = omap3xxx_dss_sdma_chs,
1581 .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_dss_sdma_chs),
1582
1583 .prcm = { 1400 .prcm = {
1584 .omap2 = { 1401 .omap2 = {
1585 .prcm_reg_id = 1, 1402 .prcm_reg_id = 1,
@@ -1600,47 +1417,12 @@ static struct omap_hwmod omap3xxx_dss_core_hwmod = {
1600 CHIP_IS_OMAP3630ES1 | CHIP_GE_OMAP3630ES1_1), 1417 CHIP_IS_OMAP3630ES1 | CHIP_GE_OMAP3630ES1_1),
1601}; 1418};
1602 1419
1603/*
1604 * 'dispc' class
1605 * display controller
1606 */
1607
1608static struct omap_hwmod_class_sysconfig omap3xxx_dispc_sysc = {
1609 .rev_offs = 0x0000,
1610 .sysc_offs = 0x0010,
1611 .syss_offs = 0x0014,
1612 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
1613 SYSC_HAS_MIDLEMODE | SYSC_HAS_ENAWAKEUP |
1614 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1615 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1616 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1617 .sysc_fields = &omap_hwmod_sysc_type1,
1618};
1619
1620static struct omap_hwmod_class omap3xxx_dispc_hwmod_class = {
1621 .name = "dispc",
1622 .sysc = &omap3xxx_dispc_sysc,
1623};
1624
1625static struct omap_hwmod_irq_info omap3xxx_dispc_irqs[] = {
1626 { .irq = 25 },
1627};
1628
1629static struct omap_hwmod_addr_space omap3xxx_dss_dispc_addrs[] = {
1630 {
1631 .pa_start = 0x48050400,
1632 .pa_end = 0x480507FF,
1633 .flags = ADDR_TYPE_RT
1634 },
1635};
1636
1637/* l4_core -> dss_dispc */ 1420/* l4_core -> dss_dispc */
1638static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = { 1421static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = {
1639 .master = &omap3xxx_l4_core_hwmod, 1422 .master = &omap3xxx_l4_core_hwmod,
1640 .slave = &omap3xxx_dss_dispc_hwmod, 1423 .slave = &omap3xxx_dss_dispc_hwmod,
1641 .clk = "dss_ick", 1424 .clk = "dss_ick",
1642 .addr = omap3xxx_dss_dispc_addrs, 1425 .addr = omap2_dss_dispc_addrs,
1643 .addr_cnt = ARRAY_SIZE(omap3xxx_dss_dispc_addrs),
1644 .fw = { 1426 .fw = {
1645 .omap2 = { 1427 .omap2 = {
1646 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DISPC_REGION, 1428 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DISPC_REGION,
@@ -1658,9 +1440,8 @@ static struct omap_hwmod_ocp_if *omap3xxx_dss_dispc_slaves[] = {
1658 1440
1659static struct omap_hwmod omap3xxx_dss_dispc_hwmod = { 1441static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
1660 .name = "dss_dispc", 1442 .name = "dss_dispc",
1661 .class = &omap3xxx_dispc_hwmod_class, 1443 .class = &omap2_dispc_hwmod_class,
1662 .mpu_irqs = omap3xxx_dispc_irqs, 1444 .mpu_irqs = omap2_dispc_irqs,
1663 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_dispc_irqs),
1664 .main_clk = "dss1_alwon_fck", 1445 .main_clk = "dss1_alwon_fck",
1665 .prcm = { 1446 .prcm = {
1666 .omap2 = { 1447 .omap2 = {
@@ -1688,6 +1469,7 @@ static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = {
1688 1469
1689static struct omap_hwmod_irq_info omap3xxx_dsi1_irqs[] = { 1470static struct omap_hwmod_irq_info omap3xxx_dsi1_irqs[] = {
1690 { .irq = 25 }, 1471 { .irq = 25 },
1472 { .irq = -1 }
1691}; 1473};
1692 1474
1693/* dss_dsi1 */ 1475/* dss_dsi1 */
@@ -1697,6 +1479,7 @@ static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = {
1697 .pa_end = 0x4804FFFF, 1479 .pa_end = 0x4804FFFF,
1698 .flags = ADDR_TYPE_RT 1480 .flags = ADDR_TYPE_RT
1699 }, 1481 },
1482 { }
1700}; 1483};
1701 1484
1702/* l4_core -> dss_dsi1 */ 1485/* l4_core -> dss_dsi1 */
@@ -1704,7 +1487,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = {
1704 .master = &omap3xxx_l4_core_hwmod, 1487 .master = &omap3xxx_l4_core_hwmod,
1705 .slave = &omap3xxx_dss_dsi1_hwmod, 1488 .slave = &omap3xxx_dss_dsi1_hwmod,
1706 .addr = omap3xxx_dss_dsi1_addrs, 1489 .addr = omap3xxx_dss_dsi1_addrs,
1707 .addr_cnt = ARRAY_SIZE(omap3xxx_dss_dsi1_addrs),
1708 .fw = { 1490 .fw = {
1709 .omap2 = { 1491 .omap2 = {
1710 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DSI_REGION, 1492 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DSI_REGION,
@@ -1724,7 +1506,6 @@ static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
1724 .name = "dss_dsi1", 1506 .name = "dss_dsi1",
1725 .class = &omap3xxx_dsi_hwmod_class, 1507 .class = &omap3xxx_dsi_hwmod_class,
1726 .mpu_irqs = omap3xxx_dsi1_irqs, 1508 .mpu_irqs = omap3xxx_dsi1_irqs,
1727 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_dsi1_irqs),
1728 .main_clk = "dss1_alwon_fck", 1509 .main_clk = "dss1_alwon_fck",
1729 .prcm = { 1510 .prcm = {
1730 .omap2 = { 1511 .omap2 = {
@@ -1741,41 +1522,12 @@ static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
1741 .flags = HWMOD_NO_IDLEST, 1522 .flags = HWMOD_NO_IDLEST,
1742}; 1523};
1743 1524
1744/*
1745 * 'rfbi' class
1746 * remote frame buffer interface
1747 */
1748
1749static struct omap_hwmod_class_sysconfig omap3xxx_rfbi_sysc = {
1750 .rev_offs = 0x0000,
1751 .sysc_offs = 0x0010,
1752 .syss_offs = 0x0014,
1753 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1754 SYSC_HAS_AUTOIDLE),
1755 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1756 .sysc_fields = &omap_hwmod_sysc_type1,
1757};
1758
1759static struct omap_hwmod_class omap3xxx_rfbi_hwmod_class = {
1760 .name = "rfbi",
1761 .sysc = &omap3xxx_rfbi_sysc,
1762};
1763
1764static struct omap_hwmod_addr_space omap3xxx_dss_rfbi_addrs[] = {
1765 {
1766 .pa_start = 0x48050800,
1767 .pa_end = 0x48050BFF,
1768 .flags = ADDR_TYPE_RT
1769 },
1770};
1771
1772/* l4_core -> dss_rfbi */ 1525/* l4_core -> dss_rfbi */
1773static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = { 1526static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = {
1774 .master = &omap3xxx_l4_core_hwmod, 1527 .master = &omap3xxx_l4_core_hwmod,
1775 .slave = &omap3xxx_dss_rfbi_hwmod, 1528 .slave = &omap3xxx_dss_rfbi_hwmod,
1776 .clk = "dss_ick", 1529 .clk = "dss_ick",
1777 .addr = omap3xxx_dss_rfbi_addrs, 1530 .addr = omap2_dss_rfbi_addrs,
1778 .addr_cnt = ARRAY_SIZE(omap3xxx_dss_rfbi_addrs),
1779 .fw = { 1531 .fw = {
1780 .omap2 = { 1532 .omap2 = {
1781 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_RFBI_REGION, 1533 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_RFBI_REGION,
@@ -1793,7 +1545,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_dss_rfbi_slaves[] = {
1793 1545
1794static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = { 1546static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
1795 .name = "dss_rfbi", 1547 .name = "dss_rfbi",
1796 .class = &omap3xxx_rfbi_hwmod_class, 1548 .class = &omap2_rfbi_hwmod_class,
1797 .main_clk = "dss1_alwon_fck", 1549 .main_clk = "dss1_alwon_fck",
1798 .prcm = { 1550 .prcm = {
1799 .omap2 = { 1551 .omap2 = {
@@ -1810,31 +1562,12 @@ static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
1810 .flags = HWMOD_NO_IDLEST, 1562 .flags = HWMOD_NO_IDLEST,
1811}; 1563};
1812 1564
1813/*
1814 * 'venc' class
1815 * video encoder
1816 */
1817
1818static struct omap_hwmod_class omap3xxx_venc_hwmod_class = {
1819 .name = "venc",
1820};
1821
1822/* dss_venc */
1823static struct omap_hwmod_addr_space omap3xxx_dss_venc_addrs[] = {
1824 {
1825 .pa_start = 0x48050C00,
1826 .pa_end = 0x48050FFF,
1827 .flags = ADDR_TYPE_RT
1828 },
1829};
1830
1831/* l4_core -> dss_venc */ 1565/* l4_core -> dss_venc */
1832static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = { 1566static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
1833 .master = &omap3xxx_l4_core_hwmod, 1567 .master = &omap3xxx_l4_core_hwmod,
1834 .slave = &omap3xxx_dss_venc_hwmod, 1568 .slave = &omap3xxx_dss_venc_hwmod,
1835 .clk = "dss_tv_fck", 1569 .clk = "dss_tv_fck",
1836 .addr = omap3xxx_dss_venc_addrs, 1570 .addr = omap2_dss_venc_addrs,
1837 .addr_cnt = ARRAY_SIZE(omap3xxx_dss_venc_addrs),
1838 .fw = { 1571 .fw = {
1839 .omap2 = { 1572 .omap2 = {
1840 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_VENC_REGION, 1573 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_VENC_REGION,
@@ -1853,7 +1586,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_dss_venc_slaves[] = {
1853 1586
1854static struct omap_hwmod omap3xxx_dss_venc_hwmod = { 1587static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
1855 .name = "dss_venc", 1588 .name = "dss_venc",
1856 .class = &omap3xxx_venc_hwmod_class, 1589 .class = &omap2_venc_hwmod_class,
1857 .main_clk = "dss1_alwon_fck", 1590 .main_clk = "dss1_alwon_fck",
1858 .prcm = { 1591 .prcm = {
1859 .omap2 = { 1592 .omap2 = {
@@ -1876,25 +1609,14 @@ static struct omap_i2c_dev_attr i2c1_dev_attr = {
1876 .fifo_depth = 8, /* bytes */ 1609 .fifo_depth = 8, /* bytes */
1877}; 1610};
1878 1611
1879static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
1880 { .irq = INT_24XX_I2C1_IRQ, },
1881};
1882
1883static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = {
1884 { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX },
1885 { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX },
1886};
1887
1888static struct omap_hwmod_ocp_if *omap3xxx_i2c1_slaves[] = { 1612static struct omap_hwmod_ocp_if *omap3xxx_i2c1_slaves[] = {
1889 &omap3_l4_core__i2c1, 1613 &omap3_l4_core__i2c1,
1890}; 1614};
1891 1615
1892static struct omap_hwmod omap3xxx_i2c1_hwmod = { 1616static struct omap_hwmod omap3xxx_i2c1_hwmod = {
1893 .name = "i2c1", 1617 .name = "i2c1",
1894 .mpu_irqs = i2c1_mpu_irqs, 1618 .mpu_irqs = omap2_i2c1_mpu_irqs,
1895 .mpu_irqs_cnt = ARRAY_SIZE(i2c1_mpu_irqs), 1619 .sdma_reqs = omap2_i2c1_sdma_reqs,
1896 .sdma_reqs = i2c1_sdma_reqs,
1897 .sdma_reqs_cnt = ARRAY_SIZE(i2c1_sdma_reqs),
1898 .main_clk = "i2c1_fck", 1620 .main_clk = "i2c1_fck",
1899 .prcm = { 1621 .prcm = {
1900 .omap2 = { 1622 .omap2 = {
@@ -1918,25 +1640,14 @@ static struct omap_i2c_dev_attr i2c2_dev_attr = {
1918 .fifo_depth = 8, /* bytes */ 1640 .fifo_depth = 8, /* bytes */
1919}; 1641};
1920 1642
1921static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
1922 { .irq = INT_24XX_I2C2_IRQ, },
1923};
1924
1925static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = {
1926 { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX },
1927 { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX },
1928};
1929
1930static struct omap_hwmod_ocp_if *omap3xxx_i2c2_slaves[] = { 1643static struct omap_hwmod_ocp_if *omap3xxx_i2c2_slaves[] = {
1931 &omap3_l4_core__i2c2, 1644 &omap3_l4_core__i2c2,
1932}; 1645};
1933 1646
1934static struct omap_hwmod omap3xxx_i2c2_hwmod = { 1647static struct omap_hwmod omap3xxx_i2c2_hwmod = {
1935 .name = "i2c2", 1648 .name = "i2c2",
1936 .mpu_irqs = i2c2_mpu_irqs, 1649 .mpu_irqs = omap2_i2c2_mpu_irqs,
1937 .mpu_irqs_cnt = ARRAY_SIZE(i2c2_mpu_irqs), 1650 .sdma_reqs = omap2_i2c2_sdma_reqs,
1938 .sdma_reqs = i2c2_sdma_reqs,
1939 .sdma_reqs_cnt = ARRAY_SIZE(i2c2_sdma_reqs),
1940 .main_clk = "i2c2_fck", 1651 .main_clk = "i2c2_fck",
1941 .prcm = { 1652 .prcm = {
1942 .omap2 = { 1653 .omap2 = {
@@ -1962,11 +1673,13 @@ static struct omap_i2c_dev_attr i2c3_dev_attr = {
1962 1673
1963static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = { 1674static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
1964 { .irq = INT_34XX_I2C3_IRQ, }, 1675 { .irq = INT_34XX_I2C3_IRQ, },
1676 { .irq = -1 }
1965}; 1677};
1966 1678
1967static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = { 1679static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = {
1968 { .name = "tx", .dma_req = OMAP34XX_DMA_I2C3_TX }, 1680 { .name = "tx", .dma_req = OMAP34XX_DMA_I2C3_TX },
1969 { .name = "rx", .dma_req = OMAP34XX_DMA_I2C3_RX }, 1681 { .name = "rx", .dma_req = OMAP34XX_DMA_I2C3_RX },
1682 { .dma_req = -1 }
1970}; 1683};
1971 1684
1972static struct omap_hwmod_ocp_if *omap3xxx_i2c3_slaves[] = { 1685static struct omap_hwmod_ocp_if *omap3xxx_i2c3_slaves[] = {
@@ -1976,9 +1689,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_i2c3_slaves[] = {
1976static struct omap_hwmod omap3xxx_i2c3_hwmod = { 1689static struct omap_hwmod omap3xxx_i2c3_hwmod = {
1977 .name = "i2c3", 1690 .name = "i2c3",
1978 .mpu_irqs = i2c3_mpu_irqs, 1691 .mpu_irqs = i2c3_mpu_irqs,
1979 .mpu_irqs_cnt = ARRAY_SIZE(i2c3_mpu_irqs),
1980 .sdma_reqs = i2c3_sdma_reqs, 1692 .sdma_reqs = i2c3_sdma_reqs,
1981 .sdma_reqs_cnt = ARRAY_SIZE(i2c3_sdma_reqs),
1982 .main_clk = "i2c3_fck", 1693 .main_clk = "i2c3_fck",
1983 .prcm = { 1694 .prcm = {
1984 .omap2 = { 1695 .omap2 = {
@@ -2003,13 +1714,13 @@ static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = {
2003 .pa_end = 0x483101ff, 1714 .pa_end = 0x483101ff,
2004 .flags = ADDR_TYPE_RT 1715 .flags = ADDR_TYPE_RT
2005 }, 1716 },
1717 { }
2006}; 1718};
2007 1719
2008static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = { 1720static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = {
2009 .master = &omap3xxx_l4_wkup_hwmod, 1721 .master = &omap3xxx_l4_wkup_hwmod,
2010 .slave = &omap3xxx_gpio1_hwmod, 1722 .slave = &omap3xxx_gpio1_hwmod,
2011 .addr = omap3xxx_gpio1_addrs, 1723 .addr = omap3xxx_gpio1_addrs,
2012 .addr_cnt = ARRAY_SIZE(omap3xxx_gpio1_addrs),
2013 .user = OCP_USER_MPU | OCP_USER_SDMA, 1724 .user = OCP_USER_MPU | OCP_USER_SDMA,
2014}; 1725};
2015 1726
@@ -2020,13 +1731,13 @@ static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = {
2020 .pa_end = 0x490501ff, 1731 .pa_end = 0x490501ff,
2021 .flags = ADDR_TYPE_RT 1732 .flags = ADDR_TYPE_RT
2022 }, 1733 },
1734 { }
2023}; 1735};
2024 1736
2025static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = { 1737static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = {
2026 .master = &omap3xxx_l4_per_hwmod, 1738 .master = &omap3xxx_l4_per_hwmod,
2027 .slave = &omap3xxx_gpio2_hwmod, 1739 .slave = &omap3xxx_gpio2_hwmod,
2028 .addr = omap3xxx_gpio2_addrs, 1740 .addr = omap3xxx_gpio2_addrs,
2029 .addr_cnt = ARRAY_SIZE(omap3xxx_gpio2_addrs),
2030 .user = OCP_USER_MPU | OCP_USER_SDMA, 1741 .user = OCP_USER_MPU | OCP_USER_SDMA,
2031}; 1742};
2032 1743
@@ -2037,13 +1748,13 @@ static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = {
2037 .pa_end = 0x490521ff, 1748 .pa_end = 0x490521ff,
2038 .flags = ADDR_TYPE_RT 1749 .flags = ADDR_TYPE_RT
2039 }, 1750 },
1751 { }
2040}; 1752};
2041 1753
2042static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = { 1754static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = {
2043 .master = &omap3xxx_l4_per_hwmod, 1755 .master = &omap3xxx_l4_per_hwmod,
2044 .slave = &omap3xxx_gpio3_hwmod, 1756 .slave = &omap3xxx_gpio3_hwmod,
2045 .addr = omap3xxx_gpio3_addrs, 1757 .addr = omap3xxx_gpio3_addrs,
2046 .addr_cnt = ARRAY_SIZE(omap3xxx_gpio3_addrs),
2047 .user = OCP_USER_MPU | OCP_USER_SDMA, 1758 .user = OCP_USER_MPU | OCP_USER_SDMA,
2048}; 1759};
2049 1760
@@ -2054,13 +1765,13 @@ static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = {
2054 .pa_end = 0x490541ff, 1765 .pa_end = 0x490541ff,
2055 .flags = ADDR_TYPE_RT 1766 .flags = ADDR_TYPE_RT
2056 }, 1767 },
1768 { }
2057}; 1769};
2058 1770
2059static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = { 1771static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = {
2060 .master = &omap3xxx_l4_per_hwmod, 1772 .master = &omap3xxx_l4_per_hwmod,
2061 .slave = &omap3xxx_gpio4_hwmod, 1773 .slave = &omap3xxx_gpio4_hwmod,
2062 .addr = omap3xxx_gpio4_addrs, 1774 .addr = omap3xxx_gpio4_addrs,
2063 .addr_cnt = ARRAY_SIZE(omap3xxx_gpio4_addrs),
2064 .user = OCP_USER_MPU | OCP_USER_SDMA, 1775 .user = OCP_USER_MPU | OCP_USER_SDMA,
2065}; 1776};
2066 1777
@@ -2071,13 +1782,13 @@ static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = {
2071 .pa_end = 0x490561ff, 1782 .pa_end = 0x490561ff,
2072 .flags = ADDR_TYPE_RT 1783 .flags = ADDR_TYPE_RT
2073 }, 1784 },
1785 { }
2074}; 1786};
2075 1787
2076static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = { 1788static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = {
2077 .master = &omap3xxx_l4_per_hwmod, 1789 .master = &omap3xxx_l4_per_hwmod,
2078 .slave = &omap3xxx_gpio5_hwmod, 1790 .slave = &omap3xxx_gpio5_hwmod,
2079 .addr = omap3xxx_gpio5_addrs, 1791 .addr = omap3xxx_gpio5_addrs,
2080 .addr_cnt = ARRAY_SIZE(omap3xxx_gpio5_addrs),
2081 .user = OCP_USER_MPU | OCP_USER_SDMA, 1792 .user = OCP_USER_MPU | OCP_USER_SDMA,
2082}; 1793};
2083 1794
@@ -2088,13 +1799,13 @@ static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = {
2088 .pa_end = 0x490581ff, 1799 .pa_end = 0x490581ff,
2089 .flags = ADDR_TYPE_RT 1800 .flags = ADDR_TYPE_RT
2090 }, 1801 },
1802 { }
2091}; 1803};
2092 1804
2093static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = { 1805static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = {
2094 .master = &omap3xxx_l4_per_hwmod, 1806 .master = &omap3xxx_l4_per_hwmod,
2095 .slave = &omap3xxx_gpio6_hwmod, 1807 .slave = &omap3xxx_gpio6_hwmod,
2096 .addr = omap3xxx_gpio6_addrs, 1808 .addr = omap3xxx_gpio6_addrs,
2097 .addr_cnt = ARRAY_SIZE(omap3xxx_gpio6_addrs),
2098 .user = OCP_USER_MPU | OCP_USER_SDMA, 1809 .user = OCP_USER_MPU | OCP_USER_SDMA,
2099}; 1810};
2100 1811
@@ -2127,10 +1838,6 @@ static struct omap_gpio_dev_attr gpio_dev_attr = {
2127}; 1838};
2128 1839
2129/* gpio1 */ 1840/* gpio1 */
2130static struct omap_hwmod_irq_info omap3xxx_gpio1_irqs[] = {
2131 { .irq = 29 }, /* INT_34XX_GPIO_BANK1 */
2132};
2133
2134static struct omap_hwmod_opt_clk gpio1_opt_clks[] = { 1841static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
2135 { .role = "dbclk", .clk = "gpio1_dbck", }, 1842 { .role = "dbclk", .clk = "gpio1_dbck", },
2136}; 1843};
@@ -2142,8 +1849,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_gpio1_slaves[] = {
2142static struct omap_hwmod omap3xxx_gpio1_hwmod = { 1849static struct omap_hwmod omap3xxx_gpio1_hwmod = {
2143 .name = "gpio1", 1850 .name = "gpio1",
2144 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 1851 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2145 .mpu_irqs = omap3xxx_gpio1_irqs, 1852 .mpu_irqs = omap2_gpio1_irqs,
2146 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio1_irqs),
2147 .main_clk = "gpio1_ick", 1853 .main_clk = "gpio1_ick",
2148 .opt_clks = gpio1_opt_clks, 1854 .opt_clks = gpio1_opt_clks,
2149 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks), 1855 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
@@ -2164,10 +1870,6 @@ static struct omap_hwmod omap3xxx_gpio1_hwmod = {
2164}; 1870};
2165 1871
2166/* gpio2 */ 1872/* gpio2 */
2167static struct omap_hwmod_irq_info omap3xxx_gpio2_irqs[] = {
2168 { .irq = 30 }, /* INT_34XX_GPIO_BANK2 */
2169};
2170
2171static struct omap_hwmod_opt_clk gpio2_opt_clks[] = { 1873static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
2172 { .role = "dbclk", .clk = "gpio2_dbck", }, 1874 { .role = "dbclk", .clk = "gpio2_dbck", },
2173}; 1875};
@@ -2179,8 +1881,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_gpio2_slaves[] = {
2179static struct omap_hwmod omap3xxx_gpio2_hwmod = { 1881static struct omap_hwmod omap3xxx_gpio2_hwmod = {
2180 .name = "gpio2", 1882 .name = "gpio2",
2181 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 1883 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2182 .mpu_irqs = omap3xxx_gpio2_irqs, 1884 .mpu_irqs = omap2_gpio2_irqs,
2183 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio2_irqs),
2184 .main_clk = "gpio2_ick", 1885 .main_clk = "gpio2_ick",
2185 .opt_clks = gpio2_opt_clks, 1886 .opt_clks = gpio2_opt_clks,
2186 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks), 1887 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
@@ -2201,10 +1902,6 @@ static struct omap_hwmod omap3xxx_gpio2_hwmod = {
2201}; 1902};
2202 1903
2203/* gpio3 */ 1904/* gpio3 */
2204static struct omap_hwmod_irq_info omap3xxx_gpio3_irqs[] = {
2205 { .irq = 31 }, /* INT_34XX_GPIO_BANK3 */
2206};
2207
2208static struct omap_hwmod_opt_clk gpio3_opt_clks[] = { 1905static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
2209 { .role = "dbclk", .clk = "gpio3_dbck", }, 1906 { .role = "dbclk", .clk = "gpio3_dbck", },
2210}; 1907};
@@ -2216,8 +1913,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_gpio3_slaves[] = {
2216static struct omap_hwmod omap3xxx_gpio3_hwmod = { 1913static struct omap_hwmod omap3xxx_gpio3_hwmod = {
2217 .name = "gpio3", 1914 .name = "gpio3",
2218 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 1915 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2219 .mpu_irqs = omap3xxx_gpio3_irqs, 1916 .mpu_irqs = omap2_gpio3_irqs,
2220 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio3_irqs),
2221 .main_clk = "gpio3_ick", 1917 .main_clk = "gpio3_ick",
2222 .opt_clks = gpio3_opt_clks, 1918 .opt_clks = gpio3_opt_clks,
2223 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks), 1919 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
@@ -2238,10 +1934,6 @@ static struct omap_hwmod omap3xxx_gpio3_hwmod = {
2238}; 1934};
2239 1935
2240/* gpio4 */ 1936/* gpio4 */
2241static struct omap_hwmod_irq_info omap3xxx_gpio4_irqs[] = {
2242 { .irq = 32 }, /* INT_34XX_GPIO_BANK4 */
2243};
2244
2245static struct omap_hwmod_opt_clk gpio4_opt_clks[] = { 1937static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
2246 { .role = "dbclk", .clk = "gpio4_dbck", }, 1938 { .role = "dbclk", .clk = "gpio4_dbck", },
2247}; 1939};
@@ -2253,8 +1945,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_gpio4_slaves[] = {
2253static struct omap_hwmod omap3xxx_gpio4_hwmod = { 1945static struct omap_hwmod omap3xxx_gpio4_hwmod = {
2254 .name = "gpio4", 1946 .name = "gpio4",
2255 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 1947 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2256 .mpu_irqs = omap3xxx_gpio4_irqs, 1948 .mpu_irqs = omap2_gpio4_irqs,
2257 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio4_irqs),
2258 .main_clk = "gpio4_ick", 1949 .main_clk = "gpio4_ick",
2259 .opt_clks = gpio4_opt_clks, 1950 .opt_clks = gpio4_opt_clks,
2260 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks), 1951 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
@@ -2277,6 +1968,7 @@ static struct omap_hwmod omap3xxx_gpio4_hwmod = {
2277/* gpio5 */ 1968/* gpio5 */
2278static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = { 1969static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = {
2279 { .irq = 33 }, /* INT_34XX_GPIO_BANK5 */ 1970 { .irq = 33 }, /* INT_34XX_GPIO_BANK5 */
1971 { .irq = -1 }
2280}; 1972};
2281 1973
2282static struct omap_hwmod_opt_clk gpio5_opt_clks[] = { 1974static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
@@ -2291,7 +1983,6 @@ static struct omap_hwmod omap3xxx_gpio5_hwmod = {
2291 .name = "gpio5", 1983 .name = "gpio5",
2292 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 1984 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2293 .mpu_irqs = omap3xxx_gpio5_irqs, 1985 .mpu_irqs = omap3xxx_gpio5_irqs,
2294 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio5_irqs),
2295 .main_clk = "gpio5_ick", 1986 .main_clk = "gpio5_ick",
2296 .opt_clks = gpio5_opt_clks, 1987 .opt_clks = gpio5_opt_clks,
2297 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks), 1988 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
@@ -2314,6 +2005,7 @@ static struct omap_hwmod omap3xxx_gpio5_hwmod = {
2314/* gpio6 */ 2005/* gpio6 */
2315static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = { 2006static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = {
2316 { .irq = 34 }, /* INT_34XX_GPIO_BANK6 */ 2007 { .irq = 34 }, /* INT_34XX_GPIO_BANK6 */
2008 { .irq = -1 }
2317}; 2009};
2318 2010
2319static struct omap_hwmod_opt_clk gpio6_opt_clks[] = { 2011static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
@@ -2328,7 +2020,6 @@ static struct omap_hwmod omap3xxx_gpio6_hwmod = {
2328 .name = "gpio6", 2020 .name = "gpio6",
2329 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 2021 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2330 .mpu_irqs = omap3xxx_gpio6_irqs, 2022 .mpu_irqs = omap3xxx_gpio6_irqs,
2331 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio6_irqs),
2332 .main_clk = "gpio6_ick", 2023 .main_clk = "gpio6_ick",
2333 .opt_clks = gpio6_opt_clks, 2024 .opt_clks = gpio6_opt_clks,
2334 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks), 2025 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
@@ -2382,19 +2073,13 @@ static struct omap_hwmod_class omap3xxx_dma_hwmod_class = {
2382}; 2073};
2383 2074
2384/* dma_system */ 2075/* dma_system */
2385static struct omap_hwmod_irq_info omap3xxx_dma_system_irqs[] = {
2386 { .name = "0", .irq = 12 }, /* INT_24XX_SDMA_IRQ0 */
2387 { .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */
2388 { .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */
2389 { .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */
2390};
2391
2392static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = { 2076static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = {
2393 { 2077 {
2394 .pa_start = 0x48056000, 2078 .pa_start = 0x48056000,
2395 .pa_end = 0x48056fff, 2079 .pa_end = 0x48056fff,
2396 .flags = ADDR_TYPE_RT 2080 .flags = ADDR_TYPE_RT
2397 }, 2081 },
2082 { }
2398}; 2083};
2399 2084
2400/* dma_system master ports */ 2085/* dma_system master ports */
@@ -2408,7 +2093,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = {
2408 .slave = &omap3xxx_dma_system_hwmod, 2093 .slave = &omap3xxx_dma_system_hwmod,
2409 .clk = "core_l4_ick", 2094 .clk = "core_l4_ick",
2410 .addr = omap3xxx_dma_system_addrs, 2095 .addr = omap3xxx_dma_system_addrs,
2411 .addr_cnt = ARRAY_SIZE(omap3xxx_dma_system_addrs),
2412 .user = OCP_USER_MPU | OCP_USER_SDMA, 2096 .user = OCP_USER_MPU | OCP_USER_SDMA,
2413}; 2097};
2414 2098
@@ -2420,8 +2104,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_dma_system_slaves[] = {
2420static struct omap_hwmod omap3xxx_dma_system_hwmod = { 2104static struct omap_hwmod omap3xxx_dma_system_hwmod = {
2421 .name = "dma", 2105 .name = "dma",
2422 .class = &omap3xxx_dma_hwmod_class, 2106 .class = &omap3xxx_dma_hwmod_class,
2423 .mpu_irqs = omap3xxx_dma_system_irqs, 2107 .mpu_irqs = omap2_dma_system_irqs,
2424 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_dma_system_irqs),
2425 .main_clk = "core_l3_ick", 2108 .main_clk = "core_l3_ick",
2426 .prcm = { 2109 .prcm = {
2427 .omap2 = { 2110 .omap2 = {
@@ -2466,11 +2149,7 @@ static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = {
2466 { .name = "irq", .irq = 16 }, 2149 { .name = "irq", .irq = 16 },
2467 { .name = "tx", .irq = 59 }, 2150 { .name = "tx", .irq = 59 },
2468 { .name = "rx", .irq = 60 }, 2151 { .name = "rx", .irq = 60 },
2469}; 2152 { .irq = -1 }
2470
2471static struct omap_hwmod_dma_info omap3xxx_mcbsp1_sdma_chs[] = {
2472 { .name = "rx", .dma_req = 32 },
2473 { .name = "tx", .dma_req = 31 },
2474}; 2153};
2475 2154
2476static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = { 2155static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = {
@@ -2480,6 +2159,7 @@ static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = {
2480 .pa_end = 0x480740ff, 2159 .pa_end = 0x480740ff,
2481 .flags = ADDR_TYPE_RT 2160 .flags = ADDR_TYPE_RT
2482 }, 2161 },
2162 { }
2483}; 2163};
2484 2164
2485/* l4_core -> mcbsp1 */ 2165/* l4_core -> mcbsp1 */
@@ -2488,7 +2168,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = {
2488 .slave = &omap3xxx_mcbsp1_hwmod, 2168 .slave = &omap3xxx_mcbsp1_hwmod,
2489 .clk = "mcbsp1_ick", 2169 .clk = "mcbsp1_ick",
2490 .addr = omap3xxx_mcbsp1_addrs, 2170 .addr = omap3xxx_mcbsp1_addrs,
2491 .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp1_addrs),
2492 .user = OCP_USER_MPU | OCP_USER_SDMA, 2171 .user = OCP_USER_MPU | OCP_USER_SDMA,
2493}; 2172};
2494 2173
@@ -2501,9 +2180,7 @@ static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
2501 .name = "mcbsp1", 2180 .name = "mcbsp1",
2502 .class = &omap3xxx_mcbsp_hwmod_class, 2181 .class = &omap3xxx_mcbsp_hwmod_class,
2503 .mpu_irqs = omap3xxx_mcbsp1_irqs, 2182 .mpu_irqs = omap3xxx_mcbsp1_irqs,
2504 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp1_irqs), 2183 .sdma_reqs = omap2_mcbsp1_sdma_reqs,
2505 .sdma_reqs = omap3xxx_mcbsp1_sdma_chs,
2506 .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp1_sdma_chs),
2507 .main_clk = "mcbsp1_fck", 2184 .main_clk = "mcbsp1_fck",
2508 .prcm = { 2185 .prcm = {
2509 .omap2 = { 2186 .omap2 = {
@@ -2524,11 +2201,7 @@ static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = {
2524 { .name = "irq", .irq = 17 }, 2201 { .name = "irq", .irq = 17 },
2525 { .name = "tx", .irq = 62 }, 2202 { .name = "tx", .irq = 62 },
2526 { .name = "rx", .irq = 63 }, 2203 { .name = "rx", .irq = 63 },
2527}; 2204 { .irq = -1 }
2528
2529static struct omap_hwmod_dma_info omap3xxx_mcbsp2_sdma_chs[] = {
2530 { .name = "rx", .dma_req = 34 },
2531 { .name = "tx", .dma_req = 33 },
2532}; 2205};
2533 2206
2534static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = { 2207static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = {
@@ -2538,6 +2211,7 @@ static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = {
2538 .pa_end = 0x490220ff, 2211 .pa_end = 0x490220ff,
2539 .flags = ADDR_TYPE_RT 2212 .flags = ADDR_TYPE_RT
2540 }, 2213 },
2214 { }
2541}; 2215};
2542 2216
2543/* l4_per -> mcbsp2 */ 2217/* l4_per -> mcbsp2 */
@@ -2546,7 +2220,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = {
2546 .slave = &omap3xxx_mcbsp2_hwmod, 2220 .slave = &omap3xxx_mcbsp2_hwmod,
2547 .clk = "mcbsp2_ick", 2221 .clk = "mcbsp2_ick",
2548 .addr = omap3xxx_mcbsp2_addrs, 2222 .addr = omap3xxx_mcbsp2_addrs,
2549 .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_addrs),
2550 .user = OCP_USER_MPU | OCP_USER_SDMA, 2223 .user = OCP_USER_MPU | OCP_USER_SDMA,
2551}; 2224};
2552 2225
@@ -2563,9 +2236,7 @@ static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
2563 .name = "mcbsp2", 2236 .name = "mcbsp2",
2564 .class = &omap3xxx_mcbsp_hwmod_class, 2237 .class = &omap3xxx_mcbsp_hwmod_class,
2565 .mpu_irqs = omap3xxx_mcbsp2_irqs, 2238 .mpu_irqs = omap3xxx_mcbsp2_irqs,
2566 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_irqs), 2239 .sdma_reqs = omap2_mcbsp2_sdma_reqs,
2567 .sdma_reqs = omap3xxx_mcbsp2_sdma_chs,
2568 .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_sdma_chs),
2569 .main_clk = "mcbsp2_fck", 2240 .main_clk = "mcbsp2_fck",
2570 .prcm = { 2241 .prcm = {
2571 .omap2 = { 2242 .omap2 = {
@@ -2587,11 +2258,7 @@ static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = {
2587 { .name = "irq", .irq = 22 }, 2258 { .name = "irq", .irq = 22 },
2588 { .name = "tx", .irq = 89 }, 2259 { .name = "tx", .irq = 89 },
2589 { .name = "rx", .irq = 90 }, 2260 { .name = "rx", .irq = 90 },
2590}; 2261 { .irq = -1 }
2591
2592static struct omap_hwmod_dma_info omap3xxx_mcbsp3_sdma_chs[] = {
2593 { .name = "rx", .dma_req = 18 },
2594 { .name = "tx", .dma_req = 17 },
2595}; 2262};
2596 2263
2597static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = { 2264static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = {
@@ -2601,6 +2268,7 @@ static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = {
2601 .pa_end = 0x490240ff, 2268 .pa_end = 0x490240ff,
2602 .flags = ADDR_TYPE_RT 2269 .flags = ADDR_TYPE_RT
2603 }, 2270 },
2271 { }
2604}; 2272};
2605 2273
2606/* l4_per -> mcbsp3 */ 2274/* l4_per -> mcbsp3 */
@@ -2609,7 +2277,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = {
2609 .slave = &omap3xxx_mcbsp3_hwmod, 2277 .slave = &omap3xxx_mcbsp3_hwmod,
2610 .clk = "mcbsp3_ick", 2278 .clk = "mcbsp3_ick",
2611 .addr = omap3xxx_mcbsp3_addrs, 2279 .addr = omap3xxx_mcbsp3_addrs,
2612 .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_addrs),
2613 .user = OCP_USER_MPU | OCP_USER_SDMA, 2280 .user = OCP_USER_MPU | OCP_USER_SDMA,
2614}; 2281};
2615 2282
@@ -2626,9 +2293,7 @@ static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
2626 .name = "mcbsp3", 2293 .name = "mcbsp3",
2627 .class = &omap3xxx_mcbsp_hwmod_class, 2294 .class = &omap3xxx_mcbsp_hwmod_class,
2628 .mpu_irqs = omap3xxx_mcbsp3_irqs, 2295 .mpu_irqs = omap3xxx_mcbsp3_irqs,
2629 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_irqs), 2296 .sdma_reqs = omap2_mcbsp3_sdma_reqs,
2630 .sdma_reqs = omap3xxx_mcbsp3_sdma_chs,
2631 .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_sdma_chs),
2632 .main_clk = "mcbsp3_fck", 2297 .main_clk = "mcbsp3_fck",
2633 .prcm = { 2298 .prcm = {
2634 .omap2 = { 2299 .omap2 = {
@@ -2650,11 +2315,13 @@ static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = {
2650 { .name = "irq", .irq = 23 }, 2315 { .name = "irq", .irq = 23 },
2651 { .name = "tx", .irq = 54 }, 2316 { .name = "tx", .irq = 54 },
2652 { .name = "rx", .irq = 55 }, 2317 { .name = "rx", .irq = 55 },
2318 { .irq = -1 }
2653}; 2319};
2654 2320
2655static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = { 2321static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = {
2656 { .name = "rx", .dma_req = 20 }, 2322 { .name = "rx", .dma_req = 20 },
2657 { .name = "tx", .dma_req = 19 }, 2323 { .name = "tx", .dma_req = 19 },
2324 { .dma_req = -1 }
2658}; 2325};
2659 2326
2660static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = { 2327static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = {
@@ -2664,6 +2331,7 @@ static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = {
2664 .pa_end = 0x490260ff, 2331 .pa_end = 0x490260ff,
2665 .flags = ADDR_TYPE_RT 2332 .flags = ADDR_TYPE_RT
2666 }, 2333 },
2334 { }
2667}; 2335};
2668 2336
2669/* l4_per -> mcbsp4 */ 2337/* l4_per -> mcbsp4 */
@@ -2672,7 +2340,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = {
2672 .slave = &omap3xxx_mcbsp4_hwmod, 2340 .slave = &omap3xxx_mcbsp4_hwmod,
2673 .clk = "mcbsp4_ick", 2341 .clk = "mcbsp4_ick",
2674 .addr = omap3xxx_mcbsp4_addrs, 2342 .addr = omap3xxx_mcbsp4_addrs,
2675 .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp4_addrs),
2676 .user = OCP_USER_MPU | OCP_USER_SDMA, 2343 .user = OCP_USER_MPU | OCP_USER_SDMA,
2677}; 2344};
2678 2345
@@ -2685,9 +2352,7 @@ static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
2685 .name = "mcbsp4", 2352 .name = "mcbsp4",
2686 .class = &omap3xxx_mcbsp_hwmod_class, 2353 .class = &omap3xxx_mcbsp_hwmod_class,
2687 .mpu_irqs = omap3xxx_mcbsp4_irqs, 2354 .mpu_irqs = omap3xxx_mcbsp4_irqs,
2688 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp4_irqs),
2689 .sdma_reqs = omap3xxx_mcbsp4_sdma_chs, 2355 .sdma_reqs = omap3xxx_mcbsp4_sdma_chs,
2690 .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp4_sdma_chs),
2691 .main_clk = "mcbsp4_fck", 2356 .main_clk = "mcbsp4_fck",
2692 .prcm = { 2357 .prcm = {
2693 .omap2 = { 2358 .omap2 = {
@@ -2708,11 +2373,13 @@ static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = {
2708 { .name = "irq", .irq = 27 }, 2373 { .name = "irq", .irq = 27 },
2709 { .name = "tx", .irq = 81 }, 2374 { .name = "tx", .irq = 81 },
2710 { .name = "rx", .irq = 82 }, 2375 { .name = "rx", .irq = 82 },
2376 { .irq = -1 }
2711}; 2377};
2712 2378
2713static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = { 2379static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = {
2714 { .name = "rx", .dma_req = 22 }, 2380 { .name = "rx", .dma_req = 22 },
2715 { .name = "tx", .dma_req = 21 }, 2381 { .name = "tx", .dma_req = 21 },
2382 { .dma_req = -1 }
2716}; 2383};
2717 2384
2718static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = { 2385static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = {
@@ -2722,6 +2389,7 @@ static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = {
2722 .pa_end = 0x480960ff, 2389 .pa_end = 0x480960ff,
2723 .flags = ADDR_TYPE_RT 2390 .flags = ADDR_TYPE_RT
2724 }, 2391 },
2392 { }
2725}; 2393};
2726 2394
2727/* l4_core -> mcbsp5 */ 2395/* l4_core -> mcbsp5 */
@@ -2730,7 +2398,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = {
2730 .slave = &omap3xxx_mcbsp5_hwmod, 2398 .slave = &omap3xxx_mcbsp5_hwmod,
2731 .clk = "mcbsp5_ick", 2399 .clk = "mcbsp5_ick",
2732 .addr = omap3xxx_mcbsp5_addrs, 2400 .addr = omap3xxx_mcbsp5_addrs,
2733 .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp5_addrs),
2734 .user = OCP_USER_MPU | OCP_USER_SDMA, 2401 .user = OCP_USER_MPU | OCP_USER_SDMA,
2735}; 2402};
2736 2403
@@ -2743,9 +2410,7 @@ static struct omap_hwmod omap3xxx_mcbsp5_hwmod = {
2743 .name = "mcbsp5", 2410 .name = "mcbsp5",
2744 .class = &omap3xxx_mcbsp_hwmod_class, 2411 .class = &omap3xxx_mcbsp_hwmod_class,
2745 .mpu_irqs = omap3xxx_mcbsp5_irqs, 2412 .mpu_irqs = omap3xxx_mcbsp5_irqs,
2746 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp5_irqs),
2747 .sdma_reqs = omap3xxx_mcbsp5_sdma_chs, 2413 .sdma_reqs = omap3xxx_mcbsp5_sdma_chs,
2748 .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp5_sdma_chs),
2749 .main_clk = "mcbsp5_fck", 2414 .main_clk = "mcbsp5_fck",
2750 .prcm = { 2415 .prcm = {
2751 .omap2 = { 2416 .omap2 = {
@@ -2776,6 +2441,7 @@ static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = {
2776/* mcbsp2_sidetone */ 2441/* mcbsp2_sidetone */
2777static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = { 2442static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = {
2778 { .name = "irq", .irq = 4 }, 2443 { .name = "irq", .irq = 4 },
2444 { .irq = -1 }
2779}; 2445};
2780 2446
2781static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = { 2447static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = {
@@ -2785,6 +2451,7 @@ static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = {
2785 .pa_end = 0x490280ff, 2451 .pa_end = 0x490280ff,
2786 .flags = ADDR_TYPE_RT 2452 .flags = ADDR_TYPE_RT
2787 }, 2453 },
2454 { }
2788}; 2455};
2789 2456
2790/* l4_per -> mcbsp2_sidetone */ 2457/* l4_per -> mcbsp2_sidetone */
@@ -2793,7 +2460,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = {
2793 .slave = &omap3xxx_mcbsp2_sidetone_hwmod, 2460 .slave = &omap3xxx_mcbsp2_sidetone_hwmod,
2794 .clk = "mcbsp2_ick", 2461 .clk = "mcbsp2_ick",
2795 .addr = omap3xxx_mcbsp2_sidetone_addrs, 2462 .addr = omap3xxx_mcbsp2_sidetone_addrs,
2796 .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_sidetone_addrs),
2797 .user = OCP_USER_MPU, 2463 .user = OCP_USER_MPU,
2798}; 2464};
2799 2465
@@ -2806,7 +2472,6 @@ static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
2806 .name = "mcbsp2_sidetone", 2472 .name = "mcbsp2_sidetone",
2807 .class = &omap3xxx_mcbsp_sidetone_hwmod_class, 2473 .class = &omap3xxx_mcbsp_sidetone_hwmod_class,
2808 .mpu_irqs = omap3xxx_mcbsp2_sidetone_irqs, 2474 .mpu_irqs = omap3xxx_mcbsp2_sidetone_irqs,
2809 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_sidetone_irqs),
2810 .main_clk = "mcbsp2_fck", 2475 .main_clk = "mcbsp2_fck",
2811 .prcm = { 2476 .prcm = {
2812 .omap2 = { 2477 .omap2 = {
@@ -2825,6 +2490,7 @@ static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
2825/* mcbsp3_sidetone */ 2490/* mcbsp3_sidetone */
2826static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = { 2491static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = {
2827 { .name = "irq", .irq = 5 }, 2492 { .name = "irq", .irq = 5 },
2493 { .irq = -1 }
2828}; 2494};
2829 2495
2830static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = { 2496static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = {
@@ -2834,6 +2500,7 @@ static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = {
2834 .pa_end = 0x4902A0ff, 2500 .pa_end = 0x4902A0ff,
2835 .flags = ADDR_TYPE_RT 2501 .flags = ADDR_TYPE_RT
2836 }, 2502 },
2503 { }
2837}; 2504};
2838 2505
2839/* l4_per -> mcbsp3_sidetone */ 2506/* l4_per -> mcbsp3_sidetone */
@@ -2842,7 +2509,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = {
2842 .slave = &omap3xxx_mcbsp3_sidetone_hwmod, 2509 .slave = &omap3xxx_mcbsp3_sidetone_hwmod,
2843 .clk = "mcbsp3_ick", 2510 .clk = "mcbsp3_ick",
2844 .addr = omap3xxx_mcbsp3_sidetone_addrs, 2511 .addr = omap3xxx_mcbsp3_sidetone_addrs,
2845 .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_sidetone_addrs),
2846 .user = OCP_USER_MPU, 2512 .user = OCP_USER_MPU,
2847}; 2513};
2848 2514
@@ -2855,7 +2521,6 @@ static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = {
2855 .name = "mcbsp3_sidetone", 2521 .name = "mcbsp3_sidetone",
2856 .class = &omap3xxx_mcbsp_sidetone_hwmod_class, 2522 .class = &omap3xxx_mcbsp_sidetone_hwmod_class,
2857 .mpu_irqs = omap3xxx_mcbsp3_sidetone_irqs, 2523 .mpu_irqs = omap3xxx_mcbsp3_sidetone_irqs,
2858 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_sidetone_irqs),
2859 .main_clk = "mcbsp3_fck", 2524 .main_clk = "mcbsp3_fck",
2860 .prcm = { 2525 .prcm = {
2861 .omap2 = { 2526 .omap2 = {
@@ -3025,6 +2690,7 @@ static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = {
3025static struct omap_hwmod omap3xxx_mailbox_hwmod; 2690static struct omap_hwmod omap3xxx_mailbox_hwmod;
3026static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = { 2691static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = {
3027 { .irq = 26 }, 2692 { .irq = 26 },
2693 { .irq = -1 }
3028}; 2694};
3029 2695
3030static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = { 2696static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = {
@@ -3033,6 +2699,7 @@ static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = {
3033 .pa_end = 0x480941ff, 2699 .pa_end = 0x480941ff,
3034 .flags = ADDR_TYPE_RT, 2700 .flags = ADDR_TYPE_RT,
3035 }, 2701 },
2702 { }
3036}; 2703};
3037 2704
3038/* l4_core -> mailbox */ 2705/* l4_core -> mailbox */
@@ -3040,7 +2707,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = {
3040 .master = &omap3xxx_l4_core_hwmod, 2707 .master = &omap3xxx_l4_core_hwmod,
3041 .slave = &omap3xxx_mailbox_hwmod, 2708 .slave = &omap3xxx_mailbox_hwmod,
3042 .addr = omap3xxx_mailbox_addrs, 2709 .addr = omap3xxx_mailbox_addrs,
3043 .addr_cnt = ARRAY_SIZE(omap3xxx_mailbox_addrs),
3044 .user = OCP_USER_MPU | OCP_USER_SDMA, 2710 .user = OCP_USER_MPU | OCP_USER_SDMA,
3045}; 2711};
3046 2712
@@ -3053,7 +2719,6 @@ static struct omap_hwmod omap3xxx_mailbox_hwmod = {
3053 .name = "mailbox", 2719 .name = "mailbox",
3054 .class = &omap3xxx_mailbox_hwmod_class, 2720 .class = &omap3xxx_mailbox_hwmod_class,
3055 .mpu_irqs = omap3xxx_mailbox_irqs, 2721 .mpu_irqs = omap3xxx_mailbox_irqs,
3056 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mailbox_irqs),
3057 .main_clk = "mailboxes_ick", 2722 .main_clk = "mailboxes_ick",
3058 .prcm = { 2723 .prcm = {
3059 .omap2 = { 2724 .omap2 = {
@@ -3070,56 +2735,29 @@ static struct omap_hwmod omap3xxx_mailbox_hwmod = {
3070}; 2735};
3071 2736
3072/* l4 core -> mcspi1 interface */ 2737/* l4 core -> mcspi1 interface */
3073static struct omap_hwmod_addr_space omap34xx_mcspi1_addr_space[] = {
3074 {
3075 .pa_start = 0x48098000,
3076 .pa_end = 0x480980ff,
3077 .flags = ADDR_TYPE_RT,
3078 },
3079};
3080
3081static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = { 2738static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = {
3082 .master = &omap3xxx_l4_core_hwmod, 2739 .master = &omap3xxx_l4_core_hwmod,
3083 .slave = &omap34xx_mcspi1, 2740 .slave = &omap34xx_mcspi1,
3084 .clk = "mcspi1_ick", 2741 .clk = "mcspi1_ick",
3085 .addr = omap34xx_mcspi1_addr_space, 2742 .addr = omap2_mcspi1_addr_space,
3086 .addr_cnt = ARRAY_SIZE(omap34xx_mcspi1_addr_space),
3087 .user = OCP_USER_MPU | OCP_USER_SDMA, 2743 .user = OCP_USER_MPU | OCP_USER_SDMA,
3088}; 2744};
3089 2745
3090/* l4 core -> mcspi2 interface */ 2746/* l4 core -> mcspi2 interface */
3091static struct omap_hwmod_addr_space omap34xx_mcspi2_addr_space[] = {
3092 {
3093 .pa_start = 0x4809a000,
3094 .pa_end = 0x4809a0ff,
3095 .flags = ADDR_TYPE_RT,
3096 },
3097};
3098
3099static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = { 2747static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = {
3100 .master = &omap3xxx_l4_core_hwmod, 2748 .master = &omap3xxx_l4_core_hwmod,
3101 .slave = &omap34xx_mcspi2, 2749 .slave = &omap34xx_mcspi2,
3102 .clk = "mcspi2_ick", 2750 .clk = "mcspi2_ick",
3103 .addr = omap34xx_mcspi2_addr_space, 2751 .addr = omap2_mcspi2_addr_space,
3104 .addr_cnt = ARRAY_SIZE(omap34xx_mcspi2_addr_space),
3105 .user = OCP_USER_MPU | OCP_USER_SDMA, 2752 .user = OCP_USER_MPU | OCP_USER_SDMA,
3106}; 2753};
3107 2754
3108/* l4 core -> mcspi3 interface */ 2755/* l4 core -> mcspi3 interface */
3109static struct omap_hwmod_addr_space omap34xx_mcspi3_addr_space[] = {
3110 {
3111 .pa_start = 0x480b8000,
3112 .pa_end = 0x480b80ff,
3113 .flags = ADDR_TYPE_RT,
3114 },
3115};
3116
3117static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = { 2756static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = {
3118 .master = &omap3xxx_l4_core_hwmod, 2757 .master = &omap3xxx_l4_core_hwmod,
3119 .slave = &omap34xx_mcspi3, 2758 .slave = &omap34xx_mcspi3,
3120 .clk = "mcspi3_ick", 2759 .clk = "mcspi3_ick",
3121 .addr = omap34xx_mcspi3_addr_space, 2760 .addr = omap2430_mcspi3_addr_space,
3122 .addr_cnt = ARRAY_SIZE(omap34xx_mcspi3_addr_space),
3123 .user = OCP_USER_MPU | OCP_USER_SDMA, 2761 .user = OCP_USER_MPU | OCP_USER_SDMA,
3124}; 2762};
3125 2763
@@ -3130,6 +2768,7 @@ static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = {
3130 .pa_end = 0x480ba0ff, 2768 .pa_end = 0x480ba0ff,
3131 .flags = ADDR_TYPE_RT, 2769 .flags = ADDR_TYPE_RT,
3132 }, 2770 },
2771 { }
3133}; 2772};
3134 2773
3135static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = { 2774static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = {
@@ -3137,7 +2776,6 @@ static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = {
3137 .slave = &omap34xx_mcspi4, 2776 .slave = &omap34xx_mcspi4,
3138 .clk = "mcspi4_ick", 2777 .clk = "mcspi4_ick",
3139 .addr = omap34xx_mcspi4_addr_space, 2778 .addr = omap34xx_mcspi4_addr_space,
3140 .addr_cnt = ARRAY_SIZE(omap34xx_mcspi4_addr_space),
3141 .user = OCP_USER_MPU | OCP_USER_SDMA, 2779 .user = OCP_USER_MPU | OCP_USER_SDMA,
3142}; 2780};
3143 2781
@@ -3165,21 +2803,6 @@ static struct omap_hwmod_class omap34xx_mcspi_class = {
3165}; 2803};
3166 2804
3167/* mcspi1 */ 2805/* mcspi1 */
3168static struct omap_hwmod_irq_info omap34xx_mcspi1_mpu_irqs[] = {
3169 { .name = "irq", .irq = 65 },
3170};
3171
3172static struct omap_hwmod_dma_info omap34xx_mcspi1_sdma_reqs[] = {
3173 { .name = "tx0", .dma_req = 35 },
3174 { .name = "rx0", .dma_req = 36 },
3175 { .name = "tx1", .dma_req = 37 },
3176 { .name = "rx1", .dma_req = 38 },
3177 { .name = "tx2", .dma_req = 39 },
3178 { .name = "rx2", .dma_req = 40 },
3179 { .name = "tx3", .dma_req = 41 },
3180 { .name = "rx3", .dma_req = 42 },
3181};
3182
3183static struct omap_hwmod_ocp_if *omap34xx_mcspi1_slaves[] = { 2806static struct omap_hwmod_ocp_if *omap34xx_mcspi1_slaves[] = {
3184 &omap34xx_l4_core__mcspi1, 2807 &omap34xx_l4_core__mcspi1,
3185}; 2808};
@@ -3190,10 +2813,8 @@ static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
3190 2813
3191static struct omap_hwmod omap34xx_mcspi1 = { 2814static struct omap_hwmod omap34xx_mcspi1 = {
3192 .name = "mcspi1", 2815 .name = "mcspi1",
3193 .mpu_irqs = omap34xx_mcspi1_mpu_irqs, 2816 .mpu_irqs = omap2_mcspi1_mpu_irqs,
3194 .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mcspi1_mpu_irqs), 2817 .sdma_reqs = omap2_mcspi1_sdma_reqs,
3195 .sdma_reqs = omap34xx_mcspi1_sdma_reqs,
3196 .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mcspi1_sdma_reqs),
3197 .main_clk = "mcspi1_fck", 2818 .main_clk = "mcspi1_fck",
3198 .prcm = { 2819 .prcm = {
3199 .omap2 = { 2820 .omap2 = {
@@ -3212,17 +2833,6 @@ static struct omap_hwmod omap34xx_mcspi1 = {
3212}; 2833};
3213 2834
3214/* mcspi2 */ 2835/* mcspi2 */
3215static struct omap_hwmod_irq_info omap34xx_mcspi2_mpu_irqs[] = {
3216 { .name = "irq", .irq = 66 },
3217};
3218
3219static struct omap_hwmod_dma_info omap34xx_mcspi2_sdma_reqs[] = {
3220 { .name = "tx0", .dma_req = 43 },
3221 { .name = "rx0", .dma_req = 44 },
3222 { .name = "tx1", .dma_req = 45 },
3223 { .name = "rx1", .dma_req = 46 },
3224};
3225
3226static struct omap_hwmod_ocp_if *omap34xx_mcspi2_slaves[] = { 2836static struct omap_hwmod_ocp_if *omap34xx_mcspi2_slaves[] = {
3227 &omap34xx_l4_core__mcspi2, 2837 &omap34xx_l4_core__mcspi2,
3228}; 2838};
@@ -3233,10 +2843,8 @@ static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
3233 2843
3234static struct omap_hwmod omap34xx_mcspi2 = { 2844static struct omap_hwmod omap34xx_mcspi2 = {
3235 .name = "mcspi2", 2845 .name = "mcspi2",
3236 .mpu_irqs = omap34xx_mcspi2_mpu_irqs, 2846 .mpu_irqs = omap2_mcspi2_mpu_irqs,
3237 .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mcspi2_mpu_irqs), 2847 .sdma_reqs = omap2_mcspi2_sdma_reqs,
3238 .sdma_reqs = omap34xx_mcspi2_sdma_reqs,
3239 .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mcspi2_sdma_reqs),
3240 .main_clk = "mcspi2_fck", 2848 .main_clk = "mcspi2_fck",
3241 .prcm = { 2849 .prcm = {
3242 .omap2 = { 2850 .omap2 = {
@@ -3257,6 +2865,7 @@ static struct omap_hwmod omap34xx_mcspi2 = {
3257/* mcspi3 */ 2865/* mcspi3 */
3258static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = { 2866static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = {
3259 { .name = "irq", .irq = 91 }, /* 91 */ 2867 { .name = "irq", .irq = 91 }, /* 91 */
2868 { .irq = -1 }
3260}; 2869};
3261 2870
3262static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = { 2871static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = {
@@ -3264,6 +2873,7 @@ static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = {
3264 { .name = "rx0", .dma_req = 16 }, 2873 { .name = "rx0", .dma_req = 16 },
3265 { .name = "tx1", .dma_req = 23 }, 2874 { .name = "tx1", .dma_req = 23 },
3266 { .name = "rx1", .dma_req = 24 }, 2875 { .name = "rx1", .dma_req = 24 },
2876 { .dma_req = -1 }
3267}; 2877};
3268 2878
3269static struct omap_hwmod_ocp_if *omap34xx_mcspi3_slaves[] = { 2879static struct omap_hwmod_ocp_if *omap34xx_mcspi3_slaves[] = {
@@ -3277,9 +2887,7 @@ static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
3277static struct omap_hwmod omap34xx_mcspi3 = { 2887static struct omap_hwmod omap34xx_mcspi3 = {
3278 .name = "mcspi3", 2888 .name = "mcspi3",
3279 .mpu_irqs = omap34xx_mcspi3_mpu_irqs, 2889 .mpu_irqs = omap34xx_mcspi3_mpu_irqs,
3280 .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mcspi3_mpu_irqs),
3281 .sdma_reqs = omap34xx_mcspi3_sdma_reqs, 2890 .sdma_reqs = omap34xx_mcspi3_sdma_reqs,
3282 .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mcspi3_sdma_reqs),
3283 .main_clk = "mcspi3_fck", 2891 .main_clk = "mcspi3_fck",
3284 .prcm = { 2892 .prcm = {
3285 .omap2 = { 2893 .omap2 = {
@@ -3300,11 +2908,13 @@ static struct omap_hwmod omap34xx_mcspi3 = {
3300/* SPI4 */ 2908/* SPI4 */
3301static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = { 2909static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = {
3302 { .name = "irq", .irq = INT_34XX_SPI4_IRQ }, /* 48 */ 2910 { .name = "irq", .irq = INT_34XX_SPI4_IRQ }, /* 48 */
2911 { .irq = -1 }
3303}; 2912};
3304 2913
3305static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = { 2914static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = {
3306 { .name = "tx0", .dma_req = 70 }, /* DMA_SPI4_TX0 */ 2915 { .name = "tx0", .dma_req = 70 }, /* DMA_SPI4_TX0 */
3307 { .name = "rx0", .dma_req = 71 }, /* DMA_SPI4_RX0 */ 2916 { .name = "rx0", .dma_req = 71 }, /* DMA_SPI4_RX0 */
2917 { .dma_req = -1 }
3308}; 2918};
3309 2919
3310static struct omap_hwmod_ocp_if *omap34xx_mcspi4_slaves[] = { 2920static struct omap_hwmod_ocp_if *omap34xx_mcspi4_slaves[] = {
@@ -3318,9 +2928,7 @@ static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = {
3318static struct omap_hwmod omap34xx_mcspi4 = { 2928static struct omap_hwmod omap34xx_mcspi4 = {
3319 .name = "mcspi4", 2929 .name = "mcspi4",
3320 .mpu_irqs = omap34xx_mcspi4_mpu_irqs, 2930 .mpu_irqs = omap34xx_mcspi4_mpu_irqs,
3321 .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mcspi4_mpu_irqs),
3322 .sdma_reqs = omap34xx_mcspi4_sdma_reqs, 2931 .sdma_reqs = omap34xx_mcspi4_sdma_reqs,
3323 .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mcspi4_sdma_reqs),
3324 .main_clk = "mcspi4_fck", 2932 .main_clk = "mcspi4_fck",
3325 .prcm = { 2933 .prcm = {
3326 .omap2 = { 2934 .omap2 = {
@@ -3362,12 +2970,12 @@ static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = {
3362 2970
3363 { .name = "mc", .irq = 92 }, 2971 { .name = "mc", .irq = 92 },
3364 { .name = "dma", .irq = 93 }, 2972 { .name = "dma", .irq = 93 },
2973 { .irq = -1 }
3365}; 2974};
3366 2975
3367static struct omap_hwmod omap3xxx_usbhsotg_hwmod = { 2976static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
3368 .name = "usb_otg_hs", 2977 .name = "usb_otg_hs",
3369 .mpu_irqs = omap3xxx_usbhsotg_mpu_irqs, 2978 .mpu_irqs = omap3xxx_usbhsotg_mpu_irqs,
3370 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_mpu_irqs),
3371 .main_clk = "hsotgusb_ick", 2979 .main_clk = "hsotgusb_ick",
3372 .prcm = { 2980 .prcm = {
3373 .omap2 = { 2981 .omap2 = {
@@ -3399,6 +3007,7 @@ static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
3399static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = { 3007static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = {
3400 3008
3401 { .name = "mc", .irq = 71 }, 3009 { .name = "mc", .irq = 71 },
3010 { .irq = -1 }
3402}; 3011};
3403 3012
3404static struct omap_hwmod_class am35xx_usbotg_class = { 3013static struct omap_hwmod_class am35xx_usbotg_class = {
@@ -3409,7 +3018,6 @@ static struct omap_hwmod_class am35xx_usbotg_class = {
3409static struct omap_hwmod am35xx_usbhsotg_hwmod = { 3018static struct omap_hwmod am35xx_usbhsotg_hwmod = {
3410 .name = "am35x_otg_hs", 3019 .name = "am35x_otg_hs",
3411 .mpu_irqs = am35xx_usbhsotg_mpu_irqs, 3020 .mpu_irqs = am35xx_usbhsotg_mpu_irqs,
3412 .mpu_irqs_cnt = ARRAY_SIZE(am35xx_usbhsotg_mpu_irqs),
3413 .main_clk = NULL, 3021 .main_clk = NULL,
3414 .prcm = { 3022 .prcm = {
3415 .omap2 = { 3023 .omap2 = {
@@ -3445,11 +3053,13 @@ static struct omap_hwmod_class omap34xx_mmc_class = {
3445 3053
3446static struct omap_hwmod_irq_info omap34xx_mmc1_mpu_irqs[] = { 3054static struct omap_hwmod_irq_info omap34xx_mmc1_mpu_irqs[] = {
3447 { .irq = 83, }, 3055 { .irq = 83, },
3056 { .irq = -1 }
3448}; 3057};
3449 3058
3450static struct omap_hwmod_dma_info omap34xx_mmc1_sdma_reqs[] = { 3059static struct omap_hwmod_dma_info omap34xx_mmc1_sdma_reqs[] = {
3451 { .name = "tx", .dma_req = 61, }, 3060 { .name = "tx", .dma_req = 61, },
3452 { .name = "rx", .dma_req = 62, }, 3061 { .name = "rx", .dma_req = 62, },
3062 { .dma_req = -1 }
3453}; 3063};
3454 3064
3455static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = { 3065static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = {
@@ -3467,9 +3077,7 @@ static struct omap_mmc_dev_attr mmc1_dev_attr = {
3467static struct omap_hwmod omap3xxx_mmc1_hwmod = { 3077static struct omap_hwmod omap3xxx_mmc1_hwmod = {
3468 .name = "mmc1", 3078 .name = "mmc1",
3469 .mpu_irqs = omap34xx_mmc1_mpu_irqs, 3079 .mpu_irqs = omap34xx_mmc1_mpu_irqs,
3470 .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mmc1_mpu_irqs),
3471 .sdma_reqs = omap34xx_mmc1_sdma_reqs, 3080 .sdma_reqs = omap34xx_mmc1_sdma_reqs,
3472 .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mmc1_sdma_reqs),
3473 .opt_clks = omap34xx_mmc1_opt_clks, 3081 .opt_clks = omap34xx_mmc1_opt_clks,
3474 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks), 3082 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
3475 .main_clk = "mmchs1_fck", 3083 .main_clk = "mmchs1_fck",
@@ -3493,11 +3101,13 @@ static struct omap_hwmod omap3xxx_mmc1_hwmod = {
3493 3101
3494static struct omap_hwmod_irq_info omap34xx_mmc2_mpu_irqs[] = { 3102static struct omap_hwmod_irq_info omap34xx_mmc2_mpu_irqs[] = {
3495 { .irq = INT_24XX_MMC2_IRQ, }, 3103 { .irq = INT_24XX_MMC2_IRQ, },
3104 { .irq = -1 }
3496}; 3105};
3497 3106
3498static struct omap_hwmod_dma_info omap34xx_mmc2_sdma_reqs[] = { 3107static struct omap_hwmod_dma_info omap34xx_mmc2_sdma_reqs[] = {
3499 { .name = "tx", .dma_req = 47, }, 3108 { .name = "tx", .dma_req = 47, },
3500 { .name = "rx", .dma_req = 48, }, 3109 { .name = "rx", .dma_req = 48, },
3110 { .dma_req = -1 }
3501}; 3111};
3502 3112
3503static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = { 3113static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = {
@@ -3511,9 +3121,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_mmc2_slaves[] = {
3511static struct omap_hwmod omap3xxx_mmc2_hwmod = { 3121static struct omap_hwmod omap3xxx_mmc2_hwmod = {
3512 .name = "mmc2", 3122 .name = "mmc2",
3513 .mpu_irqs = omap34xx_mmc2_mpu_irqs, 3123 .mpu_irqs = omap34xx_mmc2_mpu_irqs,
3514 .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mmc2_mpu_irqs),
3515 .sdma_reqs = omap34xx_mmc2_sdma_reqs, 3124 .sdma_reqs = omap34xx_mmc2_sdma_reqs,
3516 .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mmc2_sdma_reqs),
3517 .opt_clks = omap34xx_mmc2_opt_clks, 3125 .opt_clks = omap34xx_mmc2_opt_clks,
3518 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks), 3126 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
3519 .main_clk = "mmchs2_fck", 3127 .main_clk = "mmchs2_fck",
@@ -3536,11 +3144,13 @@ static struct omap_hwmod omap3xxx_mmc2_hwmod = {
3536 3144
3537static struct omap_hwmod_irq_info omap34xx_mmc3_mpu_irqs[] = { 3145static struct omap_hwmod_irq_info omap34xx_mmc3_mpu_irqs[] = {
3538 { .irq = 94, }, 3146 { .irq = 94, },
3147 { .irq = -1 }
3539}; 3148};
3540 3149
3541static struct omap_hwmod_dma_info omap34xx_mmc3_sdma_reqs[] = { 3150static struct omap_hwmod_dma_info omap34xx_mmc3_sdma_reqs[] = {
3542 { .name = "tx", .dma_req = 77, }, 3151 { .name = "tx", .dma_req = 77, },
3543 { .name = "rx", .dma_req = 78, }, 3152 { .name = "rx", .dma_req = 78, },
3153 { .dma_req = -1 }
3544}; 3154};
3545 3155
3546static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = { 3156static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = {
@@ -3554,9 +3164,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_mmc3_slaves[] = {
3554static struct omap_hwmod omap3xxx_mmc3_hwmod = { 3164static struct omap_hwmod omap3xxx_mmc3_hwmod = {
3555 .name = "mmc3", 3165 .name = "mmc3",
3556 .mpu_irqs = omap34xx_mmc3_mpu_irqs, 3166 .mpu_irqs = omap34xx_mmc3_mpu_irqs,
3557 .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mmc3_mpu_irqs),
3558 .sdma_reqs = omap34xx_mmc3_sdma_reqs, 3167 .sdma_reqs = omap34xx_mmc3_sdma_reqs,
3559 .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mmc3_sdma_reqs),
3560 .opt_clks = omap34xx_mmc3_opt_clks, 3168 .opt_clks = omap34xx_mmc3_opt_clks,
3561 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc3_opt_clks), 3169 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc3_opt_clks),
3562 .main_clk = "mmchs3_fck", 3170 .main_clk = "mmchs3_fck",
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-14 07:55:45 -0500