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-rw-r--r--arch/arm/mach-omap2/omap_hwmod_3xxx_data.c69
1 files changed, 33 insertions, 36 deletions
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index f67b7ee07dd4..8bb2628df34e 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -14,28 +14,32 @@
14 * 14 *
15 * XXX these should be marked initdata for multi-OMAP kernels 15 * XXX these should be marked initdata for multi-OMAP kernels
16 */ 16 */
17
18#include <linux/i2c-omap.h>
17#include <linux/power/smartreflex.h> 19#include <linux/power/smartreflex.h>
18#include <linux/platform_data/gpio-omap.h> 20#include <linux/platform_data/gpio-omap.h>
19 21
20#include <plat/omap_hwmod.h> 22#include <linux/omap-dma.h>
21#include <plat/dma.h>
22#include <plat/serial.h>
23#include "l3_3xxx.h" 23#include "l3_3xxx.h"
24#include "l4_3xxx.h" 24#include "l4_3xxx.h"
25#include <plat/i2c.h>
26#include <plat/mmc.h>
27#include <linux/platform_data/asoc-ti-mcbsp.h> 25#include <linux/platform_data/asoc-ti-mcbsp.h>
28#include <linux/platform_data/spi-omap2-mcspi.h> 26#include <linux/platform_data/spi-omap2-mcspi.h>
27#include <linux/platform_data/iommu-omap.h>
29#include <plat/dmtimer.h> 28#include <plat/dmtimer.h>
30#include <plat/iommu.h>
31 29
32#include "am35xx.h" 30#include "am35xx.h"
33 31
34#include "soc.h" 32#include "soc.h"
33#include "omap_hwmod.h"
35#include "omap_hwmod_common_data.h" 34#include "omap_hwmod_common_data.h"
36#include "prm-regbits-34xx.h" 35#include "prm-regbits-34xx.h"
37#include "cm-regbits-34xx.h" 36#include "cm-regbits-34xx.h"
37
38#include "dma.h"
39#include "i2c.h"
40#include "mmc.h"
38#include "wd_timer.h" 41#include "wd_timer.h"
42#include "serial.h"
39 43
40/* 44/*
41 * OMAP3xxx hardware module integration data 45 * OMAP3xxx hardware module integration data
@@ -149,29 +153,16 @@ static struct omap_hwmod omap3xxx_debugss_hwmod = {
149}; 153};
150 154
151/* timer class */ 155/* timer class */
152static struct omap_hwmod_class_sysconfig omap3xxx_timer_1ms_sysc = {
153 .rev_offs = 0x0000,
154 .sysc_offs = 0x0010,
155 .syss_offs = 0x0014,
156 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
157 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
158 SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE),
159 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
160 .sysc_fields = &omap_hwmod_sysc_type1,
161};
162
163static struct omap_hwmod_class omap3xxx_timer_1ms_hwmod_class = {
164 .name = "timer",
165 .sysc = &omap3xxx_timer_1ms_sysc,
166};
167
168static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = { 156static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = {
169 .rev_offs = 0x0000, 157 .rev_offs = 0x0000,
170 .sysc_offs = 0x0010, 158 .sysc_offs = 0x0010,
171 .syss_offs = 0x0014, 159 .syss_offs = 0x0014,
172 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP | 160 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
173 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), 161 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
162 SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE |
163 SYSS_HAS_RESET_STATUS),
174 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 164 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
165 .clockact = CLOCKACT_TEST_ICLK,
175 .sysc_fields = &omap_hwmod_sysc_type1, 166 .sysc_fields = &omap_hwmod_sysc_type1,
176}; 167};
177 168
@@ -220,7 +211,8 @@ static struct omap_hwmod omap3xxx_timer1_hwmod = {
220 }, 211 },
221 }, 212 },
222 .dev_attr = &capability_alwon_dev_attr, 213 .dev_attr = &capability_alwon_dev_attr,
223 .class = &omap3xxx_timer_1ms_hwmod_class, 214 .class = &omap3xxx_timer_hwmod_class,
215 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
224}; 216};
225 217
226/* timer2 */ 218/* timer2 */
@@ -237,7 +229,8 @@ static struct omap_hwmod omap3xxx_timer2_hwmod = {
237 .idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT, 229 .idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT,
238 }, 230 },
239 }, 231 },
240 .class = &omap3xxx_timer_1ms_hwmod_class, 232 .class = &omap3xxx_timer_hwmod_class,
233 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
241}; 234};
242 235
243/* timer3 */ 236/* timer3 */
@@ -255,6 +248,7 @@ static struct omap_hwmod omap3xxx_timer3_hwmod = {
255 }, 248 },
256 }, 249 },
257 .class = &omap3xxx_timer_hwmod_class, 250 .class = &omap3xxx_timer_hwmod_class,
251 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
258}; 252};
259 253
260/* timer4 */ 254/* timer4 */
@@ -272,6 +266,7 @@ static struct omap_hwmod omap3xxx_timer4_hwmod = {
272 }, 266 },
273 }, 267 },
274 .class = &omap3xxx_timer_hwmod_class, 268 .class = &omap3xxx_timer_hwmod_class,
269 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
275}; 270};
276 271
277/* timer5 */ 272/* timer5 */
@@ -290,6 +285,7 @@ static struct omap_hwmod omap3xxx_timer5_hwmod = {
290 }, 285 },
291 .dev_attr = &capability_dsp_dev_attr, 286 .dev_attr = &capability_dsp_dev_attr,
292 .class = &omap3xxx_timer_hwmod_class, 287 .class = &omap3xxx_timer_hwmod_class,
288 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
293}; 289};
294 290
295/* timer6 */ 291/* timer6 */
@@ -308,6 +304,7 @@ static struct omap_hwmod omap3xxx_timer6_hwmod = {
308 }, 304 },
309 .dev_attr = &capability_dsp_dev_attr, 305 .dev_attr = &capability_dsp_dev_attr,
310 .class = &omap3xxx_timer_hwmod_class, 306 .class = &omap3xxx_timer_hwmod_class,
307 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
311}; 308};
312 309
313/* timer7 */ 310/* timer7 */
@@ -326,6 +323,7 @@ static struct omap_hwmod omap3xxx_timer7_hwmod = {
326 }, 323 },
327 .dev_attr = &capability_dsp_dev_attr, 324 .dev_attr = &capability_dsp_dev_attr,
328 .class = &omap3xxx_timer_hwmod_class, 325 .class = &omap3xxx_timer_hwmod_class,
326 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
329}; 327};
330 328
331/* timer8 */ 329/* timer8 */
@@ -344,6 +342,7 @@ static struct omap_hwmod omap3xxx_timer8_hwmod = {
344 }, 342 },
345 .dev_attr = &capability_dsp_pwm_dev_attr, 343 .dev_attr = &capability_dsp_pwm_dev_attr,
346 .class = &omap3xxx_timer_hwmod_class, 344 .class = &omap3xxx_timer_hwmod_class,
345 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
347}; 346};
348 347
349/* timer9 */ 348/* timer9 */
@@ -362,6 +361,7 @@ static struct omap_hwmod omap3xxx_timer9_hwmod = {
362 }, 361 },
363 .dev_attr = &capability_pwm_dev_attr, 362 .dev_attr = &capability_pwm_dev_attr,
364 .class = &omap3xxx_timer_hwmod_class, 363 .class = &omap3xxx_timer_hwmod_class,
364 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
365}; 365};
366 366
367/* timer10 */ 367/* timer10 */
@@ -379,7 +379,8 @@ static struct omap_hwmod omap3xxx_timer10_hwmod = {
379 }, 379 },
380 }, 380 },
381 .dev_attr = &capability_pwm_dev_attr, 381 .dev_attr = &capability_pwm_dev_attr,
382 .class = &omap3xxx_timer_1ms_hwmod_class, 382 .class = &omap3xxx_timer_hwmod_class,
383 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
383}; 384};
384 385
385/* timer11 */ 386/* timer11 */
@@ -398,6 +399,7 @@ static struct omap_hwmod omap3xxx_timer11_hwmod = {
398 }, 399 },
399 .dev_attr = &capability_pwm_dev_attr, 400 .dev_attr = &capability_pwm_dev_attr,
400 .class = &omap3xxx_timer_hwmod_class, 401 .class = &omap3xxx_timer_hwmod_class,
402 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
401}; 403};
402 404
403/* timer12 */ 405/* timer12 */
@@ -421,6 +423,7 @@ static struct omap_hwmod omap3xxx_timer12_hwmod = {
421 }, 423 },
422 .dev_attr = &capability_secure_dev_attr, 424 .dev_attr = &capability_secure_dev_attr,
423 .class = &omap3xxx_timer_hwmod_class, 425 .class = &omap3xxx_timer_hwmod_class,
426 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
424}; 427};
425 428
426/* 429/*
@@ -791,9 +794,7 @@ static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
791/* I2C1 */ 794/* I2C1 */
792static struct omap_i2c_dev_attr i2c1_dev_attr = { 795static struct omap_i2c_dev_attr i2c1_dev_attr = {
793 .fifo_depth = 8, /* bytes */ 796 .fifo_depth = 8, /* bytes */
794 .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 | 797 .flags = OMAP_I2C_FLAG_BUS_SHIFT_2,
795 OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
796 OMAP_I2C_FLAG_BUS_SHIFT_2,
797}; 798};
798 799
799static struct omap_hwmod omap3xxx_i2c1_hwmod = { 800static struct omap_hwmod omap3xxx_i2c1_hwmod = {
@@ -818,9 +819,7 @@ static struct omap_hwmod omap3xxx_i2c1_hwmod = {
818/* I2C2 */ 819/* I2C2 */
819static struct omap_i2c_dev_attr i2c2_dev_attr = { 820static struct omap_i2c_dev_attr i2c2_dev_attr = {
820 .fifo_depth = 8, /* bytes */ 821 .fifo_depth = 8, /* bytes */
821 .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 | 822 .flags = OMAP_I2C_FLAG_BUS_SHIFT_2,
822 OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
823 OMAP_I2C_FLAG_BUS_SHIFT_2,
824}; 823};
825 824
826static struct omap_hwmod omap3xxx_i2c2_hwmod = { 825static struct omap_hwmod omap3xxx_i2c2_hwmod = {
@@ -845,9 +844,7 @@ static struct omap_hwmod omap3xxx_i2c2_hwmod = {
845/* I2C3 */ 844/* I2C3 */
846static struct omap_i2c_dev_attr i2c3_dev_attr = { 845static struct omap_i2c_dev_attr i2c3_dev_attr = {
847 .fifo_depth = 64, /* bytes */ 846 .fifo_depth = 64, /* bytes */
848 .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 | 847 .flags = OMAP_I2C_FLAG_BUS_SHIFT_2,
849 OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
850 OMAP_I2C_FLAG_BUS_SHIFT_2,
851}; 848};
852 849
853static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = { 850static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {