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-rw-r--r--arch/arm/mach-omap2/include/mach/entry-macro.S137
-rw-r--r--arch/arm/mach-omap2/include/mach/omap4-common.h43
-rw-r--r--arch/arm/mach-omap2/include/mach/vmalloc.h20
3 files changed, 0 insertions, 200 deletions
diff --git a/arch/arm/mach-omap2/include/mach/entry-macro.S b/arch/arm/mach-omap2/include/mach/entry-macro.S
index feb90a10945a..56964a0c4c7e 100644
--- a/arch/arm/mach-omap2/include/mach/entry-macro.S
+++ b/arch/arm/mach-omap2/include/mach/entry-macro.S
@@ -10,146 +10,9 @@
10 * License version 2. This program is licensed "as is" without any 10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied. 11 * warranty of any kind, whether express or implied.
12 */ 12 */
13#include <mach/hardware.h>
14#include <mach/io.h>
15#include <mach/irqs.h>
16#include <asm/hardware/gic.h>
17
18#include <plat/omap24xx.h>
19#include <plat/omap34xx.h>
20#include <plat/omap44xx.h>
21
22#include <plat/multi.h>
23
24#define OMAP2_IRQ_BASE OMAP2_L4_IO_ADDRESS(OMAP24XX_IC_BASE)
25#define OMAP3_IRQ_BASE OMAP2_L4_IO_ADDRESS(OMAP34XX_IC_BASE)
26#define OMAP4_IRQ_BASE OMAP2_L4_IO_ADDRESS(OMAP44XX_GIC_CPU_BASE)
27#define INTCPS_SIR_IRQ_OFFSET 0x0040 /* omap2/3 active interrupt offset */
28#define ACTIVEIRQ_MASK 0x7f /* omap2/3 active interrupt bits */
29 13
30 .macro disable_fiq 14 .macro disable_fiq
31 .endm 15 .endm
32 16
33 .macro arch_ret_to_user, tmp1, tmp2 17 .macro arch_ret_to_user, tmp1, tmp2
34 .endm 18 .endm
35
36/*
37 * Unoptimized irq functions for multi-omap2, 3 and 4
38 */
39
40#ifdef MULTI_OMAP2
41 /*
42 * Configure the interrupt base on the first interrupt.
43 * See also omap_irq_base_init for setting omap_irq_base.
44 */
45 .macro get_irqnr_preamble, base, tmp
46 ldr \base, =omap_irq_base @ irq base address
47 ldr \base, [\base, #0] @ irq base value
48 .endm
49
50 /* Check the pending interrupts. Note that base already set */
51 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
52 tst \base, #0x100 @ gic address?
53 bne 4401f @ found gic
54
55 /* Handle omap2 and omap3 */
56 ldr \irqnr, [\base, #0x98] /* IRQ pending reg 1 */
57 cmp \irqnr, #0x0
58 bne 9998f
59 ldr \irqnr, [\base, #0xb8] /* IRQ pending reg 2 */
60 cmp \irqnr, #0x0
61 bne 9998f
62 ldr \irqnr, [\base, #0xd8] /* IRQ pending reg 3 */
63 cmp \irqnr, #0x0
64 bne 9998f
65
66 /*
67 * ti816x has additional IRQ pending register. Checking this
68 * register on omap2 & omap3 has no effect (read as 0).
69 */
70 ldr \irqnr, [\base, #0xf8] /* IRQ pending reg 4 */
71 cmp \irqnr, #0x0
729998:
73 ldrne \irqnr, [\base, #INTCPS_SIR_IRQ_OFFSET]
74 and \irqnr, \irqnr, #ACTIVEIRQ_MASK /* Clear spurious bits */
75 b 9999f
76
77 /* Handle omap4 */
784401: ldr \irqstat, [\base, #GIC_CPU_INTACK]
79 ldr \tmp, =1021
80 bic \irqnr, \irqstat, #0x1c00
81 cmp \irqnr, #15
82 cmpcc \irqnr, \irqnr
83 cmpne \irqnr, \tmp
84 cmpcs \irqnr, \irqnr
859999:
86 .endm
87
88#ifdef CONFIG_SMP
89 /* We assume that irqstat (the raw value of the IRQ acknowledge
90 * register) is preserved from the macro above.
91 * If there is an IPI, we immediately signal end of interrupt
92 * on the controller, since this requires the original irqstat
93 * value which we won't easily be able to recreate later.
94 */
95
96 .macro test_for_ipi, irqnr, irqstat, base, tmp
97 bic \irqnr, \irqstat, #0x1c00
98 cmp \irqnr, #16
99 it cc
100 strcc \irqstat, [\base, #GIC_CPU_EOI]
101 it cs
102 cmpcs \irqnr, \irqnr
103 .endm
104#endif /* CONFIG_SMP */
105
106#else /* MULTI_OMAP2 */
107
108
109/*
110 * Optimized irq functions for omap2, 3 and 4
111 */
112
113#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
114 .macro get_irqnr_preamble, base, tmp
115#ifdef CONFIG_ARCH_OMAP2
116 ldr \base, =OMAP2_IRQ_BASE
117#else
118 ldr \base, =OMAP3_IRQ_BASE
119#endif
120 .endm
121
122 /* Check the pending interrupts. Note that base already set */
123 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
124 ldr \irqnr, [\base, #0x98] /* IRQ pending reg 1 */
125 cmp \irqnr, #0x0
126 bne 9999f
127 ldr \irqnr, [\base, #0xb8] /* IRQ pending reg 2 */
128 cmp \irqnr, #0x0
129 bne 9999f
130 ldr \irqnr, [\base, #0xd8] /* IRQ pending reg 3 */
131 cmp \irqnr, #0x0
132#ifdef CONFIG_SOC_OMAPTI816X
133 bne 9999f
134 ldr \irqnr, [\base, #0xf8] /* IRQ pending reg 4 */
135 cmp \irqnr, #0x0
136#endif
1379999:
138 ldrne \irqnr, [\base, #INTCPS_SIR_IRQ_OFFSET]
139 and \irqnr, \irqnr, #ACTIVEIRQ_MASK /* Clear spurious bits */
140
141 .endm
142#endif
143
144
145#ifdef CONFIG_ARCH_OMAP4
146#define HAVE_GET_IRQNR_PREAMBLE
147#include <asm/hardware/entry-macro-gic.S>
148
149 .macro get_irqnr_preamble, base, tmp
150 ldr \base, =OMAP4_IRQ_BASE
151 .endm
152
153#endif
154
155#endif /* MULTI_OMAP2 */
diff --git a/arch/arm/mach-omap2/include/mach/omap4-common.h b/arch/arm/mach-omap2/include/mach/omap4-common.h
deleted file mode 100644
index e4bd87619734..000000000000
--- a/arch/arm/mach-omap2/include/mach/omap4-common.h
+++ /dev/null
@@ -1,43 +0,0 @@
1/*
2 * omap4-common.h: OMAP4 specific common header file
3 *
4 * Copyright (C) 2010 Texas Instruments, Inc.
5 *
6 * Author:
7 * Santosh Shilimkar <santosh.shilimkar@ti.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13#ifndef OMAP_ARCH_OMAP4_COMMON_H
14#define OMAP_ARCH_OMAP4_COMMON_H
15
16/*
17 * wfi used in low power code. Directly opcode is used instead
18 * of instruction to avoid mulit-omap build break
19 */
20#ifdef CONFIG_THUMB2_KERNEL
21#define do_wfi() __asm__ __volatile__ ("wfi" : : : "memory")
22#else
23#define do_wfi() \
24 __asm__ __volatile__ (".word 0xe320f003" : : : "memory")
25#endif
26
27#ifdef CONFIG_CACHE_L2X0
28extern void __iomem *l2cache_base;
29#endif
30
31extern void __iomem *gic_dist_base_addr;
32
33extern void __init gic_init_irq(void);
34extern void omap_smc1(u32 fn, u32 arg);
35
36#ifdef CONFIG_SMP
37/* Needed for secondary core boot */
38extern void omap_secondary_startup(void);
39extern u32 omap_modify_auxcoreboot0(u32 set_mask, u32 clear_mask);
40extern void omap_auxcoreboot_addr(u32 cpu_addr);
41extern u32 omap_read_auxcoreboot0(void);
42#endif
43#endif
diff --git a/arch/arm/mach-omap2/include/mach/vmalloc.h b/arch/arm/mach-omap2/include/mach/vmalloc.h
deleted file mode 100644
index 866319947760..000000000000
--- a/arch/arm/mach-omap2/include/mach/vmalloc.h
+++ /dev/null
@@ -1,20 +0,0 @@
1/*
2 * arch/arm/plat-omap/include/mach/vmalloc.h
3 *
4 * Copyright (C) 2000 Russell King.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20#define VMALLOC_END 0xf8000000UL
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-09 21:22:54 -0500