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Diffstat (limited to 'arch/arm/mach-omap2/gpmc-onenand.c')
-rw-r--r--arch/arm/mach-omap2/gpmc-onenand.c39
1 files changed, 5 insertions, 34 deletions
diff --git a/arch/arm/mach-omap2/gpmc-onenand.c b/arch/arm/mach-omap2/gpmc-onenand.c
index 29d391b273fc..50165aa4205a 100644
--- a/arch/arm/mach-omap2/gpmc-onenand.c
+++ b/arch/arm/mach-omap2/gpmc-onenand.c
@@ -140,21 +140,10 @@ static void set_onenand_cfg(void __iomem *onenand_base)
140} 140}
141 141
142static int omap2_onenand_get_freq(struct omap_onenand_platform_data *cfg, 142static int omap2_onenand_get_freq(struct omap_onenand_platform_data *cfg,
143 void __iomem *onenand_base, bool *clk_dep) 143 void __iomem *onenand_base)
144{ 144{
145 u16 ver = readw(onenand_base + ONENAND_REG_VERSION_ID); 145 u16 ver = readw(onenand_base + ONENAND_REG_VERSION_ID);
146 int freq = 0; 146 int freq;
147
148 if (cfg->get_freq) {
149 struct onenand_freq_info fi;
150
151 fi.maf_id = readw(onenand_base + ONENAND_REG_MANUFACTURER_ID);
152 fi.dev_id = readw(onenand_base + ONENAND_REG_DEVICE_ID);
153 fi.ver_id = ver;
154 freq = cfg->get_freq(&fi, clk_dep);
155 if (freq)
156 return freq;
157 }
158 147
159 switch ((ver >> 4) & 0xf) { 148 switch ((ver >> 4) & 0xf) {
160 case 0: 149 case 0:
@@ -182,7 +171,7 @@ static int omap2_onenand_get_freq(struct omap_onenand_platform_data *cfg,
182 171
183static struct gpmc_timings 172static struct gpmc_timings
184omap2_onenand_calc_sync_timings(struct omap_onenand_platform_data *cfg, 173omap2_onenand_calc_sync_timings(struct omap_onenand_platform_data *cfg,
185 int freq, bool clk_dep) 174 int freq)
186{ 175{
187 struct gpmc_timings t; 176 struct gpmc_timings t;
188 const int t_cer = 15; 177 const int t_cer = 15;
@@ -261,22 +250,6 @@ omap2_onenand_calc_sync_timings(struct omap_onenand_platform_data *cfg,
261 else 250 else
262 latency = 4; 251 latency = 4;
263 252
264 if (clk_dep) {
265 if (gpmc_clk_ns < 12) { /* >83Mhz */
266 t_ces = 3;
267 t_avds = 4;
268 } else if (gpmc_clk_ns < 15) { /* >66Mhz */
269 t_ces = 5;
270 t_avds = 4;
271 } else if (gpmc_clk_ns < 25) { /* >40Mhz */
272 t_ces = 6;
273 t_avds = 5;
274 } else {
275 t_ces = 7;
276 t_avds = 7;
277 }
278 }
279
280 /* Set synchronous read timings */ 253 /* Set synchronous read timings */
281 memset(&t, 0, sizeof(t)); 254 memset(&t, 0, sizeof(t));
282 255
@@ -399,16 +372,14 @@ static int omap2_onenand_setup_sync(void __iomem *onenand_base, int *freq_ptr)
399{ 372{
400 int ret, freq = *freq_ptr; 373 int ret, freq = *freq_ptr;
401 struct gpmc_timings t; 374 struct gpmc_timings t;
402 bool clk_dep = false;
403 375
404 if (!freq) { 376 if (!freq) {
405 /* Very first call freq is not known */ 377 /* Very first call freq is not known */
406 freq = omap2_onenand_get_freq(gpmc_onenand_data, 378 freq = omap2_onenand_get_freq(gpmc_onenand_data, onenand_base);
407 onenand_base, &clk_dep);
408 set_onenand_cfg(onenand_base); 379 set_onenand_cfg(onenand_base);
409 } 380 }
410 381
411 t = omap2_onenand_calc_sync_timings(gpmc_onenand_data, freq, clk_dep); 382 t = omap2_onenand_calc_sync_timings(gpmc_onenand_data, freq);
412 383
413 ret = gpmc_set_sync_mode(gpmc_onenand_data->cs, &t); 384 ret = gpmc_set_sync_mode(gpmc_onenand_data->cs, &t);
414 if (IS_ERR_VALUE(ret)) 385 if (IS_ERR_VALUE(ret))