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Diffstat (limited to 'arch/arm/mach-omap2/cm2_44xx.h')
-rw-r--r--arch/arm/mach-omap2/cm2_44xx.h73
1 files changed, 11 insertions, 62 deletions
diff --git a/arch/arm/mach-omap2/cm2_44xx.h b/arch/arm/mach-omap2/cm2_44xx.h
index aa4745044065..b9de72da1a8e 100644
--- a/arch/arm/mach-omap2/cm2_44xx.h
+++ b/arch/arm/mach-omap2/cm2_44xx.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * OMAP44xx CM2 instance offset macros 2 * OMAP44xx CM2 instance offset macros
3 * 3 *
4 * Copyright (C) 2009-2010 Texas Instruments, Inc. 4 * Copyright (C) 2009-2011 Texas Instruments, Inc.
5 * Copyright (C) 2009-2010 Nokia Corporation 5 * Copyright (C) 2009-2010 Nokia Corporation
6 * 6 *
7 * Paul Walmsley (paul@pwsan.com) 7 * Paul Walmsley (paul@pwsan.com)
@@ -40,9 +40,9 @@
40#define OMAP4430_CM2_CAM_INST 0x1000 40#define OMAP4430_CM2_CAM_INST 0x1000
41#define OMAP4430_CM2_DSS_INST 0x1100 41#define OMAP4430_CM2_DSS_INST 0x1100
42#define OMAP4430_CM2_GFX_INST 0x1200 42#define OMAP4430_CM2_GFX_INST 0x1200
43#define OMAP4430_CM2_L3INIT_INST 0x1300 43#define OMAP4430_CM2_L3INIT_INST 0x1300
44#define OMAP4430_CM2_L4PER_INST 0x1400 44#define OMAP4430_CM2_L4PER_INST 0x1400
45#define OMAP4430_CM2_CEFUSE_INST 0x1600 45#define OMAP4430_CM2_CEFUSE_INST 0x1600
46#define OMAP4430_CM2_RESTORE_INST 0x1e00 46#define OMAP4430_CM2_RESTORE_INST 0x1e00
47#define OMAP4430_CM2_INSTR_INST 0x1f00 47#define OMAP4430_CM2_INSTR_INST 0x1f00
48 48
@@ -65,7 +65,6 @@
65#define OMAP4430_CM2_L4PER_L4SEC_CDOFFS 0x0180 65#define OMAP4430_CM2_L4PER_L4SEC_CDOFFS 0x0180
66#define OMAP4430_CM2_CEFUSE_CEFUSE_CDOFFS 0x0000 66#define OMAP4430_CM2_CEFUSE_CEFUSE_CDOFFS 0x0000
67 67
68
69/* CM2 */ 68/* CM2 */
70 69
71/* CM2.OCP_SOCKET_CM2 register offsets */ 70/* CM2.OCP_SOCKET_CM2 register offsets */
@@ -121,8 +120,8 @@
121#define OMAP4430_CM_DIV_M7_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0064) 120#define OMAP4430_CM_DIV_M7_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0064)
122#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_PER_OFFSET 0x0068 121#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_PER_OFFSET 0x0068
123#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0068) 122#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0068)
124#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_PER_OFFSET 0x006c 123#define OMAP4_CM_SSC_MODFREQDIV_DPLL_PER_OFFSET 0x006c
125#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x006c) 124#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x006c)
126#define OMAP4_CM_CLKMODE_DPLL_USB_OFFSET 0x0080 125#define OMAP4_CM_CLKMODE_DPLL_USB_OFFSET 0x0080
127#define OMAP4430_CM_CLKMODE_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0080) 126#define OMAP4430_CM_CLKMODE_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0080)
128#define OMAP4_CM_IDLEST_DPLL_USB_OFFSET 0x0084 127#define OMAP4_CM_IDLEST_DPLL_USB_OFFSET 0x0084
@@ -135,8 +134,8 @@
135#define OMAP4430_CM_DIV_M2_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0090) 134#define OMAP4430_CM_DIV_M2_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0090)
136#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_USB_OFFSET 0x00a8 135#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_USB_OFFSET 0x00a8
137#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00a8) 136#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00a8)
138#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_USB_OFFSET 0x00ac 137#define OMAP4_CM_SSC_MODFREQDIV_DPLL_USB_OFFSET 0x00ac
139#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00ac) 138#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00ac)
140#define OMAP4_CM_CLKDCOLDO_DPLL_USB_OFFSET 0x00b4 139#define OMAP4_CM_CLKDCOLDO_DPLL_USB_OFFSET 0x00b4
141#define OMAP4430_CM_CLKDCOLDO_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00b4) 140#define OMAP4430_CM_CLKDCOLDO_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00b4)
142#define OMAP4_CM_CLKMODE_DPLL_UNIPRO_OFFSET 0x00c0 141#define OMAP4_CM_CLKMODE_DPLL_UNIPRO_OFFSET 0x00c0
@@ -151,8 +150,8 @@
151#define OMAP4430_CM_DIV_M2_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00d0) 150#define OMAP4430_CM_DIV_M2_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00d0)
152#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_UNIPRO_OFFSET 0x00e8 151#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_UNIPRO_OFFSET 0x00e8
153#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00e8) 152#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00e8)
154#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_UNIPRO_OFFSET 0x00ec 153#define OMAP4_CM_SSC_MODFREQDIV_DPLL_UNIPRO_OFFSET 0x00ec
155#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00ec) 154#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00ec)
156 155
157/* CM2.ALWAYS_ON_CM2 register offsets */ 156/* CM2.ALWAYS_ON_CM2 register offsets */
158#define OMAP4_CM_ALWON_CLKSTCTRL_OFFSET 0x0000 157#define OMAP4_CM_ALWON_CLKSTCTRL_OFFSET 0x0000
@@ -227,8 +226,8 @@
227#define OMAP4430_CM_D2D_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0508) 226#define OMAP4430_CM_D2D_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0508)
228#define OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET 0x0520 227#define OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET 0x0520
229#define OMAP4430_CM_D2D_SAD2D_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0520) 228#define OMAP4430_CM_D2D_SAD2D_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0520)
230#define OMAP4_CM_D2D_INSTEM_ICR_CLKCTRL_OFFSET 0x0528 229#define OMAP4_CM_D2D_MODEM_ICR_CLKCTRL_OFFSET 0x0528
231#define OMAP4430_CM_D2D_INSTEM_ICR_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0528) 230#define OMAP4430_CM_D2D_MODEM_ICR_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0528)
232#define OMAP4_CM_D2D_SAD2D_FW_CLKCTRL_OFFSET 0x0530 231#define OMAP4_CM_D2D_SAD2D_FW_CLKCTRL_OFFSET 0x0530
233#define OMAP4430_CM_D2D_SAD2D_FW_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0530) 232#define OMAP4430_CM_D2D_SAD2D_FW_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0530)
234#define OMAP4_CM_L4CFG_CLKSTCTRL_OFFSET 0x0600 233#define OMAP4_CM_L4CFG_CLKSTCTRL_OFFSET 0x0600
@@ -450,56 +449,6 @@
450#define OMAP4_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET 0x0020 449#define OMAP4_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET 0x0020
451#define OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_INST, 0x0020) 450#define OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_INST, 0x0020)
452 451
453/* CM2.RESTORE_CM2 register offsets */
454#define OMAP4_CM_L3_1_CLKSTCTRL_RESTORE_OFFSET 0x0000
455#define OMAP4430_CM_L3_1_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0000)
456#define OMAP4_CM_L3_2_CLKSTCTRL_RESTORE_OFFSET 0x0004
457#define OMAP4430_CM_L3_2_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0004)
458#define OMAP4_CM_L4CFG_CLKSTCTRL_RESTORE_OFFSET 0x0008
459#define OMAP4430_CM_L4CFG_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0008)
460#define OMAP4_CM_MEMIF_CLKSTCTRL_RESTORE_OFFSET 0x000c
461#define OMAP4430_CM_MEMIF_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x000c)
462#define OMAP4_CM_L4PER_CLKSTCTRL_RESTORE_OFFSET 0x0010
463#define OMAP4430_CM_L4PER_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0010)
464#define OMAP4_CM_L3INIT_CLKSTCTRL_RESTORE_OFFSET 0x0014
465#define OMAP4430_CM_L3INIT_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0014)
466#define OMAP4_CM_L3INSTR_L3_3_CLKCTRL_RESTORE_OFFSET 0x0018
467#define OMAP4430_CM_L3INSTR_L3_3_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0018)
468#define OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE_OFFSET 0x001c
469#define OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x001c)
470#define OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE_OFFSET 0x0020
471#define OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0020)
472#define OMAP4_CM_CM2_PROFILING_CLKCTRL_RESTORE_OFFSET 0x0024
473#define OMAP4430_CM_CM2_PROFILING_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0024)
474#define OMAP4_CM_D2D_STATICDEP_RESTORE_OFFSET 0x0028
475#define OMAP4430_CM_D2D_STATICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0028)
476#define OMAP4_CM_L3_1_DYNAMICDEP_RESTORE_OFFSET 0x002c
477#define OMAP4430_CM_L3_1_DYNAMICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x002c)
478#define OMAP4_CM_L3_2_DYNAMICDEP_RESTORE_OFFSET 0x0030
479#define OMAP4430_CM_L3_2_DYNAMICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0030)
480#define OMAP4_CM_D2D_DYNAMICDEP_RESTORE_OFFSET 0x0034
481#define OMAP4430_CM_D2D_DYNAMICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0034)
482#define OMAP4_CM_L4CFG_DYNAMICDEP_RESTORE_OFFSET 0x0038
483#define OMAP4430_CM_L4CFG_DYNAMICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0038)
484#define OMAP4_CM_L4PER_DYNAMICDEP_RESTORE_OFFSET 0x003c
485#define OMAP4430_CM_L4PER_DYNAMICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x003c)
486#define OMAP4_CM_L4PER_GPIO2_CLKCTRL_RESTORE_OFFSET 0x0040
487#define OMAP4430_CM_L4PER_GPIO2_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0040)
488#define OMAP4_CM_L4PER_GPIO3_CLKCTRL_RESTORE_OFFSET 0x0044
489#define OMAP4430_CM_L4PER_GPIO3_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0044)
490#define OMAP4_CM_L4PER_GPIO4_CLKCTRL_RESTORE_OFFSET 0x0048
491#define OMAP4430_CM_L4PER_GPIO4_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0048)
492#define OMAP4_CM_L4PER_GPIO5_CLKCTRL_RESTORE_OFFSET 0x004c
493#define OMAP4430_CM_L4PER_GPIO5_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x004c)
494#define OMAP4_CM_L4PER_GPIO6_CLKCTRL_RESTORE_OFFSET 0x0050
495#define OMAP4430_CM_L4PER_GPIO6_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0050)
496#define OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_RESTORE_OFFSET 0x0054
497#define OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0054)
498#define OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_RESTORE_OFFSET 0x0058
499#define OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0058)
500#define OMAP4_CM_SDMA_STATICDEP_RESTORE_OFFSET 0x005c
501#define OMAP4430_CM_SDMA_STATICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x005c)
502
503/* Function prototypes */ 452/* Function prototypes */
504extern u32 omap4_cm2_read_inst_reg(s16 inst, u16 idx); 453extern u32 omap4_cm2_read_inst_reg(s16 inst, u16 idx);
505extern void omap4_cm2_write_inst_reg(u32 val, s16 inst, u16 idx); 454extern void omap4_cm2_write_inst_reg(u32 val, s16 inst, u16 idx);
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