1 files changed, 6 insertions, 7 deletions

diff --git a/arch/arm/mach-omap1/clock_data.c b/arch/arm/mach-omap1/clock_data.c
index 6a32b9b0dc30..9b45f4b0ee22 100644
--- a/arch/arm/mach-omap1/clock_data.c
+++ b/arch/arm/mach-omap1/clock_data.c
@@ -775,11 +775,10 @@ static struct clk_functions omap1_clk_functions = {
 
 static void __init omap1_show_rates(void)
 {
-        pr_notice("Clocking rate (xtal/DPLL1/MPU): "
-                        "%ld.%01ld/%ld.%01ld/%ld.%01ld MHz\n",
-                ck_ref.rate / 1000000, (ck_ref.rate / 100000) % 10,
-                ck_dpll1.rate / 1000000, (ck_dpll1.rate / 100000) % 10,
-                arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10);
+        pr_notice("Clocking rate (xtal/DPLL1/MPU): %ld.%01ld/%ld.%01ld/%ld.%01ld MHz\n",
+                  ck_ref.rate / 1000000, (ck_ref.rate / 100000) % 10,
+                  ck_dpll1.rate / 1000000, (ck_dpll1.rate / 100000) % 10,
+                  arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10);
 }
 
 u32 cpu_mask;
@@ -840,8 +839,8 @@ int __init omap1_clk_init(void)
         if (cpu_is_omap16xx() && crystal_type == 2)
                 ck_ref.rate = 19200000;
 
-        pr_info("Clocks: ARM_SYSST: 0x%04x DPLL_CTL: 0x%04x ARM_CKCTL: "
-                "0x%04x\n", omap_readw(ARM_SYSST), omap_readw(DPLL_CTL),
+        pr_info("Clocks: ARM_SYSST: 0x%04x DPLL_CTL: 0x%04x ARM_CKCTL: 0x%04x\n",
+                omap_readw(ARM_SYSST), omap_readw(DPLL_CTL),
                 omap_readw(ARM_CKCTL));
 
         /* We want to be in syncronous scalable mode */