1 files changed, 69 insertions, 49 deletions

diff --git a/arch/arm/mach-mx5/cpu.c b/arch/arm/mach-mx5/cpu.c
index eaacb6e9b5d0..d40671da4372 100644
--- a/arch/arm/mach-mx5/cpu.c
+++ b/arch/arm/mach-mx5/cpu.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
  *
  * The code contained herein is licensed under the GNU General Public
  * License. You may obtain a copy of the GNU General Public License
@@ -20,37 +20,18 @@
 
 static int cpu_silicon_rev = -1;
 
-#define SI_REV 0x48
+#define IIM_SREV 0x24
 
-static void query_silicon_parameter(void)
+static int get_mx51_srev(void)
 {
-        void __iomem *rom = ioremap(MX51_IROM_BASE_ADDR, MX51_IROM_SIZE);
-        u32 rev;
+        void __iomem *iim_base = MX51_IO_ADDRESS(MX51_IIM_BASE_ADDR);
+        u32 rev = readl(iim_base + IIM_SREV) & 0xff;
 
-        if (!rom) {
-                cpu_silicon_rev = -EINVAL;
-                return;
-        }
-
-        rev = readl(rom + SI_REV);
-        switch (rev) {
-        case 0x1:
-                cpu_silicon_rev = MX51_CHIP_REV_1_0;
-                break;
-        case 0x2:
-                cpu_silicon_rev = MX51_CHIP_REV_1_1;
-                break;
-        case 0x10:
-                cpu_silicon_rev = MX51_CHIP_REV_2_0;
-                break;
-        case 0x20:
-                cpu_silicon_rev = MX51_CHIP_REV_3_0;
-                break;
-        default:
-                cpu_silicon_rev = 0;
-        }
-
-        iounmap(rom);
+        if (rev == 0x0)
+                return IMX_CHIP_REVISION_2_0;
+        else if (rev == 0x10)
+                return IMX_CHIP_REVISION_3_0;
+        return 0;
 }
 
 /*
@@ -64,7 +45,7 @@ int mx51_revision(void)
                 return -EINVAL;
 
         if (cpu_silicon_rev == -1)
-                query_silicon_parameter();
+                cpu_silicon_rev = get_mx51_srev();
 
         return cpu_silicon_rev;
 }
@@ -79,7 +60,10 @@ EXPORT_SYMBOL(mx51_revision);
  */
 static int __init mx51_neon_fixup(void)
 {
-        if (mx51_revision() < MX51_CHIP_REV_3_0 && (elf_hwcap & HWCAP_NEON)) {
+        if (!cpu_is_mx51())
+                return 0;
+
+        if (mx51_revision() < IMX_CHIP_REVISION_3_0 && (elf_hwcap & HWCAP_NEON)) {
                 elf_hwcap &= ~HWCAP_NEON;
                 pr_info("Turning off NEON support, detected broken NEON implementation\n");
         }
@@ -89,29 +73,65 @@ static int __init mx51_neon_fixup(void)
 late_initcall(mx51_neon_fixup);
 #endif
 
+static int get_mx53_srev(void)
+{
+        void __iomem *iim_base = MX51_IO_ADDRESS(MX53_IIM_BASE_ADDR);
+        u32 rev = readl(iim_base + IIM_SREV) & 0xff;
+
+        if (rev == 0x0)
+                return IMX_CHIP_REVISION_1_0;
+        else if (rev == 0x10)
+                return IMX_CHIP_REVISION_2_0;
+        return 0;
+}
+
+/*
+ * Returns:
+ *      the silicon revision of the cpu
+ *      -EINVAL - not a mx53
+ */
+int mx53_revision(void)
+{
+        if (!cpu_is_mx53())
+                return -EINVAL;
+
+        if (cpu_silicon_rev == -1)
+                cpu_silicon_rev = get_mx53_srev();
+
+        return cpu_silicon_rev;
+}
+EXPORT_SYMBOL(mx53_revision);
+
 static int __init post_cpu_init(void)
 {
         unsigned int reg;
         void __iomem *base;
 
-        if (!cpu_is_mx51())
-                return 0;
-
-        base = MX51_IO_ADDRESS(MX51_AIPS1_BASE_ADDR);
-        __raw_writel(0x0, base + 0x40);
-        __raw_writel(0x0, base + 0x44);
-        __raw_writel(0x0, base + 0x48);
-        __raw_writel(0x0, base + 0x4C);
-        reg = __raw_readl(base + 0x50) & 0x00FFFFFF;
-        __raw_writel(reg, base + 0x50);
-
-        base = MX51_IO_ADDRESS(MX51_AIPS2_BASE_ADDR);
-        __raw_writel(0x0, base + 0x40);
-        __raw_writel(0x0, base + 0x44);
-        __raw_writel(0x0, base + 0x48);
-        __raw_writel(0x0, base + 0x4C);
-        reg = __raw_readl(base + 0x50) & 0x00FFFFFF;
-        __raw_writel(reg, base + 0x50);
+        if (cpu_is_mx51() || cpu_is_mx53()) {
+                if (cpu_is_mx51())
+                        base = MX51_IO_ADDRESS(MX51_AIPS1_BASE_ADDR);
+                else
+                        base = MX53_IO_ADDRESS(MX53_AIPS1_BASE_ADDR);
+
+                __raw_writel(0x0, base + 0x40);
+                __raw_writel(0x0, base + 0x44);
+                __raw_writel(0x0, base + 0x48);
+                __raw_writel(0x0, base + 0x4C);
+                reg = __raw_readl(base + 0x50) & 0x00FFFFFF;
+                __raw_writel(reg, base + 0x50);
+
+                if (cpu_is_mx51())
+                        base = MX51_IO_ADDRESS(MX51_AIPS2_BASE_ADDR);
+                else
+                        base = MX53_IO_ADDRESS(MX53_AIPS2_BASE_ADDR);
+
+                __raw_writel(0x0, base + 0x40);
+                __raw_writel(0x0, base + 0x44);
+                __raw_writel(0x0, base + 0x48);
+                __raw_writel(0x0, base + 0x4C);
+                reg = __raw_readl(base + 0x50) & 0x00FFFFFF;
+                __raw_writel(reg, base + 0x50);
+        }
 
         return 0;
 }