3 files changed, 21 insertions, 0 deletions

diff --git a/arch/arm/mach-exynos4/cpu.c b/arch/arm/mach-exynos4/cpu.c
index 479dfa1951c8..793011391943 100644
--- a/arch/arm/mach-exynos4/cpu.c
+++ b/arch/arm/mach-exynos4/cpu.c
@@ -21,6 +21,8 @@
 #include <plat/clock.h>
 #include <plat/exynos4.h>
 #include <plat/sdhci.h>
+#include <plat/devs.h>
+#include <plat/fimc-core.h>
 
 #include <mach/regs-irq.h>
 
@@ -120,6 +122,11 @@ void __init exynos4_map_io(void)
         exynos4_default_sdhci1();
         exynos4_default_sdhci2();
         exynos4_default_sdhci3();
+
+        s3c_fimc_setname(0, "exynos4-fimc");
+        s3c_fimc_setname(1, "exynos4-fimc");
+        s3c_fimc_setname(2, "exynos4-fimc");
+        s3c_fimc_setname(3, "exynos4-fimc");
 }
 
 void __init exynos4_init_clocks(int xtal)
diff --git a/arch/arm/mach-exynos4/include/mach/irqs.h b/arch/arm/mach-exynos4/include/mach/irqs.h
index e3556d45c75b..1db1de8e3e81 100644
--- a/arch/arm/mach-exynos4/include/mach/irqs.h
+++ b/arch/arm/mach-exynos4/include/mach/irqs.h
@@ -108,6 +108,11 @@
 #define IRQ_MIPI_CSIS0          COMBINER_IRQ(30, 0)
 #define IRQ_MIPI_CSIS1          COMBINER_IRQ(30, 1)
 
+#define IRQ_FIMC0               COMBINER_IRQ(32, 0)
+#define IRQ_FIMC1               COMBINER_IRQ(32, 1)
+#define IRQ_FIMC2               COMBINER_IRQ(33, 0)
+#define IRQ_FIMC3               COMBINER_IRQ(33, 1)
+
 #define IRQ_ONENAND_AUDI        COMBINER_IRQ(34, 0)
 
 #define IRQ_MCT_L1              COMBINER_IRQ(35, 3)
diff --git a/arch/arm/mach-exynos4/include/mach/map.h b/arch/arm/mach-exynos4/include/mach/map.h
index 89ab6f75776c..4f50b07a376a 100644
--- a/arch/arm/mach-exynos4/include/mach/map.h
+++ b/arch/arm/mach-exynos4/include/mach/map.h
@@ -25,6 +25,11 @@
 
 #define EXYNOS4_PA_SYSRAM               0x02020000
 
+#define EXYNOS4_PA_FIMC0                0x11800000
+#define EXYNOS4_PA_FIMC1                0x11810000
+#define EXYNOS4_PA_FIMC2                0x11820000
+#define EXYNOS4_PA_FIMC3                0x11830000
+
 #define EXYNOS4_PA_I2S0                 0x03830000
 #define EXYNOS4_PA_I2S1                 0xE3100000
 #define EXYNOS4_PA_I2S2                 0xE2A00000
@@ -120,6 +125,10 @@
 #define S3C_PA_WDT                      EXYNOS4_PA_WATCHDOG
 
 #define S5P_PA_CHIPID                   EXYNOS4_PA_CHIPID
+#define S5P_PA_FIMC0                    EXYNOS4_PA_FIMC0
+#define S5P_PA_FIMC1                    EXYNOS4_PA_FIMC1
+#define S5P_PA_FIMC2                    EXYNOS4_PA_FIMC2
+#define S5P_PA_FIMC3                    EXYNOS4_PA_FIMC3
 #define S5P_PA_MIPI_CSIS0               EXYNOS4_PA_MIPI_CSIS0
 #define S5P_PA_MIPI_CSIS1               EXYNOS4_PA_MIPI_CSIS1
 #define S5P_PA_ONENAND                  EXYNOS4_PA_ONENAND