diff options
Diffstat (limited to 'arch/arm/mach-at91/include/mach')
-rw-r--r-- | arch/arm/mach-at91/include/mach/at91_rstc.h | 18 | ||||
-rw-r--r-- | arch/arm/mach-at91/include/mach/at91cap9.h | 2 | ||||
-rw-r--r-- | arch/arm/mach-at91/include/mach/at91sam9260.h | 2 | ||||
-rw-r--r-- | arch/arm/mach-at91/include/mach/at91sam9261.h | 2 | ||||
-rw-r--r-- | arch/arm/mach-at91/include/mach/at91sam9263.h | 2 | ||||
-rw-r--r-- | arch/arm/mach-at91/include/mach/at91sam9g45.h | 2 | ||||
-rw-r--r-- | arch/arm/mach-at91/include/mach/at91sam9rl.h | 2 |
7 files changed, 21 insertions, 9 deletions
diff --git a/arch/arm/mach-at91/include/mach/at91_rstc.h b/arch/arm/mach-at91/include/mach/at91_rstc.h index cbd2bf052c1f..875fa336800b 100644 --- a/arch/arm/mach-at91/include/mach/at91_rstc.h +++ b/arch/arm/mach-at91/include/mach/at91_rstc.h | |||
@@ -16,13 +16,25 @@ | |||
16 | #ifndef AT91_RSTC_H | 16 | #ifndef AT91_RSTC_H |
17 | #define AT91_RSTC_H | 17 | #define AT91_RSTC_H |
18 | 18 | ||
19 | #define AT91_RSTC_CR (AT91_RSTC + 0x00) /* Reset Controller Control Register */ | 19 | #ifndef __ASSEMBLY__ |
20 | extern void __iomem *at91_rstc_base; | ||
21 | |||
22 | #define at91_rstc_read(field) \ | ||
23 | __raw_readl(at91_rstc_base + field) | ||
24 | |||
25 | #define at91_rstc_write(field, value) \ | ||
26 | __raw_writel(value, at91_rstc_base + field); | ||
27 | #else | ||
28 | .extern at91_rstc_base | ||
29 | #endif | ||
30 | |||
31 | #define AT91_RSTC_CR 0x00 /* Reset Controller Control Register */ | ||
20 | #define AT91_RSTC_PROCRST (1 << 0) /* Processor Reset */ | 32 | #define AT91_RSTC_PROCRST (1 << 0) /* Processor Reset */ |
21 | #define AT91_RSTC_PERRST (1 << 2) /* Peripheral Reset */ | 33 | #define AT91_RSTC_PERRST (1 << 2) /* Peripheral Reset */ |
22 | #define AT91_RSTC_EXTRST (1 << 3) /* External Reset */ | 34 | #define AT91_RSTC_EXTRST (1 << 3) /* External Reset */ |
23 | #define AT91_RSTC_KEY (0xa5 << 24) /* KEY Password */ | 35 | #define AT91_RSTC_KEY (0xa5 << 24) /* KEY Password */ |
24 | 36 | ||
25 | #define AT91_RSTC_SR (AT91_RSTC + 0x04) /* Reset Controller Status Register */ | 37 | #define AT91_RSTC_SR 0x04 /* Reset Controller Status Register */ |
26 | #define AT91_RSTC_URSTS (1 << 0) /* User Reset Status */ | 38 | #define AT91_RSTC_URSTS (1 << 0) /* User Reset Status */ |
27 | #define AT91_RSTC_RSTTYP (7 << 8) /* Reset Type */ | 39 | #define AT91_RSTC_RSTTYP (7 << 8) /* Reset Type */ |
28 | #define AT91_RSTC_RSTTYP_GENERAL (0 << 8) | 40 | #define AT91_RSTC_RSTTYP_GENERAL (0 << 8) |
@@ -33,7 +45,7 @@ | |||
33 | #define AT91_RSTC_NRSTL (1 << 16) /* NRST Pin Level */ | 45 | #define AT91_RSTC_NRSTL (1 << 16) /* NRST Pin Level */ |
34 | #define AT91_RSTC_SRCMP (1 << 17) /* Software Reset Command in Progress */ | 46 | #define AT91_RSTC_SRCMP (1 << 17) /* Software Reset Command in Progress */ |
35 | 47 | ||
36 | #define AT91_RSTC_MR (AT91_RSTC + 0x08) /* Reset Controller Mode Register */ | 48 | #define AT91_RSTC_MR 0x08 /* Reset Controller Mode Register */ |
37 | #define AT91_RSTC_URSTEN (1 << 0) /* User Reset Enable */ | 49 | #define AT91_RSTC_URSTEN (1 << 0) /* User Reset Enable */ |
38 | #define AT91_RSTC_URSTIEN (1 << 4) /* User Reset Interrupt Enable */ | 50 | #define AT91_RSTC_URSTIEN (1 << 4) /* User Reset Interrupt Enable */ |
39 | #define AT91_RSTC_ERSTL (0xf << 8) /* External Reset Length */ | 51 | #define AT91_RSTC_ERSTL (0xf << 8) /* External Reset Length */ |
diff --git a/arch/arm/mach-at91/include/mach/at91cap9.h b/arch/arm/mach-at91/include/mach/at91cap9.h index 4c0e2f6011d7..61d952902f2b 100644 --- a/arch/arm/mach-at91/include/mach/at91cap9.h +++ b/arch/arm/mach-at91/include/mach/at91cap9.h | |||
@@ -83,7 +83,6 @@ | |||
83 | #define AT91_DDRSDRC0 (0xffffe600 - AT91_BASE_SYS) | 83 | #define AT91_DDRSDRC0 (0xffffe600 - AT91_BASE_SYS) |
84 | #define AT91_MATRIX (0xffffea00 - AT91_BASE_SYS) | 84 | #define AT91_MATRIX (0xffffea00 - AT91_BASE_SYS) |
85 | #define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) | 85 | #define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) |
86 | #define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) | ||
87 | #define AT91_GPBR (cpu_is_at91cap9_revB() ? \ | 86 | #define AT91_GPBR (cpu_is_at91cap9_revB() ? \ |
88 | (0xfffffd50 - AT91_BASE_SYS) : \ | 87 | (0xfffffd50 - AT91_BASE_SYS) : \ |
89 | (0xfffffd60 - AT91_BASE_SYS)) | 88 | (0xfffffd60 - AT91_BASE_SYS)) |
@@ -96,6 +95,7 @@ | |||
96 | #define AT91CAP9_BASE_PIOB 0xfffff400 | 95 | #define AT91CAP9_BASE_PIOB 0xfffff400 |
97 | #define AT91CAP9_BASE_PIOC 0xfffff600 | 96 | #define AT91CAP9_BASE_PIOC 0xfffff600 |
98 | #define AT91CAP9_BASE_PIOD 0xfffff800 | 97 | #define AT91CAP9_BASE_PIOD 0xfffff800 |
98 | #define AT91CAP9_BASE_RSTC 0xfffffd00 | ||
99 | #define AT91CAP9_BASE_SHDWC 0xfffffd10 | 99 | #define AT91CAP9_BASE_SHDWC 0xfffffd10 |
100 | #define AT91CAP9_BASE_RTT 0xfffffd20 | 100 | #define AT91CAP9_BASE_RTT 0xfffffd20 |
101 | #define AT91CAP9_BASE_PIT 0xfffffd30 | 101 | #define AT91CAP9_BASE_PIT 0xfffffd30 |
diff --git a/arch/arm/mach-at91/include/mach/at91sam9260.h b/arch/arm/mach-at91/include/mach/at91sam9260.h index f937c476bb67..fa5ca278adeb 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9260.h +++ b/arch/arm/mach-at91/include/mach/at91sam9260.h | |||
@@ -83,7 +83,6 @@ | |||
83 | #define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS) | 83 | #define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS) |
84 | #define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS) | 84 | #define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS) |
85 | #define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) | 85 | #define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) |
86 | #define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) | ||
87 | #define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS) | 86 | #define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS) |
88 | 87 | ||
89 | #define AT91SAM9260_BASE_ECC 0xffffe800 | 88 | #define AT91SAM9260_BASE_ECC 0xffffe800 |
@@ -92,6 +91,7 @@ | |||
92 | #define AT91SAM9260_BASE_PIOA 0xfffff400 | 91 | #define AT91SAM9260_BASE_PIOA 0xfffff400 |
93 | #define AT91SAM9260_BASE_PIOB 0xfffff600 | 92 | #define AT91SAM9260_BASE_PIOB 0xfffff600 |
94 | #define AT91SAM9260_BASE_PIOC 0xfffff800 | 93 | #define AT91SAM9260_BASE_PIOC 0xfffff800 |
94 | #define AT91SAM9260_BASE_RSTC 0xfffffd00 | ||
95 | #define AT91SAM9260_BASE_SHDWC 0xfffffd10 | 95 | #define AT91SAM9260_BASE_SHDWC 0xfffffd10 |
96 | #define AT91SAM9260_BASE_RTT 0xfffffd20 | 96 | #define AT91SAM9260_BASE_RTT 0xfffffd20 |
97 | #define AT91SAM9260_BASE_PIT 0xfffffd30 | 97 | #define AT91SAM9260_BASE_PIT 0xfffffd30 |
diff --git a/arch/arm/mach-at91/include/mach/at91sam9261.h b/arch/arm/mach-at91/include/mach/at91sam9261.h index 175604e261be..7cde2d36570e 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9261.h +++ b/arch/arm/mach-at91/include/mach/at91sam9261.h | |||
@@ -68,7 +68,6 @@ | |||
68 | #define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS) | 68 | #define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS) |
69 | #define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS) | 69 | #define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS) |
70 | #define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) | 70 | #define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) |
71 | #define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) | ||
72 | #define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS) | 71 | #define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS) |
73 | 72 | ||
74 | #define AT91SAM9261_BASE_SMC 0xffffec00 | 73 | #define AT91SAM9261_BASE_SMC 0xffffec00 |
@@ -76,6 +75,7 @@ | |||
76 | #define AT91SAM9261_BASE_PIOA 0xfffff400 | 75 | #define AT91SAM9261_BASE_PIOA 0xfffff400 |
77 | #define AT91SAM9261_BASE_PIOB 0xfffff600 | 76 | #define AT91SAM9261_BASE_PIOB 0xfffff600 |
78 | #define AT91SAM9261_BASE_PIOC 0xfffff800 | 77 | #define AT91SAM9261_BASE_PIOC 0xfffff800 |
78 | #define AT91SAM9261_BASE_RSTC 0xfffffd00 | ||
79 | #define AT91SAM9261_BASE_SHDWC 0xfffffd10 | 79 | #define AT91SAM9261_BASE_SHDWC 0xfffffd10 |
80 | #define AT91SAM9261_BASE_RTT 0xfffffd20 | 80 | #define AT91SAM9261_BASE_RTT 0xfffffd20 |
81 | #define AT91SAM9261_BASE_PIT 0xfffffd30 | 81 | #define AT91SAM9261_BASE_PIT 0xfffffd30 |
diff --git a/arch/arm/mach-at91/include/mach/at91sam9263.h b/arch/arm/mach-at91/include/mach/at91sam9263.h index 80c915002d83..5949abda962b 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9263.h +++ b/arch/arm/mach-at91/include/mach/at91sam9263.h | |||
@@ -78,7 +78,6 @@ | |||
78 | #define AT91_SDRAMC1 (0xffffe800 - AT91_BASE_SYS) | 78 | #define AT91_SDRAMC1 (0xffffe800 - AT91_BASE_SYS) |
79 | #define AT91_MATRIX (0xffffec00 - AT91_BASE_SYS) | 79 | #define AT91_MATRIX (0xffffec00 - AT91_BASE_SYS) |
80 | #define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) | 80 | #define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) |
81 | #define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) | ||
82 | #define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS) | 81 | #define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS) |
83 | 82 | ||
84 | #define AT91SAM9263_BASE_ECC0 0xffffe000 | 83 | #define AT91SAM9263_BASE_ECC0 0xffffe000 |
@@ -91,6 +90,7 @@ | |||
91 | #define AT91SAM9263_BASE_PIOC 0xfffff600 | 90 | #define AT91SAM9263_BASE_PIOC 0xfffff600 |
92 | #define AT91SAM9263_BASE_PIOD 0xfffff800 | 91 | #define AT91SAM9263_BASE_PIOD 0xfffff800 |
93 | #define AT91SAM9263_BASE_PIOE 0xfffffa00 | 92 | #define AT91SAM9263_BASE_PIOE 0xfffffa00 |
93 | #define AT91SAM9263_BASE_RSTC 0xfffffd00 | ||
94 | #define AT91SAM9263_BASE_SHDWC 0xfffffd10 | 94 | #define AT91SAM9263_BASE_SHDWC 0xfffffd10 |
95 | #define AT91SAM9263_BASE_RTT0 0xfffffd20 | 95 | #define AT91SAM9263_BASE_RTT0 0xfffffd20 |
96 | #define AT91SAM9263_BASE_PIT 0xfffffd30 | 96 | #define AT91SAM9263_BASE_PIT 0xfffffd30 |
diff --git a/arch/arm/mach-at91/include/mach/at91sam9g45.h b/arch/arm/mach-at91/include/mach/at91sam9g45.h index f0c23c960dec..dd9c95ea0862 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9g45.h +++ b/arch/arm/mach-at91/include/mach/at91sam9g45.h | |||
@@ -90,7 +90,6 @@ | |||
90 | #define AT91_DDRSDRC0 (0xffffe600 - AT91_BASE_SYS) | 90 | #define AT91_DDRSDRC0 (0xffffe600 - AT91_BASE_SYS) |
91 | #define AT91_MATRIX (0xffffea00 - AT91_BASE_SYS) | 91 | #define AT91_MATRIX (0xffffea00 - AT91_BASE_SYS) |
92 | #define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) | 92 | #define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) |
93 | #define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) | ||
94 | #define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS) | 93 | #define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS) |
95 | 94 | ||
96 | #define AT91SAM9G45_BASE_ECC 0xffffe200 | 95 | #define AT91SAM9G45_BASE_ECC 0xffffe200 |
@@ -102,6 +101,7 @@ | |||
102 | #define AT91SAM9G45_BASE_PIOC 0xfffff600 | 101 | #define AT91SAM9G45_BASE_PIOC 0xfffff600 |
103 | #define AT91SAM9G45_BASE_PIOD 0xfffff800 | 102 | #define AT91SAM9G45_BASE_PIOD 0xfffff800 |
104 | #define AT91SAM9G45_BASE_PIOE 0xfffffa00 | 103 | #define AT91SAM9G45_BASE_PIOE 0xfffffa00 |
104 | #define AT91SAM9G45_BASE_RSTC 0xfffffd00 | ||
105 | #define AT91SAM9G45_BASE_SHDWC 0xfffffd10 | 105 | #define AT91SAM9G45_BASE_SHDWC 0xfffffd10 |
106 | #define AT91SAM9G45_BASE_RTT 0xfffffd20 | 106 | #define AT91SAM9G45_BASE_RTT 0xfffffd20 |
107 | #define AT91SAM9G45_BASE_PIT 0xfffffd30 | 107 | #define AT91SAM9G45_BASE_PIT 0xfffffd30 |
diff --git a/arch/arm/mach-at91/include/mach/at91sam9rl.h b/arch/arm/mach-at91/include/mach/at91sam9rl.h index 2bb359e60b97..d7bead7118da 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9rl.h +++ b/arch/arm/mach-at91/include/mach/at91sam9rl.h | |||
@@ -72,7 +72,6 @@ | |||
72 | #define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS) | 72 | #define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS) |
73 | #define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS) | 73 | #define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS) |
74 | #define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) | 74 | #define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) |
75 | #define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) | ||
76 | #define AT91_SCKCR (0xfffffd50 - AT91_BASE_SYS) | 75 | #define AT91_SCKCR (0xfffffd50 - AT91_BASE_SYS) |
77 | #define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS) | 76 | #define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS) |
78 | 77 | ||
@@ -84,6 +83,7 @@ | |||
84 | #define AT91SAM9RL_BASE_PIOB 0xfffff600 | 83 | #define AT91SAM9RL_BASE_PIOB 0xfffff600 |
85 | #define AT91SAM9RL_BASE_PIOC 0xfffff800 | 84 | #define AT91SAM9RL_BASE_PIOC 0xfffff800 |
86 | #define AT91SAM9RL_BASE_PIOD 0xfffffa00 | 85 | #define AT91SAM9RL_BASE_PIOD 0xfffffa00 |
86 | #define AT91SAM9RL_BASE_RSTC 0xfffffd00 | ||
87 | #define AT91SAM9RL_BASE_SHDWC 0xfffffd10 | 87 | #define AT91SAM9RL_BASE_SHDWC 0xfffffd10 |
88 | #define AT91SAM9RL_BASE_RTT 0xfffffd20 | 88 | #define AT91SAM9RL_BASE_RTT 0xfffffd20 |
89 | #define AT91SAM9RL_BASE_PIT 0xfffffd30 | 89 | #define AT91SAM9RL_BASE_PIT 0xfffffd30 |