diff options
Diffstat (limited to 'arch/arm/kernel/topology.c')
-rw-r--r-- | arch/arm/kernel/topology.c | 42 |
1 files changed, 6 insertions, 36 deletions
diff --git a/arch/arm/kernel/topology.c b/arch/arm/kernel/topology.c index 26c12c6440fc..79282ebcd939 100644 --- a/arch/arm/kernel/topology.c +++ b/arch/arm/kernel/topology.c | |||
@@ -196,32 +196,7 @@ static inline void parse_dt_topology(void) {} | |||
196 | static inline void update_cpu_power(unsigned int cpuid, unsigned int mpidr) {} | 196 | static inline void update_cpu_power(unsigned int cpuid, unsigned int mpidr) {} |
197 | #endif | 197 | #endif |
198 | 198 | ||
199 | 199 | /* | |
200 | /* | ||
201 | * cpu topology management | ||
202 | */ | ||
203 | |||
204 | #define MPIDR_SMP_BITMASK (0x3 << 30) | ||
205 | #define MPIDR_SMP_VALUE (0x2 << 30) | ||
206 | |||
207 | #define MPIDR_MT_BITMASK (0x1 << 24) | ||
208 | |||
209 | /* | ||
210 | * These masks reflect the current use of the affinity levels. | ||
211 | * The affinity level can be up to 16 bits according to ARM ARM | ||
212 | */ | ||
213 | #define MPIDR_HWID_BITMASK 0xFFFFFF | ||
214 | |||
215 | #define MPIDR_LEVEL0_MASK 0x3 | ||
216 | #define MPIDR_LEVEL0_SHIFT 0 | ||
217 | |||
218 | #define MPIDR_LEVEL1_MASK 0xF | ||
219 | #define MPIDR_LEVEL1_SHIFT 8 | ||
220 | |||
221 | #define MPIDR_LEVEL2_MASK 0xFF | ||
222 | #define MPIDR_LEVEL2_SHIFT 16 | ||
223 | |||
224 | /* | ||
225 | * cpu topology table | 200 | * cpu topology table |
226 | */ | 201 | */ |
227 | struct cputopo_arm cpu_topology[NR_CPUS]; | 202 | struct cputopo_arm cpu_topology[NR_CPUS]; |
@@ -282,19 +257,14 @@ void store_cpu_topology(unsigned int cpuid) | |||
282 | 257 | ||
283 | if (mpidr & MPIDR_MT_BITMASK) { | 258 | if (mpidr & MPIDR_MT_BITMASK) { |
284 | /* core performance interdependency */ | 259 | /* core performance interdependency */ |
285 | cpuid_topo->thread_id = (mpidr >> MPIDR_LEVEL0_SHIFT) | 260 | cpuid_topo->thread_id = MPIDR_AFFINITY_LEVEL(mpidr, 0); |
286 | & MPIDR_LEVEL0_MASK; | 261 | cpuid_topo->core_id = MPIDR_AFFINITY_LEVEL(mpidr, 1); |
287 | cpuid_topo->core_id = (mpidr >> MPIDR_LEVEL1_SHIFT) | 262 | cpuid_topo->socket_id = MPIDR_AFFINITY_LEVEL(mpidr, 2); |
288 | & MPIDR_LEVEL1_MASK; | ||
289 | cpuid_topo->socket_id = (mpidr >> MPIDR_LEVEL2_SHIFT) | ||
290 | & MPIDR_LEVEL2_MASK; | ||
291 | } else { | 263 | } else { |
292 | /* largely independent cores */ | 264 | /* largely independent cores */ |
293 | cpuid_topo->thread_id = -1; | 265 | cpuid_topo->thread_id = -1; |
294 | cpuid_topo->core_id = (mpidr >> MPIDR_LEVEL0_SHIFT) | 266 | cpuid_topo->core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0); |
295 | & MPIDR_LEVEL0_MASK; | 267 | cpuid_topo->socket_id = MPIDR_AFFINITY_LEVEL(mpidr, 1); |
296 | cpuid_topo->socket_id = (mpidr >> MPIDR_LEVEL1_SHIFT) | ||
297 | & MPIDR_LEVEL1_MASK; | ||
298 | } | 268 | } |
299 | } else { | 269 | } else { |
300 | /* | 270 | /* |